2 * arch/xtensa/kernel/head.S
4 * Xtensa Processor startup code.
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 * Copyright (C) 2001 - 2008 Tensilica Inc.
12 * Chris Zankel <chris@zankel.net>
13 * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
14 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
18 #include <asm/processor.h>
20 #include <asm/cacheasm.h>
21 #include <asm/initialize_mmu.h>
23 #include <linux/init.h>
24 #include <linux/linkage.h>
27 * This module contains the entry code for kernel images. It performs the
28 * minimal setup needed to call the generic C routines.
32 * - The kernel image has been loaded to the actual address where it was
34 * - a2 contains either 0 or a pointer to a list of boot parameters.
35 * (see setup.c for more details)
42 * The bootloader passes a pointer to a list of boot parameters in a2.
45 /* The first bytes of the kernel image must be an instruction, so we
46 * manually allocate and define the literal constant we need for a jx
61 .section .init.text, "ax"
65 /* Disable interrupts and exceptions. */
70 /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
74 /* Start with a fresh windowbase and windowstart. */
82 /* Set a0 to 0 for the remaining initialization. */
86 /* Clear debugging registers. */
89 #if XCHAL_NUM_IBREAK > 0
97 .rept XCHAL_NUM_DBREAK - 1
98 wsr a0, SREG_DBREAKC + _index
99 .set _index, _index + 1
103 /* Clear CCOUNT (not really necessary, but nice) */
105 wsr a0, ccount # not really necessary, but nice
107 /* Disable zero-loops. */
113 /* Disable all timers. */
116 .rept XCHAL_NUM_TIMERS
117 wsr a0, SREG_CCOMPARE + _index
118 .set _index, _index + 1
121 /* Interrupt initialization. */
123 movi a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE
127 /* Disable coprocessors. */
133 /* Set PS.INTLEVEL=LOCKLEVEL, PS.WOE=0, kernel stack, PS.EXCM=0
135 * Note: PS.EXCM must be cleared before using any loop
136 * instructions; otherwise, they are silently disabled, and
137 * at most one iteration of the loop is executed.
144 /* Initialize the caches.
145 * a2, a3 are just working registers (clobbered).
148 #if XCHAL_DCACHE_LINE_LOCKABLE
149 ___unlock_dcache_all a2 a3
152 #if XCHAL_ICACHE_LINE_LOCKABLE
153 ___unlock_icache_all a2 a3
156 ___invalidate_dcache_all a2 a3
157 ___invalidate_icache_all a2 a3
163 /* Unpack data sections
165 * The linker script used to build the Linux kernel image
166 * creates a table located at __boot_reloc_table_start
167 * that contans the information what data needs to be unpacked.
172 movi a2, __boot_reloc_table_start
173 movi a3, __boot_reloc_table_end
175 1: beq a2, a3, 3f # no more entries?
176 l32i a4, a2, 0 # start destination (in RAM)
177 l32i a5, a2, 4 # end desination (in RAM)
178 l32i a6, a2, 8 # start source (in ROM)
179 addi a2, a2, 12 # next entry
180 beq a4, a5, 1b # skip, empty entry
181 beq a4, a6, 1b # skip, source and dest. are the same
183 2: l32i a7, a6, 0 # load word
185 s32i a7, a4, 0 # store word
191 /* All code and initialized data segments have been copied.
192 * Now clear the BSS segment.
195 movi a2, __bss_start # start of BSS
196 movi a3, __bss_stop # end of BSS
198 __loopt a2, a3, a4, 2
202 #if XCHAL_DCACHE_IS_WRITEBACK
204 /* After unpacking, flush the writeback cache to memory so the
205 * instructions/data are available.
208 ___flush_dcache_all a2 a3
211 /* Setup stack and enable window exceptions (keep irqs disabled) */
213 movi a1, init_thread_union
214 addi a1, a1, KERNEL_STACK_SIZE
216 movi a2, (1 << PS_WOE_BIT) | LOCKLEVEL
217 # WOE=1, INTLEVEL=LOCKLEVEL, UM=0
218 wsr a2, ps # (enable reg-windows; progmode stack)
221 /* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
223 movi a2, debug_exception
224 wsr a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
226 /* Set up EXCSAVE[1] to point to the exc_table. */
231 /* init_arch kick-starts the linux kernel */
236 movi a4, start_kernel
240 j should_never_return
250 ENTRY(swapper_pg_dir)
251 .fill PAGE_SIZE, 1, 0
254 ENTRY(empty_zero_page)
255 .fill PAGE_SIZE, 1, 0