arch/arm/plat-iop/pci.c

   1 /*
   2  * arch/arm/plat-iop/pci.c
   3  *
   4  * PCI support for the Intel IOP32X and IOP33X processors
   5  *
   6  * Author: Rory Bolt <rorybolt@pacbell.net>
   7  * Copyright (C) 2002 Rory Bolt
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/slab.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/ioport.h>
  20 #include <asm/io.h>
  21 #include <asm/irq.h>
  22 #include <asm/system.h>
  23 #include <asm/hardware.h>
  24 #include <asm/mach/pci.h>
  25 #include <asm/hardware/iop3xx.h>
  26
  27 // #define DEBUG
  28
  29 #ifdef DEBUG
  30 #define  DBG(x...) printk(x)
  31 #else
  32 #define  DBG(x...) do { } while (0)
  33 #endif
  34
  35 /*
  36  * This routine builds either a type0 or type1 configuration command.  If the
  37  * bus is on the 803xx then a type0 made, else a type1 is created.
  38  */
  39 static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
  40 {
  41         struct pci_sys_data *sys = bus->sysdata;
  42         u32 addr;
  43
  44         if (sys->busnr == bus->number)
  45                 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
  46         else
  47                 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
  48
  49         addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
  50
  51         return addr;
  52 }
  53
  54 /*
  55  * This routine checks the status of the last configuration cycle.  If an error
  56  * was detected it returns a 1, else it returns a 0.  The errors being checked
  57  * are parity, master abort, target abort (master and target).  These types of
  58  * errors occur during a config cycle where there is no device, like during
  59  * the discovery stage.
  60  */
  61 static int iop3xx_pci_status(void)
  62 {
  63         unsigned int status;
  64         int ret = 0;
  65
  66         /*
  67          * Check the status registers.
  68          */
  69         status = *IOP3XX_ATUSR;
  70         if (status & 0xf900) {
  71                 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
  72                 *IOP3XX_ATUSR = status & 0xf900;
  73                 ret = 1;
  74         }
  75
  76         status = *IOP3XX_ATUISR;
  77         if (status & 0x679f) {
  78                 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
  79                 *IOP3XX_ATUISR = status & 0x679f;
  80                 ret = 1;
  81         }
  82
  83         return ret;
  84 }
  85
  86 /*
  87  * Simply write the address register and read the configuration
  88  * data.  Note that the 4 nop's ensure that we are able to handle
  89  * a delayed abort (in theory.)
  90  */
  91 static u32 iop3xx_read(unsigned long addr)
  92 {
  93         u32 val;
  94
  95         __asm__ __volatile__(
  96                 "str    %1, [%2]\n\t"
  97                 "ldr    %0, [%3]\n\t"
  98                 "nop\n\t"
  99                 "nop\n\t"
 100                 "nop\n\t"
 101                 "nop\n\t"
 102                 : "=r" (val)
 103                 : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
 104
 105         return val;
 106 }
 107
 108 /*
 109  * The read routines must check the error status of the last configuration
 110  * cycle.  If there was an error, the routine returns all hex f's.
 111  */
 112 static int
 113 iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 114                 int size, u32 *value)
 115 {
 116         unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
 117         u32 val = iop3xx_read(addr) >> ((where & 3) * 8);
 118
 119         if (iop3xx_pci_status())
 120                 val = 0xffffffff;
 121
 122         *value = val;
 123
 124         return PCIBIOS_SUCCESSFUL;
 125 }
 126
 127 static int
 128 iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
 129                 int size, u32 value)
 130 {
 131         unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
 132         u32 val;
 133
 134         if (size != 4) {
 135                 val = iop3xx_read(addr);
 136                 if (iop3xx_pci_status())
 137                         return PCIBIOS_SUCCESSFUL;
 138
 139                 where = (where & 3) * 8;
 140
 141                 if (size == 1)
 142                         val &= ~(0xff << where);
 143                 else
 144                         val &= ~(0xffff << where);
 145
 146                 *IOP3XX_OCCDR = val | value << where;
 147         } else {
 148                 asm volatile(
 149                         "str    %1, [%2]\n\t"
 150                         "str    %0, [%3]\n\t"
 151                         "nop\n\t"
 152                         "nop\n\t"
 153                         "nop\n\t"
 154                         "nop\n\t"
 155                         :
 156                         : "r" (value), "r" (addr),
 157                           "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
 158         }
 159
 160         return PCIBIOS_SUCCESSFUL;
 161 }
 162
 163 static struct pci_ops iop3xx_ops = {
 164         .read   = iop3xx_read_config,
 165         .write  = iop3xx_write_config,
 166 };
 167
 168 /*
 169  * When a PCI device does not exist during config cycles, the 80200 gets a
 170  * bus error instead of returning 0xffffffff. This handler simply returns.
 171  */
 172 static int
 173 iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 174 {
 175         DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
 176                 addr, fsr, regs->ARM_pc, regs->ARM_lr);
 177
 178         /*
 179          * If it was an imprecise abort, then we need to correct the
 180          * return address to be _after_ the instruction.
 181          */
 182         if (fsr & (1 << 10))
 183                 regs->ARM_pc += 4;
 184
 185         return 0;
 186 }
 187
 188 int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
 189 {
 190         struct resource *res;
 191
 192         if (nr != 0)
 193                 return 0;
 194
 195         res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
 196         if (!res)
 197                 panic("PCI: unable to alloc resources");
 198
 199         res[0].start = IOP3XX_PCI_LOWER_IO_PA;
 200         res[0].end   = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
 201         res[0].name  = "IOP3XX PCI I/O Space";
 202         res[0].flags = IORESOURCE_IO;
 203         request_resource(&ioport_resource, &res[0]);
 204
 205         res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
 206         res[1].end   = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
 207         res[1].name  = "IOP3XX PCI Memory Space";
 208         res[1].flags = IORESOURCE_MEM;
 209         request_resource(&iomem_resource, &res[1]);
 210
 211         sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
 212         sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA;
 213
 214         sys->resource[0] = &res[0];
 215         sys->resource[1] = &res[1];
 216         sys->resource[2] = NULL;
 217
 218         return 1;
 219 }
 220
 221 struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
 222 {
 223         return pci_scan_bus(sys->busnr, &iop3xx_ops, sys);
 224 }
 225
 226 void __init iop3xx_atu_setup(void)
 227 {
 228         /* BAR 0 ( Disabled ) */
 229         *IOP3XX_IAUBAR0 = 0x0;
 230         *IOP3XX_IABAR0  = 0x0;
 231         *IOP3XX_IATVR0  = 0x0;
 232         *IOP3XX_IALR0   = 0x0;
 233
 234         /* BAR 1 ( Disabled ) */
 235         *IOP3XX_IAUBAR1 = 0x0;
 236         *IOP3XX_IABAR1  = 0x0;
 237         *IOP3XX_IALR1   = 0x0;
 238
 239         /* BAR 2 (1:1 mapping with Physical RAM) */
 240         /* Set limit and enable */
 241         *IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1;
 242         *IOP3XX_IAUBAR2 = 0x0;
 243
 244         /* Align the inbound bar with the base of memory */
 245         *IOP3XX_IABAR2 = PHYS_OFFSET |
 246                                PCI_BASE_ADDRESS_MEM_TYPE_64 |
 247                                PCI_BASE_ADDRESS_MEM_PREFETCH;
 248
 249         *IOP3XX_IATVR2 = PHYS_OFFSET;
 250
 251         /* Outbound window 0 */
 252         *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA;
 253         *IOP3XX_OUMWTVR0 = 0;
 254
 255         /* Outbound window 1 */
 256         *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE;
 257         *IOP3XX_OUMWTVR1 = 0;
 258
 259         /* BAR 3 ( Disabled ) */
 260         *IOP3XX_IAUBAR3 = 0x0;
 261         *IOP3XX_IABAR3  = 0x0;
 262         *IOP3XX_IATVR3  = 0x0;
 263         *IOP3XX_IALR3   = 0x0;
 264
 265         /* Setup the I/O Bar
 266          */
 267         *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;;
 268
 269         /* Enable inbound and outbound cycles
 270          */
 271         *IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 272                                PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 273         *IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN;
 274 }
 275
 276 void __init iop3xx_atu_disable(void)
 277 {
 278         *IOP3XX_ATUCMD = 0;
 279         *IOP3XX_ATUCR = 0;
 280
 281         /* wait for cycles to quiesce */
 282         while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY |
 283                                      IOP3XX_PCSR_IN_Q_BUSY))
 284                 cpu_relax();
 285
 286         /* BAR 0 ( Disabled ) */
 287         *IOP3XX_IAUBAR0 = 0x0;
 288         *IOP3XX_IABAR0  = 0x0;
 289         *IOP3XX_IATVR0  = 0x0;
 290         *IOP3XX_IALR0   = 0x0;
 291
 292         /* BAR 1 ( Disabled ) */
 293         *IOP3XX_IAUBAR1 = 0x0;
 294         *IOP3XX_IABAR1  = 0x0;
 295         *IOP3XX_IALR1   = 0x0;
 296
 297         /* BAR 2 ( Disabled ) */
 298         *IOP3XX_IAUBAR2 = 0x0;
 299         *IOP3XX_IABAR2  = 0x0;
 300         *IOP3XX_IATVR2  = 0x0;
 301         *IOP3XX_IALR2   = 0x0;
 302
 303         /* BAR 3 ( Disabled ) */
 304         *IOP3XX_IAUBAR3 = 0x0;
 305         *IOP3XX_IABAR3  = 0x0;
 306         *IOP3XX_IATVR3  = 0x0;
 307         *IOP3XX_IALR3   = 0x0;
 308
 309         /* Clear the outbound windows */
 310         *IOP3XX_OIOWTVR  = 0;
 311
 312         /* Outbound window 0 */
 313         *IOP3XX_OMWTVR0 = 0;
 314         *IOP3XX_OUMWTVR0 = 0;
 315
 316         /* Outbound window 1 */
 317         *IOP3XX_OMWTVR1 = 0;
 318         *IOP3XX_OUMWTVR1 = 0;
 319 }
 320
 321 /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
 322 int init_atu;
 323
 324 void __init iop3xx_pci_preinit(void)
 325 {
 326         if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
 327                 iop3xx_atu_disable();
 328                 iop3xx_atu_setup();
 329         }
 330
 331         DBG("PCI:  Intel 803xx PCI init code.\n");
 332         DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
 333         DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
 334                         *IOP3XX_OMWTVR0,
 335                         *IOP3XX_OIOWTVR);
 336         DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
 337         DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
 338                         *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
 339         DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
 340         DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
 341                         *IOP3XX_IABAR1, *IOP3XX_IALR1);
 342         DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
 343                         *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
 344         DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
 345                         *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
 346         DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
 347                         *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
 348
 349         hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
 350 }
 351
 352 /* allow init_atu to be user overridden */
 353 static int __init iop3xx_init_atu_setup(char *str)
 354 {
 355         init_atu = IOP3XX_INIT_ATU_DEFAULT;
 356         if (str) {
 357                 while (*str != '\0') {
 358                         switch (*str) {
 359                         case 'y':
 360                         case 'Y':
 361                                 init_atu = IOP3XX_INIT_ATU_ENABLE;
 362                                 break;
 363                         case 'n':
 364                         case 'N':
 365                                 init_atu = IOP3XX_INIT_ATU_DISABLE;
 366                                 break;
 367                         case ',':
 368                         case '=':
 369                                 break;
 370                         default:
 371                                 printk(KERN_DEBUG "\"%s\" malformed at "
 372                                             "character: \'%c\'",
 373                                             __FUNCTION__,
 374                                             *str);
 375                                 *(str + 1) = '\0';
 376                         }
 377                         str++;
 378                 }
 379         }
 380
 381         return 1;
 382 }
 383
 384 __setup("iop3xx_init_atu", iop3xx_init_atu_setup);
 385