2 * arch/arm/plat-iop/pci.c
4 * PCI support for the Intel IOP32X and IOP33X processors
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
22 #include <asm/system.h>
23 #include <asm/hardware.h>
24 #include <asm/mach/pci.h>
25 #include <asm/hardware/iop3xx.h>
30 #define DBG(x...) printk(x)
32 #define DBG(x...) do { } while (0)
36 * This routine builds either a type0 or type1 configuration command. If the
37 * bus is on the 803xx then a type0 made, else a type1 is created.
39 static u32
iop3xx_cfg_address(struct pci_bus
*bus
, int devfn
, int where
)
41 struct pci_sys_data
*sys
= bus
->sysdata
;
44 if (sys
->busnr
== bus
->number
)
45 addr
= 1 << (PCI_SLOT(devfn
) + 16) | (PCI_SLOT(devfn
) << 11);
47 addr
= bus
->number
<< 16 | PCI_SLOT(devfn
) << 11 | 1;
49 addr
|= PCI_FUNC(devfn
) << 8 | (where
& ~3);
55 * This routine checks the status of the last configuration cycle. If an error
56 * was detected it returns a 1, else it returns a 0. The errors being checked
57 * are parity, master abort, target abort (master and target). These types of
58 * errors occur during a config cycle where there is no device, like during
59 * the discovery stage.
61 static int iop3xx_pci_status(void)
67 * Check the status registers.
69 status
= *IOP3XX_ATUSR
;
70 if (status
& 0xf900) {
71 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status
);
72 *IOP3XX_ATUSR
= status
& 0xf900;
76 status
= *IOP3XX_ATUISR
;
77 if (status
& 0x679f) {
78 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status
);
79 *IOP3XX_ATUISR
= status
& 0x679f;
87 * Simply write the address register and read the configuration
88 * data. Note that the 4 nop's ensure that we are able to handle
89 * a delayed abort (in theory.)
91 static u32
iop3xx_read(unsigned long addr
)
103 : "r" (addr
), "r" (IOP3XX_OCCAR
), "r" (IOP3XX_OCCDR
));
109 * The read routines must check the error status of the last configuration
110 * cycle. If there was an error, the routine returns all hex f's.
113 iop3xx_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
114 int size
, u32
*value
)
116 unsigned long addr
= iop3xx_cfg_address(bus
, devfn
, where
);
117 u32 val
= iop3xx_read(addr
) >> ((where
& 3) * 8);
119 if (iop3xx_pci_status())
124 return PCIBIOS_SUCCESSFUL
;
128 iop3xx_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
131 unsigned long addr
= iop3xx_cfg_address(bus
, devfn
, where
);
135 val
= iop3xx_read(addr
);
136 if (iop3xx_pci_status())
137 return PCIBIOS_SUCCESSFUL
;
139 where
= (where
& 3) * 8;
142 val
&= ~(0xff << where
);
144 val
&= ~(0xffff << where
);
146 *IOP3XX_OCCDR
= val
| value
<< where
;
156 : "r" (value
), "r" (addr
),
157 "r" (IOP3XX_OCCAR
), "r" (IOP3XX_OCCDR
));
160 return PCIBIOS_SUCCESSFUL
;
163 static struct pci_ops iop3xx_ops
= {
164 .read
= iop3xx_read_config
,
165 .write
= iop3xx_write_config
,
169 * When a PCI device does not exist during config cycles, the 80200 gets a
170 * bus error instead of returning 0xffffffff. This handler simply returns.
173 iop3xx_pci_abort(unsigned long addr
, unsigned int fsr
, struct pt_regs
*regs
)
175 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
176 addr
, fsr
, regs
->ARM_pc
, regs
->ARM_lr
);
179 * If it was an imprecise abort, then we need to correct the
180 * return address to be _after_ the instruction.
188 int iop3xx_pci_setup(int nr
, struct pci_sys_data
*sys
)
190 struct resource
*res
;
195 res
= kzalloc(2 * sizeof(struct resource
), GFP_KERNEL
);
197 panic("PCI: unable to alloc resources");
199 res
[0].start
= IOP3XX_PCI_LOWER_IO_PA
;
200 res
[0].end
= IOP3XX_PCI_LOWER_IO_PA
+ IOP3XX_PCI_IO_WINDOW_SIZE
- 1;
201 res
[0].name
= "IOP3XX PCI I/O Space";
202 res
[0].flags
= IORESOURCE_IO
;
203 request_resource(&ioport_resource
, &res
[0]);
205 res
[1].start
= IOP3XX_PCI_LOWER_MEM_PA
;
206 res
[1].end
= IOP3XX_PCI_LOWER_MEM_PA
+ IOP3XX_PCI_MEM_WINDOW_SIZE
- 1;
207 res
[1].name
= "IOP3XX PCI Memory Space";
208 res
[1].flags
= IORESOURCE_MEM
;
209 request_resource(&iomem_resource
, &res
[1]);
211 sys
->mem_offset
= IOP3XX_PCI_LOWER_MEM_PA
- IOP3XX_PCI_LOWER_MEM_BA
;
212 sys
->io_offset
= IOP3XX_PCI_LOWER_IO_PA
- IOP3XX_PCI_LOWER_IO_BA
;
214 sys
->resource
[0] = &res
[0];
215 sys
->resource
[1] = &res
[1];
216 sys
->resource
[2] = NULL
;
221 struct pci_bus
*iop3xx_pci_scan_bus(int nr
, struct pci_sys_data
*sys
)
223 return pci_scan_bus(sys
->busnr
, &iop3xx_ops
, sys
);
226 void __init
iop3xx_atu_setup(void)
228 /* BAR 0 ( Disabled ) */
229 *IOP3XX_IAUBAR0
= 0x0;
230 *IOP3XX_IABAR0
= 0x0;
231 *IOP3XX_IATVR0
= 0x0;
234 /* BAR 1 ( Disabled ) */
235 *IOP3XX_IAUBAR1
= 0x0;
236 *IOP3XX_IABAR1
= 0x0;
239 /* BAR 2 (1:1 mapping with Physical RAM) */
240 /* Set limit and enable */
241 *IOP3XX_IALR2
= ~((u32
)IOP3XX_MAX_RAM_SIZE
- 1) & ~0x1;
242 *IOP3XX_IAUBAR2
= 0x0;
244 /* Align the inbound bar with the base of memory */
245 *IOP3XX_IABAR2
= PHYS_OFFSET
|
246 PCI_BASE_ADDRESS_MEM_TYPE_64
|
247 PCI_BASE_ADDRESS_MEM_PREFETCH
;
249 *IOP3XX_IATVR2
= PHYS_OFFSET
;
251 /* Outbound window 0 */
252 *IOP3XX_OMWTVR0
= IOP3XX_PCI_LOWER_MEM_PA
;
253 *IOP3XX_OUMWTVR0
= 0;
255 /* Outbound window 1 */
256 *IOP3XX_OMWTVR1
= IOP3XX_PCI_LOWER_MEM_PA
+ IOP3XX_PCI_MEM_WINDOW_SIZE
;
257 *IOP3XX_OUMWTVR1
= 0;
259 /* BAR 3 ( Disabled ) */
260 *IOP3XX_IAUBAR3
= 0x0;
261 *IOP3XX_IABAR3
= 0x0;
262 *IOP3XX_IATVR3
= 0x0;
267 *IOP3XX_OIOWTVR
= IOP3XX_PCI_LOWER_IO_PA
;;
269 /* Enable inbound and outbound cycles
271 *IOP3XX_ATUCMD
|= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
272 PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
273 *IOP3XX_ATUCR
|= IOP3XX_ATUCR_OUT_EN
;
276 void __init
iop3xx_atu_disable(void)
281 /* wait for cycles to quiesce */
282 while (*IOP3XX_PCSR
& (IOP3XX_PCSR_OUT_Q_BUSY
|
283 IOP3XX_PCSR_IN_Q_BUSY
))
286 /* BAR 0 ( Disabled ) */
287 *IOP3XX_IAUBAR0
= 0x0;
288 *IOP3XX_IABAR0
= 0x0;
289 *IOP3XX_IATVR0
= 0x0;
292 /* BAR 1 ( Disabled ) */
293 *IOP3XX_IAUBAR1
= 0x0;
294 *IOP3XX_IABAR1
= 0x0;
297 /* BAR 2 ( Disabled ) */
298 *IOP3XX_IAUBAR2
= 0x0;
299 *IOP3XX_IABAR2
= 0x0;
300 *IOP3XX_IATVR2
= 0x0;
303 /* BAR 3 ( Disabled ) */
304 *IOP3XX_IAUBAR3
= 0x0;
305 *IOP3XX_IABAR3
= 0x0;
306 *IOP3XX_IATVR3
= 0x0;
309 /* Clear the outbound windows */
312 /* Outbound window 0 */
314 *IOP3XX_OUMWTVR0
= 0;
316 /* Outbound window 1 */
318 *IOP3XX_OUMWTVR1
= 0;
321 /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
324 void __init
iop3xx_pci_preinit(void)
326 if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE
) {
327 iop3xx_atu_disable();
331 DBG("PCI: Intel 803xx PCI init code.\n");
332 DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD
);
333 DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
336 DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR
);
337 DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
338 *IOP3XX_IABAR0
, *IOP3XX_IALR0
, *IOP3XX_IATVR0
);
339 DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0
);
340 DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
341 *IOP3XX_IABAR1
, *IOP3XX_IALR1
);
342 DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
343 *IOP3XX_ERBAR
, *IOP3XX_ERLR
, *IOP3XX_ERTVR
);
344 DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
345 *IOP3XX_IABAR2
, *IOP3XX_IALR2
, *IOP3XX_IATVR2
);
346 DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
347 *IOP3XX_IABAR3
, *IOP3XX_IALR3
, *IOP3XX_IATVR3
);
349 hook_fault_code(16+6, iop3xx_pci_abort
, SIGBUS
, "imprecise external abort");
352 /* allow init_atu to be user overridden */
353 static int __init
iop3xx_init_atu_setup(char *str
)
355 init_atu
= IOP3XX_INIT_ATU_DEFAULT
;
357 while (*str
!= '\0') {
361 init_atu
= IOP3XX_INIT_ATU_ENABLE
;
365 init_atu
= IOP3XX_INIT_ATU_DISABLE
;
371 printk(KERN_DEBUG
"\"%s\" malformed at "
384 __setup("iop3xx_init_atu", iop3xx_init_atu_setup
);