drivers/pci/pcie/aspm.c

   1 /*
   2  * File:        drivers/pci/pcie/aspm.c
   3  * Enabling PCIE link L0s/L1 state and Clock Power Management
   4  *
   5  * Copyright (C) 2007 Intel
   6  * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
   7  * Copyright (C) Shaohua Li (shaohua.li@intel.com)
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/pci_regs.h>
  15 #include <linux/errno.h>
  16 #include <linux/pm.h>
  17 #include <linux/init.h>
  18 #include <linux/slab.h>
  19 #include <linux/pci-aspm.h>
  20 #include "../pci.h"
  21
  22 #ifdef MODULE_PARAM_PREFIX
  23 #undef MODULE_PARAM_PREFIX
  24 #endif
  25 #define MODULE_PARAM_PREFIX "pcie_aspm."
  26
  27 struct endpoint_state {
  28         unsigned int l0s_acceptable_latency;
  29         unsigned int l1_acceptable_latency;
  30 };
  31
  32 struct pcie_link_state {
  33         struct list_head sibiling;
  34         struct pci_dev *pdev;
  35
  36         /* ASPM state */
  37         unsigned int support_state;
  38         unsigned int enabled_state;
  39         unsigned int bios_aspm_state;
  40         /* upstream component */
  41         unsigned int l0s_upper_latency;
  42         unsigned int l1_upper_latency;
  43         /* downstream component */
  44         unsigned int l0s_down_latency;
  45         unsigned int l1_down_latency;
  46         /* Clock PM state*/
  47         unsigned int clk_pm_capable;
  48         unsigned int clk_pm_enabled;
  49         unsigned int bios_clk_state;
  50
  51         /*
  52          * A pcie downstream port only has one slot under it, so at most there
  53          * are 8 functions
  54          */
  55         struct endpoint_state endpoints[8];
  56 };
  57
  58 static int aspm_disabled, aspm_force;
  59 static DEFINE_MUTEX(aspm_lock);
  60 static LIST_HEAD(link_list);
  61
  62 #define POLICY_DEFAULT 0        /* BIOS default setting */
  63 #define POLICY_PERFORMANCE 1    /* high performance */
  64 #define POLICY_POWERSAVE 2      /* high power saving */
  65 static int aspm_policy;
  66 static const char *policy_str[] = {
  67         [POLICY_DEFAULT] = "default",
  68         [POLICY_PERFORMANCE] = "performance",
  69         [POLICY_POWERSAVE] = "powersave"
  70 };
  71
  72 static int policy_to_aspm_state(struct pci_dev *pdev)
  73 {
  74         struct pcie_link_state *link_state = pdev->link_state;
  75
  76         switch (aspm_policy) {
  77         case POLICY_PERFORMANCE:
  78                 /* Disable ASPM and Clock PM */
  79                 return 0;
  80         case POLICY_POWERSAVE:
  81                 /* Enable ASPM L0s/L1 */
  82                 return PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1;
  83         case POLICY_DEFAULT:
  84                 return link_state->bios_aspm_state;
  85         }
  86         return 0;
  87 }
  88
  89 static int policy_to_clkpm_state(struct pci_dev *pdev)
  90 {
  91         struct pcie_link_state *link_state = pdev->link_state;
  92
  93         switch (aspm_policy) {
  94         case POLICY_PERFORMANCE:
  95                 /* Disable ASPM and Clock PM */
  96                 return 0;
  97         case POLICY_POWERSAVE:
  98                 /* Disable Clock PM */
  99                 return 1;
 100         case POLICY_DEFAULT:
 101                 return link_state->bios_clk_state;
 102         }
 103         return 0;
 104 }
 105
 106 static void pcie_set_clock_pm(struct pci_dev *pdev, int enable)
 107 {
 108         struct pci_dev *child_dev;
 109         int pos;
 110         u16 reg16;
 111         struct pcie_link_state *link_state = pdev->link_state;
 112
 113         list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
 114                 pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
 115                 if (!pos)
 116                         return;
 117                 pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, &reg16);
 118                 if (enable)
 119                         reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
 120                 else
 121                         reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
 122                 pci_write_config_word(child_dev, pos + PCI_EXP_LNKCTL, reg16);
 123         }
 124         link_state->clk_pm_enabled = !!enable;
 125 }
 126
 127 static void pcie_check_clock_pm(struct pci_dev *pdev)
 128 {
 129         int pos;
 130         u32 reg32;
 131         u16 reg16;
 132         int capable = 1, enabled = 1;
 133         struct pci_dev *child_dev;
 134         struct pcie_link_state *link_state = pdev->link_state;
 135
 136         /* All functions should have the same cap and state, take the worst */
 137         list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
 138                 pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
 139                 if (!pos)
 140                         return;
 141                 pci_read_config_dword(child_dev, pos + PCI_EXP_LNKCAP, &reg32);
 142                 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
 143                         capable = 0;
 144                         enabled = 0;
 145                         break;
 146                 }
 147                 pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, &reg16);
 148                 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
 149                         enabled = 0;
 150         }
 151         link_state->clk_pm_capable = capable;
 152         link_state->clk_pm_enabled = enabled;
 153         link_state->bios_clk_state = enabled;
 154         pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev));
 155 }
 156
 157 /*
 158  * pcie_aspm_configure_common_clock: check if the 2 ends of a link
 159  *   could use common clock. If they are, configure them to use the
 160  *   common clock. That will reduce the ASPM state exit latency.
 161  */
 162 static void pcie_aspm_configure_common_clock(struct pci_dev *pdev)
 163 {
 164         int pos, child_pos;
 165         u16 reg16 = 0;
 166         struct pci_dev *child_dev;
 167         int same_clock = 1;
 168
 169         /*
 170          * all functions of a slot should have the same Slot Clock
 171          * Configuration, so just check one function
 172          * */
 173         child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev,
 174                 bus_list);
 175         BUG_ON(!child_dev->is_pcie);
 176
 177         /* Check downstream component if bit Slot Clock Configuration is 1 */
 178         child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
 179         pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKSTA, &reg16);
 180         if (!(reg16 & PCI_EXP_LNKSTA_SLC))
 181                 same_clock = 0;
 182
 183         /* Check upstream component if bit Slot Clock Configuration is 1 */
 184         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
 185         pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, &reg16);
 186         if (!(reg16 & PCI_EXP_LNKSTA_SLC))
 187                 same_clock = 0;
 188
 189         /* Configure downstream component, all functions */
 190         list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
 191                 child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
 192                 pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKCTL,
 193                         &reg16);
 194                 if (same_clock)
 195                         reg16 |= PCI_EXP_LNKCTL_CCC;
 196                 else
 197                         reg16 &= ~PCI_EXP_LNKCTL_CCC;
 198                 pci_write_config_word(child_dev, child_pos + PCI_EXP_LNKCTL,
 199                         reg16);
 200         }
 201
 202         /* Configure upstream component */
 203         pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
 204         if (same_clock)
 205                 reg16 |= PCI_EXP_LNKCTL_CCC;
 206         else
 207                 reg16 &= ~PCI_EXP_LNKCTL_CCC;
 208         pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
 209
 210         /* retrain link */
 211         reg16 |= PCI_EXP_LNKCTL_RL;
 212         pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
 213
 214         /* Wait for link training end */
 215         while (1) {
 216                 pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, &reg16);
 217                 if (!(reg16 & PCI_EXP_LNKSTA_LT))
 218                         break;
 219                 cpu_relax();
 220         }
 221 }
 222
 223 /*
 224  * calc_L0S_latency: Convert L0s latency encoding to ns
 225  */
 226 static unsigned int calc_L0S_latency(unsigned int latency_encoding, int ac)
 227 {
 228         unsigned int ns = 64;
 229
 230         if (latency_encoding == 0x7) {
 231                 if (ac)
 232                         ns = -1U;
 233                 else
 234                         ns = 5*1000; /* > 4us */
 235         } else
 236                 ns *= (1 << latency_encoding);
 237         return ns;
 238 }
 239
 240 /*
 241  * calc_L1_latency: Convert L1 latency encoding to ns
 242  */
 243 static unsigned int calc_L1_latency(unsigned int latency_encoding, int ac)
 244 {
 245         unsigned int ns = 1000;
 246
 247         if (latency_encoding == 0x7) {
 248                 if (ac)
 249                         ns = -1U;
 250                 else
 251                         ns = 65*1000; /* > 64us */
 252         } else
 253                 ns *= (1 << latency_encoding);
 254         return ns;
 255 }
 256
 257 static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state,
 258         unsigned int *l0s, unsigned int *l1, unsigned int *enabled)
 259 {
 260         int pos;
 261         u16 reg16;
 262         u32 reg32;
 263         unsigned int latency;
 264
 265         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
 266         pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, &reg32);
 267         *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
 268         if (*state != PCIE_LINK_STATE_L0S &&
 269                 *state != (PCIE_LINK_STATE_L1|PCIE_LINK_STATE_L0S))
 270                 *state = 0;
 271         if (*state == 0)
 272                 return;
 273
 274         latency = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
 275         *l0s = calc_L0S_latency(latency, 0);
 276         if (*state & PCIE_LINK_STATE_L1) {
 277                 latency = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
 278                 *l1 = calc_L1_latency(latency, 0);
 279         }
 280         pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
 281         *enabled = reg16 & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1);
 282 }
 283
 284 static void pcie_aspm_cap_init(struct pci_dev *pdev)
 285 {
 286         struct pci_dev *child_dev;
 287         u32 state, tmp;
 288         struct pcie_link_state *link_state = pdev->link_state;
 289
 290         /* upstream component states */
 291         pcie_aspm_get_cap_device(pdev, &link_state->support_state,
 292                 &link_state->l0s_upper_latency,
 293                 &link_state->l1_upper_latency,
 294                 &link_state->enabled_state);
 295         /* downstream component states, all functions have the same setting */
 296         child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev,
 297                 bus_list);
 298         pcie_aspm_get_cap_device(child_dev, &state,
 299                 &link_state->l0s_down_latency,
 300                 &link_state->l1_down_latency,
 301                 &tmp);
 302         link_state->support_state &= state;
 303         if (!link_state->support_state)
 304                 return;
 305         link_state->enabled_state &= link_state->support_state;
 306         link_state->bios_aspm_state = link_state->enabled_state;
 307
 308         /* ENDPOINT states*/
 309         list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
 310                 int pos;
 311                 u32 reg32;
 312                 unsigned int latency;
 313                 struct endpoint_state *ep_state =
 314                         &link_state->endpoints[PCI_FUNC(child_dev->devfn)];
 315
 316                 if (child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
 317                         child_dev->pcie_type != PCI_EXP_TYPE_LEG_END)
 318                         continue;
 319
 320                 pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
 321                 pci_read_config_dword(child_dev, pos + PCI_EXP_DEVCAP, &reg32);
 322                 latency = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
 323                 latency = calc_L0S_latency(latency, 1);
 324                 ep_state->l0s_acceptable_latency = latency;
 325                 if (link_state->support_state & PCIE_LINK_STATE_L1) {
 326                         latency = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
 327                         latency = calc_L1_latency(latency, 1);
 328                         ep_state->l1_acceptable_latency = latency;
 329                 }
 330         }
 331 }
 332
 333 static unsigned int __pcie_aspm_check_state_one(struct pci_dev *pdev,
 334         unsigned int state)
 335 {
 336         struct pci_dev *parent_dev, *tmp_dev;
 337         unsigned int latency, l1_latency = 0;
 338         struct pcie_link_state *link_state;
 339         struct endpoint_state *ep_state;
 340
 341         parent_dev = pdev->bus->self;
 342         link_state = parent_dev->link_state;
 343         state &= link_state->support_state;
 344         if (state == 0)
 345                 return 0;
 346         ep_state = &link_state->endpoints[PCI_FUNC(pdev->devfn)];
 347
 348         /*
 349          * Check latency for endpoint device.
 350          * TBD: The latency from the endpoint to root complex vary per
 351          * switch's upstream link state above the device. Here we just do a
 352          * simple check which assumes all links above the device can be in L1
 353          * state, that is we just consider the worst case. If switch's upstream
 354          * link can't be put into L0S/L1, then our check is too strictly.
 355          */
 356         tmp_dev = pdev;
 357         while (state & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
 358                 parent_dev = tmp_dev->bus->self;
 359                 link_state = parent_dev->link_state;
 360                 if (state & PCIE_LINK_STATE_L0S) {
 361                         latency = max_t(unsigned int,
 362                                         link_state->l0s_upper_latency,
 363                                         link_state->l0s_down_latency);
 364                         if (latency > ep_state->l0s_acceptable_latency)
 365                                 state &= ~PCIE_LINK_STATE_L0S;
 366                 }
 367                 if (state & PCIE_LINK_STATE_L1) {
 368                         latency = max_t(unsigned int,
 369                                         link_state->l1_upper_latency,
 370                                         link_state->l1_down_latency);
 371                         if (latency + l1_latency >
 372                                         ep_state->l1_acceptable_latency)
 373                                 state &= ~PCIE_LINK_STATE_L1;
 374                 }
 375                 if (!parent_dev->bus->self) /* parent_dev is a root port */
 376                         break;
 377                 else {
 378                         /*
 379                          * parent_dev is the downstream port of a switch, make
 380                          * tmp_dev the upstream port of the switch
 381                          */
 382                         tmp_dev = parent_dev->bus->self;
 383                         /*
 384                          * every switch on the path to root complex need 1 more
 385                          * microsecond for L1. Spec doesn't mention L0S.
 386                          */
 387                         if (state & PCIE_LINK_STATE_L1)
 388                                 l1_latency += 1000;
 389                 }
 390         }
 391         return state;
 392 }
 393
 394 static unsigned int pcie_aspm_check_state(struct pci_dev *pdev,
 395         unsigned int state)
 396 {
 397         struct pci_dev *child_dev;
 398
 399         /* If no child, disable the link */
 400         if (list_empty(&pdev->subordinate->devices))
 401                 return 0;
 402         list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
 403                 if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
 404                         /*
 405                          * If downstream component of a link is pci bridge, we
 406                          * disable ASPM for now for the link
 407                          * */
 408                         state = 0;
 409                         break;
 410                 }
 411                 if ((child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
 412                         child_dev->pcie_type != PCI_EXP_TYPE_LEG_END))
 413                         continue;
 414                 /* Device not in D0 doesn't need check latency */
 415                 if (child_dev->current_state == PCI_D1 ||
 416                         child_dev->current_state == PCI_D2 ||
 417                         child_dev->current_state == PCI_D3hot ||
 418                         child_dev->current_state == PCI_D3cold)
 419                         continue;
 420                 state = __pcie_aspm_check_state_one(child_dev, state);
 421         }
 422         return state;
 423 }
 424
 425 static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state)
 426 {
 427         u16 reg16;
 428         int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
 429
 430         pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
 431         reg16 &= ~0x3;
 432         reg16 |= state;
 433         pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
 434 }
 435
 436 static void __pcie_aspm_config_link(struct pci_dev *pdev, unsigned int state)
 437 {
 438         struct pci_dev *child_dev;
 439         int valid = 1;
 440         struct pcie_link_state *link_state = pdev->link_state;
 441
 442         /*
 443          * if the downstream component has pci bridge function, don't do ASPM
 444          * now
 445          */
 446         list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
 447                 if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
 448                         valid = 0;
 449                         break;
 450                 }
 451         }
 452         if (!valid)
 453                 return;
 454
 455         /*
 456          * spec 2.0 suggests all functions should be configured the same
 457          * setting for ASPM. Enabling ASPM L1 should be done in upstream
 458          * component first and then downstream, and vice versa for disabling
 459          * ASPM L1. Spec doesn't mention L0S.
 460          */
 461         if (state & PCIE_LINK_STATE_L1)
 462                 __pcie_aspm_config_one_dev(pdev, state);
 463
 464         list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list)
 465                 __pcie_aspm_config_one_dev(child_dev, state);
 466
 467         if (!(state & PCIE_LINK_STATE_L1))
 468                 __pcie_aspm_config_one_dev(pdev, state);
 469
 470         link_state->enabled_state = state;
 471 }
 472
 473 static void __pcie_aspm_configure_link_state(struct pci_dev *pdev,
 474         unsigned int state)
 475 {
 476         struct pcie_link_state *link_state = pdev->link_state;
 477
 478         if (link_state->support_state == 0)
 479                 return;
 480         state &= PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1;
 481
 482         /* state 0 means disabling aspm */
 483         state = pcie_aspm_check_state(pdev, state);
 484         if (link_state->enabled_state == state)
 485                 return;
 486         __pcie_aspm_config_link(pdev, state);
 487 }
 488
 489 /*
 490  * pcie_aspm_configure_link_state: enable/disable PCI express link state
 491  * @pdev: the root port or switch downstream port
 492  */
 493 static void pcie_aspm_configure_link_state(struct pci_dev *pdev,
 494         unsigned int state)
 495 {
 496         down_read(&pci_bus_sem);
 497         mutex_lock(&aspm_lock);
 498         __pcie_aspm_configure_link_state(pdev, state);
 499         mutex_unlock(&aspm_lock);
 500         up_read(&pci_bus_sem);
 501 }
 502
 503 static void free_link_state(struct pci_dev *pdev)
 504 {
 505         kfree(pdev->link_state);
 506         pdev->link_state = NULL;
 507 }
 508
 509 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
 510 {
 511         struct pci_dev *child_dev;
 512         int child_pos;
 513         u32 reg32;
 514
 515         /*
 516          * Some functions in a slot might not all be PCIE functions, very
 517          * strange. Disable ASPM for the whole slot
 518          */
 519         list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
 520                 child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
 521                 if (!child_pos)
 522                         return -EINVAL;
 523
 524                 /*
 525                  * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
 526                  * RBER bit to determine if a function is 1.1 version device
 527                  */
 528                 pci_read_config_dword(child_dev, child_pos + PCI_EXP_DEVCAP,
 529                         &reg32);
 530                 if (!(reg32 & PCI_EXP_DEVCAP_RBER && !aspm_force)) {
 531                         printk("Pre-1.1 PCIe device detected, "
 532                                 "disable ASPM for %s. It can be enabled forcedly"
 533                                 " with 'pcie_aspm=force'\n", pci_name(pdev));
 534                         return -EINVAL;
 535                 }
 536         }
 537         return 0;
 538 }
 539
 540 /*
 541  * pcie_aspm_init_link_state: Initiate PCI express link state.
 542  * It is called after the pcie and its children devices are scaned.
 543  * @pdev: the root port or switch downstream port
 544  */
 545 void pcie_aspm_init_link_state(struct pci_dev *pdev)
 546 {
 547         unsigned int state;
 548         struct pcie_link_state *link_state;
 549         int error = 0;
 550
 551         if (aspm_disabled || !pdev->is_pcie || pdev->link_state)
 552                 return;
 553         if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
 554                 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
 555                 return;
 556         down_read(&pci_bus_sem);
 557         if (list_empty(&pdev->subordinate->devices))
 558                 goto out;
 559
 560         if (pcie_aspm_sanity_check(pdev))
 561                 goto out;
 562
 563         mutex_lock(&aspm_lock);
 564
 565         link_state = kzalloc(sizeof(*link_state), GFP_KERNEL);
 566         if (!link_state)
 567                 goto unlock_out;
 568         pdev->link_state = link_state;
 569
 570         pcie_aspm_configure_common_clock(pdev);
 571
 572         pcie_aspm_cap_init(pdev);
 573
 574         /* config link state to avoid BIOS error */
 575         state = pcie_aspm_check_state(pdev, policy_to_aspm_state(pdev));
 576         __pcie_aspm_config_link(pdev, state);
 577
 578         pcie_check_clock_pm(pdev);
 579
 580         link_state->pdev = pdev;
 581         list_add(&link_state->sibiling, &link_list);
 582
 583 unlock_out:
 584         if (error)
 585                 free_link_state(pdev);
 586         mutex_unlock(&aspm_lock);
 587 out:
 588         up_read(&pci_bus_sem);
 589 }
 590
 591 /* @pdev: the endpoint device */
 592 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
 593 {
 594         struct pci_dev *parent = pdev->bus->self;
 595         struct pcie_link_state *link_state = parent->link_state;
 596
 597         if (aspm_disabled || !pdev->is_pcie || !parent || !link_state)
 598                 return;
 599         if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
 600                 parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
 601                 return;
 602         down_read(&pci_bus_sem);
 603         mutex_lock(&aspm_lock);
 604
 605         /*
 606          * All PCIe functions are in one slot, remove one function will remove
 607          * the the whole slot, so just wait
 608          */
 609         if (!list_empty(&parent->subordinate->devices))
 610                 goto out;
 611
 612         /* All functions are removed, so just disable ASPM for the link */
 613         __pcie_aspm_config_one_dev(parent, 0);
 614         list_del(&link_state->sibiling);
 615         /* Clock PM is for endpoint device */
 616
 617         free_link_state(parent);
 618 out:
 619         mutex_unlock(&aspm_lock);
 620         up_read(&pci_bus_sem);
 621 }
 622
 623 /* @pdev: the root port or switch downstream port */
 624 void pcie_aspm_pm_state_change(struct pci_dev *pdev)
 625 {
 626         struct pcie_link_state *link_state = pdev->link_state;
 627
 628         if (aspm_disabled || !pdev->is_pcie || !pdev->link_state)
 629                 return;
 630         if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
 631                 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
 632                 return;
 633         /*
 634          * devices changed PM state, we should recheck if latency meets all
 635          * functions' requirement
 636          */
 637         pcie_aspm_configure_link_state(pdev, link_state->enabled_state);
 638 }
 639
 640 /*
 641  * pci_disable_link_state - disable pci device's link state, so the link will
 642  * never enter specific states
 643  */
 644 void pci_disable_link_state(struct pci_dev *pdev, int state)
 645 {
 646         struct pci_dev *parent = pdev->bus->self;
 647         struct pcie_link_state *link_state;
 648
 649         if (aspm_disabled || !pdev->is_pcie)
 650                 return;
 651         if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
 652             pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
 653                 parent = pdev;
 654         if (!parent || !parent->link_state)
 655                 return;
 656
 657         down_read(&pci_bus_sem);
 658         mutex_lock(&aspm_lock);
 659         link_state = parent->link_state;
 660         link_state->support_state &=
 661                 ~(state & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1));
 662         if (state & PCIE_LINK_STATE_CLKPM)
 663                 link_state->clk_pm_capable = 0;
 664
 665         __pcie_aspm_configure_link_state(parent, link_state->enabled_state);
 666         if (!link_state->clk_pm_capable && link_state->clk_pm_enabled)
 667                 pcie_set_clock_pm(parent, 0);
 668         mutex_unlock(&aspm_lock);
 669         up_read(&pci_bus_sem);
 670 }
 671 EXPORT_SYMBOL(pci_disable_link_state);
 672
 673 static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
 674 {
 675         int i;
 676         struct pci_dev *pdev;
 677         struct pcie_link_state *link_state;
 678
 679         for (i = 0; i < ARRAY_SIZE(policy_str); i++)
 680                 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
 681                         break;
 682         if (i >= ARRAY_SIZE(policy_str))
 683                 return -EINVAL;
 684         if (i == aspm_policy)
 685                 return 0;
 686
 687         down_read(&pci_bus_sem);
 688         mutex_lock(&aspm_lock);
 689         aspm_policy = i;
 690         list_for_each_entry(link_state, &link_list, sibiling) {
 691                 pdev = link_state->pdev;
 692                 __pcie_aspm_configure_link_state(pdev,
 693                         policy_to_aspm_state(pdev));
 694                 if (link_state->clk_pm_capable &&
 695                     link_state->clk_pm_enabled != policy_to_clkpm_state(pdev))
 696                         pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev));
 697
 698         }
 699         mutex_unlock(&aspm_lock);
 700         up_read(&pci_bus_sem);
 701         return 0;
 702 }
 703
 704 static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
 705 {
 706         int i, cnt = 0;
 707         for (i = 0; i < ARRAY_SIZE(policy_str); i++)
 708                 if (i == aspm_policy)
 709                         cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
 710                 else
 711                         cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
 712         return cnt;
 713 }
 714
 715 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
 716         NULL, 0644);
 717
 718 #ifdef CONFIG_PCIEASPM_DEBUG
 719 static ssize_t link_state_show(struct device *dev,
 720                 struct device_attribute *attr,
 721                 char *buf)
 722 {
 723         struct pci_dev *pci_device = to_pci_dev(dev);
 724         struct pcie_link_state *link_state = pci_device->link_state;
 725
 726         return sprintf(buf, "%d\n", link_state->enabled_state);
 727 }
 728
 729 static ssize_t link_state_store(struct device *dev,
 730                 struct device_attribute *attr,
 731                 const char *buf,
 732                 size_t n)
 733 {
 734         struct pci_dev *pci_device = to_pci_dev(dev);
 735         int state;
 736
 737         if (n < 1)
 738                 return -EINVAL;
 739         state = buf[0]-'0';
 740         if (state >= 0 && state <= 3) {
 741                 /* setup link aspm state */
 742                 pcie_aspm_configure_link_state(pci_device, state);
 743                 return n;
 744         }
 745
 746         return -EINVAL;
 747 }
 748
 749 static ssize_t clk_ctl_show(struct device *dev,
 750                 struct device_attribute *attr,
 751                 char *buf)
 752 {
 753         struct pci_dev *pci_device = to_pci_dev(dev);
 754         struct pcie_link_state *link_state = pci_device->link_state;
 755
 756         return sprintf(buf, "%d\n", link_state->clk_pm_enabled);
 757 }
 758
 759 static ssize_t clk_ctl_store(struct device *dev,
 760                 struct device_attribute *attr,
 761                 const char *buf,
 762                 size_t n)
 763 {
 764         struct pci_dev *pci_device = to_pci_dev(dev);
 765         int state;
 766
 767         if (n < 1)
 768                 return -EINVAL;
 769         state = buf[0]-'0';
 770
 771         down_read(&pci_bus_sem);
 772         mutex_lock(&aspm_lock);
 773         pcie_set_clock_pm(pci_device, !!state);
 774         mutex_unlock(&aspm_lock);
 775         up_read(&pci_bus_sem);
 776
 777         return n;
 778 }
 779
 780 static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
 781 static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
 782
 783 static char power_group[] = "power";
 784 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
 785 {
 786         struct pcie_link_state *link_state = pdev->link_state;
 787
 788         if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
 789                 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
 790                 return;
 791
 792         if (link_state->support_state)
 793                 sysfs_add_file_to_group(&pdev->dev.kobj,
 794                         &dev_attr_link_state.attr, power_group);
 795         if (link_state->clk_pm_capable)
 796                 sysfs_add_file_to_group(&pdev->dev.kobj,
 797                         &dev_attr_clk_ctl.attr, power_group);
 798 }
 799
 800 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
 801 {
 802         struct pcie_link_state *link_state = pdev->link_state;
 803
 804         if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
 805                 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
 806                 return;
 807
 808         if (link_state->support_state)
 809                 sysfs_remove_file_from_group(&pdev->dev.kobj,
 810                         &dev_attr_link_state.attr, power_group);
 811         if (link_state->clk_pm_capable)
 812                 sysfs_remove_file_from_group(&pdev->dev.kobj,
 813                         &dev_attr_clk_ctl.attr, power_group);
 814 }
 815 #endif
 816
 817 static int __init pcie_aspm_disable(char *str)
 818 {
 819         if (!strcmp(str, "off")) {
 820                 aspm_disabled = 1;
 821                 printk(KERN_INFO "PCIe ASPM is disabled\n");
 822         } else if (!strcmp(str, "force")) {
 823                 aspm_force = 1;
 824                 printk(KERN_INFO "PCIe ASPM is forcedly enabled\n");
 825         }
 826         return 1;
 827 }
 828
 829 __setup("pcie_aspm=", pcie_aspm_disable);
 830
 831 void pcie_no_aspm(void)
 832 {
 833         if (!aspm_force)
 834                 aspm_disabled = 1;
 835 }
 836
 837 #ifdef CONFIG_ACPI
 838 #include <acpi/acpi_bus.h>
 839 #include <linux/pci-acpi.h>
 840 static void pcie_aspm_platform_init(void)
 841 {
 842         pcie_osc_support_set(OSC_ACTIVE_STATE_PWR_SUPPORT|
 843                 OSC_CLOCK_PWR_CAPABILITY_SUPPORT);
 844 }
 845 #else
 846 static inline void pcie_aspm_platform_init(void) { }
 847 #endif
 848
 849 static int __init pcie_aspm_init(void)
 850 {
 851         if (aspm_disabled)
 852                 return 0;
 853         pcie_aspm_platform_init();
 854         return 0;
 855 }
 856
 857 fs_initcall(pcie_aspm_init);