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[PATCH] mark struct file_operations const 5
[linux-2.6/btrfs-unstable.git] / drivers / ata / sata_sx4.c
blob06e87a37738239d7b8b427673cf1ac005fa00f27
1 /*
2 * sata_sx4.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
46
47 #define DRV_NAME "sata_sx4"
48 #define DRV_VERSION "0.9"
49
50
51 enum {
52 PDC_MMIO_BAR = 3,
53 PDC_DIMM_BAR = 4,
54
55 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
56
57 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
58 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
59 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
60 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
61
62 PDC_20621_SEQCTL = 0x400,
63 PDC_20621_SEQMASK = 0x480,
64 PDC_20621_GENERAL_CTL = 0x484,
65 PDC_20621_PAGE_SIZE = (32 * 1024),
66
67 /* chosen, not constant, values; we design our own DIMM mem map */
68 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
69 PDC_20621_DIMM_BASE = 0x00200000,
70 PDC_20621_DIMM_DATA = (64 * 1024),
71 PDC_DIMM_DATA_STEP = (256 * 1024),
72 PDC_DIMM_WINDOW_STEP = (8 * 1024),
73 PDC_DIMM_HOST_PRD = (6 * 1024),
74 PDC_DIMM_HOST_PKT = (128 * 0),
75 PDC_DIMM_HPKT_PRD = (128 * 1),
76 PDC_DIMM_ATA_PKT = (128 * 2),
77 PDC_DIMM_APKT_PRD = (128 * 3),
78 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
79 PDC_PAGE_WINDOW = 0x40,
80 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
81 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
82 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
83
84 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
85
86 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
87 (1<<23),
88
89 board_20621 = 0, /* FastTrak S150 SX4 */
90
91 PDC_RESET = (1 << 11), /* HDMA reset */
92
93 PDC_MAX_HDMA = 32,
94 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
95
96 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
97 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
98 PDC_MAX_DIMM_MODULE = 0x02,
99 PDC_I2C_CONTROL_OFFSET = 0x48,
100 PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
101 PDC_DIMM0_CONTROL_OFFSET = 0x80,
102 PDC_DIMM1_CONTROL_OFFSET = 0x84,
103 PDC_SDRAM_CONTROL_OFFSET = 0x88,
104 PDC_I2C_WRITE = 0x00000000,
105 PDC_I2C_READ = 0x00000040,
106 PDC_I2C_START = 0x00000080,
107 PDC_I2C_MASK_INT = 0x00000020,
108 PDC_I2C_COMPLETE = 0x00010000,
109 PDC_I2C_NO_ACK = 0x00100000,
110 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
111 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
112 PDC_DIMM_SPD_ROW_NUM = 3,
113 PDC_DIMM_SPD_COLUMN_NUM = 4,
114 PDC_DIMM_SPD_MODULE_ROW = 5,
115 PDC_DIMM_SPD_TYPE = 11,
116 PDC_DIMM_SPD_FRESH_RATE = 12,
117 PDC_DIMM_SPD_BANK_NUM = 17,
118 PDC_DIMM_SPD_CAS_LATENCY = 18,
119 PDC_DIMM_SPD_ATTRIBUTE = 21,
120 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
121 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
122 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
123 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
124 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
125 PDC_CTL_STATUS = 0x08,
126 PDC_DIMM_WINDOW_CTLR = 0x0C,
127 PDC_TIME_CONTROL = 0x3C,
128 PDC_TIME_PERIOD = 0x40,
129 PDC_TIME_COUNTER = 0x44,
130 PDC_GENERAL_CTLR = 0x484,
131 PCI_PLL_INIT = 0x8A531824,
132 PCI_X_TCOUNT = 0xEE1E5CFF
133 };
134
135
136 struct pdc_port_priv {
137 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
138 u8 *pkt;
139 dma_addr_t pkt_dma;
140 };
141
142 struct pdc_host_priv {
143 unsigned int doing_hdma;
144 unsigned int hdma_prod;
145 unsigned int hdma_cons;
146 struct {
147 struct ata_queued_cmd *qc;
148 unsigned int seq;
149 unsigned long pkt_ofs;
150 } hdma[32];
151 };
152
153
154 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
155 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance);
156 static void pdc_eng_timeout(struct ata_port *ap);
157 static void pdc_20621_phy_reset (struct ata_port *ap);
158 static int pdc_port_start(struct ata_port *ap);
159 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
160 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
161 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
162 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
163 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
164 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
165 u32 device, u32 subaddr, u32 *pdata);
166 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
167 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
168 #ifdef ATA_VERBOSE_DEBUG
169 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
170 void *psource, u32 offset, u32 size);
171 #endif
172 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
173 void *psource, u32 offset, u32 size);
174 static void pdc20621_irq_clear(struct ata_port *ap);
175 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
176
177
178 static struct scsi_host_template pdc_sata_sht = {
179 .module = THIS_MODULE,
180 .name = DRV_NAME,
181 .ioctl = ata_scsi_ioctl,
182 .queuecommand = ata_scsi_queuecmd,
183 .can_queue = ATA_DEF_QUEUE,
184 .this_id = ATA_SHT_THIS_ID,
185 .sg_tablesize = LIBATA_MAX_PRD,
186 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
187 .emulated = ATA_SHT_EMULATED,
188 .use_clustering = ATA_SHT_USE_CLUSTERING,
189 .proc_name = DRV_NAME,
190 .dma_boundary = ATA_DMA_BOUNDARY,
191 .slave_configure = ata_scsi_slave_config,
192 .slave_destroy = ata_scsi_slave_destroy,
193 .bios_param = ata_std_bios_param,
194 };
195
196 static const struct ata_port_operations pdc_20621_ops = {
197 .port_disable = ata_port_disable,
198 .tf_load = pdc_tf_load_mmio,
199 .tf_read = ata_tf_read,
200 .check_status = ata_check_status,
201 .exec_command = pdc_exec_command_mmio,
202 .dev_select = ata_std_dev_select,
203 .phy_reset = pdc_20621_phy_reset,
204 .qc_prep = pdc20621_qc_prep,
205 .qc_issue = pdc20621_qc_issue_prot,
206 .data_xfer = ata_data_xfer,
207 .eng_timeout = pdc_eng_timeout,
208 .irq_handler = pdc20621_interrupt,
209 .irq_clear = pdc20621_irq_clear,
210 .irq_on = ata_irq_on,
211 .irq_ack = ata_irq_ack,
212 .port_start = pdc_port_start,
213 };
214
215 static const struct ata_port_info pdc_port_info[] = {
216 /* board_20621 */
217 {
218 .sht = &pdc_sata_sht,
219 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
220 ATA_FLAG_SRST | ATA_FLAG_MMIO |
221 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
222 .pio_mask = 0x1f, /* pio0-4 */
223 .mwdma_mask = 0x07, /* mwdma0-2 */
224 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
225 .port_ops = &pdc_20621_ops,
226 },
227
228 };
229
230 static const struct pci_device_id pdc_sata_pci_tbl[] = {
231 { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
232
233 { } /* terminate list */
234 };
235
236 static struct pci_driver pdc_sata_pci_driver = {
237 .name = DRV_NAME,
238 .id_table = pdc_sata_pci_tbl,
239 .probe = pdc_sata_init_one,
240 .remove = ata_pci_remove_one,
241 };
242
243
244 static int pdc_port_start(struct ata_port *ap)
245 {
246 struct device *dev = ap->host->dev;
247 struct pdc_port_priv *pp;
248 int rc;
249
250 rc = ata_port_start(ap);
251 if (rc)
252 return rc;
253
254 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
255 if (!pp)
256 return -ENOMEM;
257
258 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
259 if (!pp->pkt)
260 return -ENOMEM;
261
262 ap->private_data = pp;
263
264 return 0;
265 }
266
267 static void pdc_20621_phy_reset (struct ata_port *ap)
268 {
269 VPRINTK("ENTER\n");
270 ap->cbl = ATA_CBL_SATA;
271 ata_port_probe(ap);
272 ata_bus_reset(ap);
273 }
274
275 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
276 unsigned int portno,
277 unsigned int total_len)
278 {
279 u32 addr;
280 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
281 u32 *buf32 = (u32 *) buf;
282
283 /* output ATA packet S/G table */
284 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
285 (PDC_DIMM_DATA_STEP * portno);
286 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
287 buf32[dw] = cpu_to_le32(addr);
288 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
289
290 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
291 PDC_20621_DIMM_BASE +
292 (PDC_DIMM_WINDOW_STEP * portno) +
293 PDC_DIMM_APKT_PRD,
294 buf32[dw], buf32[dw + 1]);
295 }
296
297 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
298 unsigned int portno,
299 unsigned int total_len)
300 {
301 u32 addr;
302 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
303 u32 *buf32 = (u32 *) buf;
304
305 /* output Host DMA packet S/G table */
306 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
307 (PDC_DIMM_DATA_STEP * portno);
308
309 buf32[dw] = cpu_to_le32(addr);
310 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
311
312 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
313 PDC_20621_DIMM_BASE +
314 (PDC_DIMM_WINDOW_STEP * portno) +
315 PDC_DIMM_HPKT_PRD,
316 buf32[dw], buf32[dw + 1]);
317 }
318
319 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
320 unsigned int devno, u8 *buf,
321 unsigned int portno)
322 {
323 unsigned int i, dw;
324 u32 *buf32 = (u32 *) buf;
325 u8 dev_reg;
326
327 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
328 (PDC_DIMM_WINDOW_STEP * portno) +
329 PDC_DIMM_APKT_PRD;
330 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
331
332 i = PDC_DIMM_ATA_PKT;
333
334 /*
335 * Set up ATA packet
336 */
337 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
338 buf[i++] = PDC_PKT_READ;
339 else if (tf->protocol == ATA_PROT_NODATA)
340 buf[i++] = PDC_PKT_NODATA;
341 else
342 buf[i++] = 0;
343 buf[i++] = 0; /* reserved */
344 buf[i++] = portno + 1; /* seq. id */
345 buf[i++] = 0xff; /* delay seq. id */
346
347 /* dimm dma S/G, and next-pkt */
348 dw = i >> 2;
349 if (tf->protocol == ATA_PROT_NODATA)
350 buf32[dw] = 0;
351 else
352 buf32[dw] = cpu_to_le32(dimm_sg);
353 buf32[dw + 1] = 0;
354 i += 8;
355
356 if (devno == 0)
357 dev_reg = ATA_DEVICE_OBS;
358 else
359 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
360
361 /* select device */
362 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
363 buf[i++] = dev_reg;
364
365 /* device control register */
366 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
367 buf[i++] = tf->ctl;
368
369 return i;
370 }
371
372 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
373 unsigned int portno)
374 {
375 unsigned int dw;
376 u32 tmp, *buf32 = (u32 *) buf;
377
378 unsigned int host_sg = PDC_20621_DIMM_BASE +
379 (PDC_DIMM_WINDOW_STEP * portno) +
380 PDC_DIMM_HOST_PRD;
381 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
382 (PDC_DIMM_WINDOW_STEP * portno) +
383 PDC_DIMM_HPKT_PRD;
384 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
385 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
386
387 dw = PDC_DIMM_HOST_PKT >> 2;
388
389 /*
390 * Set up Host DMA packet
391 */
392 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
393 tmp = PDC_PKT_READ;
394 else
395 tmp = 0;
396 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
397 tmp |= (0xff << 24); /* delay seq. id */
398 buf32[dw + 0] = cpu_to_le32(tmp);
399 buf32[dw + 1] = cpu_to_le32(host_sg);
400 buf32[dw + 2] = cpu_to_le32(dimm_sg);
401 buf32[dw + 3] = 0;
402
403 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
404 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
405 PDC_DIMM_HOST_PKT,
406 buf32[dw + 0],
407 buf32[dw + 1],
408 buf32[dw + 2],
409 buf32[dw + 3]);
410 }
411
412 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
413 {
414 struct scatterlist *sg;
415 struct ata_port *ap = qc->ap;
416 struct pdc_port_priv *pp = ap->private_data;
417 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
418 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
419 unsigned int portno = ap->port_no;
420 unsigned int i, idx, total_len = 0, sgt_len;
421 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
422
423 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
424
425 VPRINTK("ata%u: ENTER\n", ap->id);
426
427 /* hard-code chip #0 */
428 mmio += PDC_CHIP0_OFS;
429
430 /*
431 * Build S/G table
432 */
433 idx = 0;
434 ata_for_each_sg(sg, qc) {
435 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
436 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
437 total_len += sg_dma_len(sg);
438 }
439 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
440 sgt_len = idx * 4;
441
442 /*
443 * Build ATA, host DMA packets
444 */
445 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
446 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
447
448 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
449 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
450
451 if (qc->tf.flags & ATA_TFLAG_LBA48)
452 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
453 else
454 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
455
456 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
457
458 /* copy three S/G tables and two packets to DIMM MMIO window */
459 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
460 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
461 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
462 PDC_DIMM_HOST_PRD,
463 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
464
465 /* force host FIFO dump */
466 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
467
468 readl(dimm_mmio); /* MMIO PCI posting flush */
469
470 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
471 }
472
473 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
474 {
475 struct ata_port *ap = qc->ap;
476 struct pdc_port_priv *pp = ap->private_data;
477 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
478 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
479 unsigned int portno = ap->port_no;
480 unsigned int i;
481
482 VPRINTK("ata%u: ENTER\n", ap->id);
483
484 /* hard-code chip #0 */
485 mmio += PDC_CHIP0_OFS;
486
487 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
488
489 if (qc->tf.flags & ATA_TFLAG_LBA48)
490 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
491 else
492 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
493
494 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
495
496 /* copy three S/G tables and two packets to DIMM MMIO window */
497 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
498 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
499
500 /* force host FIFO dump */
501 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
502
503 readl(dimm_mmio); /* MMIO PCI posting flush */
504
505 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
506 }
507
508 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
509 {
510 switch (qc->tf.protocol) {
511 case ATA_PROT_DMA:
512 pdc20621_dma_prep(qc);
513 break;
514 case ATA_PROT_NODATA:
515 pdc20621_nodata_prep(qc);
516 break;
517 default:
518 break;
519 }
520 }
521
522 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
523 unsigned int seq,
524 u32 pkt_ofs)
525 {
526 struct ata_port *ap = qc->ap;
527 struct ata_host *host = ap->host;
528 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
529
530 /* hard-code chip #0 */
531 mmio += PDC_CHIP0_OFS;
532
533 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
534 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
535
536 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
537 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
538 }
539
540 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
541 unsigned int seq,
542 u32 pkt_ofs)
543 {
544 struct ata_port *ap = qc->ap;
545 struct pdc_host_priv *pp = ap->host->private_data;
546 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
547
548 if (!pp->doing_hdma) {
549 __pdc20621_push_hdma(qc, seq, pkt_ofs);
550 pp->doing_hdma = 1;
551 return;
552 }
553
554 pp->hdma[idx].qc = qc;
555 pp->hdma[idx].seq = seq;
556 pp->hdma[idx].pkt_ofs = pkt_ofs;
557 pp->hdma_prod++;
558 }
559
560 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
561 {
562 struct ata_port *ap = qc->ap;
563 struct pdc_host_priv *pp = ap->host->private_data;
564 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
565
566 /* if nothing on queue, we're done */
567 if (pp->hdma_prod == pp->hdma_cons) {
568 pp->doing_hdma = 0;
569 return;
570 }
571
572 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
573 pp->hdma[idx].pkt_ofs);
574 pp->hdma_cons++;
575 }
576
577 #ifdef ATA_VERBOSE_DEBUG
578 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
579 {
580 struct ata_port *ap = qc->ap;
581 unsigned int port_no = ap->port_no;
582 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
583
584 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
585 dimm_mmio += PDC_DIMM_HOST_PKT;
586
587 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
588 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
589 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
590 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
591 }
592 #else
593 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
594 #endif /* ATA_VERBOSE_DEBUG */
595
596 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
597 {
598 struct ata_port *ap = qc->ap;
599 struct ata_host *host = ap->host;
600 unsigned int port_no = ap->port_no;
601 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
602 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
603 u8 seq = (u8) (port_no + 1);
604 unsigned int port_ofs;
605
606 /* hard-code chip #0 */
607 mmio += PDC_CHIP0_OFS;
608
609 VPRINTK("ata%u: ENTER\n", ap->id);
610
611 wmb(); /* flush PRD, pkt writes */
612
613 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
614
615 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
616 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
617 seq += 4;
618
619 pdc20621_dump_hdma(qc);
620 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
621 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
622 port_ofs + PDC_DIMM_HOST_PKT,
623 port_ofs + PDC_DIMM_HOST_PKT,
624 seq);
625 } else {
626 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
627 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
628
629 writel(port_ofs + PDC_DIMM_ATA_PKT,
630 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
631 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
632 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
633 port_ofs + PDC_DIMM_ATA_PKT,
634 port_ofs + PDC_DIMM_ATA_PKT,
635 seq);
636 }
637 }
638
639 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
640 {
641 switch (qc->tf.protocol) {
642 case ATA_PROT_DMA:
643 case ATA_PROT_NODATA:
644 pdc20621_packet_start(qc);
645 return 0;
646
647 case ATA_PROT_ATAPI_DMA:
648 BUG();
649 break;
650
651 default:
652 break;
653 }
654
655 return ata_qc_issue_prot(qc);
656 }
657
658 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
659 struct ata_queued_cmd *qc,
660 unsigned int doing_hdma,
661 void __iomem *mmio)
662 {
663 unsigned int port_no = ap->port_no;
664 unsigned int port_ofs =
665 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
666 u8 status;
667 unsigned int handled = 0;
668
669 VPRINTK("ENTER\n");
670
671 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
672 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
673
674 /* step two - DMA from DIMM to host */
675 if (doing_hdma) {
676 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
677 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
678 /* get drive status; clear intr; complete txn */
679 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
680 ata_qc_complete(qc);
681 pdc20621_pop_hdma(qc);
682 }
683
684 /* step one - exec ATA command */
685 else {
686 u8 seq = (u8) (port_no + 1 + 4);
687 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
688 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
689
690 /* submit hdma pkt */
691 pdc20621_dump_hdma(qc);
692 pdc20621_push_hdma(qc, seq,
693 port_ofs + PDC_DIMM_HOST_PKT);
694 }
695 handled = 1;
696
697 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
698
699 /* step one - DMA from host to DIMM */
700 if (doing_hdma) {
701 u8 seq = (u8) (port_no + 1);
702 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
703 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
704
705 /* submit ata pkt */
706 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
707 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
708 writel(port_ofs + PDC_DIMM_ATA_PKT,
709 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
710 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
711 }
712
713 /* step two - execute ATA command */
714 else {
715 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
716 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
717 /* get drive status; clear intr; complete txn */
718 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
719 ata_qc_complete(qc);
720 pdc20621_pop_hdma(qc);
721 }
722 handled = 1;
723
724 /* command completion, but no data xfer */
725 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
726
727 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
728 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
729 qc->err_mask |= ac_err_mask(status);
730 ata_qc_complete(qc);
731 handled = 1;
732
733 } else {
734 ap->stats.idle_irq++;
735 }
736
737 return handled;
738 }
739
740 static void pdc20621_irq_clear(struct ata_port *ap)
741 {
742 struct ata_host *host = ap->host;
743 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
744
745 mmio += PDC_CHIP0_OFS;
746
747 readl(mmio + PDC_20621_SEQMASK);
748 }
749
750 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
751 {
752 struct ata_host *host = dev_instance;
753 struct ata_port *ap;
754 u32 mask = 0;
755 unsigned int i, tmp, port_no;
756 unsigned int handled = 0;
757 void __iomem *mmio_base;
758
759 VPRINTK("ENTER\n");
760
761 if (!host || !host->iomap[PDC_MMIO_BAR]) {
762 VPRINTK("QUICK EXIT\n");
763 return IRQ_NONE;
764 }
765
766 mmio_base = host->iomap[PDC_MMIO_BAR];
767
768 /* reading should also clear interrupts */
769 mmio_base += PDC_CHIP0_OFS;
770 mask = readl(mmio_base + PDC_20621_SEQMASK);
771 VPRINTK("mask == 0x%x\n", mask);
772
773 if (mask == 0xffffffff) {
774 VPRINTK("QUICK EXIT 2\n");
775 return IRQ_NONE;
776 }
777 mask &= 0xffff; /* only 16 tags possible */
778 if (!mask) {
779 VPRINTK("QUICK EXIT 3\n");
780 return IRQ_NONE;
781 }
782
783 spin_lock(&host->lock);
784
785 for (i = 1; i < 9; i++) {
786 port_no = i - 1;
787 if (port_no > 3)
788 port_no -= 4;
789 if (port_no >= host->n_ports)
790 ap = NULL;
791 else
792 ap = host->ports[port_no];
793 tmp = mask & (1 << i);
794 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
795 if (tmp && ap &&
796 !(ap->flags & ATA_FLAG_DISABLED)) {
797 struct ata_queued_cmd *qc;
798
799 qc = ata_qc_from_tag(ap, ap->active_tag);
800 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
801 handled += pdc20621_host_intr(ap, qc, (i > 4),
802 mmio_base);
803 }
804 }
805
806 spin_unlock(&host->lock);
807
808 VPRINTK("mask == 0x%x\n", mask);
809
810 VPRINTK("EXIT\n");
811
812 return IRQ_RETVAL(handled);
813 }
814
815 static void pdc_eng_timeout(struct ata_port *ap)
816 {
817 u8 drv_stat;
818 struct ata_host *host = ap->host;
819 struct ata_queued_cmd *qc;
820 unsigned long flags;
821
822 DPRINTK("ENTER\n");
823
824 spin_lock_irqsave(&host->lock, flags);
825
826 qc = ata_qc_from_tag(ap, ap->active_tag);
827
828 switch (qc->tf.protocol) {
829 case ATA_PROT_DMA:
830 case ATA_PROT_NODATA:
831 ata_port_printk(ap, KERN_ERR, "command timeout\n");
832 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
833 break;
834
835 default:
836 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
837
838 ata_port_printk(ap, KERN_ERR,
839 "unknown timeout, cmd 0x%x stat 0x%x\n",
840 qc->tf.command, drv_stat);
841
842 qc->err_mask |= ac_err_mask(drv_stat);
843 break;
844 }
845
846 spin_unlock_irqrestore(&host->lock, flags);
847 ata_eh_qc_complete(qc);
848 DPRINTK("EXIT\n");
849 }
850
851 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
852 {
853 WARN_ON (tf->protocol == ATA_PROT_DMA ||
854 tf->protocol == ATA_PROT_NODATA);
855 ata_tf_load(ap, tf);
856 }
857
858
859 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
860 {
861 WARN_ON (tf->protocol == ATA_PROT_DMA ||
862 tf->protocol == ATA_PROT_NODATA);
863 ata_exec_command(ap, tf);
864 }
865
866
867 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
868 {
869 port->cmd_addr = base;
870 port->data_addr = base;
871 port->feature_addr =
872 port->error_addr = base + 0x4;
873 port->nsect_addr = base + 0x8;
874 port->lbal_addr = base + 0xc;
875 port->lbam_addr = base + 0x10;
876 port->lbah_addr = base + 0x14;
877 port->device_addr = base + 0x18;
878 port->command_addr =
879 port->status_addr = base + 0x1c;
880 port->altstatus_addr =
881 port->ctl_addr = base + 0x38;
882 }
883
884
885 #ifdef ATA_VERBOSE_DEBUG
886 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
887 u32 offset, u32 size)
888 {
889 u32 window_size;
890 u16 idx;
891 u8 page_mask;
892 long dist;
893 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
894 void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR];
895
896 /* hard-code chip #0 */
897 mmio += PDC_CHIP0_OFS;
898
899 page_mask = 0x00;
900 window_size = 0x2000 * 4; /* 32K byte uchar size */
901 idx = (u16) (offset / window_size);
902
903 writel(0x01, mmio + PDC_GENERAL_CTLR);
904 readl(mmio + PDC_GENERAL_CTLR);
905 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
906 readl(mmio + PDC_DIMM_WINDOW_CTLR);
907
908 offset -= (idx * window_size);
909 idx++;
910 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
911 (long) (window_size - offset);
912 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
913 dist);
914
915 psource += dist;
916 size -= dist;
917 for (; (long) size >= (long) window_size ;) {
918 writel(0x01, mmio + PDC_GENERAL_CTLR);
919 readl(mmio + PDC_GENERAL_CTLR);
920 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
921 readl(mmio + PDC_DIMM_WINDOW_CTLR);
922 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
923 window_size / 4);
924 psource += window_size;
925 size -= window_size;
926 idx ++;
927 }
928
929 if (size) {
930 writel(0x01, mmio + PDC_GENERAL_CTLR);
931 readl(mmio + PDC_GENERAL_CTLR);
932 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
933 readl(mmio + PDC_DIMM_WINDOW_CTLR);
934 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
935 size / 4);
936 }
937 }
938 #endif
939
940
941 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
942 u32 offset, u32 size)
943 {
944 u32 window_size;
945 u16 idx;
946 u8 page_mask;
947 long dist;
948 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
949 void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR];
950
951 /* hard-code chip #0 */
952 mmio += PDC_CHIP0_OFS;
953
954 page_mask = 0x00;
955 window_size = 0x2000 * 4; /* 32K byte uchar size */
956 idx = (u16) (offset / window_size);
957
958 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
959 readl(mmio + PDC_DIMM_WINDOW_CTLR);
960 offset -= (idx * window_size);
961 idx++;
962 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
963 (long) (window_size - offset);
964 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
965 writel(0x01, mmio + PDC_GENERAL_CTLR);
966 readl(mmio + PDC_GENERAL_CTLR);
967
968 psource += dist;
969 size -= dist;
970 for (; (long) size >= (long) window_size ;) {
971 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
972 readl(mmio + PDC_DIMM_WINDOW_CTLR);
973 memcpy_toio(dimm_mmio, psource, window_size / 4);
974 writel(0x01, mmio + PDC_GENERAL_CTLR);
975 readl(mmio + PDC_GENERAL_CTLR);
976 psource += window_size;
977 size -= window_size;
978 idx ++;
979 }
980
981 if (size) {
982 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
983 readl(mmio + PDC_DIMM_WINDOW_CTLR);
984 memcpy_toio(dimm_mmio, psource, size / 4);
985 writel(0x01, mmio + PDC_GENERAL_CTLR);
986 readl(mmio + PDC_GENERAL_CTLR);
987 }
988 }
989
990
991 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
992 u32 subaddr, u32 *pdata)
993 {
994 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
995 u32 i2creg = 0;
996 u32 status;
997 u32 count =0;
998
999 /* hard-code chip #0 */
1000 mmio += PDC_CHIP0_OFS;
1001
1002 i2creg |= device << 24;
1003 i2creg |= subaddr << 16;
1004
1005 /* Set the device and subaddress */
1006 writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1007 readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1008
1009 /* Write Control to perform read operation, mask int */
1010 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1011 mmio + PDC_I2C_CONTROL_OFFSET);
1012
1013 for (count = 0; count <= 1000; count ++) {
1014 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1015 if (status & PDC_I2C_COMPLETE) {
1016 status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1017 break;
1018 } else if (count == 1000)
1019 return 0;
1020 }
1021
1022 *pdata = (status >> 8) & 0x000000ff;
1023 return 1;
1024 }
1025
1026
1027 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1028 {
1029 u32 data=0 ;
1030 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1031 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1032 if (data == 100)
1033 return 100;
1034 } else
1035 return 0;
1036
1037 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1038 if(data <= 0x75)
1039 return 133;
1040 } else
1041 return 0;
1042
1043 return 0;
1044 }
1045
1046
1047 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1048 {
1049 u32 spd0[50];
1050 u32 data = 0;
1051 int size, i;
1052 u8 bdimmsize;
1053 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
1054 static const struct {
1055 unsigned int reg;
1056 unsigned int ofs;
1057 } pdc_i2c_read_data [] = {
1058 { PDC_DIMM_SPD_TYPE, 11 },
1059 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1060 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1061 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1062 { PDC_DIMM_SPD_ROW_NUM, 3 },
1063 { PDC_DIMM_SPD_BANK_NUM, 17 },
1064 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1065 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1066 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1067 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1068 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1069 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1070 };
1071
1072 /* hard-code chip #0 */
1073 mmio += PDC_CHIP0_OFS;
1074
1075 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1076 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1077 pdc_i2c_read_data[i].reg,
1078 &spd0[pdc_i2c_read_data[i].ofs]);
1079
1080 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1081 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1082 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1083 data |= (((((spd0[29] > spd0[28])
1084 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1085 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1086
1087 if (spd0[18] & 0x08)
1088 data |= ((0x03) << 14);
1089 else if (spd0[18] & 0x04)
1090 data |= ((0x02) << 14);
1091 else if (spd0[18] & 0x01)
1092 data |= ((0x01) << 14);
1093 else
1094 data |= (0 << 14);
1095
1096 /*
1097 Calculate the size of bDIMMSize (power of 2) and
1098 merge the DIMM size by program start/end address.
1099 */
1100
1101 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1102 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1103 data |= (((size / 16) - 1) << 16);
1104 data |= (0 << 23);
1105 data |= 8;
1106 writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1107 readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1108 return size;
1109 }
1110
1111
1112 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1113 {
1114 u32 data, spd0;
1115 int error, i;
1116 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
1117
1118 /* hard-code chip #0 */
1119 mmio += PDC_CHIP0_OFS;
1120
1121 /*
1122 Set To Default : DIMM Module Global Control Register (0x022259F1)
1123 DIMM Arbitration Disable (bit 20)
1124 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1125 Refresh Enable (bit 17)
1126 */
1127
1128 data = 0x022259F1;
1129 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1130 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1131
1132 /* Turn on for ECC */
1133 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1134 PDC_DIMM_SPD_TYPE, &spd0);
1135 if (spd0 == 0x02) {
1136 data |= (0x01 << 16);
1137 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1138 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1139 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1140 }
1141
1142 /* DIMM Initialization Select/Enable (bit 18/19) */
1143 data &= (~(1<<18));
1144 data |= (1<<19);
1145 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1146
1147 error = 1;
1148 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1149 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1150 if (!(data & (1<<19))) {
1151 error = 0;
1152 break;
1153 }
1154 msleep(i*100);
1155 }
1156 return error;
1157 }
1158
1159
1160 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1161 {
1162 int speed, size, length;
1163 u32 addr,spd0,pci_status;
1164 u32 tmp=0;
1165 u32 time_period=0;
1166 u32 tcount=0;
1167 u32 ticks=0;
1168 u32 clock=0;
1169 u32 fparam=0;
1170 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
1171
1172 /* hard-code chip #0 */
1173 mmio += PDC_CHIP0_OFS;
1174
1175 /* Initialize PLL based upon PCI Bus Frequency */
1176
1177 /* Initialize Time Period Register */
1178 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1179 time_period = readl(mmio + PDC_TIME_PERIOD);
1180 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1181
1182 /* Enable timer */
1183 writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1184 readl(mmio + PDC_TIME_CONTROL);
1185
1186 /* Wait 3 seconds */
1187 msleep(3000);
1188
1189 /*
1190 When timer is enabled, counter is decreased every internal
1191 clock cycle.
1192 */
1193
1194 tcount = readl(mmio + PDC_TIME_COUNTER);
1195 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1196
1197 /*
1198 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1199 register should be >= (0xffffffff - 3x10^8).
1200 */
1201 if(tcount >= PCI_X_TCOUNT) {
1202 ticks = (time_period - tcount);
1203 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1204
1205 clock = (ticks / 300000);
1206 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1207
1208 clock = (clock * 33);
1209 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1210
1211 /* PLL F Param (bit 22:16) */
1212 fparam = (1400000 / clock) - 2;
1213 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1214
1215 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1216 pci_status = (0x8a001824 | (fparam << 16));
1217 } else
1218 pci_status = PCI_PLL_INIT;
1219
1220 /* Initialize PLL. */
1221 VPRINTK("pci_status: 0x%x\n", pci_status);
1222 writel(pci_status, mmio + PDC_CTL_STATUS);
1223 readl(mmio + PDC_CTL_STATUS);
1224
1225 /*
1226 Read SPD of DIMM by I2C interface,
1227 and program the DIMM Module Controller.
1228 */
1229 if (!(speed = pdc20621_detect_dimm(pe))) {
1230 printk(KERN_ERR "Detect Local DIMM Fail\n");
1231 return 1; /* DIMM error */
1232 }
1233 VPRINTK("Local DIMM Speed = %d\n", speed);
1234
1235 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1236 size = pdc20621_prog_dimm0(pe);
1237 VPRINTK("Local DIMM Size = %dMB\n",size);
1238
1239 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1240 if (pdc20621_prog_dimm_global(pe)) {
1241 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1242 return 1;
1243 }
1244
1245 #ifdef ATA_VERBOSE_DEBUG
1246 {
1247 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1248 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1249 '1','.','1','0',
1250 '9','8','0','3','1','6','1','2',0,0};
1251 u8 test_parttern2[40] = {0};
1252
1253 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1254 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1255
1256 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1257 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1258 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1259 test_parttern2[1], &(test_parttern2[2]));
1260 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1261 40);
1262 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1263 test_parttern2[1], &(test_parttern2[2]));
1264
1265 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1266 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1267 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1268 test_parttern2[1], &(test_parttern2[2]));
1269 }
1270 #endif
1271
1272 /* ECC initiliazation. */
1273
1274 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1275 PDC_DIMM_SPD_TYPE, &spd0);
1276 if (spd0 == 0x02) {
1277 VPRINTK("Start ECC initialization\n");
1278 addr = 0;
1279 length = size * 1024 * 1024;
1280 while (addr < length) {
1281 pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1282 sizeof(u32));
1283 addr += sizeof(u32);
1284 }
1285 VPRINTK("Finish ECC initialization\n");
1286 }
1287 return 0;
1288 }
1289
1290
1291 static void pdc_20621_init(struct ata_probe_ent *pe)
1292 {
1293 u32 tmp;
1294 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
1295
1296 /* hard-code chip #0 */
1297 mmio += PDC_CHIP0_OFS;
1298
1299 /*
1300 * Select page 0x40 for our 32k DIMM window
1301 */
1302 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1303 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1304 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1305
1306 /*
1307 * Reset Host DMA
1308 */
1309 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1310 tmp |= PDC_RESET;
1311 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1312 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1313
1314 udelay(10);
1315
1316 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1317 tmp &= ~PDC_RESET;
1318 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1319 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1320 }
1321
1322 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1323 {
1324 static int printed_version;
1325 struct ata_probe_ent *probe_ent;
1326 void __iomem *base;
1327 struct pdc_host_priv *hpriv;
1328 unsigned int board_idx = (unsigned int) ent->driver_data;
1329 int rc;
1330
1331 if (!printed_version++)
1332 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1333
1334 rc = pcim_enable_device(pdev);
1335 if (rc)
1336 return rc;
1337
1338 rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1339 DRV_NAME);
1340 if (rc == -EBUSY)
1341 pcim_pin_device(pdev);
1342 if (rc)
1343 return rc;
1344
1345 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1346 if (rc)
1347 return rc;
1348 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1349 if (rc)
1350 return rc;
1351
1352 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
1353 if (probe_ent == NULL)
1354 return -ENOMEM;
1355
1356 probe_ent->dev = pci_dev_to_dev(pdev);
1357 INIT_LIST_HEAD(&probe_ent->node);
1358
1359 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1360 if (!hpriv)
1361 return -ENOMEM;
1362
1363 probe_ent->sht = pdc_port_info[board_idx].sht;
1364 probe_ent->port_flags = pdc_port_info[board_idx].flags;
1365 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1366 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
1367 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1368 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1369
1370 probe_ent->irq = pdev->irq;
1371 probe_ent->irq_flags = IRQF_SHARED;
1372 probe_ent->iomap = pcim_iomap_table(pdev);
1373
1374 probe_ent->private_data = hpriv;
1375 base = probe_ent->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1376
1377 probe_ent->n_ports = 4;
1378 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1379 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1380 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1381 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1382
1383 pci_set_master(pdev);
1384
1385 /* initialize adapter */
1386 /* initialize local dimm */
1387 if (pdc20621_dimm_init(probe_ent))
1388 return -ENOMEM;
1389 pdc_20621_init(probe_ent);
1390
1391 if (!ata_device_add(probe_ent))
1392 return -ENODEV;
1393
1394 devm_kfree(&pdev->dev, probe_ent);
1395 return 0;
1396 }
1397
1398
1399 static int __init pdc_sata_init(void)
1400 {
1401 return pci_register_driver(&pdc_sata_pci_driver);
1402 }
1403
1404
1405 static void __exit pdc_sata_exit(void)
1406 {
1407 pci_unregister_driver(&pdc_sata_pci_driver);
1408 }
1409
1410
1411 MODULE_AUTHOR("Jeff Garzik");
1412 MODULE_DESCRIPTION("Promise SATA low-level driver");
1413 MODULE_LICENSE("GPL");
1414 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1415 MODULE_VERSION(DRV_VERSION);
1416
1417 module_init(pdc_sata_init);
1418 module_exit(pdc_sata_exit);
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