2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * Gianfar: AKA Lambda Draconis, "Dragon"
29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
36 * last descriptor of the ring.
38 * When a packet is received, the RXF bit in the
39 * IEVENT register is set, triggering an interrupt when the
40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
43 * of frames or amount of time have passed). In NAPI, the
44 * interrupt handler will signal there is work to be done, and
45 * exit. This method will start at the last known empty
46 * descriptor, and process every subsequent descriptor until there
47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
65 #include <linux/kernel.h>
66 #include <linux/string.h>
67 #include <linux/errno.h>
68 #include <linux/unistd.h>
69 #include <linux/slab.h>
70 #include <linux/interrupt.h>
71 #include <linux/init.h>
72 #include <linux/delay.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_vlan.h>
77 #include <linux/spinlock.h>
79 #include <linux/of_mdio.h>
80 #include <linux/of_platform.h>
82 #include <linux/tcp.h>
83 #include <linux/udp.h>
88 #include <asm/uaccess.h>
89 #include <linux/module.h>
90 #include <linux/dma-mapping.h>
91 #include <linux/crc32.h>
92 #include <linux/mii.h>
93 #include <linux/phy.h>
94 #include <linux/phy_fixed.h>
98 #include "fsl_pq_mdio.h"
100 #define TX_TIMEOUT (1*HZ)
101 #undef BRIEF_GFAR_ERRORS
102 #undef VERBOSE_GFAR_ERRORS
104 const char gfar_driver_name
[] = "Gianfar Ethernet";
105 const char gfar_driver_version
[] = "1.3";
107 static int gfar_enet_open(struct net_device
*dev
);
108 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
109 static void gfar_reset_task(struct work_struct
*work
);
110 static void gfar_timeout(struct net_device
*dev
);
111 static int gfar_close(struct net_device
*dev
);
112 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
113 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
114 struct sk_buff
*skb
);
115 static int gfar_set_mac_address(struct net_device
*dev
);
116 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
117 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
118 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
119 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
120 static void adjust_link(struct net_device
*dev
);
121 static void init_registers(struct net_device
*dev
);
122 static int init_phy(struct net_device
*dev
);
123 static int gfar_probe(struct of_device
*ofdev
,
124 const struct of_device_id
*match
);
125 static int gfar_remove(struct of_device
*ofdev
);
126 static void free_skb_resources(struct gfar_private
*priv
);
127 static void gfar_set_multi(struct net_device
*dev
);
128 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
129 static void gfar_configure_serdes(struct net_device
*dev
);
130 static int gfar_poll(struct napi_struct
*napi
, int budget
);
131 #ifdef CONFIG_NET_POLL_CONTROLLER
132 static void gfar_netpoll(struct net_device
*dev
);
134 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
);
135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
);
136 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
138 static void gfar_vlan_rx_register(struct net_device
*netdev
,
139 struct vlan_group
*grp
);
140 void gfar_halt(struct net_device
*dev
);
141 static void gfar_halt_nodisable(struct net_device
*dev
);
142 void gfar_start(struct net_device
*dev
);
143 static void gfar_clear_exact_match(struct net_device
*dev
);
144 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
145 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
146 u16
gfar_select_queue(struct net_device
*dev
, struct sk_buff
*skb
);
148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150 MODULE_LICENSE("GPL");
152 static void gfar_init_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
159 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
160 if (bdp
== rx_queue
->rx_bd_base
+ rx_queue
->rx_ring_size
- 1)
161 lstatus
|= BD_LFLAG(RXBD_WRAP
);
165 bdp
->lstatus
= lstatus
;
168 static int gfar_init_bds(struct net_device
*ndev
)
170 struct gfar_private
*priv
= netdev_priv(ndev
);
171 struct gfar_priv_tx_q
*tx_queue
= NULL
;
172 struct gfar_priv_rx_q
*rx_queue
= NULL
;
177 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
178 tx_queue
= priv
->tx_queue
[i
];
179 /* Initialize some variables in our dev structure */
180 tx_queue
->num_txbdfree
= tx_queue
->tx_ring_size
;
181 tx_queue
->dirty_tx
= tx_queue
->tx_bd_base
;
182 tx_queue
->cur_tx
= tx_queue
->tx_bd_base
;
183 tx_queue
->skb_curtx
= 0;
184 tx_queue
->skb_dirtytx
= 0;
186 /* Initialize Transmit Descriptor Ring */
187 txbdp
= tx_queue
->tx_bd_base
;
188 for (j
= 0; j
< tx_queue
->tx_ring_size
; j
++) {
194 /* Set the last descriptor in the ring to indicate wrap */
196 txbdp
->status
|= TXBD_WRAP
;
199 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
200 rx_queue
= priv
->rx_queue
[i
];
201 rx_queue
->cur_rx
= rx_queue
->rx_bd_base
;
202 rx_queue
->skb_currx
= 0;
203 rxbdp
= rx_queue
->rx_bd_base
;
205 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++) {
206 struct sk_buff
*skb
= rx_queue
->rx_skbuff
[j
];
209 gfar_init_rxbdp(rx_queue
, rxbdp
,
212 skb
= gfar_new_skb(ndev
);
214 pr_err("%s: Can't allocate RX buffers\n",
216 goto err_rxalloc_fail
;
218 rx_queue
->rx_skbuff
[j
] = skb
;
220 gfar_new_rxbdp(rx_queue
, rxbdp
, skb
);
231 free_skb_resources(priv
);
235 static int gfar_alloc_skb_resources(struct net_device
*ndev
)
240 struct gfar_private
*priv
= netdev_priv(ndev
);
241 struct device
*dev
= &priv
->ofdev
->dev
;
242 struct gfar_priv_tx_q
*tx_queue
= NULL
;
243 struct gfar_priv_rx_q
*rx_queue
= NULL
;
245 priv
->total_tx_ring_size
= 0;
246 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
247 priv
->total_tx_ring_size
+= priv
->tx_queue
[i
]->tx_ring_size
;
249 priv
->total_rx_ring_size
= 0;
250 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
251 priv
->total_rx_ring_size
+= priv
->rx_queue
[i
]->rx_ring_size
;
253 /* Allocate memory for the buffer descriptors */
254 vaddr
= dma_alloc_coherent(dev
,
255 sizeof(struct txbd8
) * priv
->total_tx_ring_size
+
256 sizeof(struct rxbd8
) * priv
->total_rx_ring_size
,
259 if (netif_msg_ifup(priv
))
260 pr_err("%s: Could not allocate buffer descriptors!\n",
265 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
266 tx_queue
= priv
->tx_queue
[i
];
267 tx_queue
->tx_bd_base
= (struct txbd8
*) vaddr
;
268 tx_queue
->tx_bd_dma_base
= addr
;
269 tx_queue
->dev
= ndev
;
270 /* enet DMA only understands physical addresses */
271 addr
+= sizeof(struct txbd8
) *tx_queue
->tx_ring_size
;
272 vaddr
+= sizeof(struct txbd8
) *tx_queue
->tx_ring_size
;
275 /* Start the rx descriptor ring where the tx ring leaves off */
276 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
277 rx_queue
= priv
->rx_queue
[i
];
278 rx_queue
->rx_bd_base
= (struct rxbd8
*) vaddr
;
279 rx_queue
->rx_bd_dma_base
= addr
;
280 rx_queue
->dev
= ndev
;
281 addr
+= sizeof (struct rxbd8
) * rx_queue
->rx_ring_size
;
282 vaddr
+= sizeof (struct rxbd8
) * rx_queue
->rx_ring_size
;
285 /* Setup the skbuff rings */
286 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
287 tx_queue
= priv
->tx_queue
[i
];
288 tx_queue
->tx_skbuff
= kmalloc(sizeof(*tx_queue
->tx_skbuff
) *
289 tx_queue
->tx_ring_size
, GFP_KERNEL
);
290 if (!tx_queue
->tx_skbuff
) {
291 if (netif_msg_ifup(priv
))
292 pr_err("%s: Could not allocate tx_skbuff\n",
297 for (k
= 0; k
< tx_queue
->tx_ring_size
; k
++)
298 tx_queue
->tx_skbuff
[k
] = NULL
;
301 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
302 rx_queue
= priv
->rx_queue
[i
];
303 rx_queue
->rx_skbuff
= kmalloc(sizeof(*rx_queue
->rx_skbuff
) *
304 rx_queue
->rx_ring_size
, GFP_KERNEL
);
306 if (!rx_queue
->rx_skbuff
) {
307 if (netif_msg_ifup(priv
))
308 pr_err("%s: Could not allocate rx_skbuff\n",
313 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++)
314 rx_queue
->rx_skbuff
[j
] = NULL
;
317 if (gfar_init_bds(ndev
))
323 free_skb_resources(priv
);
327 static void gfar_init_tx_rx_base(struct gfar_private
*priv
)
329 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
333 baddr
= ®s
->tbase0
;
334 for(i
= 0; i
< priv
->num_tx_queues
; i
++) {
335 gfar_write(baddr
, priv
->tx_queue
[i
]->tx_bd_dma_base
);
339 baddr
= ®s
->rbase0
;
340 for(i
= 0; i
< priv
->num_rx_queues
; i
++) {
341 gfar_write(baddr
, priv
->rx_queue
[i
]->rx_bd_dma_base
);
346 static void gfar_init_mac(struct net_device
*ndev
)
348 struct gfar_private
*priv
= netdev_priv(ndev
);
349 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
354 /* write the tx/rx base registers */
355 gfar_init_tx_rx_base(priv
);
357 /* Configure the coalescing support */
358 gfar_configure_coalescing(priv
, 0xFF, 0xFF);
360 if (priv
->rx_filer_enable
)
361 rctrl
|= RCTRL_FILREN
;
363 if (priv
->rx_csum_enable
)
364 rctrl
|= RCTRL_CHECKSUMMING
;
366 if (priv
->extended_hash
) {
367 rctrl
|= RCTRL_EXTHASH
;
369 gfar_clear_exact_match(ndev
);
374 rctrl
&= ~RCTRL_PAL_MASK
;
375 rctrl
|= RCTRL_PADDING(priv
->padding
);
378 /* keep vlan related bits if it's enabled */
380 rctrl
|= RCTRL_VLEX
| RCTRL_PRSDEP_INIT
;
381 tctrl
|= TCTRL_VLINS
;
384 /* Init rctrl based on our settings */
385 gfar_write(®s
->rctrl
, rctrl
);
387 if (ndev
->features
& NETIF_F_IP_CSUM
)
388 tctrl
|= TCTRL_INIT_CSUM
;
390 tctrl
|= TCTRL_TXSCHED_PRIO
;
392 gfar_write(®s
->tctrl
, tctrl
);
394 /* Set the extraction length and index */
395 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
396 ATTRELI_EI(priv
->rx_stash_index
);
398 gfar_write(®s
->attreli
, attrs
);
400 /* Start with defaults, and add stashing or locking
401 * depending on the approprate variables */
402 attrs
= ATTR_INIT_SETTINGS
;
404 if (priv
->bd_stash_en
)
405 attrs
|= ATTR_BDSTASH
;
407 if (priv
->rx_stash_size
!= 0)
408 attrs
|= ATTR_BUFSTASH
;
410 gfar_write(®s
->attr
, attrs
);
412 gfar_write(®s
->fifo_tx_thr
, priv
->fifo_threshold
);
413 gfar_write(®s
->fifo_tx_starve
, priv
->fifo_starve
);
414 gfar_write(®s
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
417 static const struct net_device_ops gfar_netdev_ops
= {
418 .ndo_open
= gfar_enet_open
,
419 .ndo_start_xmit
= gfar_start_xmit
,
420 .ndo_stop
= gfar_close
,
421 .ndo_change_mtu
= gfar_change_mtu
,
422 .ndo_set_multicast_list
= gfar_set_multi
,
423 .ndo_tx_timeout
= gfar_timeout
,
424 .ndo_do_ioctl
= gfar_ioctl
,
425 .ndo_select_queue
= gfar_select_queue
,
426 .ndo_vlan_rx_register
= gfar_vlan_rx_register
,
427 .ndo_set_mac_address
= eth_mac_addr
,
428 .ndo_validate_addr
= eth_validate_addr
,
429 #ifdef CONFIG_NET_POLL_CONTROLLER
430 .ndo_poll_controller
= gfar_netpoll
,
434 unsigned int ftp_rqfpr
[MAX_FILER_IDX
+ 1];
435 unsigned int ftp_rqfcr
[MAX_FILER_IDX
+ 1];
437 void lock_rx_qs(struct gfar_private
*priv
)
441 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
442 spin_lock(&priv
->rx_queue
[i
]->rxlock
);
445 void lock_tx_qs(struct gfar_private
*priv
)
449 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
450 spin_lock(&priv
->tx_queue
[i
]->txlock
);
453 void unlock_rx_qs(struct gfar_private
*priv
)
457 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
458 spin_unlock(&priv
->rx_queue
[i
]->rxlock
);
461 void unlock_tx_qs(struct gfar_private
*priv
)
465 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
466 spin_unlock(&priv
->tx_queue
[i
]->txlock
);
469 /* Returns 1 if incoming frames use an FCB */
470 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
472 return priv
->vlgrp
|| priv
->rx_csum_enable
;
475 u16
gfar_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
477 return skb_get_queue_mapping(skb
);
479 static void free_tx_pointers(struct gfar_private
*priv
)
483 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
484 kfree(priv
->tx_queue
[i
]);
487 static void free_rx_pointers(struct gfar_private
*priv
)
491 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
492 kfree(priv
->rx_queue
[i
]);
495 static void unmap_group_regs(struct gfar_private
*priv
)
499 for (i
= 0; i
< MAXGROUPS
; i
++)
500 if (priv
->gfargrp
[i
].regs
)
501 iounmap(priv
->gfargrp
[i
].regs
);
504 static void disable_napi(struct gfar_private
*priv
)
508 for (i
= 0; i
< priv
->num_grps
; i
++)
509 napi_disable(&priv
->gfargrp
[i
].napi
);
512 static void enable_napi(struct gfar_private
*priv
)
516 for (i
= 0; i
< priv
->num_grps
; i
++)
517 napi_enable(&priv
->gfargrp
[i
].napi
);
520 static int gfar_parse_group(struct device_node
*np
,
521 struct gfar_private
*priv
, const char *model
)
526 addr
= of_translate_address(np
,
527 of_get_address(np
, 0, &size
, NULL
));
528 priv
->gfargrp
[priv
->num_grps
].regs
= ioremap(addr
, size
);
530 if (!priv
->gfargrp
[priv
->num_grps
].regs
)
533 priv
->gfargrp
[priv
->num_grps
].interruptTransmit
=
534 irq_of_parse_and_map(np
, 0);
536 /* If we aren't the FEC we have multiple interrupts */
537 if (model
&& strcasecmp(model
, "FEC")) {
538 priv
->gfargrp
[priv
->num_grps
].interruptReceive
=
539 irq_of_parse_and_map(np
, 1);
540 priv
->gfargrp
[priv
->num_grps
].interruptError
=
541 irq_of_parse_and_map(np
,2);
542 if (priv
->gfargrp
[priv
->num_grps
].interruptTransmit
< 0 ||
543 priv
->gfargrp
[priv
->num_grps
].interruptReceive
< 0 ||
544 priv
->gfargrp
[priv
->num_grps
].interruptError
< 0) {
549 priv
->gfargrp
[priv
->num_grps
].grp_id
= priv
->num_grps
;
550 priv
->gfargrp
[priv
->num_grps
].priv
= priv
;
551 spin_lock_init(&priv
->gfargrp
[priv
->num_grps
].grplock
);
552 if(priv
->mode
== MQ_MG_MODE
) {
553 queue_mask
= (u32
*)of_get_property(np
,
554 "fsl,rx-bit-map", NULL
);
555 priv
->gfargrp
[priv
->num_grps
].rx_bit_map
=
556 queue_mask
? *queue_mask
:(DEFAULT_MAPPING
>> priv
->num_grps
);
557 queue_mask
= (u32
*)of_get_property(np
,
558 "fsl,tx-bit-map", NULL
);
559 priv
->gfargrp
[priv
->num_grps
].tx_bit_map
=
560 queue_mask
? *queue_mask
: (DEFAULT_MAPPING
>> priv
->num_grps
);
562 priv
->gfargrp
[priv
->num_grps
].rx_bit_map
= 0xFF;
563 priv
->gfargrp
[priv
->num_grps
].tx_bit_map
= 0xFF;
570 static int gfar_of_init(struct of_device
*ofdev
, struct net_device
**pdev
)
574 const void *mac_addr
;
576 struct net_device
*dev
= NULL
;
577 struct gfar_private
*priv
= NULL
;
578 struct device_node
*np
= ofdev
->node
;
579 struct device_node
*child
= NULL
;
581 const u32
*stash_len
;
582 const u32
*stash_idx
;
583 unsigned int num_tx_qs
, num_rx_qs
;
584 u32
*tx_queues
, *rx_queues
;
586 if (!np
|| !of_device_is_available(np
))
589 /* parse the num of tx and rx queues */
590 tx_queues
= (u32
*)of_get_property(np
, "fsl,num_tx_queues", NULL
);
591 num_tx_qs
= tx_queues
? *tx_queues
: 1;
593 if (num_tx_qs
> MAX_TX_QS
) {
594 printk(KERN_ERR
"num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
595 num_tx_qs
, MAX_TX_QS
);
596 printk(KERN_ERR
"Cannot do alloc_etherdev, aborting\n");
600 rx_queues
= (u32
*)of_get_property(np
, "fsl,num_rx_queues", NULL
);
601 num_rx_qs
= rx_queues
? *rx_queues
: 1;
603 if (num_rx_qs
> MAX_RX_QS
) {
604 printk(KERN_ERR
"num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
605 num_tx_qs
, MAX_TX_QS
);
606 printk(KERN_ERR
"Cannot do alloc_etherdev, aborting\n");
610 *pdev
= alloc_etherdev_mq(sizeof(*priv
), num_tx_qs
);
615 priv
= netdev_priv(dev
);
616 priv
->node
= ofdev
->node
;
619 dev
->num_tx_queues
= num_tx_qs
;
620 dev
->real_num_tx_queues
= num_tx_qs
;
621 priv
->num_tx_queues
= num_tx_qs
;
622 priv
->num_rx_queues
= num_rx_qs
;
623 priv
->num_grps
= 0x0;
625 model
= of_get_property(np
, "model", NULL
);
627 for (i
= 0; i
< MAXGROUPS
; i
++)
628 priv
->gfargrp
[i
].regs
= NULL
;
630 /* Parse and initialize group specific information */
631 if (of_device_is_compatible(np
, "fsl,etsec2")) {
632 priv
->mode
= MQ_MG_MODE
;
633 for_each_child_of_node(np
, child
) {
634 err
= gfar_parse_group(child
, priv
, model
);
639 priv
->mode
= SQ_SG_MODE
;
640 err
= gfar_parse_group(np
, priv
, model
);
645 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
646 priv
->tx_queue
[i
] = NULL
;
647 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
648 priv
->rx_queue
[i
] = NULL
;
650 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
651 priv
->tx_queue
[i
] = (struct gfar_priv_tx_q
*)kmalloc(
652 sizeof (struct gfar_priv_tx_q
), GFP_KERNEL
);
653 if (!priv
->tx_queue
[i
]) {
655 goto tx_alloc_failed
;
657 priv
->tx_queue
[i
]->tx_skbuff
= NULL
;
658 priv
->tx_queue
[i
]->qindex
= i
;
659 priv
->tx_queue
[i
]->dev
= dev
;
660 spin_lock_init(&(priv
->tx_queue
[i
]->txlock
));
663 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
664 priv
->rx_queue
[i
] = (struct gfar_priv_rx_q
*)kmalloc(
665 sizeof (struct gfar_priv_rx_q
), GFP_KERNEL
);
666 if (!priv
->rx_queue
[i
]) {
668 goto rx_alloc_failed
;
670 priv
->rx_queue
[i
]->rx_skbuff
= NULL
;
671 priv
->rx_queue
[i
]->qindex
= i
;
672 priv
->rx_queue
[i
]->dev
= dev
;
673 spin_lock_init(&(priv
->rx_queue
[i
]->rxlock
));
677 stash
= of_get_property(np
, "bd-stash", NULL
);
680 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BD_STASHING
;
681 priv
->bd_stash_en
= 1;
684 stash_len
= of_get_property(np
, "rx-stash-len", NULL
);
687 priv
->rx_stash_size
= *stash_len
;
689 stash_idx
= of_get_property(np
, "rx-stash-idx", NULL
);
692 priv
->rx_stash_index
= *stash_idx
;
694 if (stash_len
|| stash_idx
)
695 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BUF_STASHING
;
697 mac_addr
= of_get_mac_address(np
);
699 memcpy(dev
->dev_addr
, mac_addr
, MAC_ADDR_LEN
);
701 if (model
&& !strcasecmp(model
, "TSEC"))
703 FSL_GIANFAR_DEV_HAS_GIGABIT
|
704 FSL_GIANFAR_DEV_HAS_COALESCE
|
705 FSL_GIANFAR_DEV_HAS_RMON
|
706 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
707 if (model
&& !strcasecmp(model
, "eTSEC"))
709 FSL_GIANFAR_DEV_HAS_GIGABIT
|
710 FSL_GIANFAR_DEV_HAS_COALESCE
|
711 FSL_GIANFAR_DEV_HAS_RMON
|
712 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
713 FSL_GIANFAR_DEV_HAS_PADDING
|
714 FSL_GIANFAR_DEV_HAS_CSUM
|
715 FSL_GIANFAR_DEV_HAS_VLAN
|
716 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
717 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
;
719 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
721 /* We only care about rgmii-id. The rest are autodetected */
722 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
723 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
725 priv
->interface
= PHY_INTERFACE_MODE_MII
;
727 if (of_get_property(np
, "fsl,magic-packet", NULL
))
728 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
730 priv
->phy_node
= of_parse_phandle(np
, "phy-handle", 0);
732 /* Find the TBI PHY. If it's not there, we don't support SGMII */
733 priv
->tbi_node
= of_parse_phandle(np
, "tbi-handle", 0);
738 free_rx_pointers(priv
);
740 free_tx_pointers(priv
);
742 unmap_group_regs(priv
);
747 /* Ioctl MII Interface */
748 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
750 struct gfar_private
*priv
= netdev_priv(dev
);
752 if (!netif_running(dev
))
758 return phy_mii_ioctl(priv
->phydev
, if_mii(rq
), cmd
);
761 static unsigned int reverse_bitmap(unsigned int bit_map
, unsigned int max_qs
)
763 unsigned int new_bit_map
= 0x0;
764 int mask
= 0x1 << (max_qs
- 1), i
;
765 for (i
= 0; i
< max_qs
; i
++) {
767 new_bit_map
= new_bit_map
+ (1 << i
);
773 static u32
cluster_entry_per_class(struct gfar_private
*priv
, u32 rqfar
,
776 u32 rqfpr
= FPR_FILER_MASK
;
780 rqfcr
= RQFCR_CLE
| RQFCR_PID_MASK
| RQFCR_CMP_EXACT
;
781 ftp_rqfpr
[rqfar
] = rqfpr
;
782 ftp_rqfcr
[rqfar
] = rqfcr
;
783 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
786 rqfcr
= RQFCR_CMP_NOMATCH
;
787 ftp_rqfpr
[rqfar
] = rqfpr
;
788 ftp_rqfcr
[rqfar
] = rqfcr
;
789 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
792 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_PARSE
| RQFCR_CLE
| RQFCR_AND
;
794 ftp_rqfcr
[rqfar
] = rqfcr
;
795 ftp_rqfpr
[rqfar
] = rqfpr
;
796 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
799 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_MASK
| RQFCR_AND
;
801 ftp_rqfcr
[rqfar
] = rqfcr
;
802 ftp_rqfpr
[rqfar
] = rqfpr
;
803 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
808 static void gfar_init_filer_table(struct gfar_private
*priv
)
811 u32 rqfar
= MAX_FILER_IDX
;
813 u32 rqfpr
= FPR_FILER_MASK
;
816 rqfcr
= RQFCR_CMP_MATCH
;
817 ftp_rqfcr
[rqfar
] = rqfcr
;
818 ftp_rqfpr
[rqfar
] = rqfpr
;
819 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
821 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
);
822 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_UDP
);
823 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_TCP
);
824 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
);
825 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_UDP
);
826 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_TCP
);
828 /* cur_filer_idx indicated the fisrt non-masked rule */
829 priv
->cur_filer_idx
= rqfar
;
831 /* Rest are masked rules */
832 rqfcr
= RQFCR_CMP_NOMATCH
;
833 for (i
= 0; i
< rqfar
; i
++) {
834 ftp_rqfcr
[i
] = rqfcr
;
835 ftp_rqfpr
[i
] = rqfpr
;
836 gfar_write_filer(priv
, i
, rqfcr
, rqfpr
);
840 /* Set up the ethernet device structure, private data,
841 * and anything else we need before we start */
842 static int gfar_probe(struct of_device
*ofdev
,
843 const struct of_device_id
*match
)
846 struct net_device
*dev
= NULL
;
847 struct gfar_private
*priv
= NULL
;
848 struct gfar __iomem
*regs
= NULL
;
849 int err
= 0, i
, grp_idx
= 0;
851 u32 rstat
= 0, tstat
= 0, rqueue
= 0, tqueue
= 0;
855 err
= gfar_of_init(ofdev
, &dev
);
860 priv
= netdev_priv(dev
);
863 priv
->node
= ofdev
->node
;
864 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
866 spin_lock_init(&priv
->bflock
);
867 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
869 dev_set_drvdata(&ofdev
->dev
, priv
);
870 regs
= priv
->gfargrp
[0].regs
;
872 /* Stop the DMA engine now, in case it was running before */
873 /* (The firmware could have used it, and left it running). */
876 /* Reset MAC layer */
877 gfar_write(®s
->maccfg1
, MACCFG1_SOFT_RESET
);
879 /* We need to delay at least 3 TX clocks */
882 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
883 gfar_write(®s
->maccfg1
, tempval
);
885 /* Initialize MACCFG2. */
886 gfar_write(®s
->maccfg2
, MACCFG2_INIT_SETTINGS
);
888 /* Initialize ECNTRL */
889 gfar_write(®s
->ecntrl
, ECNTRL_INIT_SETTINGS
);
891 /* Set the dev->base_addr to the gfar reg region */
892 dev
->base_addr
= (unsigned long) regs
;
894 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
896 /* Fill in the dev structure */
897 dev
->watchdog_timeo
= TX_TIMEOUT
;
899 dev
->netdev_ops
= &gfar_netdev_ops
;
900 dev
->ethtool_ops
= &gfar_ethtool_ops
;
902 /* Register for napi ...We are registering NAPI for each grp */
903 for (i
= 0; i
< priv
->num_grps
; i
++)
904 netif_napi_add(dev
, &priv
->gfargrp
[i
].napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
906 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
907 priv
->rx_csum_enable
= 1;
908 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_HIGHDMA
;
910 priv
->rx_csum_enable
= 0;
914 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
)
915 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
917 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
918 priv
->extended_hash
= 1;
919 priv
->hash_width
= 9;
921 priv
->hash_regs
[0] = ®s
->igaddr0
;
922 priv
->hash_regs
[1] = ®s
->igaddr1
;
923 priv
->hash_regs
[2] = ®s
->igaddr2
;
924 priv
->hash_regs
[3] = ®s
->igaddr3
;
925 priv
->hash_regs
[4] = ®s
->igaddr4
;
926 priv
->hash_regs
[5] = ®s
->igaddr5
;
927 priv
->hash_regs
[6] = ®s
->igaddr6
;
928 priv
->hash_regs
[7] = ®s
->igaddr7
;
929 priv
->hash_regs
[8] = ®s
->gaddr0
;
930 priv
->hash_regs
[9] = ®s
->gaddr1
;
931 priv
->hash_regs
[10] = ®s
->gaddr2
;
932 priv
->hash_regs
[11] = ®s
->gaddr3
;
933 priv
->hash_regs
[12] = ®s
->gaddr4
;
934 priv
->hash_regs
[13] = ®s
->gaddr5
;
935 priv
->hash_regs
[14] = ®s
->gaddr6
;
936 priv
->hash_regs
[15] = ®s
->gaddr7
;
939 priv
->extended_hash
= 0;
940 priv
->hash_width
= 8;
942 priv
->hash_regs
[0] = ®s
->gaddr0
;
943 priv
->hash_regs
[1] = ®s
->gaddr1
;
944 priv
->hash_regs
[2] = ®s
->gaddr2
;
945 priv
->hash_regs
[3] = ®s
->gaddr3
;
946 priv
->hash_regs
[4] = ®s
->gaddr4
;
947 priv
->hash_regs
[5] = ®s
->gaddr5
;
948 priv
->hash_regs
[6] = ®s
->gaddr6
;
949 priv
->hash_regs
[7] = ®s
->gaddr7
;
952 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
953 priv
->padding
= DEFAULT_PADDING
;
957 if (dev
->features
& NETIF_F_IP_CSUM
)
958 dev
->hard_header_len
+= GMAC_FCB_LEN
;
960 /* Program the isrg regs only if number of grps > 1 */
961 if (priv
->num_grps
> 1) {
962 baddr
= ®s
->isrg0
;
963 for (i
= 0; i
< priv
->num_grps
; i
++) {
964 isrg
|= (priv
->gfargrp
[i
].rx_bit_map
<< ISRG_SHIFT_RX
);
965 isrg
|= (priv
->gfargrp
[i
].tx_bit_map
<< ISRG_SHIFT_TX
);
966 gfar_write(baddr
, isrg
);
972 /* Need to reverse the bit maps as bit_map's MSB is q0
973 * but, for_each_bit parses from right to left, which
974 * basically reverses the queue numbers */
975 for (i
= 0; i
< priv
->num_grps
; i
++) {
976 priv
->gfargrp
[i
].tx_bit_map
= reverse_bitmap(
977 priv
->gfargrp
[i
].tx_bit_map
, MAX_TX_QS
);
978 priv
->gfargrp
[i
].rx_bit_map
= reverse_bitmap(
979 priv
->gfargrp
[i
].rx_bit_map
, MAX_RX_QS
);
982 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
983 * also assign queues to groups */
984 for (grp_idx
= 0; grp_idx
< priv
->num_grps
; grp_idx
++) {
985 priv
->gfargrp
[grp_idx
].num_rx_queues
= 0x0;
986 for_each_bit(i
, &priv
->gfargrp
[grp_idx
].rx_bit_map
,
987 priv
->num_rx_queues
) {
988 priv
->gfargrp
[grp_idx
].num_rx_queues
++;
989 priv
->rx_queue
[i
]->grp
= &priv
->gfargrp
[grp_idx
];
990 rstat
= rstat
| (RSTAT_CLEAR_RHALT
>> i
);
991 rqueue
= rqueue
| ((RQUEUE_EN0
| RQUEUE_EX0
) >> i
);
993 priv
->gfargrp
[grp_idx
].num_tx_queues
= 0x0;
994 for_each_bit (i
, &priv
->gfargrp
[grp_idx
].tx_bit_map
,
995 priv
->num_tx_queues
) {
996 priv
->gfargrp
[grp_idx
].num_tx_queues
++;
997 priv
->tx_queue
[i
]->grp
= &priv
->gfargrp
[grp_idx
];
998 tstat
= tstat
| (TSTAT_CLEAR_THALT
>> i
);
999 tqueue
= tqueue
| (TQUEUE_EN0
>> i
);
1001 priv
->gfargrp
[grp_idx
].rstat
= rstat
;
1002 priv
->gfargrp
[grp_idx
].tstat
= tstat
;
1006 gfar_write(®s
->rqueue
, rqueue
);
1007 gfar_write(®s
->tqueue
, tqueue
);
1009 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
1011 /* Initializing some of the rx/tx queue level parameters */
1012 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1013 priv
->tx_queue
[i
]->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
1014 priv
->tx_queue
[i
]->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
1015 priv
->tx_queue
[i
]->txcoalescing
= DEFAULT_TX_COALESCE
;
1016 priv
->tx_queue
[i
]->txic
= DEFAULT_TXIC
;
1019 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1020 priv
->rx_queue
[i
]->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
1021 priv
->rx_queue
[i
]->rxcoalescing
= DEFAULT_RX_COALESCE
;
1022 priv
->rx_queue
[i
]->rxic
= DEFAULT_RXIC
;
1025 /* Enable most messages by default */
1026 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
1028 /* Carrier starts down, phylib will bring it up */
1029 netif_carrier_off(dev
);
1031 err
= register_netdev(dev
);
1034 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
1039 device_init_wakeup(&dev
->dev
,
1040 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1042 /* fill out IRQ number and name fields */
1043 len_devname
= strlen(dev
->name
);
1044 for (i
= 0; i
< priv
->num_grps
; i
++) {
1045 strncpy(&priv
->gfargrp
[i
].int_name_tx
[0], dev
->name
,
1047 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1048 strncpy(&priv
->gfargrp
[i
].int_name_tx
[len_devname
],
1049 "_g", sizeof("_g"));
1050 priv
->gfargrp
[i
].int_name_tx
[
1051 strlen(priv
->gfargrp
[i
].int_name_tx
)] = i
+48;
1052 strncpy(&priv
->gfargrp
[i
].int_name_tx
[strlen(
1053 priv
->gfargrp
[i
].int_name_tx
)],
1054 "_tx", sizeof("_tx") + 1);
1056 strncpy(&priv
->gfargrp
[i
].int_name_rx
[0], dev
->name
,
1058 strncpy(&priv
->gfargrp
[i
].int_name_rx
[len_devname
],
1059 "_g", sizeof("_g"));
1060 priv
->gfargrp
[i
].int_name_rx
[
1061 strlen(priv
->gfargrp
[i
].int_name_rx
)] = i
+48;
1062 strncpy(&priv
->gfargrp
[i
].int_name_rx
[strlen(
1063 priv
->gfargrp
[i
].int_name_rx
)],
1064 "_rx", sizeof("_rx") + 1);
1066 strncpy(&priv
->gfargrp
[i
].int_name_er
[0], dev
->name
,
1068 strncpy(&priv
->gfargrp
[i
].int_name_er
[len_devname
],
1069 "_g", sizeof("_g"));
1070 priv
->gfargrp
[i
].int_name_er
[strlen(
1071 priv
->gfargrp
[i
].int_name_er
)] = i
+48;
1072 strncpy(&priv
->gfargrp
[i
].int_name_er
[strlen(\
1073 priv
->gfargrp
[i
].int_name_er
)],
1074 "_er", sizeof("_er") + 1);
1076 priv
->gfargrp
[i
].int_name_tx
[len_devname
] = '\0';
1079 /* Initialize the filer table */
1080 gfar_init_filer_table(priv
);
1082 /* Create all the sysfs files */
1083 gfar_init_sysfs(dev
);
1085 /* Print out the device info */
1086 printk(KERN_INFO DEVICE_NAME
"%pM\n", dev
->name
, dev
->dev_addr
);
1088 /* Even more device info helps when determining which kernel */
1089 /* provided which set of benchmarks. */
1090 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
1091 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
1092 printk(KERN_INFO
"%s: :RX BD ring size for Q[%d]: %d\n",
1093 dev
->name
, i
, priv
->rx_queue
[i
]->rx_ring_size
);
1094 for(i
= 0; i
< priv
->num_tx_queues
; i
++)
1095 printk(KERN_INFO
"%s:TX BD ring size for Q[%d]: %d\n",
1096 dev
->name
, i
, priv
->tx_queue
[i
]->tx_ring_size
);
1101 unmap_group_regs(priv
);
1102 free_tx_pointers(priv
);
1103 free_rx_pointers(priv
);
1105 of_node_put(priv
->phy_node
);
1107 of_node_put(priv
->tbi_node
);
1112 static int gfar_remove(struct of_device
*ofdev
)
1114 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
1117 of_node_put(priv
->phy_node
);
1119 of_node_put(priv
->tbi_node
);
1121 dev_set_drvdata(&ofdev
->dev
, NULL
);
1123 unregister_netdev(priv
->ndev
);
1124 unmap_group_regs(priv
);
1125 free_netdev(priv
->ndev
);
1132 static int gfar_suspend(struct device
*dev
)
1134 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1135 struct net_device
*ndev
= priv
->ndev
;
1136 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1137 unsigned long flags
;
1140 int magic_packet
= priv
->wol_en
&&
1141 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1143 netif_device_detach(ndev
);
1145 if (netif_running(ndev
)) {
1147 local_irq_save(flags
);
1151 gfar_halt_nodisable(ndev
);
1153 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1154 tempval
= gfar_read(®s
->maccfg1
);
1156 tempval
&= ~MACCFG1_TX_EN
;
1159 tempval
&= ~MACCFG1_RX_EN
;
1161 gfar_write(®s
->maccfg1
, tempval
);
1165 local_irq_restore(flags
);
1170 /* Enable interrupt on Magic Packet */
1171 gfar_write(®s
->imask
, IMASK_MAG
);
1173 /* Enable Magic Packet mode */
1174 tempval
= gfar_read(®s
->maccfg2
);
1175 tempval
|= MACCFG2_MPEN
;
1176 gfar_write(®s
->maccfg2
, tempval
);
1178 phy_stop(priv
->phydev
);
1185 static int gfar_resume(struct device
*dev
)
1187 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1188 struct net_device
*ndev
= priv
->ndev
;
1189 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1190 unsigned long flags
;
1192 int magic_packet
= priv
->wol_en
&&
1193 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1195 if (!netif_running(ndev
)) {
1196 netif_device_attach(ndev
);
1200 if (!magic_packet
&& priv
->phydev
)
1201 phy_start(priv
->phydev
);
1203 /* Disable Magic Packet mode, in case something
1206 local_irq_save(flags
);
1210 tempval
= gfar_read(®s
->maccfg2
);
1211 tempval
&= ~MACCFG2_MPEN
;
1212 gfar_write(®s
->maccfg2
, tempval
);
1218 local_irq_restore(flags
);
1220 netif_device_attach(ndev
);
1227 static int gfar_restore(struct device
*dev
)
1229 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1230 struct net_device
*ndev
= priv
->ndev
;
1232 if (!netif_running(ndev
))
1235 gfar_init_bds(ndev
);
1236 init_registers(ndev
);
1237 gfar_set_mac_address(ndev
);
1238 gfar_init_mac(ndev
);
1243 priv
->oldduplex
= -1;
1246 phy_start(priv
->phydev
);
1248 netif_device_attach(ndev
);
1254 static struct dev_pm_ops gfar_pm_ops
= {
1255 .suspend
= gfar_suspend
,
1256 .resume
= gfar_resume
,
1257 .freeze
= gfar_suspend
,
1258 .thaw
= gfar_resume
,
1259 .restore
= gfar_restore
,
1262 #define GFAR_PM_OPS (&gfar_pm_ops)
1264 static int gfar_legacy_suspend(struct of_device
*ofdev
, pm_message_t state
)
1266 return gfar_suspend(&ofdev
->dev
);
1269 static int gfar_legacy_resume(struct of_device
*ofdev
)
1271 return gfar_resume(&ofdev
->dev
);
1276 #define GFAR_PM_OPS NULL
1277 #define gfar_legacy_suspend NULL
1278 #define gfar_legacy_resume NULL
1282 /* Reads the controller's registers to determine what interface
1283 * connects it to the PHY.
1285 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
1287 struct gfar_private
*priv
= netdev_priv(dev
);
1288 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1291 ecntrl
= gfar_read(®s
->ecntrl
);
1293 if (ecntrl
& ECNTRL_SGMII_MODE
)
1294 return PHY_INTERFACE_MODE_SGMII
;
1296 if (ecntrl
& ECNTRL_TBI_MODE
) {
1297 if (ecntrl
& ECNTRL_REDUCED_MODE
)
1298 return PHY_INTERFACE_MODE_RTBI
;
1300 return PHY_INTERFACE_MODE_TBI
;
1303 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
1304 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
1305 return PHY_INTERFACE_MODE_RMII
;
1307 phy_interface_t interface
= priv
->interface
;
1310 * This isn't autodetected right now, so it must
1311 * be set by the device tree or platform code.
1313 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
1314 return PHY_INTERFACE_MODE_RGMII_ID
;
1316 return PHY_INTERFACE_MODE_RGMII
;
1320 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
1321 return PHY_INTERFACE_MODE_GMII
;
1323 return PHY_INTERFACE_MODE_MII
;
1327 /* Initializes driver's PHY state, and attaches to the PHY.
1328 * Returns 0 on success.
1330 static int init_phy(struct net_device
*dev
)
1332 struct gfar_private
*priv
= netdev_priv(dev
);
1333 uint gigabit_support
=
1334 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
1335 SUPPORTED_1000baseT_Full
: 0;
1336 phy_interface_t interface
;
1340 priv
->oldduplex
= -1;
1342 interface
= gfar_get_interface(dev
);
1344 priv
->phydev
= of_phy_connect(dev
, priv
->phy_node
, &adjust_link
, 0,
1347 priv
->phydev
= of_phy_connect_fixed_link(dev
, &adjust_link
,
1349 if (!priv
->phydev
) {
1350 dev_err(&dev
->dev
, "could not attach to PHY\n");
1354 if (interface
== PHY_INTERFACE_MODE_SGMII
)
1355 gfar_configure_serdes(dev
);
1357 /* Remove any features not supported by the controller */
1358 priv
->phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
1359 priv
->phydev
->advertising
= priv
->phydev
->supported
;
1365 * Initialize TBI PHY interface for communicating with the
1366 * SERDES lynx PHY on the chip. We communicate with this PHY
1367 * through the MDIO bus on each controller, treating it as a
1368 * "normal" PHY at the address found in the TBIPA register. We assume
1369 * that the TBIPA register is valid. Either the MDIO bus code will set
1370 * it to a value that doesn't conflict with other PHYs on the bus, or the
1371 * value doesn't matter, as there are no other PHYs on the bus.
1373 static void gfar_configure_serdes(struct net_device
*dev
)
1375 struct gfar_private
*priv
= netdev_priv(dev
);
1376 struct phy_device
*tbiphy
;
1378 if (!priv
->tbi_node
) {
1379 dev_warn(&dev
->dev
, "error: SGMII mode requires that the "
1380 "device tree specify a tbi-handle\n");
1384 tbiphy
= of_phy_find_device(priv
->tbi_node
);
1386 dev_err(&dev
->dev
, "error: Could not get TBI device\n");
1391 * If the link is already up, we must already be ok, and don't need to
1392 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1393 * everything for us? Resetting it takes the link down and requires
1394 * several seconds for it to come back.
1396 if (phy_read(tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
1399 /* Single clk mode, mii mode off(for serdes communication) */
1400 phy_write(tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
1402 phy_write(tbiphy
, MII_ADVERTISE
,
1403 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
1404 ADVERTISE_1000XPSE_ASYM
);
1406 phy_write(tbiphy
, MII_BMCR
, BMCR_ANENABLE
|
1407 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
1410 static void init_registers(struct net_device
*dev
)
1412 struct gfar_private
*priv
= netdev_priv(dev
);
1413 struct gfar __iomem
*regs
= NULL
;
1416 for (i
= 0; i
< priv
->num_grps
; i
++) {
1417 regs
= priv
->gfargrp
[i
].regs
;
1419 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1421 /* Initialize IMASK */
1422 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1425 regs
= priv
->gfargrp
[0].regs
;
1426 /* Init hash registers to zero */
1427 gfar_write(®s
->igaddr0
, 0);
1428 gfar_write(®s
->igaddr1
, 0);
1429 gfar_write(®s
->igaddr2
, 0);
1430 gfar_write(®s
->igaddr3
, 0);
1431 gfar_write(®s
->igaddr4
, 0);
1432 gfar_write(®s
->igaddr5
, 0);
1433 gfar_write(®s
->igaddr6
, 0);
1434 gfar_write(®s
->igaddr7
, 0);
1436 gfar_write(®s
->gaddr0
, 0);
1437 gfar_write(®s
->gaddr1
, 0);
1438 gfar_write(®s
->gaddr2
, 0);
1439 gfar_write(®s
->gaddr3
, 0);
1440 gfar_write(®s
->gaddr4
, 0);
1441 gfar_write(®s
->gaddr5
, 0);
1442 gfar_write(®s
->gaddr6
, 0);
1443 gfar_write(®s
->gaddr7
, 0);
1445 /* Zero out the rmon mib registers if it has them */
1446 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
1447 memset_io(&(regs
->rmon
), 0, sizeof (struct rmon_mib
));
1449 /* Mask off the CAM interrupts */
1450 gfar_write(®s
->rmon
.cam1
, 0xffffffff);
1451 gfar_write(®s
->rmon
.cam2
, 0xffffffff);
1454 /* Initialize the max receive buffer length */
1455 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
1457 /* Initialize the Minimum Frame Length Register */
1458 gfar_write(®s
->minflr
, MINFLR_INIT_SETTINGS
);
1462 /* Halt the receive and transmit queues */
1463 static void gfar_halt_nodisable(struct net_device
*dev
)
1465 struct gfar_private
*priv
= netdev_priv(dev
);
1466 struct gfar __iomem
*regs
= NULL
;
1470 for (i
= 0; i
< priv
->num_grps
; i
++) {
1471 regs
= priv
->gfargrp
[i
].regs
;
1472 /* Mask all interrupts */
1473 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1475 /* Clear all interrupts */
1476 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1479 regs
= priv
->gfargrp
[0].regs
;
1480 /* Stop the DMA, and wait for it to stop */
1481 tempval
= gfar_read(®s
->dmactrl
);
1482 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
1483 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
1484 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
1485 gfar_write(®s
->dmactrl
, tempval
);
1487 while (!(gfar_read(®s
->ievent
) &
1488 (IEVENT_GRSC
| IEVENT_GTSC
)))
1493 /* Halt the receive and transmit queues */
1494 void gfar_halt(struct net_device
*dev
)
1496 struct gfar_private
*priv
= netdev_priv(dev
);
1497 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1500 gfar_halt_nodisable(dev
);
1502 /* Disable Rx and Tx */
1503 tempval
= gfar_read(®s
->maccfg1
);
1504 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1505 gfar_write(®s
->maccfg1
, tempval
);
1508 static void free_grp_irqs(struct gfar_priv_grp
*grp
)
1510 free_irq(grp
->interruptError
, grp
);
1511 free_irq(grp
->interruptTransmit
, grp
);
1512 free_irq(grp
->interruptReceive
, grp
);
1515 void stop_gfar(struct net_device
*dev
)
1517 struct gfar_private
*priv
= netdev_priv(dev
);
1518 unsigned long flags
;
1521 phy_stop(priv
->phydev
);
1525 local_irq_save(flags
);
1533 local_irq_restore(flags
);
1536 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1537 for (i
= 0; i
< priv
->num_grps
; i
++)
1538 free_grp_irqs(&priv
->gfargrp
[i
]);
1540 for (i
= 0; i
< priv
->num_grps
; i
++)
1541 free_irq(priv
->gfargrp
[i
].interruptTransmit
,
1545 free_skb_resources(priv
);
1548 static void free_skb_tx_queue(struct gfar_priv_tx_q
*tx_queue
)
1550 struct txbd8
*txbdp
;
1551 struct gfar_private
*priv
= netdev_priv(tx_queue
->dev
);
1554 txbdp
= tx_queue
->tx_bd_base
;
1556 for (i
= 0; i
< tx_queue
->tx_ring_size
; i
++) {
1557 if (!tx_queue
->tx_skbuff
[i
])
1560 dma_unmap_single(&priv
->ofdev
->dev
, txbdp
->bufPtr
,
1561 txbdp
->length
, DMA_TO_DEVICE
);
1563 for (j
= 0; j
< skb_shinfo(tx_queue
->tx_skbuff
[i
])->nr_frags
;
1566 dma_unmap_page(&priv
->ofdev
->dev
, txbdp
->bufPtr
,
1567 txbdp
->length
, DMA_TO_DEVICE
);
1570 dev_kfree_skb_any(tx_queue
->tx_skbuff
[i
]);
1571 tx_queue
->tx_skbuff
[i
] = NULL
;
1573 kfree(tx_queue
->tx_skbuff
);
1576 static void free_skb_rx_queue(struct gfar_priv_rx_q
*rx_queue
)
1578 struct rxbd8
*rxbdp
;
1579 struct gfar_private
*priv
= netdev_priv(rx_queue
->dev
);
1582 rxbdp
= rx_queue
->rx_bd_base
;
1584 for (i
= 0; i
< rx_queue
->rx_ring_size
; i
++) {
1585 if (rx_queue
->rx_skbuff
[i
]) {
1586 dma_unmap_single(&priv
->ofdev
->dev
,
1587 rxbdp
->bufPtr
, priv
->rx_buffer_size
,
1589 dev_kfree_skb_any(rx_queue
->rx_skbuff
[i
]);
1590 rx_queue
->rx_skbuff
[i
] = NULL
;
1596 kfree(rx_queue
->rx_skbuff
);
1599 /* If there are any tx skbs or rx skbs still around, free them.
1600 * Then free tx_skbuff and rx_skbuff */
1601 static void free_skb_resources(struct gfar_private
*priv
)
1603 struct gfar_priv_tx_q
*tx_queue
= NULL
;
1604 struct gfar_priv_rx_q
*rx_queue
= NULL
;
1607 /* Go through all the buffer descriptors and free their data buffers */
1608 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1609 tx_queue
= priv
->tx_queue
[i
];
1610 if(!tx_queue
->tx_skbuff
)
1611 free_skb_tx_queue(tx_queue
);
1614 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1615 rx_queue
= priv
->rx_queue
[i
];
1616 if(!rx_queue
->rx_skbuff
)
1617 free_skb_rx_queue(rx_queue
);
1620 dma_free_coherent(&priv
->ofdev
->dev
,
1621 sizeof(struct txbd8
) * priv
->total_tx_ring_size
+
1622 sizeof(struct rxbd8
) * priv
->total_rx_ring_size
,
1623 priv
->tx_queue
[0]->tx_bd_base
,
1624 priv
->tx_queue
[0]->tx_bd_dma_base
);
1627 void gfar_start(struct net_device
*dev
)
1629 struct gfar_private
*priv
= netdev_priv(dev
);
1630 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1634 /* Enable Rx and Tx in MACCFG1 */
1635 tempval
= gfar_read(®s
->maccfg1
);
1636 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1637 gfar_write(®s
->maccfg1
, tempval
);
1639 /* Initialize DMACTRL to have WWR and WOP */
1640 tempval
= gfar_read(®s
->dmactrl
);
1641 tempval
|= DMACTRL_INIT_SETTINGS
;
1642 gfar_write(®s
->dmactrl
, tempval
);
1644 /* Make sure we aren't stopped */
1645 tempval
= gfar_read(®s
->dmactrl
);
1646 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
1647 gfar_write(®s
->dmactrl
, tempval
);
1649 for (i
= 0; i
< priv
->num_grps
; i
++) {
1650 regs
= priv
->gfargrp
[i
].regs
;
1651 /* Clear THLT/RHLT, so that the DMA starts polling now */
1652 gfar_write(®s
->tstat
, priv
->gfargrp
[i
].tstat
);
1653 gfar_write(®s
->rstat
, priv
->gfargrp
[i
].rstat
);
1654 /* Unmask the interrupts we look for */
1655 gfar_write(®s
->imask
, IMASK_DEFAULT
);
1658 dev
->trans_start
= jiffies
;
1661 void gfar_configure_coalescing(struct gfar_private
*priv
,
1662 unsigned long tx_mask
, unsigned long rx_mask
)
1664 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1668 /* Backward compatible case ---- even if we enable
1669 * multiple queues, there's only single reg to program
1671 gfar_write(®s
->txic
, 0);
1672 if(likely(priv
->tx_queue
[0]->txcoalescing
))
1673 gfar_write(®s
->txic
, priv
->tx_queue
[0]->txic
);
1675 gfar_write(®s
->rxic
, 0);
1676 if(unlikely(priv
->rx_queue
[0]->rxcoalescing
))
1677 gfar_write(®s
->rxic
, priv
->rx_queue
[0]->rxic
);
1679 if (priv
->mode
== MQ_MG_MODE
) {
1680 baddr
= ®s
->txic0
;
1681 for_each_bit (i
, &tx_mask
, priv
->num_tx_queues
) {
1682 if (likely(priv
->tx_queue
[i
]->txcoalescing
)) {
1683 gfar_write(baddr
+ i
, 0);
1684 gfar_write(baddr
+ i
, priv
->tx_queue
[i
]->txic
);
1688 baddr
= ®s
->rxic0
;
1689 for_each_bit (i
, &rx_mask
, priv
->num_rx_queues
) {
1690 if (likely(priv
->rx_queue
[i
]->rxcoalescing
)) {
1691 gfar_write(baddr
+ i
, 0);
1692 gfar_write(baddr
+ i
, priv
->rx_queue
[i
]->rxic
);
1698 static int register_grp_irqs(struct gfar_priv_grp
*grp
)
1700 struct gfar_private
*priv
= grp
->priv
;
1701 struct net_device
*dev
= priv
->ndev
;
1704 /* If the device has multiple interrupts, register for
1705 * them. Otherwise, only register for the one */
1706 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1707 /* Install our interrupt handlers for Error,
1708 * Transmit, and Receive */
1709 if ((err
= request_irq(grp
->interruptError
, gfar_error
, 0,
1710 grp
->int_name_er
,grp
)) < 0) {
1711 if (netif_msg_intr(priv
))
1712 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1713 dev
->name
, grp
->interruptError
);
1718 if ((err
= request_irq(grp
->interruptTransmit
, gfar_transmit
,
1719 0, grp
->int_name_tx
, grp
)) < 0) {
1720 if (netif_msg_intr(priv
))
1721 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1722 dev
->name
, grp
->interruptTransmit
);
1726 if ((err
= request_irq(grp
->interruptReceive
, gfar_receive
, 0,
1727 grp
->int_name_rx
, grp
)) < 0) {
1728 if (netif_msg_intr(priv
))
1729 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1730 dev
->name
, grp
->interruptReceive
);
1734 if ((err
= request_irq(grp
->interruptTransmit
, gfar_interrupt
, 0,
1735 grp
->int_name_tx
, grp
)) < 0) {
1736 if (netif_msg_intr(priv
))
1737 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1738 dev
->name
, grp
->interruptTransmit
);
1746 free_irq(grp
->interruptTransmit
, grp
);
1748 free_irq(grp
->interruptError
, grp
);
1754 /* Bring the controller up and running */
1755 int startup_gfar(struct net_device
*ndev
)
1757 struct gfar_private
*priv
= netdev_priv(ndev
);
1758 struct gfar __iomem
*regs
= NULL
;
1761 for (i
= 0; i
< priv
->num_grps
; i
++) {
1762 regs
= priv
->gfargrp
[i
].regs
;
1763 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1766 regs
= priv
->gfargrp
[0].regs
;
1767 err
= gfar_alloc_skb_resources(ndev
);
1771 gfar_init_mac(ndev
);
1773 for (i
= 0; i
< priv
->num_grps
; i
++) {
1774 err
= register_grp_irqs(&priv
->gfargrp
[i
]);
1776 for (j
= 0; j
< i
; j
++)
1777 free_grp_irqs(&priv
->gfargrp
[j
]);
1782 /* Start the controller */
1785 phy_start(priv
->phydev
);
1787 gfar_configure_coalescing(priv
, 0xFF, 0xFF);
1792 free_skb_resources(priv
);
1796 /* Called when something needs to use the ethernet device */
1797 /* Returns 0 for success. */
1798 static int gfar_enet_open(struct net_device
*dev
)
1800 struct gfar_private
*priv
= netdev_priv(dev
);
1805 skb_queue_head_init(&priv
->rx_recycle
);
1807 /* Initialize a bunch of registers */
1808 init_registers(dev
);
1810 gfar_set_mac_address(dev
);
1812 err
= init_phy(dev
);
1819 err
= startup_gfar(dev
);
1825 netif_tx_start_all_queues(dev
);
1827 device_set_wakeup_enable(&dev
->dev
, priv
->wol_en
);
1832 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
1834 struct txfcb
*fcb
= (struct txfcb
*)skb_push(skb
, GMAC_FCB_LEN
);
1836 memset(fcb
, 0, GMAC_FCB_LEN
);
1841 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1845 /* If we're here, it's a IP packet with a TCP or UDP
1846 * payload. We set it to checksum, using a pseudo-header
1849 flags
= TXFCB_DEFAULT
;
1851 /* Tell the controller what the protocol is */
1852 /* And provide the already calculated phcs */
1853 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1855 fcb
->phcs
= udp_hdr(skb
)->check
;
1857 fcb
->phcs
= tcp_hdr(skb
)->check
;
1859 /* l3os is the distance between the start of the
1860 * frame (skb->data) and the start of the IP hdr.
1861 * l4os is the distance between the start of the
1862 * l3 hdr and the l4 hdr */
1863 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1864 fcb
->l4os
= skb_network_header_len(skb
);
1869 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1871 fcb
->flags
|= TXFCB_VLN
;
1872 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1875 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
1876 struct txbd8
*base
, int ring_size
)
1878 struct txbd8
*new_bd
= bdp
+ stride
;
1880 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
1883 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
1886 return skip_txbd(bdp
, 1, base
, ring_size
);
1889 /* This is called by the kernel when a frame is ready for transmission. */
1890 /* It is pointed to by the dev->hard_start_xmit function pointer */
1891 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1893 struct gfar_private
*priv
= netdev_priv(dev
);
1894 struct gfar_priv_tx_q
*tx_queue
= NULL
;
1895 struct netdev_queue
*txq
;
1896 struct gfar __iomem
*regs
= NULL
;
1897 struct txfcb
*fcb
= NULL
;
1898 struct txbd8
*txbdp
, *txbdp_start
, *base
;
1902 unsigned long flags
;
1903 unsigned int nr_frags
, length
;
1906 rq
= skb
->queue_mapping
;
1907 tx_queue
= priv
->tx_queue
[rq
];
1908 txq
= netdev_get_tx_queue(dev
, rq
);
1909 base
= tx_queue
->tx_bd_base
;
1910 regs
= tx_queue
->grp
->regs
;
1912 /* make space for additional header when fcb is needed */
1913 if (((skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
1914 (priv
->vlgrp
&& vlan_tx_tag_present(skb
))) &&
1915 (skb_headroom(skb
) < GMAC_FCB_LEN
)) {
1916 struct sk_buff
*skb_new
;
1918 skb_new
= skb_realloc_headroom(skb
, GMAC_FCB_LEN
);
1920 dev
->stats
.tx_errors
++;
1922 return NETDEV_TX_OK
;
1928 /* total number of fragments in the SKB */
1929 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1931 /* check if there is space to queue this packet */
1932 if ((nr_frags
+1) > tx_queue
->num_txbdfree
) {
1933 /* no space, stop the queue */
1934 netif_tx_stop_queue(txq
);
1935 dev
->stats
.tx_fifo_errors
++;
1936 return NETDEV_TX_BUSY
;
1939 /* Update transmit stats */
1940 dev
->stats
.tx_bytes
+= skb
->len
;
1942 txbdp
= txbdp_start
= tx_queue
->cur_tx
;
1944 if (nr_frags
== 0) {
1945 lstatus
= txbdp
->lstatus
| BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1947 /* Place the fragment addresses and lengths into the TxBDs */
1948 for (i
= 0; i
< nr_frags
; i
++) {
1949 /* Point at the next BD, wrapping as needed */
1950 txbdp
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
1952 length
= skb_shinfo(skb
)->frags
[i
].size
;
1954 lstatus
= txbdp
->lstatus
| length
|
1955 BD_LFLAG(TXBD_READY
);
1957 /* Handle the last BD specially */
1958 if (i
== nr_frags
- 1)
1959 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1961 bufaddr
= dma_map_page(&priv
->ofdev
->dev
,
1962 skb_shinfo(skb
)->frags
[i
].page
,
1963 skb_shinfo(skb
)->frags
[i
].page_offset
,
1967 /* set the TxBD length and buffer pointer */
1968 txbdp
->bufPtr
= bufaddr
;
1969 txbdp
->lstatus
= lstatus
;
1972 lstatus
= txbdp_start
->lstatus
;
1975 /* Set up checksumming */
1976 if (CHECKSUM_PARTIAL
== skb
->ip_summed
) {
1977 fcb
= gfar_add_fcb(skb
);
1978 lstatus
|= BD_LFLAG(TXBD_TOE
);
1979 gfar_tx_checksum(skb
, fcb
);
1982 if (priv
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1983 if (unlikely(NULL
== fcb
)) {
1984 fcb
= gfar_add_fcb(skb
);
1985 lstatus
|= BD_LFLAG(TXBD_TOE
);
1988 gfar_tx_vlan(skb
, fcb
);
1991 /* setup the TxBD length and buffer pointer for the first BD */
1992 tx_queue
->tx_skbuff
[tx_queue
->skb_curtx
] = skb
;
1993 txbdp_start
->bufPtr
= dma_map_single(&priv
->ofdev
->dev
, skb
->data
,
1994 skb_headlen(skb
), DMA_TO_DEVICE
);
1996 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
1999 * We can work in parallel with gfar_clean_tx_ring(), except
2000 * when modifying num_txbdfree. Note that we didn't grab the lock
2001 * when we were reading the num_txbdfree and checking for available
2002 * space, that's because outside of this function it can only grow,
2003 * and once we've got needed space, it cannot suddenly disappear.
2005 * The lock also protects us from gfar_error(), which can modify
2006 * regs->tstat and thus retrigger the transfers, which is why we
2007 * also must grab the lock before setting ready bit for the first
2008 * to be transmitted BD.
2010 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2013 * The powerpc-specific eieio() is used, as wmb() has too strong
2014 * semantics (it requires synchronization between cacheable and
2015 * uncacheable mappings, which eieio doesn't provide and which we
2016 * don't need), thus requiring a more expensive sync instruction. At
2017 * some point, the set of architecture-independent barrier functions
2018 * should be expanded to include weaker barriers.
2022 txbdp_start
->lstatus
= lstatus
;
2024 /* Update the current skb pointer to the next entry we will use
2025 * (wrapping if necessary) */
2026 tx_queue
->skb_curtx
= (tx_queue
->skb_curtx
+ 1) &
2027 TX_RING_MOD_MASK(tx_queue
->tx_ring_size
);
2029 tx_queue
->cur_tx
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2031 /* reduce TxBD free count */
2032 tx_queue
->num_txbdfree
-= (nr_frags
+ 1);
2034 dev
->trans_start
= jiffies
;
2036 /* If the next BD still needs to be cleaned up, then the bds
2037 are full. We need to tell the kernel to stop sending us stuff. */
2038 if (!tx_queue
->num_txbdfree
) {
2039 netif_tx_stop_queue(txq
);
2041 dev
->stats
.tx_fifo_errors
++;
2044 /* Tell the DMA to go go go */
2045 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
>> tx_queue
->qindex
);
2048 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2050 return NETDEV_TX_OK
;
2053 /* Stops the kernel queue, and halts the controller */
2054 static int gfar_close(struct net_device
*dev
)
2056 struct gfar_private
*priv
= netdev_priv(dev
);
2060 skb_queue_purge(&priv
->rx_recycle
);
2061 cancel_work_sync(&priv
->reset_task
);
2064 /* Disconnect from the PHY */
2065 phy_disconnect(priv
->phydev
);
2066 priv
->phydev
= NULL
;
2068 netif_tx_stop_all_queues(dev
);
2073 /* Changes the mac address if the controller is not running. */
2074 static int gfar_set_mac_address(struct net_device
*dev
)
2076 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
2082 /* Enables and disables VLAN insertion/extraction */
2083 static void gfar_vlan_rx_register(struct net_device
*dev
,
2084 struct vlan_group
*grp
)
2086 struct gfar_private
*priv
= netdev_priv(dev
);
2087 struct gfar __iomem
*regs
= NULL
;
2088 unsigned long flags
;
2091 regs
= priv
->gfargrp
[0].regs
;
2092 local_irq_save(flags
);
2098 /* Enable VLAN tag insertion */
2099 tempval
= gfar_read(®s
->tctrl
);
2100 tempval
|= TCTRL_VLINS
;
2102 gfar_write(®s
->tctrl
, tempval
);
2104 /* Enable VLAN tag extraction */
2105 tempval
= gfar_read(®s
->rctrl
);
2106 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
2107 gfar_write(®s
->rctrl
, tempval
);
2109 /* Disable VLAN tag insertion */
2110 tempval
= gfar_read(®s
->tctrl
);
2111 tempval
&= ~TCTRL_VLINS
;
2112 gfar_write(®s
->tctrl
, tempval
);
2114 /* Disable VLAN tag extraction */
2115 tempval
= gfar_read(®s
->rctrl
);
2116 tempval
&= ~RCTRL_VLEX
;
2117 /* If parse is no longer required, then disable parser */
2118 if (tempval
& RCTRL_REQ_PARSER
)
2119 tempval
|= RCTRL_PRSDEP_INIT
;
2121 tempval
&= ~RCTRL_PRSDEP_INIT
;
2122 gfar_write(®s
->rctrl
, tempval
);
2125 gfar_change_mtu(dev
, dev
->mtu
);
2128 local_irq_restore(flags
);
2131 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
2133 int tempsize
, tempval
;
2134 struct gfar_private
*priv
= netdev_priv(dev
);
2135 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2136 int oldsize
= priv
->rx_buffer_size
;
2137 int frame_size
= new_mtu
+ ETH_HLEN
;
2140 frame_size
+= VLAN_HLEN
;
2142 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
2143 if (netif_msg_drv(priv
))
2144 printk(KERN_ERR
"%s: Invalid MTU setting\n",
2149 if (gfar_uses_fcb(priv
))
2150 frame_size
+= GMAC_FCB_LEN
;
2152 frame_size
+= priv
->padding
;
2155 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
2156 INCREMENTAL_BUFFER_SIZE
;
2158 /* Only stop and start the controller if it isn't already
2159 * stopped, and we changed something */
2160 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2163 priv
->rx_buffer_size
= tempsize
;
2167 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
2168 gfar_write(®s
->maxfrm
, priv
->rx_buffer_size
);
2170 /* If the mtu is larger than the max size for standard
2171 * ethernet frames (ie, a jumbo frame), then set maccfg2
2172 * to allow huge frames, and to check the length */
2173 tempval
= gfar_read(®s
->maccfg2
);
2175 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
2176 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2178 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2180 gfar_write(®s
->maccfg2
, tempval
);
2182 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2188 /* gfar_reset_task gets scheduled when a packet has not been
2189 * transmitted after a set amount of time.
2190 * For now, assume that clearing out all the structures, and
2191 * starting over will fix the problem.
2193 static void gfar_reset_task(struct work_struct
*work
)
2195 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
2197 struct net_device
*dev
= priv
->ndev
;
2199 if (dev
->flags
& IFF_UP
) {
2200 netif_tx_stop_all_queues(dev
);
2203 netif_tx_start_all_queues(dev
);
2206 netif_tx_schedule_all(dev
);
2209 static void gfar_timeout(struct net_device
*dev
)
2211 struct gfar_private
*priv
= netdev_priv(dev
);
2213 dev
->stats
.tx_errors
++;
2214 schedule_work(&priv
->reset_task
);
2217 /* Interrupt Handler for Transmit complete */
2218 static int gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
)
2220 struct net_device
*dev
= tx_queue
->dev
;
2221 struct gfar_private
*priv
= netdev_priv(dev
);
2222 struct gfar_priv_rx_q
*rx_queue
= NULL
;
2224 struct txbd8
*lbdp
= NULL
;
2225 struct txbd8
*base
= tx_queue
->tx_bd_base
;
2226 struct sk_buff
*skb
;
2228 int tx_ring_size
= tx_queue
->tx_ring_size
;
2234 rx_queue
= priv
->rx_queue
[tx_queue
->qindex
];
2235 bdp
= tx_queue
->dirty_tx
;
2236 skb_dirtytx
= tx_queue
->skb_dirtytx
;
2238 while ((skb
= tx_queue
->tx_skbuff
[skb_dirtytx
])) {
2239 unsigned long flags
;
2241 frags
= skb_shinfo(skb
)->nr_frags
;
2242 lbdp
= skip_txbd(bdp
, frags
, base
, tx_ring_size
);
2244 lstatus
= lbdp
->lstatus
;
2246 /* Only clean completed frames */
2247 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
2248 (lstatus
& BD_LENGTH_MASK
))
2251 dma_unmap_single(&priv
->ofdev
->dev
,
2256 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2257 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2259 for (i
= 0; i
< frags
; i
++) {
2260 dma_unmap_page(&priv
->ofdev
->dev
,
2264 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2265 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2269 * If there's room in the queue (limit it to rx_buffer_size)
2270 * we add this skb back into the pool, if it's the right size
2272 if (skb_queue_len(&priv
->rx_recycle
) < rx_queue
->rx_ring_size
&&
2273 skb_recycle_check(skb
, priv
->rx_buffer_size
+
2275 __skb_queue_head(&priv
->rx_recycle
, skb
);
2277 dev_kfree_skb_any(skb
);
2279 tx_queue
->tx_skbuff
[skb_dirtytx
] = NULL
;
2281 skb_dirtytx
= (skb_dirtytx
+ 1) &
2282 TX_RING_MOD_MASK(tx_ring_size
);
2285 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2286 tx_queue
->num_txbdfree
+= frags
+ 1;
2287 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2290 /* If we freed a buffer, we can restart transmission, if necessary */
2291 if (__netif_subqueue_stopped(dev
, tx_queue
->qindex
) && tx_queue
->num_txbdfree
)
2292 netif_wake_subqueue(dev
, tx_queue
->qindex
);
2294 /* Update dirty indicators */
2295 tx_queue
->skb_dirtytx
= skb_dirtytx
;
2296 tx_queue
->dirty_tx
= bdp
;
2298 dev
->stats
.tx_packets
+= howmany
;
2303 static void gfar_schedule_cleanup(struct gfar_priv_grp
*gfargrp
)
2305 unsigned long flags
;
2307 spin_lock_irqsave(&gfargrp
->grplock
, flags
);
2308 if (napi_schedule_prep(&gfargrp
->napi
)) {
2309 gfar_write(&gfargrp
->regs
->imask
, IMASK_RTX_DISABLED
);
2310 __napi_schedule(&gfargrp
->napi
);
2313 * Clear IEVENT, so interrupts aren't called again
2314 * because of the packets that have already arrived.
2316 gfar_write(&gfargrp
->regs
->ievent
, IEVENT_RTX_MASK
);
2318 spin_unlock_irqrestore(&gfargrp
->grplock
, flags
);
2322 /* Interrupt Handler for Transmit complete */
2323 static irqreturn_t
gfar_transmit(int irq
, void *grp_id
)
2325 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2329 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
2330 struct sk_buff
*skb
)
2332 struct net_device
*dev
= rx_queue
->dev
;
2333 struct gfar_private
*priv
= netdev_priv(dev
);
2336 buf
= dma_map_single(&priv
->ofdev
->dev
, skb
->data
,
2337 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2338 gfar_init_rxbdp(rx_queue
, bdp
, buf
);
2342 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
2344 unsigned int alignamount
;
2345 struct gfar_private
*priv
= netdev_priv(dev
);
2346 struct sk_buff
*skb
= NULL
;
2348 skb
= __skb_dequeue(&priv
->rx_recycle
);
2350 skb
= netdev_alloc_skb(dev
,
2351 priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
2356 alignamount
= RXBUF_ALIGNMENT
-
2357 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
2359 /* We need the data buffer to be aligned properly. We will reserve
2360 * as many bytes as needed to align the data properly
2362 skb_reserve(skb
, alignamount
);
2367 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
2369 struct gfar_private
*priv
= netdev_priv(dev
);
2370 struct net_device_stats
*stats
= &dev
->stats
;
2371 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
2373 /* If the packet was truncated, none of the other errors
2375 if (status
& RXBD_TRUNCATED
) {
2376 stats
->rx_length_errors
++;
2382 /* Count the errors, if there were any */
2383 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
2384 stats
->rx_length_errors
++;
2386 if (status
& RXBD_LARGE
)
2391 if (status
& RXBD_NONOCTET
) {
2392 stats
->rx_frame_errors
++;
2393 estats
->rx_nonoctet
++;
2395 if (status
& RXBD_CRCERR
) {
2396 estats
->rx_crcerr
++;
2397 stats
->rx_crc_errors
++;
2399 if (status
& RXBD_OVERRUN
) {
2400 estats
->rx_overrun
++;
2401 stats
->rx_crc_errors
++;
2405 irqreturn_t
gfar_receive(int irq
, void *grp_id
)
2407 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2411 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
2413 /* If valid headers were found, and valid sums
2414 * were verified, then we tell the kernel that no
2415 * checksumming is necessary. Otherwise, it is */
2416 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
2417 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2419 skb
->ip_summed
= CHECKSUM_NONE
;
2423 /* gfar_process_frame() -- handle one incoming packet if skb
2425 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
2428 struct gfar_private
*priv
= netdev_priv(dev
);
2429 struct rxfcb
*fcb
= NULL
;
2433 /* fcb is at the beginning if exists */
2434 fcb
= (struct rxfcb
*)skb
->data
;
2436 /* Remove the FCB from the skb */
2437 skb_set_queue_mapping(skb
, fcb
->rq
);
2438 /* Remove the padded bytes, if there are any */
2440 skb_pull(skb
, amount_pull
);
2442 if (priv
->rx_csum_enable
)
2443 gfar_rx_checksum(skb
, fcb
);
2445 /* Tell the skb what kind of packet this is */
2446 skb
->protocol
= eth_type_trans(skb
, dev
);
2448 /* Send the packet up the stack */
2449 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
2450 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
, fcb
->vlctl
);
2452 ret
= netif_receive_skb(skb
);
2454 if (NET_RX_DROP
== ret
)
2455 priv
->extra_stats
.kernel_dropped
++;
2460 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2461 * until the budget/quota has been reached. Returns the number
2464 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
)
2466 struct net_device
*dev
= rx_queue
->dev
;
2467 struct rxbd8
*bdp
, *base
;
2468 struct sk_buff
*skb
;
2472 struct gfar_private
*priv
= netdev_priv(dev
);
2474 /* Get the first full descriptor */
2475 bdp
= rx_queue
->cur_rx
;
2476 base
= rx_queue
->rx_bd_base
;
2478 amount_pull
= (gfar_uses_fcb(priv
) ? GMAC_FCB_LEN
: 0) +
2481 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
2482 struct sk_buff
*newskb
;
2485 /* Add another skb for the future */
2486 newskb
= gfar_new_skb(dev
);
2488 skb
= rx_queue
->rx_skbuff
[rx_queue
->skb_currx
];
2490 dma_unmap_single(&priv
->ofdev
->dev
, bdp
->bufPtr
,
2491 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2493 /* We drop the frame if we failed to allocate a new buffer */
2494 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
2495 bdp
->status
& RXBD_ERR
)) {
2496 count_errors(bdp
->status
, dev
);
2498 if (unlikely(!newskb
))
2502 * We need to reset ->data to what it
2503 * was before gfar_new_skb() re-aligned
2504 * it to an RXBUF_ALIGNMENT boundary
2505 * before we put the skb back on the
2508 skb
->data
= skb
->head
+ NET_SKB_PAD
;
2509 __skb_queue_head(&priv
->rx_recycle
, skb
);
2512 /* Increment the number of packets */
2513 dev
->stats
.rx_packets
++;
2517 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
2518 /* Remove the FCS from the packet length */
2519 skb_put(skb
, pkt_len
);
2520 dev
->stats
.rx_bytes
+= pkt_len
;
2522 gfar_process_frame(dev
, skb
, amount_pull
);
2525 if (netif_msg_rx_err(priv
))
2527 "%s: Missing skb!\n", dev
->name
);
2528 dev
->stats
.rx_dropped
++;
2529 priv
->extra_stats
.rx_skbmissing
++;
2534 rx_queue
->rx_skbuff
[rx_queue
->skb_currx
] = newskb
;
2536 /* Setup the new bdp */
2537 gfar_new_rxbdp(rx_queue
, bdp
, newskb
);
2539 /* Update to the next pointer */
2540 bdp
= next_bd(bdp
, base
, rx_queue
->rx_ring_size
);
2542 /* update to point at the next skb */
2543 rx_queue
->skb_currx
=
2544 (rx_queue
->skb_currx
+ 1) &
2545 RX_RING_MOD_MASK(rx_queue
->rx_ring_size
);
2548 /* Update the current rxbd pointer to be the next one */
2549 rx_queue
->cur_rx
= bdp
;
2554 static int gfar_poll(struct napi_struct
*napi
, int budget
)
2556 struct gfar_priv_grp
*gfargrp
= container_of(napi
,
2557 struct gfar_priv_grp
, napi
);
2558 struct gfar_private
*priv
= gfargrp
->priv
;
2559 struct gfar __iomem
*regs
= gfargrp
->regs
;
2560 struct gfar_priv_tx_q
*tx_queue
= NULL
;
2561 struct gfar_priv_rx_q
*rx_queue
= NULL
;
2562 int rx_cleaned
= 0, budget_per_queue
= 0, rx_cleaned_per_queue
= 0;
2563 int tx_cleaned
= 0, i
, left_over_budget
= budget
;
2564 unsigned long serviced_queues
= 0;
2567 num_queues
= gfargrp
->num_rx_queues
;
2568 budget_per_queue
= budget
/num_queues
;
2570 /* Clear IEVENT, so interrupts aren't called again
2571 * because of the packets that have already arrived */
2572 gfar_write(®s
->ievent
, IEVENT_RTX_MASK
);
2574 while (num_queues
&& left_over_budget
) {
2576 budget_per_queue
= left_over_budget
/num_queues
;
2577 left_over_budget
= 0;
2579 for_each_bit(i
, &gfargrp
->rx_bit_map
, priv
->num_rx_queues
) {
2580 if (test_bit(i
, &serviced_queues
))
2582 rx_queue
= priv
->rx_queue
[i
];
2583 tx_queue
= priv
->tx_queue
[rx_queue
->qindex
];
2585 tx_cleaned
+= gfar_clean_tx_ring(tx_queue
);
2586 rx_cleaned_per_queue
= gfar_clean_rx_ring(rx_queue
,
2588 rx_cleaned
+= rx_cleaned_per_queue
;
2589 if(rx_cleaned_per_queue
< budget_per_queue
) {
2590 left_over_budget
= left_over_budget
+
2591 (budget_per_queue
- rx_cleaned_per_queue
);
2592 set_bit(i
, &serviced_queues
);
2601 if (rx_cleaned
< budget
) {
2602 napi_complete(napi
);
2604 /* Clear the halt bit in RSTAT */
2605 gfar_write(®s
->rstat
, gfargrp
->rstat
);
2607 gfar_write(®s
->imask
, IMASK_DEFAULT
);
2609 /* If we are coalescing interrupts, update the timer */
2610 /* Otherwise, clear it */
2611 gfar_configure_coalescing(priv
,
2612 gfargrp
->rx_bit_map
, gfargrp
->tx_bit_map
);
2618 #ifdef CONFIG_NET_POLL_CONTROLLER
2620 * Polling 'interrupt' - used by things like netconsole to send skbs
2621 * without having to re-enable interrupts. It's not called while
2622 * the interrupt routine is executing.
2624 static void gfar_netpoll(struct net_device
*dev
)
2626 struct gfar_private
*priv
= netdev_priv(dev
);
2629 /* If the device has multiple interrupts, run tx/rx */
2630 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
2631 for (i
= 0; i
< priv
->num_grps
; i
++) {
2632 disable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2633 disable_irq(priv
->gfargrp
[i
].interruptReceive
);
2634 disable_irq(priv
->gfargrp
[i
].interruptError
);
2635 gfar_interrupt(priv
->gfargrp
[i
].interruptTransmit
,
2637 enable_irq(priv
->gfargrp
[i
].interruptError
);
2638 enable_irq(priv
->gfargrp
[i
].interruptReceive
);
2639 enable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2642 for (i
= 0; i
< priv
->num_grps
; i
++) {
2643 disable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2644 gfar_interrupt(priv
->gfargrp
[i
].interruptTransmit
,
2646 enable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2651 /* The interrupt handler for devices with one interrupt */
2652 static irqreturn_t
gfar_interrupt(int irq
, void *grp_id
)
2654 struct gfar_priv_grp
*gfargrp
= grp_id
;
2656 /* Save ievent for future reference */
2657 u32 events
= gfar_read(&gfargrp
->regs
->ievent
);
2659 /* Check for reception */
2660 if (events
& IEVENT_RX_MASK
)
2661 gfar_receive(irq
, grp_id
);
2663 /* Check for transmit completion */
2664 if (events
& IEVENT_TX_MASK
)
2665 gfar_transmit(irq
, grp_id
);
2667 /* Check for errors */
2668 if (events
& IEVENT_ERR_MASK
)
2669 gfar_error(irq
, grp_id
);
2674 /* Called every time the controller might need to be made
2675 * aware of new link state. The PHY code conveys this
2676 * information through variables in the phydev structure, and this
2677 * function converts those variables into the appropriate
2678 * register values, and can bring down the device if needed.
2680 static void adjust_link(struct net_device
*dev
)
2682 struct gfar_private
*priv
= netdev_priv(dev
);
2683 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2684 unsigned long flags
;
2685 struct phy_device
*phydev
= priv
->phydev
;
2688 local_irq_save(flags
);
2692 u32 tempval
= gfar_read(®s
->maccfg2
);
2693 u32 ecntrl
= gfar_read(®s
->ecntrl
);
2695 /* Now we make sure that we can be in full duplex mode.
2696 * If not, we operate in half-duplex mode. */
2697 if (phydev
->duplex
!= priv
->oldduplex
) {
2699 if (!(phydev
->duplex
))
2700 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
2702 tempval
|= MACCFG2_FULL_DUPLEX
;
2704 priv
->oldduplex
= phydev
->duplex
;
2707 if (phydev
->speed
!= priv
->oldspeed
) {
2709 switch (phydev
->speed
) {
2712 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
2714 ecntrl
&= ~(ECNTRL_R100
);
2719 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
2721 /* Reduced mode distinguishes
2722 * between 10 and 100 */
2723 if (phydev
->speed
== SPEED_100
)
2724 ecntrl
|= ECNTRL_R100
;
2726 ecntrl
&= ~(ECNTRL_R100
);
2729 if (netif_msg_link(priv
))
2731 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2732 dev
->name
, phydev
->speed
);
2736 priv
->oldspeed
= phydev
->speed
;
2739 gfar_write(®s
->maccfg2
, tempval
);
2740 gfar_write(®s
->ecntrl
, ecntrl
);
2742 if (!priv
->oldlink
) {
2746 } else if (priv
->oldlink
) {
2750 priv
->oldduplex
= -1;
2753 if (new_state
&& netif_msg_link(priv
))
2754 phy_print_status(phydev
);
2756 local_irq_restore(flags
);
2759 /* Update the hash table based on the current list of multicast
2760 * addresses we subscribe to. Also, change the promiscuity of
2761 * the device based on the flags (this function is called
2762 * whenever dev->flags is changed */
2763 static void gfar_set_multi(struct net_device
*dev
)
2765 struct dev_mc_list
*mc_ptr
;
2766 struct gfar_private
*priv
= netdev_priv(dev
);
2767 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2770 if (dev
->flags
& IFF_PROMISC
) {
2771 /* Set RCTRL to PROM */
2772 tempval
= gfar_read(®s
->rctrl
);
2773 tempval
|= RCTRL_PROM
;
2774 gfar_write(®s
->rctrl
, tempval
);
2776 /* Set RCTRL to not PROM */
2777 tempval
= gfar_read(®s
->rctrl
);
2778 tempval
&= ~(RCTRL_PROM
);
2779 gfar_write(®s
->rctrl
, tempval
);
2782 if (dev
->flags
& IFF_ALLMULTI
) {
2783 /* Set the hash to rx all multicast frames */
2784 gfar_write(®s
->igaddr0
, 0xffffffff);
2785 gfar_write(®s
->igaddr1
, 0xffffffff);
2786 gfar_write(®s
->igaddr2
, 0xffffffff);
2787 gfar_write(®s
->igaddr3
, 0xffffffff);
2788 gfar_write(®s
->igaddr4
, 0xffffffff);
2789 gfar_write(®s
->igaddr5
, 0xffffffff);
2790 gfar_write(®s
->igaddr6
, 0xffffffff);
2791 gfar_write(®s
->igaddr7
, 0xffffffff);
2792 gfar_write(®s
->gaddr0
, 0xffffffff);
2793 gfar_write(®s
->gaddr1
, 0xffffffff);
2794 gfar_write(®s
->gaddr2
, 0xffffffff);
2795 gfar_write(®s
->gaddr3
, 0xffffffff);
2796 gfar_write(®s
->gaddr4
, 0xffffffff);
2797 gfar_write(®s
->gaddr5
, 0xffffffff);
2798 gfar_write(®s
->gaddr6
, 0xffffffff);
2799 gfar_write(®s
->gaddr7
, 0xffffffff);
2804 /* zero out the hash */
2805 gfar_write(®s
->igaddr0
, 0x0);
2806 gfar_write(®s
->igaddr1
, 0x0);
2807 gfar_write(®s
->igaddr2
, 0x0);
2808 gfar_write(®s
->igaddr3
, 0x0);
2809 gfar_write(®s
->igaddr4
, 0x0);
2810 gfar_write(®s
->igaddr5
, 0x0);
2811 gfar_write(®s
->igaddr6
, 0x0);
2812 gfar_write(®s
->igaddr7
, 0x0);
2813 gfar_write(®s
->gaddr0
, 0x0);
2814 gfar_write(®s
->gaddr1
, 0x0);
2815 gfar_write(®s
->gaddr2
, 0x0);
2816 gfar_write(®s
->gaddr3
, 0x0);
2817 gfar_write(®s
->gaddr4
, 0x0);
2818 gfar_write(®s
->gaddr5
, 0x0);
2819 gfar_write(®s
->gaddr6
, 0x0);
2820 gfar_write(®s
->gaddr7
, 0x0);
2822 /* If we have extended hash tables, we need to
2823 * clear the exact match registers to prepare for
2825 if (priv
->extended_hash
) {
2826 em_num
= GFAR_EM_NUM
+ 1;
2827 gfar_clear_exact_match(dev
);
2834 if (dev
->mc_count
== 0)
2837 /* Parse the list, and set the appropriate bits */
2838 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
2840 gfar_set_mac_for_addr(dev
, idx
,
2844 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
2852 /* Clears each of the exact match registers to zero, so they
2853 * don't interfere with normal reception */
2854 static void gfar_clear_exact_match(struct net_device
*dev
)
2857 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
2859 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
2860 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
2863 /* Set the appropriate hash bit for the given addr */
2864 /* The algorithm works like so:
2865 * 1) Take the Destination Address (ie the multicast address), and
2866 * do a CRC on it (little endian), and reverse the bits of the
2868 * 2) Use the 8 most significant bits as a hash into a 256-entry
2869 * table. The table is controlled through 8 32-bit registers:
2870 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2871 * gaddr7. This means that the 3 most significant bits in the
2872 * hash index which gaddr register to use, and the 5 other bits
2873 * indicate which bit (assuming an IBM numbering scheme, which
2874 * for PowerPC (tm) is usually the case) in the register holds
2876 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
2879 struct gfar_private
*priv
= netdev_priv(dev
);
2880 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
2881 int width
= priv
->hash_width
;
2882 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
2883 u8 whichreg
= result
>> (32 - width
+ 5);
2884 u32 value
= (1 << (31-whichbit
));
2886 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
2888 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
2894 /* There are multiple MAC Address register pairs on some controllers
2895 * This function sets the numth pair to a given address
2897 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
2899 struct gfar_private
*priv
= netdev_priv(dev
);
2900 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2902 char tmpbuf
[MAC_ADDR_LEN
];
2904 u32 __iomem
*macptr
= ®s
->macstnaddr1
;
2908 /* Now copy it into the mac registers backwards, cuz */
2909 /* little endian is silly */
2910 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
2911 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
2913 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
2915 tempval
= *((u32
*) (tmpbuf
+ 4));
2917 gfar_write(macptr
+1, tempval
);
2920 /* GFAR error interrupt handler */
2921 static irqreturn_t
gfar_error(int irq
, void *grp_id
)
2923 struct gfar_priv_grp
*gfargrp
= grp_id
;
2924 struct gfar __iomem
*regs
= gfargrp
->regs
;
2925 struct gfar_private
*priv
= gfargrp
->priv
;
2926 struct net_device
*dev
= priv
->ndev
;
2928 /* Save ievent for future reference */
2929 u32 events
= gfar_read(®s
->ievent
);
2932 gfar_write(®s
->ievent
, events
& IEVENT_ERR_MASK
);
2934 /* Magic Packet is not an error. */
2935 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
2936 (events
& IEVENT_MAG
))
2937 events
&= ~IEVENT_MAG
;
2940 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
2941 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2942 dev
->name
, events
, gfar_read(®s
->imask
));
2944 /* Update the error counters */
2945 if (events
& IEVENT_TXE
) {
2946 dev
->stats
.tx_errors
++;
2948 if (events
& IEVENT_LC
)
2949 dev
->stats
.tx_window_errors
++;
2950 if (events
& IEVENT_CRL
)
2951 dev
->stats
.tx_aborted_errors
++;
2952 if (events
& IEVENT_XFUN
) {
2953 unsigned long flags
;
2955 if (netif_msg_tx_err(priv
))
2956 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
2957 "packet dropped.\n", dev
->name
);
2958 dev
->stats
.tx_dropped
++;
2959 priv
->extra_stats
.tx_underrun
++;
2961 local_irq_save(flags
);
2964 /* Reactivate the Tx Queues */
2965 gfar_write(®s
->tstat
, gfargrp
->tstat
);
2968 local_irq_restore(flags
);
2970 if (netif_msg_tx_err(priv
))
2971 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
2973 if (events
& IEVENT_BSY
) {
2974 dev
->stats
.rx_errors
++;
2975 priv
->extra_stats
.rx_bsy
++;
2977 gfar_receive(irq
, grp_id
);
2979 if (netif_msg_rx_err(priv
))
2980 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
2981 dev
->name
, gfar_read(®s
->rstat
));
2983 if (events
& IEVENT_BABR
) {
2984 dev
->stats
.rx_errors
++;
2985 priv
->extra_stats
.rx_babr
++;
2987 if (netif_msg_rx_err(priv
))
2988 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
2990 if (events
& IEVENT_EBERR
) {
2991 priv
->extra_stats
.eberr
++;
2992 if (netif_msg_rx_err(priv
))
2993 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
2995 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
2996 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
2998 if (events
& IEVENT_BABT
) {
2999 priv
->extra_stats
.tx_babt
++;
3000 if (netif_msg_tx_err(priv
))
3001 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
3006 static struct of_device_id gfar_match
[] =
3010 .compatible
= "gianfar",
3013 .compatible
= "fsl,etsec2",
3017 MODULE_DEVICE_TABLE(of
, gfar_match
);
3019 /* Structure for a device driver */
3020 static struct of_platform_driver gfar_driver
= {
3021 .name
= "fsl-gianfar",
3022 .match_table
= gfar_match
,
3024 .probe
= gfar_probe
,
3025 .remove
= gfar_remove
,
3026 .suspend
= gfar_legacy_suspend
,
3027 .resume
= gfar_legacy_resume
,
3028 .driver
.pm
= GFAR_PM_OPS
,
3031 static int __init
gfar_init(void)
3033 return of_register_platform_driver(&gfar_driver
);
3036 static void __exit
gfar_exit(void)
3038 of_unregister_platform_driver(&gfar_driver
);
3041 module_init(gfar_init
);
3042 module_exit(gfar_exit
);