drivers/usb/chipidea/ci.h

   1 /*
   2  * ci.h - common structures, functions, and macros of the ChipIdea driver
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
  14 #define __DRIVERS_USB_CHIPIDEA_CI_H
  15
  16 #include <linux/list.h>
  17 #include <linux/irqreturn.h>
  18 #include <linux/usb.h>
  19 #include <linux/usb/gadget.h>
  20
  21 /******************************************************************************
  22  * DEFINE
  23  *****************************************************************************/
  24 #define TD_PAGE_COUNT      5
  25 #define CI13XXX_PAGE_SIZE  4096ul /* page size for TD's */
  26 #define ENDPT_MAX          32
  27
  28 /******************************************************************************
  29  * STRUCTURES
  30  *****************************************************************************/
  31 /**
  32  * struct ci13xxx_ep - endpoint representation
  33  * @ep: endpoint structure for gadget drivers
  34  * @dir: endpoint direction (TX/RX)
  35  * @num: endpoint number
  36  * @type: endpoint type
  37  * @name: string description of the endpoint
  38  * @qh: queue head for this endpoint
  39  * @wedge: is the endpoint wedged
  40  * @ci: pointer to the controller
  41  * @lock: pointer to controller's spinlock
  42  * @td_pool: pointer to controller's TD pool
  43  */
  44 struct ci13xxx_ep {
  45         struct usb_ep                           ep;
  46         u8                                      dir;
  47         u8                                      num;
  48         u8                                      type;
  49         char                                    name[16];
  50         struct {
  51                 struct list_head        queue;
  52                 struct ci13xxx_qh       *ptr;
  53                 dma_addr_t              dma;
  54         }                                       qh;
  55         int                                     wedge;
  56
  57         /* global resources */
  58         struct ci13xxx                          *ci;
  59         spinlock_t                              *lock;
  60         struct dma_pool                         *td_pool;
  61 };
  62
  63 enum ci_role {
  64         CI_ROLE_HOST = 0,
  65         CI_ROLE_GADGET,
  66         CI_ROLE_END,
  67 };
  68
  69 /**
  70  * struct ci_role_driver - host/gadget role driver
  71  * start: start this role
  72  * stop: stop this role
  73  * irq: irq handler for this role
  74  * name: role name string (host/gadget)
  75  */
  76 struct ci_role_driver {
  77         int             (*start)(struct ci13xxx *);
  78         void            (*stop)(struct ci13xxx *);
  79         irqreturn_t     (*irq)(struct ci13xxx *);
  80         const char      *name;
  81 };
  82
  83 /**
  84  * struct hw_bank - hardware register mapping representation
  85  * @lpm: set if the device is LPM capable
  86  * @phys: physical address of the controller's registers
  87  * @abs: absolute address of the beginning of register window
  88  * @cap: capability registers
  89  * @op: operational registers
  90  * @size: size of the register window
  91  * @regmap: register lookup table
  92  */
  93 struct hw_bank {
  94         unsigned        lpm;
  95         resource_size_t phys;
  96         void __iomem    *abs;
  97         void __iomem    *cap;
  98         void __iomem    *op;
  99         size_t          size;
 100         void __iomem    **regmap;
 101 };
 102
 103 /**
 104  * struct ci13xxx - chipidea device representation
 105  * @dev: pointer to parent device
 106  * @lock: access synchronization
 107  * @hw_bank: hardware register mapping
 108  * @irq: IRQ number
 109  * @roles: array of supported roles for this controller
 110  * @role: current role
 111  * @is_otg: if the device is otg-capable
 112  * @work: work for role changing
 113  * @wq: workqueue thread
 114  * @qh_pool: allocation pool for queue heads
 115  * @td_pool: allocation pool for transfer descriptors
 116  * @gadget: device side representation for peripheral controller
 117  * @driver: gadget driver
 118  * @hw_ep_max: total number of endpoints supported by hardware
 119  * @ci13xxx_ep: array of endpoints
 120  * @ep0_dir: ep0 direction
 121  * @ep0out: pointer to ep0 OUT endpoint
 122  * @ep0in: pointer to ep0 IN endpoint
 123  * @status: ep0 status request
 124  * @setaddr: if we should set the address on status completion
 125  * @address: usb address received from the host
 126  * @remote_wakeup: host-enabled remote wakeup
 127  * @suspended: suspended by host
 128  * @test_mode: the selected test mode
 129  * @platdata: platform specific information supplied by parent device
 130  * @vbus_active: is VBUS active
 131  * @transceiver: pointer to USB PHY, if any
 132  * @hcd: pointer to usb_hcd for ehci host driver
 133  * @debugfs: root dentry for this controller in debugfs
 134  */
 135 struct ci13xxx {
 136         struct device                   *dev;
 137         spinlock_t                      lock;
 138         struct hw_bank                  hw_bank;
 139         int                             irq;
 140         struct ci_role_driver           *roles[CI_ROLE_END];
 141         enum ci_role                    role;
 142         bool                            is_otg;
 143         struct work_struct              work;
 144         struct workqueue_struct         *wq;
 145
 146         struct dma_pool                 *qh_pool;
 147         struct dma_pool                 *td_pool;
 148
 149         struct usb_gadget               gadget;
 150         struct usb_gadget_driver        *driver;
 151         unsigned                        hw_ep_max;
 152         struct ci13xxx_ep               ci13xxx_ep[ENDPT_MAX];
 153         u32                             ep0_dir;
 154         struct ci13xxx_ep               *ep0out, *ep0in;
 155
 156         struct usb_request              *status;
 157         bool                            setaddr;
 158         u8                              address;
 159         u8                              remote_wakeup;
 160         u8                              suspended;
 161         u8                              test_mode;
 162
 163         struct ci13xxx_platform_data    *platdata;
 164         int                             vbus_active;
 165         /* FIXME: some day, we'll not use global phy */
 166         bool                            global_phy;
 167         struct usb_phy                  *transceiver;
 168         struct usb_hcd                  *hcd;
 169         struct dentry                   *debugfs;
 170 };
 171
 172 static inline struct ci_role_driver *ci_role(struct ci13xxx *ci)
 173 {
 174         BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
 175         return ci->roles[ci->role];
 176 }
 177
 178 static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role)
 179 {
 180         int ret;
 181
 182         if (role >= CI_ROLE_END)
 183                 return -EINVAL;
 184
 185         if (!ci->roles[role])
 186                 return -ENXIO;
 187
 188         ret = ci->roles[role]->start(ci);
 189         if (!ret)
 190                 ci->role = role;
 191         return ret;
 192 }
 193
 194 static inline void ci_role_stop(struct ci13xxx *ci)
 195 {
 196         enum ci_role role = ci->role;
 197
 198         if (role == CI_ROLE_END)
 199                 return;
 200
 201         ci->role = CI_ROLE_END;
 202
 203         ci->roles[role]->stop(ci);
 204 }
 205
 206 /******************************************************************************
 207  * REGISTERS
 208  *****************************************************************************/
 209 /* register size */
 210 #define REG_BITS   (32)
 211
 212 /* register indices */
 213 enum ci13xxx_regs {
 214         CAP_CAPLENGTH,
 215         CAP_HCCPARAMS,
 216         CAP_DCCPARAMS,
 217         CAP_TESTMODE,
 218         CAP_LAST = CAP_TESTMODE,
 219         OP_USBCMD,
 220         OP_USBSTS,
 221         OP_USBINTR,
 222         OP_DEVICEADDR,
 223         OP_ENDPTLISTADDR,
 224         OP_PORTSC,
 225         OP_DEVLC,
 226         OP_OTGSC,
 227         OP_USBMODE,
 228         OP_ENDPTSETUPSTAT,
 229         OP_ENDPTPRIME,
 230         OP_ENDPTFLUSH,
 231         OP_ENDPTSTAT,
 232         OP_ENDPTCOMPLETE,
 233         OP_ENDPTCTRL,
 234         /* endptctrl1..15 follow */
 235         OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
 236 };
 237
 238 /**
 239  * hw_read: reads from a hw register
 240  * @reg:  register index
 241  * @mask: bitfield mask
 242  *
 243  * This function returns register contents
 244  */
 245 static inline u32 hw_read(struct ci13xxx *ci, enum ci13xxx_regs reg, u32 mask)
 246 {
 247         return ioread32(ci->hw_bank.regmap[reg]) & mask;
 248 }
 249
 250 /**
 251  * hw_write: writes to a hw register
 252  * @reg:  register index
 253  * @mask: bitfield mask
 254  * @data: new value
 255  */
 256 static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
 257                             u32 mask, u32 data)
 258 {
 259         if (~mask)
 260                 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
 261                         | (data & mask);
 262
 263         iowrite32(data, ci->hw_bank.regmap[reg]);
 264 }
 265
 266 /**
 267  * hw_test_and_clear: tests & clears a hw register
 268  * @reg:  register index
 269  * @mask: bitfield mask
 270  *
 271  * This function returns register contents
 272  */
 273 static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg,
 274                                     u32 mask)
 275 {
 276         u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
 277
 278         iowrite32(val, ci->hw_bank.regmap[reg]);
 279         return val;
 280 }
 281
 282 /**
 283  * hw_test_and_write: tests & writes a hw register
 284  * @reg:  register index
 285  * @mask: bitfield mask
 286  * @data: new value
 287  *
 288  * This function returns register contents
 289  */
 290 static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
 291                                     u32 mask, u32 data)
 292 {
 293         u32 val = hw_read(ci, reg, ~0);
 294
 295         hw_write(ci, reg, mask, data);
 296         return (val & mask) >> __ffs(mask);
 297 }
 298
 299 int hw_device_reset(struct ci13xxx *ci, u32 mode);
 300
 301 int hw_port_test_set(struct ci13xxx *ci, u8 mode);
 302
 303 u8 hw_port_test_get(struct ci13xxx *ci);
 304
 305 #endif  /* __DRIVERS_USB_CHIPIDEA_CI_H */