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Blackfin: remove CONFIG_DEBUG_VERBOSE from trace.c
[linux-2.6/btrfs-unstable.git] / arch / blackfin / include / asm / def_LPBlackfin.h
blobf342ff0319df8f86d47aed829d5cd2543828826e
1 /*
2 * Blackfin core register bit & address definitions
3 *
4 * Copyright 2005-2008 Analog Devices Inc.
5 *
6 * Licensed under the ADI BSD license or GPL-2 (or later).
7 */
8
9 #ifndef _DEF_LPBLACKFIN_H
10 #define _DEF_LPBLACKFIN_H
11
12 #include <mach/anomaly.h>
13
14 #define MK_BMSK_(x) (1<<x)
15 #define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask))
16 #define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask))
17
18 #ifndef __ASSEMBLY__
19
20 #include <linux/types.h>
21
22 #if ANOMALY_05000198
23 # define NOP_PAD_ANOMALY_05000198 "nop;"
24 #else
25 # define NOP_PAD_ANOMALY_05000198
26 #endif
27
28 #define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
29 u32 __v; \
30 __asm__ __volatile__( \
31 NOP_PAD_ANOMALY_05000198 \
32 "%0 = " #asm_size "[%1]" #asm_ext ";" \
33 : "=d" (__v) \
34 : "a" (addr) \
35 ); \
36 __v; })
37 #define _bfin_writeX(addr, val, size, asm_size) \
38 __asm__ __volatile__( \
39 NOP_PAD_ANOMALY_05000198 \
40 #asm_size "[%0] = %1;" \
41 : \
42 : "a" (addr), "d" ((u##size)(val)) \
43 : "memory" \
44 )
45
46 #define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
47 #define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
48 #define bfin_read32(addr) _bfin_readX(addr, 32, , )
49 #define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
50 #define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
51 #define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
52
53 #endif /* __ASSEMBLY__ */
54
55 /**************************************************
56 * System Register Bits
57 **************************************************/
58
59 /**************************************************
60 * ASTAT register
61 **************************************************/
62
63 /* definitions of ASTAT bit positions*/
64
65 /*Result of last ALU0 or shifter operation is zero*/
66 #define ASTAT_AZ_P 0x00000000
67 /*Result of last ALU0 or shifter operation is negative*/
68 #define ASTAT_AN_P 0x00000001
69 /*Condition Code, used for holding comparison results*/
70 #define ASTAT_CC_P 0x00000005
71 /*Quotient Bit*/
72 #define ASTAT_AQ_P 0x00000006
73 /*Rounding mode, set for biased, clear for unbiased*/
74 #define ASTAT_RND_MOD_P 0x00000008
75 /*Result of last ALU0 operation generated a carry*/
76 #define ASTAT_AC0_P 0x0000000C
77 /*Result of last ALU0 operation generated a carry*/
78 #define ASTAT_AC0_COPY_P 0x00000002
79 /*Result of last ALU1 operation generated a carry*/
80 #define ASTAT_AC1_P 0x0000000D
81 /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
82 #define ASTAT_AV0_P 0x00000010
83 /*Sticky version of ASTAT_AV0 */
84 #define ASTAT_AV0S_P 0x00000011
85 /*Result of last MAC1 operation overflowed, sticky for MAC*/
86 #define ASTAT_AV1_P 0x00000012
87 /*Sticky version of ASTAT_AV1 */
88 #define ASTAT_AV1S_P 0x00000013
89 /*Result of last ALU0 or MAC0 operation overflowed*/
90 #define ASTAT_V_P 0x00000018
91 /*Result of last ALU0 or MAC0 operation overflowed*/
92 #define ASTAT_V_COPY_P 0x00000003
93 /*Sticky version of ASTAT_V*/
94 #define ASTAT_VS_P 0x00000019
95
96 /* Masks */
97
98 /*Result of last ALU0 or shifter operation is zero*/
99 #define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
100 /*Result of last ALU0 or shifter operation is negative*/
101 #define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
102 /*Result of last ALU0 operation generated a carry*/
103 #define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
104 /*Result of last ALU0 operation generated a carry*/
105 #define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
106 /*Result of last ALU0 operation generated a carry*/
107 #define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
108 /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
109 #define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
110 /*Result of last MAC1 operation overflowed, sticky for MAC*/
111 #define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
112 /*Condition Code, used for holding comparison results*/
113 #define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
114 /*Quotient Bit*/
115 #define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
116 /*Rounding mode, set for biased, clear for unbiased*/
117 #define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
118 /*Overflow Bit*/
119 #define ASTAT_V MK_BMSK_(ASTAT_V_P)
120 /*Overflow Bit*/
121 #define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
122
123 /**************************************************
124 * SEQSTAT register
125 **************************************************/
126
127 /* Bit Positions */
128 #define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
129 #define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
130 #define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
131 #define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
132 #define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
133 #define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
134 #define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
135 * set by IDLE instruction.
136 */
137 #define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
138 * reset was a software reset
139 * (=1)
140 */
141 #define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
142 #define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
143 #define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
144 #define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
145 #define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
146 /* Masks */
147 /* Exception cause */
148 #define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
149 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
150 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
151 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
152 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
153 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
154 0)
155
156 /* Indicates whether the last reset was a software reset (=1) */
157 #define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
158
159 /* Last hw error cause */
160 #define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
161 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
162 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
163 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
164 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
165 0)
166
167 /* Translate bits to something useful */
168
169 /* Last hw error cause */
170 #define SEQSTAT_HWERRCAUSE_SHIFT (14)
171 #define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
172 #define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
173 #define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
174 #define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
175
176 /**************************************************
177 * SYSCFG register
178 **************************************************/
179
180 /* Bit Positions */
181 #define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
182 * set it forces an exception
183 * for each instruction executed
184 */
185 #define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
186 #define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
187
188 /* Masks */
189
190 /* Supervisor single step, when set it forces an exception for each
191 *instruction executed
192 */
193 #define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
194 /* Enable cycle counter (=1) */
195 #define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
196 /* Self Nesting Interrupt Enable */
197 #define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
198 /* Backward-compatibility for typos in prior releases */
199 #define SYSCFG_SSSSTEP SYSCFG_SSSTEP
200 #define SYSCFG_CCCEN SYSCFG_CCEN
201
202 /****************************************************
203 * Core MMR Register Map
204 ****************************************************/
205
206 /* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
207
208 #define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
209 #define DMEM_CONTROL 0xFFE00004 /* Data memory control */
210 #define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
211 * Buffer Status
212 */
213 #define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
214 #define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
215 * Buffer Fault Address
216 */
217 #define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
218 * Buffer 0
219 */
220 #define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
221 * Buffer 1
222 */
223 #define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
224 * Buffer 2
225 */
226 #define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
227 * Lookaside Buffer 3
228 */
229 #define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
230 * Lookaside Buffer 4
231 */
232 #define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
233 * Lookaside Buffer 5
234 */
235 #define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
236 * Lookaside Buffer 6
237 */
238 #define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
239 * Lookaside Buffer 7
240 */
241 #define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
242 * Lookaside Buffer 8
243 */
244 #define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
245 * Lookaside Buffer 9
246 */
247 #define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
248 * Lookaside Buffer 10
249 */
250 #define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
251 * Lookaside Buffer 11
252 */
253 #define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
254 * Lookaside Buffer 12
255 */
256 #define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
257 * Lookaside Buffer 13
258 */
259 #define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
260 * Lookaside Buffer 14
261 */
262 #define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
263 * Lookaside Buffer 15
264 */
265 #define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
266 #define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
267 #define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
268 #define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
269 #define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
270 #define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
271 #define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
272 #define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
273 #define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
274 #define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
275 #define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
276 #define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
277 #define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
278 #define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
279 #define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
280 #define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
281 #define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
282
283 #define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
284 #define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
285 #define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
286
287 /* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
288
289 #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
290 #define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
291 #define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
292 #define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
293 #define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
294 #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
295 * Protection Lookaside Buffer 0
296 */
297 #define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
298 * Protection Lookaside Buffer 1
299 */
300 #define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
301 * Protection Lookaside Buffer 2
302 */
303 #define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
304 * Protection Lookaside Buffer 3
305 */
306 #define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
307 * Protection Lookaside Buffer 4
308 */
309 #define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
310 * Protection Lookaside Buffer 5
311 */
312 #define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
313 * Protection Lookaside Buffer 6
314 */
315 #define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
316 * Protection Lookaside Buffer 7
317 */
318 #define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
319 * Protection Lookaside Buffer 8
320 */
321 #define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
322 * Protection Lookaside Buffer 9
323 */
324 #define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
325 * Protection Lookaside Buffer 10
326 */
327 #define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
328 * Protection Lookaside Buffer 11
329 */
330 #define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
331 * Protection Lookaside Buffer 12
332 */
333 #define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
334 * Protection Lookaside Buffer 13
335 */
336 #define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
337 * Protection Lookaside Buffer 14
338 */
339 #define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
340 * Protection Lookaside Buffer 15
341 */
342 #define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
343 #define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
344 #define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
345 #define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
346 #define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
347 #define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
348 #define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
349 #define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
350 #define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
351 #define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
352 #define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
353 #define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
354 #define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
355 #define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
356 #define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
357 #define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
358 #define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
359 #define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
360 #define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
361
362 /* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
363
364 #define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
365 #define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
366 #define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
367 #define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
368 #define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
369 #define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
370 #define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
371 #define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
372 #define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
373 #define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
374 #define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
375 #define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
376 #define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
377 #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
378 #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
379 #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
380 #define IMASK 0xFFE02104 /* Interrupt Mask Register */
381 #define IPEND 0xFFE02108 /* Interrupt Pending Register */
382 #define ILAT 0xFFE0210C /* Interrupt Latch Register */
383 #define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
384
385 /* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
386
387 #define TCNTL 0xFFE03000 /* Core Timer Control Register */
388 #define TPERIOD 0xFFE03004 /* Core Timer Period Register */
389 #define TSCALE 0xFFE03008 /* Core Timer Scale Register */
390 #define TCOUNT 0xFFE0300C /* Core Timer Count Register */
391
392 /* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
393 #define DSPID 0xFFE05000 /* DSP Processor ID Register for
394 * MP implementations
395 */
396
397 #define DBGSTAT 0xFFE05008 /* Debug Status Register */
398
399 /* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
400
401 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
402 #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
403 #define TBUF 0xFFE06100 /* Trace Buffer */
404
405 /* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
406
407 /* Watchpoint Instruction Address Control Register */
408 #define WPIACTL 0xFFE07000
409 /* Watchpoint Instruction Address Register 0 */
410 #define WPIA0 0xFFE07040
411 /* Watchpoint Instruction Address Register 1 */
412 #define WPIA1 0xFFE07044
413 /* Watchpoint Instruction Address Register 2 */
414 #define WPIA2 0xFFE07048
415 /* Watchpoint Instruction Address Register 3 */
416 #define WPIA3 0xFFE0704C
417 /* Watchpoint Instruction Address Register 4 */
418 #define WPIA4 0xFFE07050
419 /* Watchpoint Instruction Address Register 5 */
420 #define WPIA5 0xFFE07054
421 /* Watchpoint Instruction Address Count Register 0 */
422 #define WPIACNT0 0xFFE07080
423 /* Watchpoint Instruction Address Count Register 1 */
424 #define WPIACNT1 0xFFE07084
425 /* Watchpoint Instruction Address Count Register 2 */
426 #define WPIACNT2 0xFFE07088
427 /* Watchpoint Instruction Address Count Register 3 */
428 #define WPIACNT3 0xFFE0708C
429 /* Watchpoint Instruction Address Count Register 4 */
430 #define WPIACNT4 0xFFE07090
431 /* Watchpoint Instruction Address Count Register 5 */
432 #define WPIACNT5 0xFFE07094
433 /* Watchpoint Data Address Control Register */
434 #define WPDACTL 0xFFE07100
435 /* Watchpoint Data Address Register 0 */
436 #define WPDA0 0xFFE07140
437 /* Watchpoint Data Address Register 1 */
438 #define WPDA1 0xFFE07144
439 /* Watchpoint Data Address Count Value Register 0 */
440 #define WPDACNT0 0xFFE07180
441 /* Watchpoint Data Address Count Value Register 1 */
442 #define WPDACNT1 0xFFE07184
443 /* Watchpoint Status Register */
444 #define WPSTAT 0xFFE07200
445
446 /* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
447
448 /* Performance Monitor Control Register */
449 #define PFCTL 0xFFE08000
450 /* Performance Monitor Counter Register 0 */
451 #define PFCNTR0 0xFFE08100
452 /* Performance Monitor Counter Register 1 */
453 #define PFCNTR1 0xFFE08104
454
455 /****************************************************
456 * Core MMR Register Bits
457 ****************************************************/
458
459 /**************************************************
460 * EVT registers (ILAT, IMASK, and IPEND).
461 **************************************************/
462
463 /* Bit Positions */
464 #define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
465 #define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
466 #define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
467 #define EVT_EVX_P 0x00000003 /* Exception bit position */
468 #define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
469 #define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
470 #define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
471 #define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
472 #define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
473 #define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
474 #define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
475 #define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
476 #define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
477 #define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
478 #define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
479 #define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
480
481 /* Masks */
482 #define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
483 #define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
484 #define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
485 #define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
486 #define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
487 #define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
488 #define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
489 #define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
490 #define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
491 #define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
492 #define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
493 #define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
494 #define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
495 #define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
496 #define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
497 #define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
498
499 /**************************************************
500 * DMEM_CONTROL Register
501 **************************************************/
502 /* Bit Positions */
503 #define ENDM_P 0x00 /* (doesn't really exist) Enable
504 *Data Memory L1
505 */
506 #define DMCTL_ENDM_P ENDM_P /* "" (older define) */
507
508 #define ENDCPLB_P 0x01 /* Enable DCPLBS */
509 #define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
510 #define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
511 #define DMCTL_DMC0_P DMC0_P /* "" (older define) */
512 #define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
513 #define DMCTL_DMC1_P DMC1_P /* "" (older define) */
514 #define DCBS_P 0x04 /* L1 Data Cache Bank Select */
515 #define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
516 #define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
517
518 /* Masks */
519 #define ENDM 0x00000001 /* (doesn't really exist) Enable
520 * Data Memory L1
521 */
522 #define ENDCPLB 0x00000002 /* Enable DCPLB */
523 #define ASRAM_BSRAM 0x00000000
524 #define ACACHE_BSRAM 0x00000008
525 #define ACACHE_BCACHE 0x0000000C
526 #define DCBS 0x00000010 /* L1 Data Cache Bank Select */
527 #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
528 #define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
529
530 /* IMEM_CONTROL Register */
531 /* Bit Positions */
532 #define ENIM_P 0x00 /* Enable L1 Code Memory */
533 #define IMCTL_ENIM_P 0x00 /* "" (older define) */
534 #define ENICPLB_P 0x01 /* Enable ICPLB */
535 #define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
536 #define IMC_P 0x02 /* Enable */
537 #define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
538 * cache (0=SRAM)
539 */
540 #define ILOC0_P 0x03 /* Lock Way 0 */
541 #define ILOC1_P 0x04 /* Lock Way 1 */
542 #define ILOC2_P 0x05 /* Lock Way 2 */
543 #define ILOC3_P 0x06 /* Lock Way 3 */
544 #define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
545 * Priority
546 */
547 /* Masks */
548 #define ENIM 0x00000001 /* Enable L1 Code Memory */
549 #define ENICPLB 0x00000002 /* Enable ICPLB */
550 #define IMC 0x00000004 /* Configure L1 code memory as
551 * cache (0=SRAM)
552 */
553 #define ILOC0 0x00000008 /* Lock Way 0 */
554 #define ILOC1 0x00000010 /* Lock Way 1 */
555 #define ILOC2 0x00000020 /* Lock Way 2 */
556 #define ILOC3 0x00000040 /* Lock Way 3 */
557 #define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
558 * Priority
559 */
560
561 /* TCNTL Masks */
562 #define TMPWR 0x00000001 /* Timer Low Power Control,
563 * 0=low power mode, 1=active state
564 */
565 #define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
566 #define TAUTORLD 0x00000004 /* Timer auto reload */
567 #define TINT 0x00000008 /* Timer generated interrupt 0=no
568 * interrupt has been generated,
569 * 1=interrupt has been generated
570 * (sticky)
571 */
572
573 /* DCPLB_DATA and ICPLB_DATA Registers */
574 /* Bit Positions */
575 #define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
576 #define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
577 * locked
578 */
579 #define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
580 * allowed (user mode)
581 */
582 /* Masks */
583 #define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
584 #define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
585 * locked
586 */
587 #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
588 * allowed (user mode)
589 */
590
591 #define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
592 #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
593 #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
594 #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
595 #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
596 * mapped to L1
597 */
598 #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
599 * priority port
600 */
601 #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
602 * in L1
603 */
604 /* ICPLB_DATA only */
605 #define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
606 * 1=priority for non-replacement
607 */
608 /* DCPLB_DATA only */
609 #define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
610 * access allowed (user mode)
611 */
612 #define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
613 * access allowed (supervisor mode)
614 */
615 #define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
616 #define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
617 * write-through writes,
618 * 1= allocate cache lines on
619 * write-through writes.
620 */
621 #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
622
623 #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
624
625 /* TBUFCTL Masks */
626 #define TBUFPWR 0x0001
627 #define TBUFEN 0x0002
628 #define TBUFOVF 0x0004
629 #define TBUFCMPLP_SINGLE 0x0008
630 #define TBUFCMPLP_DOUBLE 0x0010
631 #define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
632
633 /* TBUFSTAT Masks */
634 #define TBUFCNT 0x001F
635
636 /* ITEST_COMMAND and DTEST_COMMAND Registers */
637 /* Masks */
638 #define TEST_READ 0x00000000 /* Read Access */
639 #define TEST_WRITE 0x00000002 /* Write Access */
640 #define TEST_TAG 0x00000000 /* Access TAG */
641 #define TEST_DATA 0x00000004 /* Access DATA */
642 #define TEST_DW0 0x00000000 /* Select Double Word 0 */
643 #define TEST_DW1 0x00000008 /* Select Double Word 1 */
644 #define TEST_DW2 0x00000010 /* Select Double Word 2 */
645 #define TEST_DW3 0x00000018 /* Select Double Word 3 */
646 #define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
647 #define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
648 #define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
649 #define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
650 #define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
651 #define TEST_WAY0 0x00000000 /* Access Way0 */
652 #define TEST_WAY1 0x04000000 /* Access Way1 */
653 /* ITEST_COMMAND only */
654 #define TEST_WAY2 0x08000000 /* Access Way2 */
655 #define TEST_WAY3 0x0C000000 /* Access Way3 */
656 /* DTEST_COMMAND only */
657 #define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
658 #define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
659
660 #endif /* _DEF_LPBLACKFIN_H */
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