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mmc: dw_mmc: Give a good reset after we give power
[linux-2.6/btrfs-unstable.git] / drivers / mmc / host / dw_mmc.c
blobd7fca9d799c49a5af759f491be9f5cce2daa64d9
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/of.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
41
42 #include "dw_mmc.h"
43
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
55
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
59 #ifdef CONFIG_MMC_DW_IDMAC
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
65 struct idmac_desc_64addr {
66 u32 des0; /* Control Descriptor */
67
68 u32 des1; /* Reserved */
69
70 u32 des2; /*Buffer sizes */
71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
72 ((d)->des2 = ((d)->des2 & 0x03ffe000) | ((s) & 0x1fff))
73
74 u32 des3; /* Reserved */
75
76 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
77 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
78
79 u32 des6; /* Lower 32-bits of Next Descriptor Address */
80 u32 des7; /* Upper 32-bits of Next Descriptor Address */
81 };
82
83 struct idmac_desc {
84 u32 des0; /* Control Descriptor */
85 #define IDMAC_DES0_DIC BIT(1)
86 #define IDMAC_DES0_LD BIT(2)
87 #define IDMAC_DES0_FD BIT(3)
88 #define IDMAC_DES0_CH BIT(4)
89 #define IDMAC_DES0_ER BIT(5)
90 #define IDMAC_DES0_CES BIT(30)
91 #define IDMAC_DES0_OWN BIT(31)
92
93 u32 des1; /* Buffer sizes */
94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
95 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
96
97 u32 des2; /* buffer 1 physical address */
98
99 u32 des3; /* buffer 2 physical address */
100 };
101 #endif /* CONFIG_MMC_DW_IDMAC */
102
103 static bool dw_mci_reset(struct dw_mci *host);
104 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
105
106 #if defined(CONFIG_DEBUG_FS)
107 static int dw_mci_req_show(struct seq_file *s, void *v)
108 {
109 struct dw_mci_slot *slot = s->private;
110 struct mmc_request *mrq;
111 struct mmc_command *cmd;
112 struct mmc_command *stop;
113 struct mmc_data *data;
114
115 /* Make sure we get a consistent snapshot */
116 spin_lock_bh(&slot->host->lock);
117 mrq = slot->mrq;
118
119 if (mrq) {
120 cmd = mrq->cmd;
121 data = mrq->data;
122 stop = mrq->stop;
123
124 if (cmd)
125 seq_printf(s,
126 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
127 cmd->opcode, cmd->arg, cmd->flags,
128 cmd->resp[0], cmd->resp[1], cmd->resp[2],
129 cmd->resp[2], cmd->error);
130 if (data)
131 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
132 data->bytes_xfered, data->blocks,
133 data->blksz, data->flags, data->error);
134 if (stop)
135 seq_printf(s,
136 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
137 stop->opcode, stop->arg, stop->flags,
138 stop->resp[0], stop->resp[1], stop->resp[2],
139 stop->resp[2], stop->error);
140 }
141
142 spin_unlock_bh(&slot->host->lock);
143
144 return 0;
145 }
146
147 static int dw_mci_req_open(struct inode *inode, struct file *file)
148 {
149 return single_open(file, dw_mci_req_show, inode->i_private);
150 }
151
152 static const struct file_operations dw_mci_req_fops = {
153 .owner = THIS_MODULE,
154 .open = dw_mci_req_open,
155 .read = seq_read,
156 .llseek = seq_lseek,
157 .release = single_release,
158 };
159
160 static int dw_mci_regs_show(struct seq_file *s, void *v)
161 {
162 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
163 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
164 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
165 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
166 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
167 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
168
169 return 0;
170 }
171
172 static int dw_mci_regs_open(struct inode *inode, struct file *file)
173 {
174 return single_open(file, dw_mci_regs_show, inode->i_private);
175 }
176
177 static const struct file_operations dw_mci_regs_fops = {
178 .owner = THIS_MODULE,
179 .open = dw_mci_regs_open,
180 .read = seq_read,
181 .llseek = seq_lseek,
182 .release = single_release,
183 };
184
185 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
186 {
187 struct mmc_host *mmc = slot->mmc;
188 struct dw_mci *host = slot->host;
189 struct dentry *root;
190 struct dentry *node;
191
192 root = mmc->debugfs_root;
193 if (!root)
194 return;
195
196 node = debugfs_create_file("regs", S_IRUSR, root, host,
197 &dw_mci_regs_fops);
198 if (!node)
199 goto err;
200
201 node = debugfs_create_file("req", S_IRUSR, root, slot,
202 &dw_mci_req_fops);
203 if (!node)
204 goto err;
205
206 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
207 if (!node)
208 goto err;
209
210 node = debugfs_create_x32("pending_events", S_IRUSR, root,
211 (u32 *)&host->pending_events);
212 if (!node)
213 goto err;
214
215 node = debugfs_create_x32("completed_events", S_IRUSR, root,
216 (u32 *)&host->completed_events);
217 if (!node)
218 goto err;
219
220 return;
221
222 err:
223 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
224 }
225 #endif /* defined(CONFIG_DEBUG_FS) */
226
227 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
228
229 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
230 {
231 struct mmc_data *data;
232 struct dw_mci_slot *slot = mmc_priv(mmc);
233 struct dw_mci *host = slot->host;
234 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
235 u32 cmdr;
236 cmd->error = -EINPROGRESS;
237
238 cmdr = cmd->opcode;
239
240 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
241 cmd->opcode == MMC_GO_IDLE_STATE ||
242 cmd->opcode == MMC_GO_INACTIVE_STATE ||
243 (cmd->opcode == SD_IO_RW_DIRECT &&
244 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
245 cmdr |= SDMMC_CMD_STOP;
246 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
247 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
248
249 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
250 u32 clk_en_a;
251
252 /* Special bit makes CMD11 not die */
253 cmdr |= SDMMC_CMD_VOLT_SWITCH;
254
255 /* Change state to continue to handle CMD11 weirdness */
256 WARN_ON(slot->host->state != STATE_SENDING_CMD);
257 slot->host->state = STATE_SENDING_CMD11;
258
259 /*
260 * We need to disable low power mode (automatic clock stop)
261 * while doing voltage switch so we don't confuse the card,
262 * since stopping the clock is a specific part of the UHS
263 * voltage change dance.
264 *
265 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
266 * unconditionally turned back on in dw_mci_setup_bus() if it's
267 * ever called with a non-zero clock. That shouldn't happen
268 * until the voltage change is all done.
269 */
270 clk_en_a = mci_readl(host, CLKENA);
271 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
272 mci_writel(host, CLKENA, clk_en_a);
273 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
274 SDMMC_CMD_PRV_DAT_WAIT, 0);
275 }
276
277 if (cmd->flags & MMC_RSP_PRESENT) {
278 /* We expect a response, so set this bit */
279 cmdr |= SDMMC_CMD_RESP_EXP;
280 if (cmd->flags & MMC_RSP_136)
281 cmdr |= SDMMC_CMD_RESP_LONG;
282 }
283
284 if (cmd->flags & MMC_RSP_CRC)
285 cmdr |= SDMMC_CMD_RESP_CRC;
286
287 data = cmd->data;
288 if (data) {
289 cmdr |= SDMMC_CMD_DAT_EXP;
290 if (data->flags & MMC_DATA_STREAM)
291 cmdr |= SDMMC_CMD_STRM_MODE;
292 if (data->flags & MMC_DATA_WRITE)
293 cmdr |= SDMMC_CMD_DAT_WR;
294 }
295
296 if (drv_data && drv_data->prepare_command)
297 drv_data->prepare_command(slot->host, &cmdr);
298
299 return cmdr;
300 }
301
302 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
303 {
304 struct mmc_command *stop;
305 u32 cmdr;
306
307 if (!cmd->data)
308 return 0;
309
310 stop = &host->stop_abort;
311 cmdr = cmd->opcode;
312 memset(stop, 0, sizeof(struct mmc_command));
313
314 if (cmdr == MMC_READ_SINGLE_BLOCK ||
315 cmdr == MMC_READ_MULTIPLE_BLOCK ||
316 cmdr == MMC_WRITE_BLOCK ||
317 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
318 cmdr == MMC_SEND_TUNING_BLOCK ||
319 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
320 stop->opcode = MMC_STOP_TRANSMISSION;
321 stop->arg = 0;
322 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
323 } else if (cmdr == SD_IO_RW_EXTENDED) {
324 stop->opcode = SD_IO_RW_DIRECT;
325 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
326 ((cmd->arg >> 28) & 0x7);
327 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
328 } else {
329 return 0;
330 }
331
332 cmdr = stop->opcode | SDMMC_CMD_STOP |
333 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
334
335 return cmdr;
336 }
337
338 static void dw_mci_start_command(struct dw_mci *host,
339 struct mmc_command *cmd, u32 cmd_flags)
340 {
341 host->cmd = cmd;
342 dev_vdbg(host->dev,
343 "start command: ARGR=0x%08x CMDR=0x%08x\n",
344 cmd->arg, cmd_flags);
345
346 mci_writel(host, CMDARG, cmd->arg);
347 wmb();
348
349 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
350 }
351
352 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
353 {
354 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
355 dw_mci_start_command(host, stop, host->stop_cmdr);
356 }
357
358 /* DMA interface functions */
359 static void dw_mci_stop_dma(struct dw_mci *host)
360 {
361 if (host->using_dma) {
362 host->dma_ops->stop(host);
363 host->dma_ops->cleanup(host);
364 }
365
366 /* Data transfer was stopped by the interrupt handler */
367 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
368 }
369
370 static int dw_mci_get_dma_dir(struct mmc_data *data)
371 {
372 if (data->flags & MMC_DATA_WRITE)
373 return DMA_TO_DEVICE;
374 else
375 return DMA_FROM_DEVICE;
376 }
377
378 #ifdef CONFIG_MMC_DW_IDMAC
379 static void dw_mci_dma_cleanup(struct dw_mci *host)
380 {
381 struct mmc_data *data = host->data;
382
383 if (data)
384 if (!data->host_cookie)
385 dma_unmap_sg(host->dev,
386 data->sg,
387 data->sg_len,
388 dw_mci_get_dma_dir(data));
389 }
390
391 static void dw_mci_idmac_reset(struct dw_mci *host)
392 {
393 u32 bmod = mci_readl(host, BMOD);
394 /* Software reset of DMA */
395 bmod |= SDMMC_IDMAC_SWRESET;
396 mci_writel(host, BMOD, bmod);
397 }
398
399 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
400 {
401 u32 temp;
402
403 /* Disable and reset the IDMAC interface */
404 temp = mci_readl(host, CTRL);
405 temp &= ~SDMMC_CTRL_USE_IDMAC;
406 temp |= SDMMC_CTRL_DMA_RESET;
407 mci_writel(host, CTRL, temp);
408
409 /* Stop the IDMAC running */
410 temp = mci_readl(host, BMOD);
411 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
412 temp |= SDMMC_IDMAC_SWRESET;
413 mci_writel(host, BMOD, temp);
414 }
415
416 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
417 {
418 struct mmc_data *data = host->data;
419
420 dev_vdbg(host->dev, "DMA complete\n");
421
422 host->dma_ops->cleanup(host);
423
424 /*
425 * If the card was removed, data will be NULL. No point in trying to
426 * send the stop command or waiting for NBUSY in this case.
427 */
428 if (data) {
429 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
430 tasklet_schedule(&host->tasklet);
431 }
432 }
433
434 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
435 unsigned int sg_len)
436 {
437 int i;
438 if (host->dma_64bit_address == 1) {
439 struct idmac_desc_64addr *desc = host->sg_cpu;
440
441 for (i = 0; i < sg_len; i++, desc++) {
442 unsigned int length = sg_dma_len(&data->sg[i]);
443 u64 mem_addr = sg_dma_address(&data->sg[i]);
444
445 /*
446 * Set the OWN bit and disable interrupts for this
447 * descriptor
448 */
449 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
450 IDMAC_DES0_CH;
451 /* Buffer length */
452 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length);
453
454 /* Physical address to DMA to/from */
455 desc->des4 = mem_addr & 0xffffffff;
456 desc->des5 = mem_addr >> 32;
457 }
458
459 /* Set first descriptor */
460 desc = host->sg_cpu;
461 desc->des0 |= IDMAC_DES0_FD;
462
463 /* Set last descriptor */
464 desc = host->sg_cpu + (i - 1) *
465 sizeof(struct idmac_desc_64addr);
466 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
467 desc->des0 |= IDMAC_DES0_LD;
468
469 } else {
470 struct idmac_desc *desc = host->sg_cpu;
471
472 for (i = 0; i < sg_len; i++, desc++) {
473 unsigned int length = sg_dma_len(&data->sg[i]);
474 u32 mem_addr = sg_dma_address(&data->sg[i]);
475
476 /*
477 * Set the OWN bit and disable interrupts for this
478 * descriptor
479 */
480 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
481 IDMAC_DES0_CH;
482 /* Buffer length */
483 IDMAC_SET_BUFFER1_SIZE(desc, length);
484
485 /* Physical address to DMA to/from */
486 desc->des2 = mem_addr;
487 }
488
489 /* Set first descriptor */
490 desc = host->sg_cpu;
491 desc->des0 |= IDMAC_DES0_FD;
492
493 /* Set last descriptor */
494 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
495 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
496 desc->des0 |= IDMAC_DES0_LD;
497 }
498
499 wmb();
500 }
501
502 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
503 {
504 u32 temp;
505
506 dw_mci_translate_sglist(host, host->data, sg_len);
507
508 /* Make sure to reset DMA in case we did PIO before this */
509 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
510 dw_mci_idmac_reset(host);
511
512 /* Select IDMAC interface */
513 temp = mci_readl(host, CTRL);
514 temp |= SDMMC_CTRL_USE_IDMAC;
515 mci_writel(host, CTRL, temp);
516
517 wmb();
518
519 /* Enable the IDMAC */
520 temp = mci_readl(host, BMOD);
521 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
522 mci_writel(host, BMOD, temp);
523
524 /* Start it running */
525 mci_writel(host, PLDMND, 1);
526 }
527
528 static int dw_mci_idmac_init(struct dw_mci *host)
529 {
530 int i;
531
532 if (host->dma_64bit_address == 1) {
533 struct idmac_desc_64addr *p;
534 /* Number of descriptors in the ring buffer */
535 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
536
537 /* Forward link the descriptor list */
538 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
539 i++, p++) {
540 p->des6 = (host->sg_dma +
541 (sizeof(struct idmac_desc_64addr) *
542 (i + 1))) & 0xffffffff;
543
544 p->des7 = (u64)(host->sg_dma +
545 (sizeof(struct idmac_desc_64addr) *
546 (i + 1))) >> 32;
547 /* Initialize reserved and buffer size fields to "0" */
548 p->des1 = 0;
549 p->des2 = 0;
550 p->des3 = 0;
551 }
552
553 /* Set the last descriptor as the end-of-ring descriptor */
554 p->des6 = host->sg_dma & 0xffffffff;
555 p->des7 = (u64)host->sg_dma >> 32;
556 p->des0 = IDMAC_DES0_ER;
557
558 } else {
559 struct idmac_desc *p;
560 /* Number of descriptors in the ring buffer */
561 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
562
563 /* Forward link the descriptor list */
564 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
565 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) *
566 (i + 1));
567
568 /* Set the last descriptor as the end-of-ring descriptor */
569 p->des3 = host->sg_dma;
570 p->des0 = IDMAC_DES0_ER;
571 }
572
573 dw_mci_idmac_reset(host);
574
575 if (host->dma_64bit_address == 1) {
576 /* Mask out interrupts - get Tx & Rx complete only */
577 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
578 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
579 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
580
581 /* Set the descriptor base address */
582 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
583 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
584
585 } else {
586 /* Mask out interrupts - get Tx & Rx complete only */
587 mci_writel(host, IDSTS, IDMAC_INT_CLR);
588 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
589 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
590
591 /* Set the descriptor base address */
592 mci_writel(host, DBADDR, host->sg_dma);
593 }
594
595 return 0;
596 }
597
598 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
599 .init = dw_mci_idmac_init,
600 .start = dw_mci_idmac_start_dma,
601 .stop = dw_mci_idmac_stop_dma,
602 .complete = dw_mci_idmac_complete_dma,
603 .cleanup = dw_mci_dma_cleanup,
604 };
605 #endif /* CONFIG_MMC_DW_IDMAC */
606
607 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
608 struct mmc_data *data,
609 bool next)
610 {
611 struct scatterlist *sg;
612 unsigned int i, sg_len;
613
614 if (!next && data->host_cookie)
615 return data->host_cookie;
616
617 /*
618 * We don't do DMA on "complex" transfers, i.e. with
619 * non-word-aligned buffers or lengths. Also, we don't bother
620 * with all the DMA setup overhead for short transfers.
621 */
622 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
623 return -EINVAL;
624
625 if (data->blksz & 3)
626 return -EINVAL;
627
628 for_each_sg(data->sg, sg, data->sg_len, i) {
629 if (sg->offset & 3 || sg->length & 3)
630 return -EINVAL;
631 }
632
633 sg_len = dma_map_sg(host->dev,
634 data->sg,
635 data->sg_len,
636 dw_mci_get_dma_dir(data));
637 if (sg_len == 0)
638 return -EINVAL;
639
640 if (next)
641 data->host_cookie = sg_len;
642
643 return sg_len;
644 }
645
646 static void dw_mci_pre_req(struct mmc_host *mmc,
647 struct mmc_request *mrq,
648 bool is_first_req)
649 {
650 struct dw_mci_slot *slot = mmc_priv(mmc);
651 struct mmc_data *data = mrq->data;
652
653 if (!slot->host->use_dma || !data)
654 return;
655
656 if (data->host_cookie) {
657 data->host_cookie = 0;
658 return;
659 }
660
661 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
662 data->host_cookie = 0;
663 }
664
665 static void dw_mci_post_req(struct mmc_host *mmc,
666 struct mmc_request *mrq,
667 int err)
668 {
669 struct dw_mci_slot *slot = mmc_priv(mmc);
670 struct mmc_data *data = mrq->data;
671
672 if (!slot->host->use_dma || !data)
673 return;
674
675 if (data->host_cookie)
676 dma_unmap_sg(slot->host->dev,
677 data->sg,
678 data->sg_len,
679 dw_mci_get_dma_dir(data));
680 data->host_cookie = 0;
681 }
682
683 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
684 {
685 #ifdef CONFIG_MMC_DW_IDMAC
686 unsigned int blksz = data->blksz;
687 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
688 u32 fifo_width = 1 << host->data_shift;
689 u32 blksz_depth = blksz / fifo_width, fifoth_val;
690 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
691 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
692
693 tx_wmark = (host->fifo_depth) / 2;
694 tx_wmark_invers = host->fifo_depth - tx_wmark;
695
696 /*
697 * MSIZE is '1',
698 * if blksz is not a multiple of the FIFO width
699 */
700 if (blksz % fifo_width) {
701 msize = 0;
702 rx_wmark = 1;
703 goto done;
704 }
705
706 do {
707 if (!((blksz_depth % mszs[idx]) ||
708 (tx_wmark_invers % mszs[idx]))) {
709 msize = idx;
710 rx_wmark = mszs[idx] - 1;
711 break;
712 }
713 } while (--idx > 0);
714 /*
715 * If idx is '0', it won't be tried
716 * Thus, initial values are uesed
717 */
718 done:
719 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
720 mci_writel(host, FIFOTH, fifoth_val);
721 #endif
722 }
723
724 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
725 {
726 unsigned int blksz = data->blksz;
727 u32 blksz_depth, fifo_depth;
728 u16 thld_size;
729
730 WARN_ON(!(data->flags & MMC_DATA_READ));
731
732 /*
733 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
734 * in the FIFO region, so we really shouldn't access it).
735 */
736 if (host->verid < DW_MMC_240A)
737 return;
738
739 if (host->timing != MMC_TIMING_MMC_HS200 &&
740 host->timing != MMC_TIMING_UHS_SDR104)
741 goto disable;
742
743 blksz_depth = blksz / (1 << host->data_shift);
744 fifo_depth = host->fifo_depth;
745
746 if (blksz_depth > fifo_depth)
747 goto disable;
748
749 /*
750 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
751 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
752 * Currently just choose blksz.
753 */
754 thld_size = blksz;
755 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
756 return;
757
758 disable:
759 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
760 }
761
762 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
763 {
764 unsigned long irqflags;
765 int sg_len;
766 u32 temp;
767
768 host->using_dma = 0;
769
770 /* If we don't have a channel, we can't do DMA */
771 if (!host->use_dma)
772 return -ENODEV;
773
774 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
775 if (sg_len < 0) {
776 host->dma_ops->stop(host);
777 return sg_len;
778 }
779
780 host->using_dma = 1;
781
782 dev_vdbg(host->dev,
783 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
784 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
785 sg_len);
786
787 /*
788 * Decide the MSIZE and RX/TX Watermark.
789 * If current block size is same with previous size,
790 * no need to update fifoth.
791 */
792 if (host->prev_blksz != data->blksz)
793 dw_mci_adjust_fifoth(host, data);
794
795 /* Enable the DMA interface */
796 temp = mci_readl(host, CTRL);
797 temp |= SDMMC_CTRL_DMA_ENABLE;
798 mci_writel(host, CTRL, temp);
799
800 /* Disable RX/TX IRQs, let DMA handle it */
801 spin_lock_irqsave(&host->irq_lock, irqflags);
802 temp = mci_readl(host, INTMASK);
803 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
804 mci_writel(host, INTMASK, temp);
805 spin_unlock_irqrestore(&host->irq_lock, irqflags);
806
807 host->dma_ops->start(host, sg_len);
808
809 return 0;
810 }
811
812 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
813 {
814 unsigned long irqflags;
815 u32 temp;
816
817 data->error = -EINPROGRESS;
818
819 WARN_ON(host->data);
820 host->sg = NULL;
821 host->data = data;
822
823 if (data->flags & MMC_DATA_READ) {
824 host->dir_status = DW_MCI_RECV_STATUS;
825 dw_mci_ctrl_rd_thld(host, data);
826 } else {
827 host->dir_status = DW_MCI_SEND_STATUS;
828 }
829
830 if (dw_mci_submit_data_dma(host, data)) {
831 int flags = SG_MITER_ATOMIC;
832 if (host->data->flags & MMC_DATA_READ)
833 flags |= SG_MITER_TO_SG;
834 else
835 flags |= SG_MITER_FROM_SG;
836
837 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
838 host->sg = data->sg;
839 host->part_buf_start = 0;
840 host->part_buf_count = 0;
841
842 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
843
844 spin_lock_irqsave(&host->irq_lock, irqflags);
845 temp = mci_readl(host, INTMASK);
846 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
847 mci_writel(host, INTMASK, temp);
848 spin_unlock_irqrestore(&host->irq_lock, irqflags);
849
850 temp = mci_readl(host, CTRL);
851 temp &= ~SDMMC_CTRL_DMA_ENABLE;
852 mci_writel(host, CTRL, temp);
853
854 /*
855 * Use the initial fifoth_val for PIO mode.
856 * If next issued data may be transfered by DMA mode,
857 * prev_blksz should be invalidated.
858 */
859 mci_writel(host, FIFOTH, host->fifoth_val);
860 host->prev_blksz = 0;
861 } else {
862 /*
863 * Keep the current block size.
864 * It will be used to decide whether to update
865 * fifoth register next time.
866 */
867 host->prev_blksz = data->blksz;
868 }
869 }
870
871 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
872 {
873 struct dw_mci *host = slot->host;
874 unsigned long timeout = jiffies + msecs_to_jiffies(500);
875 unsigned int cmd_status = 0;
876
877 mci_writel(host, CMDARG, arg);
878 wmb();
879 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
880
881 while (time_before(jiffies, timeout)) {
882 cmd_status = mci_readl(host, CMD);
883 if (!(cmd_status & SDMMC_CMD_START))
884 return;
885 }
886 dev_err(&slot->mmc->class_dev,
887 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
888 cmd, arg, cmd_status);
889 }
890
891 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
892 {
893 struct dw_mci *host = slot->host;
894 unsigned int clock = slot->clock;
895 u32 div;
896 u32 clk_en_a;
897 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
898
899 /* We must continue to set bit 28 in CMD until the change is complete */
900 if (host->state == STATE_WAITING_CMD11_DONE)
901 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
902
903 if (!clock) {
904 mci_writel(host, CLKENA, 0);
905 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
906 } else if (clock != host->current_speed || force_clkinit) {
907 div = host->bus_hz / clock;
908 if (host->bus_hz % clock && host->bus_hz > clock)
909 /*
910 * move the + 1 after the divide to prevent
911 * over-clocking the card.
912 */
913 div += 1;
914
915 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
916
917 if ((clock << div) != slot->__clk_old || force_clkinit)
918 dev_info(&slot->mmc->class_dev,
919 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
920 slot->id, host->bus_hz, clock,
921 div ? ((host->bus_hz / div) >> 1) :
922 host->bus_hz, div);
923
924 /* disable clock */
925 mci_writel(host, CLKENA, 0);
926 mci_writel(host, CLKSRC, 0);
927
928 /* inform CIU */
929 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
930
931 /* set clock to desired speed */
932 mci_writel(host, CLKDIV, div);
933
934 /* inform CIU */
935 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
936
937 /* enable clock; only low power if no SDIO */
938 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
939 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
940 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
941 mci_writel(host, CLKENA, clk_en_a);
942
943 /* inform CIU */
944 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
945
946 /* keep the clock with reflecting clock dividor */
947 slot->__clk_old = clock << div;
948 }
949
950 host->current_speed = clock;
951
952 /* Set the current slot bus width */
953 mci_writel(host, CTYPE, (slot->ctype << slot->id));
954 }
955
956 static void __dw_mci_start_request(struct dw_mci *host,
957 struct dw_mci_slot *slot,
958 struct mmc_command *cmd)
959 {
960 struct mmc_request *mrq;
961 struct mmc_data *data;
962 u32 cmdflags;
963
964 mrq = slot->mrq;
965
966 host->cur_slot = slot;
967 host->mrq = mrq;
968
969 host->pending_events = 0;
970 host->completed_events = 0;
971 host->cmd_status = 0;
972 host->data_status = 0;
973 host->dir_status = 0;
974
975 data = cmd->data;
976 if (data) {
977 mci_writel(host, TMOUT, 0xFFFFFFFF);
978 mci_writel(host, BYTCNT, data->blksz*data->blocks);
979 mci_writel(host, BLKSIZ, data->blksz);
980 }
981
982 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
983
984 /* this is the first command, send the initialization clock */
985 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
986 cmdflags |= SDMMC_CMD_INIT;
987
988 if (data) {
989 dw_mci_submit_data(host, data);
990 wmb();
991 }
992
993 dw_mci_start_command(host, cmd, cmdflags);
994
995 if (mrq->stop)
996 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
997 else
998 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
999 }
1000
1001 static void dw_mci_start_request(struct dw_mci *host,
1002 struct dw_mci_slot *slot)
1003 {
1004 struct mmc_request *mrq = slot->mrq;
1005 struct mmc_command *cmd;
1006
1007 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1008 __dw_mci_start_request(host, slot, cmd);
1009 }
1010
1011 /* must be called with host->lock held */
1012 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1013 struct mmc_request *mrq)
1014 {
1015 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1016 host->state);
1017
1018 slot->mrq = mrq;
1019
1020 if (host->state == STATE_WAITING_CMD11_DONE) {
1021 dev_warn(&slot->mmc->class_dev,
1022 "Voltage change didn't complete\n");
1023 /*
1024 * this case isn't expected to happen, so we can
1025 * either crash here or just try to continue on
1026 * in the closest possible state
1027 */
1028 host->state = STATE_IDLE;
1029 }
1030
1031 if (host->state == STATE_IDLE) {
1032 host->state = STATE_SENDING_CMD;
1033 dw_mci_start_request(host, slot);
1034 } else {
1035 list_add_tail(&slot->queue_node, &host->queue);
1036 }
1037 }
1038
1039 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1040 {
1041 struct dw_mci_slot *slot = mmc_priv(mmc);
1042 struct dw_mci *host = slot->host;
1043
1044 WARN_ON(slot->mrq);
1045
1046 /*
1047 * The check for card presence and queueing of the request must be
1048 * atomic, otherwise the card could be removed in between and the
1049 * request wouldn't fail until another card was inserted.
1050 */
1051 spin_lock_bh(&host->lock);
1052
1053 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1054 spin_unlock_bh(&host->lock);
1055 mrq->cmd->error = -ENOMEDIUM;
1056 mmc_request_done(mmc, mrq);
1057 return;
1058 }
1059
1060 dw_mci_queue_request(host, slot, mrq);
1061
1062 spin_unlock_bh(&host->lock);
1063 }
1064
1065 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1066 {
1067 struct dw_mci_slot *slot = mmc_priv(mmc);
1068 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1069 u32 regs;
1070 int ret;
1071
1072 switch (ios->bus_width) {
1073 case MMC_BUS_WIDTH_4:
1074 slot->ctype = SDMMC_CTYPE_4BIT;
1075 break;
1076 case MMC_BUS_WIDTH_8:
1077 slot->ctype = SDMMC_CTYPE_8BIT;
1078 break;
1079 default:
1080 /* set default 1 bit mode */
1081 slot->ctype = SDMMC_CTYPE_1BIT;
1082 }
1083
1084 regs = mci_readl(slot->host, UHS_REG);
1085
1086 /* DDR mode set */
1087 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1088 ios->timing == MMC_TIMING_MMC_HS400)
1089 regs |= ((0x1 << slot->id) << 16);
1090 else
1091 regs &= ~((0x1 << slot->id) << 16);
1092
1093 mci_writel(slot->host, UHS_REG, regs);
1094 slot->host->timing = ios->timing;
1095
1096 /*
1097 * Use mirror of ios->clock to prevent race with mmc
1098 * core ios update when finding the minimum.
1099 */
1100 slot->clock = ios->clock;
1101
1102 if (drv_data && drv_data->set_ios)
1103 drv_data->set_ios(slot->host, ios);
1104
1105 switch (ios->power_mode) {
1106 case MMC_POWER_UP:
1107 if (!IS_ERR(mmc->supply.vmmc)) {
1108 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1109 ios->vdd);
1110 if (ret) {
1111 dev_err(slot->host->dev,
1112 "failed to enable vmmc regulator\n");
1113 /*return, if failed turn on vmmc*/
1114 return;
1115 }
1116 }
1117 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1118 regs = mci_readl(slot->host, PWREN);
1119 regs |= (1 << slot->id);
1120 mci_writel(slot->host, PWREN, regs);
1121 break;
1122 case MMC_POWER_ON:
1123 if (!slot->host->vqmmc_enabled) {
1124 if (!IS_ERR(mmc->supply.vqmmc)) {
1125 ret = regulator_enable(mmc->supply.vqmmc);
1126 if (ret < 0)
1127 dev_err(slot->host->dev,
1128 "failed to enable vqmmc\n");
1129 else
1130 slot->host->vqmmc_enabled = true;
1131
1132 } else {
1133 /* Keep track so we don't reset again */
1134 slot->host->vqmmc_enabled = true;
1135 }
1136
1137 /* Reset our state machine after powering on */
1138 dw_mci_ctrl_reset(slot->host,
1139 SDMMC_CTRL_ALL_RESET_FLAGS);
1140 }
1141
1142 /* Adjust clock / bus width after power is up */
1143 dw_mci_setup_bus(slot, false);
1144
1145 break;
1146 case MMC_POWER_OFF:
1147 /* Turn clock off before power goes down */
1148 dw_mci_setup_bus(slot, false);
1149
1150 if (!IS_ERR(mmc->supply.vmmc))
1151 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1152
1153 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1154 regulator_disable(mmc->supply.vqmmc);
1155 slot->host->vqmmc_enabled = false;
1156
1157 regs = mci_readl(slot->host, PWREN);
1158 regs &= ~(1 << slot->id);
1159 mci_writel(slot->host, PWREN, regs);
1160 break;
1161 default:
1162 break;
1163 }
1164
1165 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1166 slot->host->state = STATE_IDLE;
1167 }
1168
1169 static int dw_mci_card_busy(struct mmc_host *mmc)
1170 {
1171 struct dw_mci_slot *slot = mmc_priv(mmc);
1172 u32 status;
1173
1174 /*
1175 * Check the busy bit which is low when DAT[3:0]
1176 * (the data lines) are 0000
1177 */
1178 status = mci_readl(slot->host, STATUS);
1179
1180 return !!(status & SDMMC_STATUS_BUSY);
1181 }
1182
1183 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1184 {
1185 struct dw_mci_slot *slot = mmc_priv(mmc);
1186 struct dw_mci *host = slot->host;
1187 u32 uhs;
1188 u32 v18 = SDMMC_UHS_18V << slot->id;
1189 int min_uv, max_uv;
1190 int ret;
1191
1192 /*
1193 * Program the voltage. Note that some instances of dw_mmc may use
1194 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1195 * does no harm but you need to set the regulator directly. Try both.
1196 */
1197 uhs = mci_readl(host, UHS_REG);
1198 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1199 min_uv = 2700000;
1200 max_uv = 3600000;
1201 uhs &= ~v18;
1202 } else {
1203 min_uv = 1700000;
1204 max_uv = 1950000;
1205 uhs |= v18;
1206 }
1207 if (!IS_ERR(mmc->supply.vqmmc)) {
1208 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1209
1210 if (ret) {
1211 dev_dbg(&mmc->class_dev,
1212 "Regulator set error %d: %d - %d\n",
1213 ret, min_uv, max_uv);
1214 return ret;
1215 }
1216 }
1217 mci_writel(host, UHS_REG, uhs);
1218
1219 return 0;
1220 }
1221
1222 static int dw_mci_get_ro(struct mmc_host *mmc)
1223 {
1224 int read_only;
1225 struct dw_mci_slot *slot = mmc_priv(mmc);
1226 int gpio_ro = mmc_gpio_get_ro(mmc);
1227
1228 /* Use platform get_ro function, else try on board write protect */
1229 if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
1230 (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
1231 read_only = 0;
1232 else if (!IS_ERR_VALUE(gpio_ro))
1233 read_only = gpio_ro;
1234 else
1235 read_only =
1236 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1237
1238 dev_dbg(&mmc->class_dev, "card is %s\n",
1239 read_only ? "read-only" : "read-write");
1240
1241 return read_only;
1242 }
1243
1244 static int dw_mci_get_cd(struct mmc_host *mmc)
1245 {
1246 int present;
1247 struct dw_mci_slot *slot = mmc_priv(mmc);
1248 struct dw_mci_board *brd = slot->host->pdata;
1249 struct dw_mci *host = slot->host;
1250 int gpio_cd = mmc_gpio_get_cd(mmc);
1251
1252 /* Use platform get_cd function, else try onboard card detect */
1253 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1254 present = 1;
1255 else if (!IS_ERR_VALUE(gpio_cd))
1256 present = gpio_cd;
1257 else
1258 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1259 == 0 ? 1 : 0;
1260
1261 spin_lock_bh(&host->lock);
1262 if (present) {
1263 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1264 dev_dbg(&mmc->class_dev, "card is present\n");
1265 } else {
1266 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1267 dev_dbg(&mmc->class_dev, "card is not present\n");
1268 }
1269 spin_unlock_bh(&host->lock);
1270
1271 return present;
1272 }
1273
1274 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1275 {
1276 struct dw_mci_slot *slot = mmc_priv(mmc);
1277 struct dw_mci *host = slot->host;
1278
1279 /*
1280 * Low power mode will stop the card clock when idle. According to the
1281 * description of the CLKENA register we should disable low power mode
1282 * for SDIO cards if we need SDIO interrupts to work.
1283 */
1284 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1285 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1286 u32 clk_en_a_old;
1287 u32 clk_en_a;
1288
1289 clk_en_a_old = mci_readl(host, CLKENA);
1290
1291 if (card->type == MMC_TYPE_SDIO ||
1292 card->type == MMC_TYPE_SD_COMBO) {
1293 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1294 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1295 } else {
1296 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1297 clk_en_a = clk_en_a_old | clken_low_pwr;
1298 }
1299
1300 if (clk_en_a != clk_en_a_old) {
1301 mci_writel(host, CLKENA, clk_en_a);
1302 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1303 SDMMC_CMD_PRV_DAT_WAIT, 0);
1304 }
1305 }
1306 }
1307
1308 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1309 {
1310 struct dw_mci_slot *slot = mmc_priv(mmc);
1311 struct dw_mci *host = slot->host;
1312 unsigned long irqflags;
1313 u32 int_mask;
1314
1315 spin_lock_irqsave(&host->irq_lock, irqflags);
1316
1317 /* Enable/disable Slot Specific SDIO interrupt */
1318 int_mask = mci_readl(host, INTMASK);
1319 if (enb)
1320 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1321 else
1322 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1323 mci_writel(host, INTMASK, int_mask);
1324
1325 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1326 }
1327
1328 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1329 {
1330 struct dw_mci_slot *slot = mmc_priv(mmc);
1331 struct dw_mci *host = slot->host;
1332 const struct dw_mci_drv_data *drv_data = host->drv_data;
1333 int err = -ENOSYS;
1334
1335 if (drv_data && drv_data->execute_tuning)
1336 err = drv_data->execute_tuning(slot);
1337 return err;
1338 }
1339
1340 int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1341 {
1342 struct dw_mci_slot *slot = mmc_priv(mmc);
1343 struct dw_mci *host = slot->host;
1344 const struct dw_mci_drv_data *drv_data = host->drv_data;
1345
1346 if (drv_data && drv_data->prepare_hs400_tuning)
1347 return drv_data->prepare_hs400_tuning(host, ios);
1348
1349 return 0;
1350 }
1351
1352 static const struct mmc_host_ops dw_mci_ops = {
1353 .request = dw_mci_request,
1354 .pre_req = dw_mci_pre_req,
1355 .post_req = dw_mci_post_req,
1356 .set_ios = dw_mci_set_ios,
1357 .get_ro = dw_mci_get_ro,
1358 .get_cd = dw_mci_get_cd,
1359 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1360 .execute_tuning = dw_mci_execute_tuning,
1361 .card_busy = dw_mci_card_busy,
1362 .start_signal_voltage_switch = dw_mci_switch_voltage,
1363 .init_card = dw_mci_init_card,
1364 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1365 };
1366
1367 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1368 __releases(&host->lock)
1369 __acquires(&host->lock)
1370 {
1371 struct dw_mci_slot *slot;
1372 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1373
1374 WARN_ON(host->cmd || host->data);
1375
1376 host->cur_slot->mrq = NULL;
1377 host->mrq = NULL;
1378 if (!list_empty(&host->queue)) {
1379 slot = list_entry(host->queue.next,
1380 struct dw_mci_slot, queue_node);
1381 list_del(&slot->queue_node);
1382 dev_vdbg(host->dev, "list not empty: %s is next\n",
1383 mmc_hostname(slot->mmc));
1384 host->state = STATE_SENDING_CMD;
1385 dw_mci_start_request(host, slot);
1386 } else {
1387 dev_vdbg(host->dev, "list empty\n");
1388
1389 if (host->state == STATE_SENDING_CMD11)
1390 host->state = STATE_WAITING_CMD11_DONE;
1391 else
1392 host->state = STATE_IDLE;
1393 }
1394
1395 spin_unlock(&host->lock);
1396 mmc_request_done(prev_mmc, mrq);
1397 spin_lock(&host->lock);
1398 }
1399
1400 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1401 {
1402 u32 status = host->cmd_status;
1403
1404 host->cmd_status = 0;
1405
1406 /* Read the response from the card (up to 16 bytes) */
1407 if (cmd->flags & MMC_RSP_PRESENT) {
1408 if (cmd->flags & MMC_RSP_136) {
1409 cmd->resp[3] = mci_readl(host, RESP0);
1410 cmd->resp[2] = mci_readl(host, RESP1);
1411 cmd->resp[1] = mci_readl(host, RESP2);
1412 cmd->resp[0] = mci_readl(host, RESP3);
1413 } else {
1414 cmd->resp[0] = mci_readl(host, RESP0);
1415 cmd->resp[1] = 0;
1416 cmd->resp[2] = 0;
1417 cmd->resp[3] = 0;
1418 }
1419 }
1420
1421 if (status & SDMMC_INT_RTO)
1422 cmd->error = -ETIMEDOUT;
1423 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1424 cmd->error = -EILSEQ;
1425 else if (status & SDMMC_INT_RESP_ERR)
1426 cmd->error = -EIO;
1427 else
1428 cmd->error = 0;
1429
1430 if (cmd->error) {
1431 /* newer ip versions need a delay between retries */
1432 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1433 mdelay(20);
1434 }
1435
1436 return cmd->error;
1437 }
1438
1439 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1440 {
1441 u32 status = host->data_status;
1442
1443 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1444 if (status & SDMMC_INT_DRTO) {
1445 data->error = -ETIMEDOUT;
1446 } else if (status & SDMMC_INT_DCRC) {
1447 data->error = -EILSEQ;
1448 } else if (status & SDMMC_INT_EBE) {
1449 if (host->dir_status ==
1450 DW_MCI_SEND_STATUS) {
1451 /*
1452 * No data CRC status was returned.
1453 * The number of bytes transferred
1454 * will be exaggerated in PIO mode.
1455 */
1456 data->bytes_xfered = 0;
1457 data->error = -ETIMEDOUT;
1458 } else if (host->dir_status ==
1459 DW_MCI_RECV_STATUS) {
1460 data->error = -EIO;
1461 }
1462 } else {
1463 /* SDMMC_INT_SBE is included */
1464 data->error = -EIO;
1465 }
1466
1467 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1468
1469 /*
1470 * After an error, there may be data lingering
1471 * in the FIFO
1472 */
1473 dw_mci_reset(host);
1474 } else {
1475 data->bytes_xfered = data->blocks * data->blksz;
1476 data->error = 0;
1477 }
1478
1479 return data->error;
1480 }
1481
1482 static void dw_mci_tasklet_func(unsigned long priv)
1483 {
1484 struct dw_mci *host = (struct dw_mci *)priv;
1485 struct mmc_data *data;
1486 struct mmc_command *cmd;
1487 struct mmc_request *mrq;
1488 enum dw_mci_state state;
1489 enum dw_mci_state prev_state;
1490 unsigned int err;
1491
1492 spin_lock(&host->lock);
1493
1494 state = host->state;
1495 data = host->data;
1496 mrq = host->mrq;
1497
1498 do {
1499 prev_state = state;
1500
1501 switch (state) {
1502 case STATE_IDLE:
1503 case STATE_WAITING_CMD11_DONE:
1504 break;
1505
1506 case STATE_SENDING_CMD11:
1507 case STATE_SENDING_CMD:
1508 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1509 &host->pending_events))
1510 break;
1511
1512 cmd = host->cmd;
1513 host->cmd = NULL;
1514 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1515 err = dw_mci_command_complete(host, cmd);
1516 if (cmd == mrq->sbc && !err) {
1517 prev_state = state = STATE_SENDING_CMD;
1518 __dw_mci_start_request(host, host->cur_slot,
1519 mrq->cmd);
1520 goto unlock;
1521 }
1522
1523 if (cmd->data && err) {
1524 dw_mci_stop_dma(host);
1525 send_stop_abort(host, data);
1526 state = STATE_SENDING_STOP;
1527 break;
1528 }
1529
1530 if (!cmd->data || err) {
1531 dw_mci_request_end(host, mrq);
1532 goto unlock;
1533 }
1534
1535 prev_state = state = STATE_SENDING_DATA;
1536 /* fall through */
1537
1538 case STATE_SENDING_DATA:
1539 /*
1540 * We could get a data error and never a transfer
1541 * complete so we'd better check for it here.
1542 *
1543 * Note that we don't really care if we also got a
1544 * transfer complete; stopping the DMA and sending an
1545 * abort won't hurt.
1546 */
1547 if (test_and_clear_bit(EVENT_DATA_ERROR,
1548 &host->pending_events)) {
1549 dw_mci_stop_dma(host);
1550 if (data->stop ||
1551 !(host->data_status & (SDMMC_INT_DRTO |
1552 SDMMC_INT_EBE)))
1553 send_stop_abort(host, data);
1554 state = STATE_DATA_ERROR;
1555 break;
1556 }
1557
1558 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1559 &host->pending_events))
1560 break;
1561
1562 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1563
1564 /*
1565 * Handle an EVENT_DATA_ERROR that might have shown up
1566 * before the transfer completed. This might not have
1567 * been caught by the check above because the interrupt
1568 * could have gone off between the previous check and
1569 * the check for transfer complete.
1570 *
1571 * Technically this ought not be needed assuming we
1572 * get a DATA_COMPLETE eventually (we'll notice the
1573 * error and end the request), but it shouldn't hurt.
1574 *
1575 * This has the advantage of sending the stop command.
1576 */
1577 if (test_and_clear_bit(EVENT_DATA_ERROR,
1578 &host->pending_events)) {
1579 dw_mci_stop_dma(host);
1580 if (data->stop ||
1581 !(host->data_status & (SDMMC_INT_DRTO |
1582 SDMMC_INT_EBE)))
1583 send_stop_abort(host, data);
1584 state = STATE_DATA_ERROR;
1585 break;
1586 }
1587 prev_state = state = STATE_DATA_BUSY;
1588
1589 /* fall through */
1590
1591 case STATE_DATA_BUSY:
1592 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1593 &host->pending_events))
1594 break;
1595
1596 host->data = NULL;
1597 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1598 err = dw_mci_data_complete(host, data);
1599
1600 if (!err) {
1601 if (!data->stop || mrq->sbc) {
1602 if (mrq->sbc && data->stop)
1603 data->stop->error = 0;
1604 dw_mci_request_end(host, mrq);
1605 goto unlock;
1606 }
1607
1608 /* stop command for open-ended transfer*/
1609 if (data->stop)
1610 send_stop_abort(host, data);
1611 } else {
1612 /*
1613 * If we don't have a command complete now we'll
1614 * never get one since we just reset everything;
1615 * better end the request.
1616 *
1617 * If we do have a command complete we'll fall
1618 * through to the SENDING_STOP command and
1619 * everything will be peachy keen.
1620 */
1621 if (!test_bit(EVENT_CMD_COMPLETE,
1622 &host->pending_events)) {
1623 host->cmd = NULL;
1624 dw_mci_request_end(host, mrq);
1625 goto unlock;
1626 }
1627 }
1628
1629 /*
1630 * If err has non-zero,
1631 * stop-abort command has been already issued.
1632 */
1633 prev_state = state = STATE_SENDING_STOP;
1634
1635 /* fall through */
1636
1637 case STATE_SENDING_STOP:
1638 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1639 &host->pending_events))
1640 break;
1641
1642 /* CMD error in data command */
1643 if (mrq->cmd->error && mrq->data)
1644 dw_mci_reset(host);
1645
1646 host->cmd = NULL;
1647 host->data = NULL;
1648
1649 if (mrq->stop)
1650 dw_mci_command_complete(host, mrq->stop);
1651 else
1652 host->cmd_status = 0;
1653
1654 dw_mci_request_end(host, mrq);
1655 goto unlock;
1656
1657 case STATE_DATA_ERROR:
1658 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1659 &host->pending_events))
1660 break;
1661
1662 state = STATE_DATA_BUSY;
1663 break;
1664 }
1665 } while (state != prev_state);
1666
1667 host->state = state;
1668 unlock:
1669 spin_unlock(&host->lock);
1670
1671 }
1672
1673 /* push final bytes to part_buf, only use during push */
1674 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1675 {
1676 memcpy((void *)&host->part_buf, buf, cnt);
1677 host->part_buf_count = cnt;
1678 }
1679
1680 /* append bytes to part_buf, only use during push */
1681 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1682 {
1683 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1684 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1685 host->part_buf_count += cnt;
1686 return cnt;
1687 }
1688
1689 /* pull first bytes from part_buf, only use during pull */
1690 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1691 {
1692 cnt = min(cnt, (int)host->part_buf_count);
1693 if (cnt) {
1694 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1695 cnt);
1696 host->part_buf_count -= cnt;
1697 host->part_buf_start += cnt;
1698 }
1699 return cnt;
1700 }
1701
1702 /* pull final bytes from the part_buf, assuming it's just been filled */
1703 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1704 {
1705 memcpy(buf, &host->part_buf, cnt);
1706 host->part_buf_start = cnt;
1707 host->part_buf_count = (1 << host->data_shift) - cnt;
1708 }
1709
1710 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1711 {
1712 struct mmc_data *data = host->data;
1713 int init_cnt = cnt;
1714
1715 /* try and push anything in the part_buf */
1716 if (unlikely(host->part_buf_count)) {
1717 int len = dw_mci_push_part_bytes(host, buf, cnt);
1718 buf += len;
1719 cnt -= len;
1720 if (host->part_buf_count == 2) {
1721 mci_writew(host, DATA(host->data_offset),
1722 host->part_buf16);
1723 host->part_buf_count = 0;
1724 }
1725 }
1726 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1727 if (unlikely((unsigned long)buf & 0x1)) {
1728 while (cnt >= 2) {
1729 u16 aligned_buf[64];
1730 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1731 int items = len >> 1;
1732 int i;
1733 /* memcpy from input buffer into aligned buffer */
1734 memcpy(aligned_buf, buf, len);
1735 buf += len;
1736 cnt -= len;
1737 /* push data from aligned buffer into fifo */
1738 for (i = 0; i < items; ++i)
1739 mci_writew(host, DATA(host->data_offset),
1740 aligned_buf[i]);
1741 }
1742 } else
1743 #endif
1744 {
1745 u16 *pdata = buf;
1746 for (; cnt >= 2; cnt -= 2)
1747 mci_writew(host, DATA(host->data_offset), *pdata++);
1748 buf = pdata;
1749 }
1750 /* put anything remaining in the part_buf */
1751 if (cnt) {
1752 dw_mci_set_part_bytes(host, buf, cnt);
1753 /* Push data if we have reached the expected data length */
1754 if ((data->bytes_xfered + init_cnt) ==
1755 (data->blksz * data->blocks))
1756 mci_writew(host, DATA(host->data_offset),
1757 host->part_buf16);
1758 }
1759 }
1760
1761 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1762 {
1763 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1764 if (unlikely((unsigned long)buf & 0x1)) {
1765 while (cnt >= 2) {
1766 /* pull data from fifo into aligned buffer */
1767 u16 aligned_buf[64];
1768 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1769 int items = len >> 1;
1770 int i;
1771 for (i = 0; i < items; ++i)
1772 aligned_buf[i] = mci_readw(host,
1773 DATA(host->data_offset));
1774 /* memcpy from aligned buffer into output buffer */
1775 memcpy(buf, aligned_buf, len);
1776 buf += len;
1777 cnt -= len;
1778 }
1779 } else
1780 #endif
1781 {
1782 u16 *pdata = buf;
1783 for (; cnt >= 2; cnt -= 2)
1784 *pdata++ = mci_readw(host, DATA(host->data_offset));
1785 buf = pdata;
1786 }
1787 if (cnt) {
1788 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1789 dw_mci_pull_final_bytes(host, buf, cnt);
1790 }
1791 }
1792
1793 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1794 {
1795 struct mmc_data *data = host->data;
1796 int init_cnt = cnt;
1797
1798 /* try and push anything in the part_buf */
1799 if (unlikely(host->part_buf_count)) {
1800 int len = dw_mci_push_part_bytes(host, buf, cnt);
1801 buf += len;
1802 cnt -= len;
1803 if (host->part_buf_count == 4) {
1804 mci_writel(host, DATA(host->data_offset),
1805 host->part_buf32);
1806 host->part_buf_count = 0;
1807 }
1808 }
1809 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1810 if (unlikely((unsigned long)buf & 0x3)) {
1811 while (cnt >= 4) {
1812 u32 aligned_buf[32];
1813 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1814 int items = len >> 2;
1815 int i;
1816 /* memcpy from input buffer into aligned buffer */
1817 memcpy(aligned_buf, buf, len);
1818 buf += len;
1819 cnt -= len;
1820 /* push data from aligned buffer into fifo */
1821 for (i = 0; i < items; ++i)
1822 mci_writel(host, DATA(host->data_offset),
1823 aligned_buf[i]);
1824 }
1825 } else
1826 #endif
1827 {
1828 u32 *pdata = buf;
1829 for (; cnt >= 4; cnt -= 4)
1830 mci_writel(host, DATA(host->data_offset), *pdata++);
1831 buf = pdata;
1832 }
1833 /* put anything remaining in the part_buf */
1834 if (cnt) {
1835 dw_mci_set_part_bytes(host, buf, cnt);
1836 /* Push data if we have reached the expected data length */
1837 if ((data->bytes_xfered + init_cnt) ==
1838 (data->blksz * data->blocks))
1839 mci_writel(host, DATA(host->data_offset),
1840 host->part_buf32);
1841 }
1842 }
1843
1844 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1845 {
1846 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1847 if (unlikely((unsigned long)buf & 0x3)) {
1848 while (cnt >= 4) {
1849 /* pull data from fifo into aligned buffer */
1850 u32 aligned_buf[32];
1851 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1852 int items = len >> 2;
1853 int i;
1854 for (i = 0; i < items; ++i)
1855 aligned_buf[i] = mci_readl(host,
1856 DATA(host->data_offset));
1857 /* memcpy from aligned buffer into output buffer */
1858 memcpy(buf, aligned_buf, len);
1859 buf += len;
1860 cnt -= len;
1861 }
1862 } else
1863 #endif
1864 {
1865 u32 *pdata = buf;
1866 for (; cnt >= 4; cnt -= 4)
1867 *pdata++ = mci_readl(host, DATA(host->data_offset));
1868 buf = pdata;
1869 }
1870 if (cnt) {
1871 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1872 dw_mci_pull_final_bytes(host, buf, cnt);
1873 }
1874 }
1875
1876 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1877 {
1878 struct mmc_data *data = host->data;
1879 int init_cnt = cnt;
1880
1881 /* try and push anything in the part_buf */
1882 if (unlikely(host->part_buf_count)) {
1883 int len = dw_mci_push_part_bytes(host, buf, cnt);
1884 buf += len;
1885 cnt -= len;
1886
1887 if (host->part_buf_count == 8) {
1888 mci_writeq(host, DATA(host->data_offset),
1889 host->part_buf);
1890 host->part_buf_count = 0;
1891 }
1892 }
1893 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1894 if (unlikely((unsigned long)buf & 0x7)) {
1895 while (cnt >= 8) {
1896 u64 aligned_buf[16];
1897 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1898 int items = len >> 3;
1899 int i;
1900 /* memcpy from input buffer into aligned buffer */
1901 memcpy(aligned_buf, buf, len);
1902 buf += len;
1903 cnt -= len;
1904 /* push data from aligned buffer into fifo */
1905 for (i = 0; i < items; ++i)
1906 mci_writeq(host, DATA(host->data_offset),
1907 aligned_buf[i]);
1908 }
1909 } else
1910 #endif
1911 {
1912 u64 *pdata = buf;
1913 for (; cnt >= 8; cnt -= 8)
1914 mci_writeq(host, DATA(host->data_offset), *pdata++);
1915 buf = pdata;
1916 }
1917 /* put anything remaining in the part_buf */
1918 if (cnt) {
1919 dw_mci_set_part_bytes(host, buf, cnt);
1920 /* Push data if we have reached the expected data length */
1921 if ((data->bytes_xfered + init_cnt) ==
1922 (data->blksz * data->blocks))
1923 mci_writeq(host, DATA(host->data_offset),
1924 host->part_buf);
1925 }
1926 }
1927
1928 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1929 {
1930 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1931 if (unlikely((unsigned long)buf & 0x7)) {
1932 while (cnt >= 8) {
1933 /* pull data from fifo into aligned buffer */
1934 u64 aligned_buf[16];
1935 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1936 int items = len >> 3;
1937 int i;
1938 for (i = 0; i < items; ++i)
1939 aligned_buf[i] = mci_readq(host,
1940 DATA(host->data_offset));
1941 /* memcpy from aligned buffer into output buffer */
1942 memcpy(buf, aligned_buf, len);
1943 buf += len;
1944 cnt -= len;
1945 }
1946 } else
1947 #endif
1948 {
1949 u64 *pdata = buf;
1950 for (; cnt >= 8; cnt -= 8)
1951 *pdata++ = mci_readq(host, DATA(host->data_offset));
1952 buf = pdata;
1953 }
1954 if (cnt) {
1955 host->part_buf = mci_readq(host, DATA(host->data_offset));
1956 dw_mci_pull_final_bytes(host, buf, cnt);
1957 }
1958 }
1959
1960 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1961 {
1962 int len;
1963
1964 /* get remaining partial bytes */
1965 len = dw_mci_pull_part_bytes(host, buf, cnt);
1966 if (unlikely(len == cnt))
1967 return;
1968 buf += len;
1969 cnt -= len;
1970
1971 /* get the rest of the data */
1972 host->pull_data(host, buf, cnt);
1973 }
1974
1975 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
1976 {
1977 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1978 void *buf;
1979 unsigned int offset;
1980 struct mmc_data *data = host->data;
1981 int shift = host->data_shift;
1982 u32 status;
1983 unsigned int len;
1984 unsigned int remain, fcnt;
1985
1986 do {
1987 if (!sg_miter_next(sg_miter))
1988 goto done;
1989
1990 host->sg = sg_miter->piter.sg;
1991 buf = sg_miter->addr;
1992 remain = sg_miter->length;
1993 offset = 0;
1994
1995 do {
1996 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1997 << shift) + host->part_buf_count;
1998 len = min(remain, fcnt);
1999 if (!len)
2000 break;
2001 dw_mci_pull_data(host, (void *)(buf + offset), len);
2002 data->bytes_xfered += len;
2003 offset += len;
2004 remain -= len;
2005 } while (remain);
2006
2007 sg_miter->consumed = offset;
2008 status = mci_readl(host, MINTSTS);
2009 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2010 /* if the RXDR is ready read again */
2011 } while ((status & SDMMC_INT_RXDR) ||
2012 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2013
2014 if (!remain) {
2015 if (!sg_miter_next(sg_miter))
2016 goto done;
2017 sg_miter->consumed = 0;
2018 }
2019 sg_miter_stop(sg_miter);
2020 return;
2021
2022 done:
2023 sg_miter_stop(sg_miter);
2024 host->sg = NULL;
2025 smp_wmb();
2026 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2027 }
2028
2029 static void dw_mci_write_data_pio(struct dw_mci *host)
2030 {
2031 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2032 void *buf;
2033 unsigned int offset;
2034 struct mmc_data *data = host->data;
2035 int shift = host->data_shift;
2036 u32 status;
2037 unsigned int len;
2038 unsigned int fifo_depth = host->fifo_depth;
2039 unsigned int remain, fcnt;
2040
2041 do {
2042 if (!sg_miter_next(sg_miter))
2043 goto done;
2044
2045 host->sg = sg_miter->piter.sg;
2046 buf = sg_miter->addr;
2047 remain = sg_miter->length;
2048 offset = 0;
2049
2050 do {
2051 fcnt = ((fifo_depth -
2052 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2053 << shift) - host->part_buf_count;
2054 len = min(remain, fcnt);
2055 if (!len)
2056 break;
2057 host->push_data(host, (void *)(buf + offset), len);
2058 data->bytes_xfered += len;
2059 offset += len;
2060 remain -= len;
2061 } while (remain);
2062
2063 sg_miter->consumed = offset;
2064 status = mci_readl(host, MINTSTS);
2065 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2066 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2067
2068 if (!remain) {
2069 if (!sg_miter_next(sg_miter))
2070 goto done;
2071 sg_miter->consumed = 0;
2072 }
2073 sg_miter_stop(sg_miter);
2074 return;
2075
2076 done:
2077 sg_miter_stop(sg_miter);
2078 host->sg = NULL;
2079 smp_wmb();
2080 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2081 }
2082
2083 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2084 {
2085 if (!host->cmd_status)
2086 host->cmd_status = status;
2087
2088 smp_wmb();
2089
2090 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2091 tasklet_schedule(&host->tasklet);
2092 }
2093
2094 static void dw_mci_handle_cd(struct dw_mci *host)
2095 {
2096 int i;
2097
2098 for (i = 0; i < host->num_slots; i++) {
2099 struct dw_mci_slot *slot = host->slot[i];
2100
2101 if (!slot)
2102 continue;
2103
2104 if (slot->mmc->ops->card_event)
2105 slot->mmc->ops->card_event(slot->mmc);
2106 mmc_detect_change(slot->mmc,
2107 msecs_to_jiffies(host->pdata->detect_delay_ms));
2108 }
2109 }
2110
2111 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2112 {
2113 struct dw_mci *host = dev_id;
2114 u32 pending;
2115 int i;
2116
2117 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2118
2119 /*
2120 * DTO fix - version 2.10a and below, and only if internal DMA
2121 * is configured.
2122 */
2123 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2124 if (!pending &&
2125 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2126 pending |= SDMMC_INT_DATA_OVER;
2127 }
2128
2129 if (pending) {
2130 /* Check volt switch first, since it can look like an error */
2131 if ((host->state == STATE_SENDING_CMD11) &&
2132 (pending & SDMMC_INT_VOLT_SWITCH)) {
2133 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2134 pending &= ~SDMMC_INT_VOLT_SWITCH;
2135 dw_mci_cmd_interrupt(host, pending);
2136 }
2137
2138 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2139 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2140 host->cmd_status = pending;
2141 smp_wmb();
2142 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2143 }
2144
2145 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2146 /* if there is an error report DATA_ERROR */
2147 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2148 host->data_status = pending;
2149 smp_wmb();
2150 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2151 tasklet_schedule(&host->tasklet);
2152 }
2153
2154 if (pending & SDMMC_INT_DATA_OVER) {
2155 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2156 if (!host->data_status)
2157 host->data_status = pending;
2158 smp_wmb();
2159 if (host->dir_status == DW_MCI_RECV_STATUS) {
2160 if (host->sg != NULL)
2161 dw_mci_read_data_pio(host, true);
2162 }
2163 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2164 tasklet_schedule(&host->tasklet);
2165 }
2166
2167 if (pending & SDMMC_INT_RXDR) {
2168 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2169 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2170 dw_mci_read_data_pio(host, false);
2171 }
2172
2173 if (pending & SDMMC_INT_TXDR) {
2174 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2175 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2176 dw_mci_write_data_pio(host);
2177 }
2178
2179 if (pending & SDMMC_INT_CMD_DONE) {
2180 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2181 dw_mci_cmd_interrupt(host, pending);
2182 }
2183
2184 if (pending & SDMMC_INT_CD) {
2185 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2186 dw_mci_handle_cd(host);
2187 }
2188
2189 /* Handle SDIO Interrupts */
2190 for (i = 0; i < host->num_slots; i++) {
2191 struct dw_mci_slot *slot = host->slot[i];
2192 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2193 mci_writel(host, RINTSTS,
2194 SDMMC_INT_SDIO(slot->sdio_id));
2195 mmc_signal_sdio_irq(slot->mmc);
2196 }
2197 }
2198
2199 }
2200
2201 #ifdef CONFIG_MMC_DW_IDMAC
2202 /* Handle DMA interrupts */
2203 if (host->dma_64bit_address == 1) {
2204 pending = mci_readl(host, IDSTS64);
2205 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2206 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2207 SDMMC_IDMAC_INT_RI);
2208 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2209 host->dma_ops->complete(host);
2210 }
2211 } else {
2212 pending = mci_readl(host, IDSTS);
2213 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2214 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2215 SDMMC_IDMAC_INT_RI);
2216 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2217 host->dma_ops->complete(host);
2218 }
2219 }
2220 #endif
2221
2222 return IRQ_HANDLED;
2223 }
2224
2225 #ifdef CONFIG_OF
2226 /* given a slot id, find out the device node representing that slot */
2227 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2228 {
2229 struct device_node *np;
2230 const __be32 *addr;
2231 int len;
2232
2233 if (!dev || !dev->of_node)
2234 return NULL;
2235
2236 for_each_child_of_node(dev->of_node, np) {
2237 addr = of_get_property(np, "reg", &len);
2238 if (!addr || (len < sizeof(int)))
2239 continue;
2240 if (be32_to_cpup(addr) == slot)
2241 return np;
2242 }
2243 return NULL;
2244 }
2245
2246 static struct dw_mci_of_slot_quirks {
2247 char *quirk;
2248 int id;
2249 } of_slot_quirks[] = {
2250 {
2251 .quirk = "disable-wp",
2252 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
2253 },
2254 };
2255
2256 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2257 {
2258 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2259 int quirks = 0;
2260 int idx;
2261
2262 /* get quirks */
2263 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
2264 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
2265 dev_warn(dev, "Slot quirk %s is deprecated\n",
2266 of_slot_quirks[idx].quirk);
2267 quirks |= of_slot_quirks[idx].id;
2268 }
2269
2270 return quirks;
2271 }
2272 #else /* CONFIG_OF */
2273 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2274 {
2275 return 0;
2276 }
2277 #endif /* CONFIG_OF */
2278
2279 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2280 {
2281 struct mmc_host *mmc;
2282 struct dw_mci_slot *slot;
2283 const struct dw_mci_drv_data *drv_data = host->drv_data;
2284 int ctrl_id, ret;
2285 u32 freq[2];
2286
2287 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2288 if (!mmc)
2289 return -ENOMEM;
2290
2291 slot = mmc_priv(mmc);
2292 slot->id = id;
2293 slot->sdio_id = host->sdio_id0 + id;
2294 slot->mmc = mmc;
2295 slot->host = host;
2296 host->slot[id] = slot;
2297
2298 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2299
2300 mmc->ops = &dw_mci_ops;
2301 if (of_property_read_u32_array(host->dev->of_node,
2302 "clock-freq-min-max", freq, 2)) {
2303 mmc->f_min = DW_MCI_FREQ_MIN;
2304 mmc->f_max = DW_MCI_FREQ_MAX;
2305 } else {
2306 mmc->f_min = freq[0];
2307 mmc->f_max = freq[1];
2308 }
2309
2310 /*if there are external regulators, get them*/
2311 ret = mmc_regulator_get_supply(mmc);
2312 if (ret == -EPROBE_DEFER)
2313 goto err_host_allocated;
2314
2315 if (!mmc->ocr_avail)
2316 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2317
2318 if (host->pdata->caps)
2319 mmc->caps = host->pdata->caps;
2320
2321 if (host->pdata->pm_caps)
2322 mmc->pm_caps = host->pdata->pm_caps;
2323
2324 if (host->dev->of_node) {
2325 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2326 if (ctrl_id < 0)
2327 ctrl_id = 0;
2328 } else {
2329 ctrl_id = to_platform_device(host->dev)->id;
2330 }
2331 if (drv_data && drv_data->caps)
2332 mmc->caps |= drv_data->caps[ctrl_id];
2333
2334 if (host->pdata->caps2)
2335 mmc->caps2 = host->pdata->caps2;
2336
2337 ret = mmc_of_parse(mmc);
2338 if (ret)
2339 goto err_host_allocated;
2340
2341 if (host->pdata->blk_settings) {
2342 mmc->max_segs = host->pdata->blk_settings->max_segs;
2343 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2344 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2345 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2346 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2347 } else {
2348 /* Useful defaults if platform data is unset. */
2349 #ifdef CONFIG_MMC_DW_IDMAC
2350 mmc->max_segs = host->ring_size;
2351 mmc->max_blk_size = 65536;
2352 mmc->max_seg_size = 0x1000;
2353 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2354 mmc->max_blk_count = mmc->max_req_size / 512;
2355 #else
2356 mmc->max_segs = 64;
2357 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2358 mmc->max_blk_count = 512;
2359 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2360 mmc->max_seg_size = mmc->max_req_size;
2361 #endif /* CONFIG_MMC_DW_IDMAC */
2362 }
2363
2364 if (dw_mci_get_cd(mmc))
2365 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2366 else
2367 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2368
2369 ret = mmc_add_host(mmc);
2370 if (ret)
2371 goto err_host_allocated;
2372
2373 #if defined(CONFIG_DEBUG_FS)
2374 dw_mci_init_debugfs(slot);
2375 #endif
2376
2377 return 0;
2378
2379 err_host_allocated:
2380 mmc_free_host(mmc);
2381 return ret;
2382 }
2383
2384 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2385 {
2386 /* Debugfs stuff is cleaned up by mmc core */
2387 mmc_remove_host(slot->mmc);
2388 slot->host->slot[id] = NULL;
2389 mmc_free_host(slot->mmc);
2390 }
2391
2392 static void dw_mci_init_dma(struct dw_mci *host)
2393 {
2394 int addr_config;
2395 /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
2396 addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
2397
2398 if (addr_config == 1) {
2399 /* host supports IDMAC in 64-bit address mode */
2400 host->dma_64bit_address = 1;
2401 dev_info(host->dev, "IDMAC supports 64-bit address mode.\n");
2402 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2403 dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64));
2404 } else {
2405 /* host supports IDMAC in 32-bit address mode */
2406 host->dma_64bit_address = 0;
2407 dev_info(host->dev, "IDMAC supports 32-bit address mode.\n");
2408 }
2409
2410 /* Alloc memory for sg translation */
2411 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2412 &host->sg_dma, GFP_KERNEL);
2413 if (!host->sg_cpu) {
2414 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2415 __func__);
2416 goto no_dma;
2417 }
2418
2419 /* Determine which DMA interface to use */
2420 #ifdef CONFIG_MMC_DW_IDMAC
2421 host->dma_ops = &dw_mci_idmac_ops;
2422 dev_info(host->dev, "Using internal DMA controller.\n");
2423 #endif
2424
2425 if (!host->dma_ops)
2426 goto no_dma;
2427
2428 if (host->dma_ops->init && host->dma_ops->start &&
2429 host->dma_ops->stop && host->dma_ops->cleanup) {
2430 if (host->dma_ops->init(host)) {
2431 dev_err(host->dev, "%s: Unable to initialize "
2432 "DMA Controller.\n", __func__);
2433 goto no_dma;
2434 }
2435 } else {
2436 dev_err(host->dev, "DMA initialization not found.\n");
2437 goto no_dma;
2438 }
2439
2440 host->use_dma = 1;
2441 return;
2442
2443 no_dma:
2444 dev_info(host->dev, "Using PIO mode.\n");
2445 host->use_dma = 0;
2446 return;
2447 }
2448
2449 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2450 {
2451 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2452 u32 ctrl;
2453
2454 ctrl = mci_readl(host, CTRL);
2455 ctrl |= reset;
2456 mci_writel(host, CTRL, ctrl);
2457
2458 /* wait till resets clear */
2459 do {
2460 ctrl = mci_readl(host, CTRL);
2461 if (!(ctrl & reset))
2462 return true;
2463 } while (time_before(jiffies, timeout));
2464
2465 dev_err(host->dev,
2466 "Timeout resetting block (ctrl reset %#x)\n",
2467 ctrl & reset);
2468
2469 return false;
2470 }
2471
2472 static bool dw_mci_reset(struct dw_mci *host)
2473 {
2474 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2475 bool ret = false;
2476
2477 /*
2478 * Reseting generates a block interrupt, hence setting
2479 * the scatter-gather pointer to NULL.
2480 */
2481 if (host->sg) {
2482 sg_miter_stop(&host->sg_miter);
2483 host->sg = NULL;
2484 }
2485
2486 if (host->use_dma)
2487 flags |= SDMMC_CTRL_DMA_RESET;
2488
2489 if (dw_mci_ctrl_reset(host, flags)) {
2490 /*
2491 * In all cases we clear the RAWINTS register to clear any
2492 * interrupts.
2493 */
2494 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2495
2496 /* if using dma we wait for dma_req to clear */
2497 if (host->use_dma) {
2498 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2499 u32 status;
2500 do {
2501 status = mci_readl(host, STATUS);
2502 if (!(status & SDMMC_STATUS_DMA_REQ))
2503 break;
2504 cpu_relax();
2505 } while (time_before(jiffies, timeout));
2506
2507 if (status & SDMMC_STATUS_DMA_REQ) {
2508 dev_err(host->dev,
2509 "%s: Timeout waiting for dma_req to "
2510 "clear during reset\n", __func__);
2511 goto ciu_out;
2512 }
2513
2514 /* when using DMA next we reset the fifo again */
2515 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2516 goto ciu_out;
2517 }
2518 } else {
2519 /* if the controller reset bit did clear, then set clock regs */
2520 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2521 dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2522 "clear but ciu was reset, doing clock update\n",
2523 __func__);
2524 goto ciu_out;
2525 }
2526 }
2527
2528 #if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2529 /* It is also recommended that we reset and reprogram idmac */
2530 dw_mci_idmac_reset(host);
2531 #endif
2532
2533 ret = true;
2534
2535 ciu_out:
2536 /* After a CTRL reset we need to have CIU set clock registers */
2537 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2538
2539 return ret;
2540 }
2541
2542 #ifdef CONFIG_OF
2543 static struct dw_mci_of_quirks {
2544 char *quirk;
2545 int id;
2546 } of_quirks[] = {
2547 {
2548 .quirk = "broken-cd",
2549 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2550 }, {
2551 .quirk = "disable-wp",
2552 .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
2553 },
2554 };
2555
2556 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2557 {
2558 struct dw_mci_board *pdata;
2559 struct device *dev = host->dev;
2560 struct device_node *np = dev->of_node;
2561 const struct dw_mci_drv_data *drv_data = host->drv_data;
2562 int idx, ret;
2563 u32 clock_frequency;
2564
2565 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2566 if (!pdata)
2567 return ERR_PTR(-ENOMEM);
2568
2569 /* find out number of slots supported */
2570 if (of_property_read_u32(dev->of_node, "num-slots",
2571 &pdata->num_slots)) {
2572 dev_info(dev, "num-slots property not found, "
2573 "assuming 1 slot is available\n");
2574 pdata->num_slots = 1;
2575 }
2576
2577 /* get quirks */
2578 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2579 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2580 pdata->quirks |= of_quirks[idx].id;
2581
2582 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2583 dev_info(dev, "fifo-depth property not found, using "
2584 "value of FIFOTH register as default\n");
2585
2586 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2587
2588 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2589 pdata->bus_hz = clock_frequency;
2590
2591 if (drv_data && drv_data->parse_dt) {
2592 ret = drv_data->parse_dt(host);
2593 if (ret)
2594 return ERR_PTR(ret);
2595 }
2596
2597 if (of_find_property(np, "supports-highspeed", NULL))
2598 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2599
2600 return pdata;
2601 }
2602
2603 #else /* CONFIG_OF */
2604 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2605 {
2606 return ERR_PTR(-EINVAL);
2607 }
2608 #endif /* CONFIG_OF */
2609
2610 int dw_mci_probe(struct dw_mci *host)
2611 {
2612 const struct dw_mci_drv_data *drv_data = host->drv_data;
2613 int width, i, ret = 0;
2614 u32 fifo_size;
2615 int init_slots = 0;
2616
2617 if (!host->pdata) {
2618 host->pdata = dw_mci_parse_dt(host);
2619 if (IS_ERR(host->pdata)) {
2620 dev_err(host->dev, "platform data not available\n");
2621 return -EINVAL;
2622 }
2623 }
2624
2625 if (host->pdata->num_slots > 1) {
2626 dev_err(host->dev,
2627 "Platform data must supply num_slots.\n");
2628 return -ENODEV;
2629 }
2630
2631 host->biu_clk = devm_clk_get(host->dev, "biu");
2632 if (IS_ERR(host->biu_clk)) {
2633 dev_dbg(host->dev, "biu clock not available\n");
2634 } else {
2635 ret = clk_prepare_enable(host->biu_clk);
2636 if (ret) {
2637 dev_err(host->dev, "failed to enable biu clock\n");
2638 return ret;
2639 }
2640 }
2641
2642 host->ciu_clk = devm_clk_get(host->dev, "ciu");
2643 if (IS_ERR(host->ciu_clk)) {
2644 dev_dbg(host->dev, "ciu clock not available\n");
2645 host->bus_hz = host->pdata->bus_hz;
2646 } else {
2647 ret = clk_prepare_enable(host->ciu_clk);
2648 if (ret) {
2649 dev_err(host->dev, "failed to enable ciu clock\n");
2650 goto err_clk_biu;
2651 }
2652
2653 if (host->pdata->bus_hz) {
2654 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2655 if (ret)
2656 dev_warn(host->dev,
2657 "Unable to set bus rate to %uHz\n",
2658 host->pdata->bus_hz);
2659 }
2660 host->bus_hz = clk_get_rate(host->ciu_clk);
2661 }
2662
2663 if (!host->bus_hz) {
2664 dev_err(host->dev,
2665 "Platform data must supply bus speed\n");
2666 ret = -ENODEV;
2667 goto err_clk_ciu;
2668 }
2669
2670 if (drv_data && drv_data->init) {
2671 ret = drv_data->init(host);
2672 if (ret) {
2673 dev_err(host->dev,
2674 "implementation specific init failed\n");
2675 goto err_clk_ciu;
2676 }
2677 }
2678
2679 if (drv_data && drv_data->setup_clock) {
2680 ret = drv_data->setup_clock(host);
2681 if (ret) {
2682 dev_err(host->dev,
2683 "implementation specific clock setup failed\n");
2684 goto err_clk_ciu;
2685 }
2686 }
2687
2688 host->quirks = host->pdata->quirks;
2689
2690 spin_lock_init(&host->lock);
2691 spin_lock_init(&host->irq_lock);
2692 INIT_LIST_HEAD(&host->queue);
2693
2694 /*
2695 * Get the host data width - this assumes that HCON has been set with
2696 * the correct values.
2697 */
2698 i = (mci_readl(host, HCON) >> 7) & 0x7;
2699 if (!i) {
2700 host->push_data = dw_mci_push_data16;
2701 host->pull_data = dw_mci_pull_data16;
2702 width = 16;
2703 host->data_shift = 1;
2704 } else if (i == 2) {
2705 host->push_data = dw_mci_push_data64;
2706 host->pull_data = dw_mci_pull_data64;
2707 width = 64;
2708 host->data_shift = 3;
2709 } else {
2710 /* Check for a reserved value, and warn if it is */
2711 WARN((i != 1),
2712 "HCON reports a reserved host data width!\n"
2713 "Defaulting to 32-bit access.\n");
2714 host->push_data = dw_mci_push_data32;
2715 host->pull_data = dw_mci_pull_data32;
2716 width = 32;
2717 host->data_shift = 2;
2718 }
2719
2720 /* Reset all blocks */
2721 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2722 return -ENODEV;
2723
2724 host->dma_ops = host->pdata->dma_ops;
2725 dw_mci_init_dma(host);
2726
2727 /* Clear the interrupts for the host controller */
2728 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2729 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2730
2731 /* Put in max timeout */
2732 mci_writel(host, TMOUT, 0xFFFFFFFF);
2733
2734 /*
2735 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2736 * Tx Mark = fifo_size / 2 DMA Size = 8
2737 */
2738 if (!host->pdata->fifo_depth) {
2739 /*
2740 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2741 * have been overwritten by the bootloader, just like we're
2742 * about to do, so if you know the value for your hardware, you
2743 * should put it in the platform data.
2744 */
2745 fifo_size = mci_readl(host, FIFOTH);
2746 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2747 } else {
2748 fifo_size = host->pdata->fifo_depth;
2749 }
2750 host->fifo_depth = fifo_size;
2751 host->fifoth_val =
2752 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
2753 mci_writel(host, FIFOTH, host->fifoth_val);
2754
2755 /* disable clock to CIU */
2756 mci_writel(host, CLKENA, 0);
2757 mci_writel(host, CLKSRC, 0);
2758
2759 /*
2760 * In 2.40a spec, Data offset is changed.
2761 * Need to check the version-id and set data-offset for DATA register.
2762 */
2763 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2764 dev_info(host->dev, "Version ID is %04x\n", host->verid);
2765
2766 if (host->verid < DW_MMC_240A)
2767 host->data_offset = DATA_OFFSET;
2768 else
2769 host->data_offset = DATA_240A_OFFSET;
2770
2771 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2772 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2773 host->irq_flags, "dw-mci", host);
2774 if (ret)
2775 goto err_dmaunmap;
2776
2777 if (host->pdata->num_slots)
2778 host->num_slots = host->pdata->num_slots;
2779 else
2780 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2781
2782 /*
2783 * Enable interrupts for command done, data over, data empty, card det,
2784 * receive ready and error such as transmit, receive timeout, crc error
2785 */
2786 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2787 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2788 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2789 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2790 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2791
2792 dev_info(host->dev, "DW MMC controller at irq %d, "
2793 "%d bit host data width, "
2794 "%u deep fifo\n",
2795 host->irq, width, fifo_size);
2796
2797 /* We need at least one slot to succeed */
2798 for (i = 0; i < host->num_slots; i++) {
2799 ret = dw_mci_init_slot(host, i);
2800 if (ret)
2801 dev_dbg(host->dev, "slot %d init failed\n", i);
2802 else
2803 init_slots++;
2804 }
2805
2806 if (init_slots) {
2807 dev_info(host->dev, "%d slots initialized\n", init_slots);
2808 } else {
2809 dev_dbg(host->dev, "attempted to initialize %d slots, "
2810 "but failed on all\n", host->num_slots);
2811 goto err_dmaunmap;
2812 }
2813
2814 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2815 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2816
2817 return 0;
2818
2819 err_dmaunmap:
2820 if (host->use_dma && host->dma_ops->exit)
2821 host->dma_ops->exit(host);
2822
2823 err_clk_ciu:
2824 if (!IS_ERR(host->ciu_clk))
2825 clk_disable_unprepare(host->ciu_clk);
2826
2827 err_clk_biu:
2828 if (!IS_ERR(host->biu_clk))
2829 clk_disable_unprepare(host->biu_clk);
2830
2831 return ret;
2832 }
2833 EXPORT_SYMBOL(dw_mci_probe);
2834
2835 void dw_mci_remove(struct dw_mci *host)
2836 {
2837 int i;
2838
2839 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2840 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2841
2842 for (i = 0; i < host->num_slots; i++) {
2843 dev_dbg(host->dev, "remove slot %d\n", i);
2844 if (host->slot[i])
2845 dw_mci_cleanup_slot(host->slot[i], i);
2846 }
2847
2848 /* disable clock to CIU */
2849 mci_writel(host, CLKENA, 0);
2850 mci_writel(host, CLKSRC, 0);
2851
2852 if (host->use_dma && host->dma_ops->exit)
2853 host->dma_ops->exit(host);
2854
2855 if (!IS_ERR(host->ciu_clk))
2856 clk_disable_unprepare(host->ciu_clk);
2857
2858 if (!IS_ERR(host->biu_clk))
2859 clk_disable_unprepare(host->biu_clk);
2860 }
2861 EXPORT_SYMBOL(dw_mci_remove);
2862
2863
2864
2865 #ifdef CONFIG_PM_SLEEP
2866 /*
2867 * TODO: we should probably disable the clock to the card in the suspend path.
2868 */
2869 int dw_mci_suspend(struct dw_mci *host)
2870 {
2871 return 0;
2872 }
2873 EXPORT_SYMBOL(dw_mci_suspend);
2874
2875 int dw_mci_resume(struct dw_mci *host)
2876 {
2877 int i, ret;
2878
2879 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2880 ret = -ENODEV;
2881 return ret;
2882 }
2883
2884 if (host->use_dma && host->dma_ops->init)
2885 host->dma_ops->init(host);
2886
2887 /*
2888 * Restore the initial value at FIFOTH register
2889 * And Invalidate the prev_blksz with zero
2890 */
2891 mci_writel(host, FIFOTH, host->fifoth_val);
2892 host->prev_blksz = 0;
2893
2894 /* Put in max timeout */
2895 mci_writel(host, TMOUT, 0xFFFFFFFF);
2896
2897 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2898 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2899 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2900 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2901 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2902
2903 for (i = 0; i < host->num_slots; i++) {
2904 struct dw_mci_slot *slot = host->slot[i];
2905 if (!slot)
2906 continue;
2907 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2908 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2909 dw_mci_setup_bus(slot, true);
2910 }
2911 }
2912 return 0;
2913 }
2914 EXPORT_SYMBOL(dw_mci_resume);
2915 #endif /* CONFIG_PM_SLEEP */
2916
2917 static int __init dw_mci_init(void)
2918 {
2919 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
2920 return 0;
2921 }
2922
2923 static void __exit dw_mci_exit(void)
2924 {
2925 }
2926
2927 module_init(dw_mci_init);
2928 module_exit(dw_mci_exit);
2929
2930 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2931 MODULE_AUTHOR("NXP Semiconductor VietNam");
2932 MODULE_AUTHOR("Imagination Technologies Ltd");
2933 MODULE_LICENSE("GPL v2");
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