ARM: mvebu: add Device Tree description of AHCI interfaces on Armada 38x
[linux-2.6/btrfs-unstable.git] / arch / arm / mach-socfpga / core.h
blob572b8f719ffbf040c6d6e5f4b5274f21e89045db
1 /*
2 * Copyright 2012 Pavel Machek <pavel@denx.de>
3 * Copyright (C) 2012 Altera Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef __MACH_CORE_H
21 #define __MACH_CORE_H
23 #define SOCFPGA_RSTMGR_CTRL 0x04
24 #define SOCFPGA_RSTMGR_MODPERRST 0x14
25 #define SOCFPGA_RSTMGR_BRGMODRST 0x1c
27 /* System Manager bits */
28 #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
29 #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
31 extern void socfpga_secondary_startup(void);
32 extern void __iomem *socfpga_scu_base_addr;
34 extern void socfpga_init_clocks(void);
35 extern void socfpga_sysmgr_init(void);
37 extern void __iomem *sys_manager_base_addr;
38 extern void __iomem *rst_manager_base_addr;
40 extern struct smp_operations socfpga_smp_ops;
41 extern char secondary_trampoline, secondary_trampoline_end;
43 extern unsigned long cpu1start_addr;
45 #define SOCFPGA_SCU_VIRT_BASE 0xfffec000
47 #endif