arch/arm/boot/dts/armada-38x.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 38x family of SoCs.
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include "skeleton.dtsi"
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/interrupt-controller/irq.h>
  18
  19 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  20
  21 / {
  22         model = "Marvell Armada 38x family SoC";
  23         compatible = "marvell,armada38x";
  24
  25         aliases {
  26                 gpio0 = &gpio0;
  27                 gpio1 = &gpio1;
  28                 eth0 = &eth0;
  29                 eth1 = &eth1;
  30                 eth2 = &eth2;
  31         };
  32
  33         soc {
  34                 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
  35                              "simple-bus";
  36                 #address-cells = <2>;
  37                 #size-cells = <1>;
  38                 controller = <&mbusc>;
  39                 interrupt-parent = <&gic>;
  40                 pcie-mem-aperture = <0xe0000000 0x8000000>;
  41                 pcie-io-aperture  = <0xe8000000 0x100000>;
  42
  43                 bootrom {
  44                         compatible = "marvell,bootrom";
  45                         reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
  46                 };
  47
  48                 devbus-bootcs {
  49                         compatible = "marvell,mvebu-devbus";
  50                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  51                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  52                         #address-cells = <1>;
  53                         #size-cells = <1>;
  54                         clocks = <&coreclk 0>;
  55                         status = "disabled";
  56                 };
  57
  58                 devbus-cs0 {
  59                         compatible = "marvell,mvebu-devbus";
  60                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  61                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  62                         #address-cells = <1>;
  63                         #size-cells = <1>;
  64                         clocks = <&coreclk 0>;
  65                         status = "disabled";
  66                 };
  67
  68                 devbus-cs1 {
  69                         compatible = "marvell,mvebu-devbus";
  70                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
  71                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         clocks = <&coreclk 0>;
  75                         status = "disabled";
  76                 };
  77
  78                 devbus-cs2 {
  79                         compatible = "marvell,mvebu-devbus";
  80                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
  81                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84                         clocks = <&coreclk 0>;
  85                         status = "disabled";
  86                 };
  87
  88                 devbus-cs3 {
  89                         compatible = "marvell,mvebu-devbus";
  90                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
  91                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94                         clocks = <&coreclk 0>;
  95                         status = "disabled";
  96                 };
  97
  98                 internal-regs {
  99                         compatible = "simple-bus";
 100                         #address-cells = <1>;
 101                         #size-cells = <1>;
 102                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 103
 104                         L2: cache-controller@8000 {
 105                                 compatible = "arm,pl310-cache";
 106                                 reg = <0x8000 0x1000>;
 107                                 cache-unified;
 108                                 cache-level = <2>;
 109                         };
 110
 111                         scu@c000 {
 112                                 compatible = "arm,cortex-a9-scu";
 113                                 reg = <0xc000 0x58>;
 114                         };
 115
 116                         timer@c600 {
 117                                 compatible = "arm,cortex-a9-twd-timer";
 118                                 reg = <0xc600 0x20>;
 119                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
 120                                 clocks = <&coreclk 2>;
 121                         };
 122
 123                         gic: interrupt-controller@d000 {
 124                                 compatible = "arm,cortex-a9-gic";
 125                                 #interrupt-cells = <3>;
 126                                 #size-cells = <0>;
 127                                 interrupt-controller;
 128                                 reg = <0xd000 0x1000>,
 129                                       <0xc100 0x100>;
 130                         };
 131
 132                         spi0: spi@10600 {
 133                                 compatible = "marvell,orion-spi";
 134                                 reg = <0x10600 0x50>;
 135                                 #address-cells = <1>;
 136                                 #size-cells = <0>;
 137                                 cell-index = <0>;
 138                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 139                                 clocks = <&coreclk 0>;
 140                                 status = "disabled";
 141                         };
 142
 143                         spi1: spi@10680 {
 144                                 compatible = "marvell,orion-spi";
 145                                 reg = <0x10680 0x50>;
 146                                 #address-cells = <1>;
 147                                 #size-cells = <0>;
 148                                 cell-index = <1>;
 149                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 150                                 clocks = <&coreclk 0>;
 151                                 status = "disabled";
 152                         };
 153
 154                         i2c0: i2c@11000 {
 155                                 compatible = "marvell,mv64xxx-i2c";
 156                                 reg = <0x11000 0x20>;
 157                                 #address-cells = <1>;
 158                                 #size-cells = <0>;
 159                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 160                                 timeout-ms = <1000>;
 161                                 clocks = <&coreclk 0>;
 162                                 status = "disabled";
 163                         };
 164
 165                         i2c1: i2c@11100 {
 166                                 compatible = "marvell,mv64xxx-i2c";
 167                                 reg = <0x11100 0x20>;
 168                                 #address-cells = <1>;
 169                                 #size-cells = <0>;
 170                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 171                                 timeout-ms = <1000>;
 172                                 clocks = <&coreclk 0>;
 173                                 status = "disabled";
 174                         };
 175
 176                         serial@12000 {
 177                                 compatible = "snps,dw-apb-uart";
 178                                 reg = <0x12000 0x100>;
 179                                 reg-shift = <2>;
 180                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 181                                 reg-io-width = <1>;
 182                                 status = "disabled";
 183                         };
 184
 185                         serial@12100 {
 186                                 compatible = "snps,dw-apb-uart";
 187                                 reg = <0x12100 0x100>;
 188                                 reg-shift = <2>;
 189                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 190                                 reg-io-width = <1>;
 191                                 status = "disabled";
 192                         };
 193
 194                         pinctrl {
 195                                 compatible = "marvell,mv88f6820-pinctrl";
 196                                 reg = <0x18000 0x20>;
 197                         };
 198
 199                         gpio0: gpio@18100 {
 200                                 compatible = "marvell,orion-gpio";
 201                                 reg = <0x18100 0x40>;
 202                                 ngpios = <32>;
 203                                 gpio-controller;
 204                                 #gpio-cells = <2>;
 205                                 interrupt-controller;
 206                                 #interrupt-cells = <2>;
 207                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 208                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 209                                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 210                                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 211                         };
 212
 213                         gpio1: gpio@18140 {
 214                                 compatible = "marvell,orion-gpio";
 215                                 reg = <0x18140 0x40>;
 216                                 ngpios = <28>;
 217                                 gpio-controller;
 218                                 #gpio-cells = <2>;
 219                                 interrupt-controller;
 220                                 #interrupt-cells = <2>;
 221                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 222                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 223                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 224                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 225                         };
 226
 227                         system-controller@18200 {
 228                                 compatible = "marvell,armada-380-system-controller",
 229                                              "marvell,armada-370-xp-system-controller";
 230                                 reg = <0x18200 0x100>;
 231                         };
 232
 233                         gateclk: clock-gating-control@18220 {
 234                                 compatible = "marvell,armada-380-gating-clock";
 235                                 reg = <0x18220 0x4>;
 236                                 clocks = <&coreclk 0>;
 237                                 #clock-cells = <1>;
 238                         };
 239
 240                         coreclk: mvebu-sar@18600 {
 241                                 compatible = "marvell,armada-380-core-clock";
 242                                 reg = <0x18600 0x04>;
 243                                 #clock-cells = <1>;
 244                         };
 245
 246                         mbusc: mbus-controller@20000 {
 247                                 compatible = "marvell,mbus-controller";
 248                                 reg = <0x20000 0x100>, <0x20180 0x20>;
 249                         };
 250
 251                         mpic: interrupt-controller@20000 {
 252                                 compatible = "marvell,mpic";
 253                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 254                                 #interrupt-cells = <1>;
 255                                 #size-cells = <1>;
 256                                 interrupt-controller;
 257                                 msi-controller;
 258                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 259                         };
 260
 261                         timer@20300 {
 262                                 compatible = "marvell,armada-380-timer",
 263                                              "marvell,armada-xp-timer";
 264                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 265                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 266                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 267                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 268                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 269                                                       <&mpic 5>,
 270                                                       <&mpic 6>;
 271                                 clocks = <&coreclk 2>, <&refclk>;
 272                                 clock-names = "nbclk", "fixed";
 273                         };
 274
 275                         watchdog@20300 {
 276                                 compatible = "marvell,armada-380-wdt";
 277                                 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
 278                                 clocks = <&coreclk 2>, <&refclk>;
 279                                 clock-names = "nbclk", "fixed";
 280                         };
 281
 282                         cpurst@20800 {
 283                                 compatible = "marvell,armada-370-cpu-reset";
 284                                 reg = <0x20800 0x10>;
 285                         };
 286
 287                         coherency-fabric@21010 {
 288                                 compatible = "marvell,armada-380-coherency-fabric";
 289                                 reg = <0x21010 0x1c>;
 290                         };
 291
 292                         pmsu@22000 {
 293                                 compatible = "marvell,armada-380-pmsu";
 294                                 reg = <0x22000 0x1000>;
 295                         };
 296
 297                         eth1: ethernet@30000 {
 298                                 compatible = "marvell,armada-370-neta";
 299                                 reg = <0x30000 0x4000>;
 300                                 interrupts-extended = <&mpic 10>;
 301                                 clocks = <&gateclk 3>;
 302                                 status = "disabled";
 303                         };
 304
 305                         eth2: ethernet@34000 {
 306                                 compatible = "marvell,armada-370-neta";
 307                                 reg = <0x34000 0x4000>;
 308                                 interrupts-extended = <&mpic 12>;
 309                                 clocks = <&gateclk 2>;
 310                                 status = "disabled";
 311                         };
 312
 313                         xor@60800 {
 314                                 compatible = "marvell,orion-xor";
 315                                 reg = <0x60800 0x100
 316                                        0x60a00 0x100>;
 317                                 clocks = <&gateclk 22>;
 318                                 status = "okay";
 319
 320                                 xor00 {
 321                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 322                                         dmacap,memcpy;
 323                                         dmacap,xor;
 324                                 };
 325                                 xor01 {
 326                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 327                                         dmacap,memcpy;
 328                                         dmacap,xor;
 329                                         dmacap,memset;
 330                                 };
 331                         };
 332
 333                         xor@60900 {
 334                                 compatible = "marvell,orion-xor";
 335                                 reg = <0x60900 0x100
 336                                        0x60b00 0x100>;
 337                                 clocks = <&gateclk 28>;
 338                                 status = "okay";
 339
 340                                 xor10 {
 341                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 342                                         dmacap,memcpy;
 343                                         dmacap,xor;
 344                                 };
 345                                 xor11 {
 346                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 347                                         dmacap,memcpy;
 348                                         dmacap,xor;
 349                                         dmacap,memset;
 350                                 };
 351                         };
 352
 353                         eth0: ethernet@70000 {
 354                                 compatible = "marvell,armada-370-neta";
 355                                 reg = <0x70000 0x4000>;
 356                                 interrupts-extended = <&mpic 8>;
 357                                 clocks = <&gateclk 4>;
 358                                 status = "disabled";
 359                         };
 360
 361                         mdio {
 362                                 #address-cells = <1>;
 363                                 #size-cells = <0>;
 364                                 compatible = "marvell,orion-mdio";
 365                                 reg = <0x72004 0x4>;
 366                         };
 367
 368                         sata@a8000 {
 369                                 compatible = "marvell,armada-380-ahci";
 370                                 reg = <0xa8000 0x2000>;
 371                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 372                                 clocks = <&gateclk 15>;
 373                                 status = "disabled";
 374                         };
 375
 376                         sata@e0000 {
 377                                 compatible = "marvell,armada-380-ahci";
 378                                 reg = <0xe0000 0x2000>;
 379                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 380                                 clocks = <&gateclk 30>;
 381                                 status = "disabled";
 382                         };
 383
 384                         coredivclk: clock@e4250 {
 385                                 compatible = "marvell,armada-380-corediv-clock";
 386                                 reg = <0xe4250 0xc>;
 387                                 #clock-cells = <1>;
 388                                 clocks = <&mainpll>;
 389                                 clock-output-names = "nand";
 390                         };
 391
 392                         flash@d0000 {
 393                                 compatible = "marvell,armada370-nand";
 394                                 reg = <0xd0000 0x54>;
 395                                 #address-cells = <1>;
 396                                 #size-cells = <1>;
 397                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 398                                 clocks = <&coredivclk 0>;
 399                                 status = "disabled";
 400                         };
 401
 402                         sdhci@d8000 {
 403                                 compatible = "marvell,armada-380-sdhci";
 404                                 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
 405                                 interrupts = <0 25 0x4>;
 406                                 clocks = <&gateclk 17>;
 407                                 mrvl,clk-delay-cycles = <0x1F>;
 408                                 status = "disabled";
 409                         };
 410                 };
 411         };
 412
 413         clocks {
 414                 /* 2 GHz fixed main PLL */
 415                 mainpll: mainpll {
 416                         compatible = "fixed-clock";
 417                         #clock-cells = <0>;
 418                         clock-frequency = <2000000000>;
 419                 };
 420
 421                 /* 25 MHz reference crystal */
 422                 refclk: oscillator {
 423                         compatible = "fixed-clock";
 424                         #clock-cells = <0>;
 425                         clock-frequency = <25000000>;
 426                 };
 427         };
 428 };