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i40e: increase reset wait time
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
blobfd2b573d30505e638b5a1bdefc91dd7c509fe744
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_SFP_X710:
47 case I40E_DEV_ID_QEMU:
48 case I40E_DEV_ID_KX_A:
49 case I40E_DEV_ID_KX_B:
50 case I40E_DEV_ID_KX_C:
51 case I40E_DEV_ID_KX_D:
52 case I40E_DEV_ID_QSFP_A:
53 case I40E_DEV_ID_QSFP_B:
54 case I40E_DEV_ID_QSFP_C:
55 hw->mac.type = I40E_MAC_XL710;
56 break;
57 case I40E_DEV_ID_VF:
58 case I40E_DEV_ID_VF_HV:
59 hw->mac.type = I40E_MAC_VF;
60 break;
61 default:
62 hw->mac.type = I40E_MAC_GENERIC;
63 break;
64 }
65 } else {
66 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
67 }
68
69 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
70 hw->mac.type, status);
71 return status;
72 }
73
74 /**
75 * i40e_debug_aq
76 * @hw: debug mask related to admin queue
77 * @mask: debug mask
78 * @desc: pointer to admin queue descriptor
79 * @buffer: pointer to command buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer)
85 {
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u8 *aq_buffer = (u8 *)buffer;
88 u32 data[4];
89 u32 i = 0;
90
91 if ((!(mask & hw->debug_mask)) || (desc == NULL))
92 return;
93
94 i40e_debug(hw, mask,
95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
96 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
97 aq_desc->retval);
98 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
99 aq_desc->cookie_high, aq_desc->cookie_low);
100 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
101 aq_desc->params.internal.param0,
102 aq_desc->params.internal.param1);
103 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
104 aq_desc->params.external.addr_high,
105 aq_desc->params.external.addr_low);
106
107 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
108 memset(data, 0, sizeof(data));
109 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
110 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
111 data[((i % 16) / 4)] |=
112 ((u32)aq_buffer[i]) << (8 * (i % 4));
113 if ((i % 16) == 15) {
114 i40e_debug(hw, mask,
115 "\t0x%04X %08X %08X %08X %08X\n",
116 i - 15, data[0], data[1], data[2],
117 data[3]);
118 memset(data, 0, sizeof(data));
119 }
120 }
121 if ((i % 16) != 0)
122 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
123 i - (i % 16), data[0], data[1], data[2],
124 data[3]);
125 }
126 }
127
128 /**
129 * i40e_check_asq_alive
130 * @hw: pointer to the hw struct
131 *
132 * Returns true if Queue is enabled else false.
133 **/
134 bool i40e_check_asq_alive(struct i40e_hw *hw)
135 {
136 if (hw->aq.asq.len)
137 return !!(rd32(hw, hw->aq.asq.len) &
138 I40E_PF_ATQLEN_ATQENABLE_MASK);
139 else
140 return false;
141 }
142
143 /**
144 * i40e_aq_queue_shutdown
145 * @hw: pointer to the hw struct
146 * @unloading: is the driver unloading itself
147 *
148 * Tell the Firmware that we're shutting down the AdminQ and whether
149 * or not the driver is unloading as well.
150 **/
151 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
152 bool unloading)
153 {
154 struct i40e_aq_desc desc;
155 struct i40e_aqc_queue_shutdown *cmd =
156 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
157 i40e_status status;
158
159 i40e_fill_default_direct_cmd_desc(&desc,
160 i40e_aqc_opc_queue_shutdown);
161
162 if (unloading)
163 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
164 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
165
166 return status;
167 }
168
169 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
170 * hardware to a bit-field that can be used by SW to more easily determine the
171 * packet type.
172 *
173 * Macros are used to shorten the table lines and make this table human
174 * readable.
175 *
176 * We store the PTYPE in the top byte of the bit field - this is just so that
177 * we can check that the table doesn't have a row missing, as the index into
178 * the table should be the PTYPE.
179 *
180 * Typical work flow:
181 *
182 * IF NOT i40e_ptype_lookup[ptype].known
183 * THEN
184 * Packet is unknown
185 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
186 * Use the rest of the fields to look at the tunnels, inner protocols, etc
187 * ELSE
188 * Use the enum i40e_rx_l2_ptype to decode the packet type
189 * ENDIF
190 */
191
192 /* macro to make the table lines short */
193 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
194 { PTYPE, \
195 1, \
196 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
197 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
198 I40E_RX_PTYPE_##OUTER_FRAG, \
199 I40E_RX_PTYPE_TUNNEL_##T, \
200 I40E_RX_PTYPE_TUNNEL_END_##TE, \
201 I40E_RX_PTYPE_##TEF, \
202 I40E_RX_PTYPE_INNER_PROT_##I, \
203 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
204
205 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
206 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
207
208 /* shorter macros makes the table fit but are terse */
209 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
210 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
211 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
212
213 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
214 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
215 /* L2 Packet types */
216 I40E_PTT_UNUSED_ENTRY(0),
217 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
218 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
219 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
220 I40E_PTT_UNUSED_ENTRY(4),
221 I40E_PTT_UNUSED_ENTRY(5),
222 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
223 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
224 I40E_PTT_UNUSED_ENTRY(8),
225 I40E_PTT_UNUSED_ENTRY(9),
226 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
227 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
228 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
229 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
230 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
231 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
237 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
238
239 /* Non Tunneled IPv4 */
240 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
241 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
242 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
243 I40E_PTT_UNUSED_ENTRY(25),
244 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
245 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
246 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
247
248 /* IPv4 --> IPv4 */
249 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
250 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
251 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
252 I40E_PTT_UNUSED_ENTRY(32),
253 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
254 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
255 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
256
257 /* IPv4 --> IPv6 */
258 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
259 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
260 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
261 I40E_PTT_UNUSED_ENTRY(39),
262 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
263 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
264 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
265
266 /* IPv4 --> GRE/NAT */
267 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
268
269 /* IPv4 --> GRE/NAT --> IPv4 */
270 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
271 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
272 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
273 I40E_PTT_UNUSED_ENTRY(47),
274 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
275 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
276 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
277
278 /* IPv4 --> GRE/NAT --> IPv6 */
279 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
280 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
281 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
282 I40E_PTT_UNUSED_ENTRY(54),
283 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
284 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
285 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
286
287 /* IPv4 --> GRE/NAT --> MAC */
288 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
289
290 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
291 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
292 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
293 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
294 I40E_PTT_UNUSED_ENTRY(62),
295 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
296 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
297 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
298
299 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
300 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
301 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
302 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
303 I40E_PTT_UNUSED_ENTRY(69),
304 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
305 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
306 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
307
308 /* IPv4 --> GRE/NAT --> MAC/VLAN */
309 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
310
311 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
312 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
313 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
314 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
315 I40E_PTT_UNUSED_ENTRY(77),
316 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
317 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
318 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
319
320 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
321 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
322 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
323 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
324 I40E_PTT_UNUSED_ENTRY(84),
325 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
326 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
327 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
328
329 /* Non Tunneled IPv6 */
330 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
331 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
332 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
333 I40E_PTT_UNUSED_ENTRY(91),
334 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
335 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
336 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
337
338 /* IPv6 --> IPv4 */
339 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
340 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
341 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
342 I40E_PTT_UNUSED_ENTRY(98),
343 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
344 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
345 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
346
347 /* IPv6 --> IPv6 */
348 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
349 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
350 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
351 I40E_PTT_UNUSED_ENTRY(105),
352 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
353 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
354 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
355
356 /* IPv6 --> GRE/NAT */
357 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
358
359 /* IPv6 --> GRE/NAT -> IPv4 */
360 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
361 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
362 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
363 I40E_PTT_UNUSED_ENTRY(113),
364 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
365 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
366 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
367
368 /* IPv6 --> GRE/NAT -> IPv6 */
369 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
370 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
371 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
372 I40E_PTT_UNUSED_ENTRY(120),
373 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
374 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
375 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
376
377 /* IPv6 --> GRE/NAT -> MAC */
378 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
379
380 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
381 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
382 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
383 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
384 I40E_PTT_UNUSED_ENTRY(128),
385 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
386 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
387 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
388
389 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
390 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
391 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
392 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
393 I40E_PTT_UNUSED_ENTRY(135),
394 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
395 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
396 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
397
398 /* IPv6 --> GRE/NAT -> MAC/VLAN */
399 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
400
401 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
402 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
403 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
404 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
405 I40E_PTT_UNUSED_ENTRY(143),
406 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
407 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
408 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
409
410 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
411 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
412 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
413 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
414 I40E_PTT_UNUSED_ENTRY(150),
415 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
416 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
417 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
418
419 /* unused entries */
420 I40E_PTT_UNUSED_ENTRY(154),
421 I40E_PTT_UNUSED_ENTRY(155),
422 I40E_PTT_UNUSED_ENTRY(156),
423 I40E_PTT_UNUSED_ENTRY(157),
424 I40E_PTT_UNUSED_ENTRY(158),
425 I40E_PTT_UNUSED_ENTRY(159),
426
427 I40E_PTT_UNUSED_ENTRY(160),
428 I40E_PTT_UNUSED_ENTRY(161),
429 I40E_PTT_UNUSED_ENTRY(162),
430 I40E_PTT_UNUSED_ENTRY(163),
431 I40E_PTT_UNUSED_ENTRY(164),
432 I40E_PTT_UNUSED_ENTRY(165),
433 I40E_PTT_UNUSED_ENTRY(166),
434 I40E_PTT_UNUSED_ENTRY(167),
435 I40E_PTT_UNUSED_ENTRY(168),
436 I40E_PTT_UNUSED_ENTRY(169),
437
438 I40E_PTT_UNUSED_ENTRY(170),
439 I40E_PTT_UNUSED_ENTRY(171),
440 I40E_PTT_UNUSED_ENTRY(172),
441 I40E_PTT_UNUSED_ENTRY(173),
442 I40E_PTT_UNUSED_ENTRY(174),
443 I40E_PTT_UNUSED_ENTRY(175),
444 I40E_PTT_UNUSED_ENTRY(176),
445 I40E_PTT_UNUSED_ENTRY(177),
446 I40E_PTT_UNUSED_ENTRY(178),
447 I40E_PTT_UNUSED_ENTRY(179),
448
449 I40E_PTT_UNUSED_ENTRY(180),
450 I40E_PTT_UNUSED_ENTRY(181),
451 I40E_PTT_UNUSED_ENTRY(182),
452 I40E_PTT_UNUSED_ENTRY(183),
453 I40E_PTT_UNUSED_ENTRY(184),
454 I40E_PTT_UNUSED_ENTRY(185),
455 I40E_PTT_UNUSED_ENTRY(186),
456 I40E_PTT_UNUSED_ENTRY(187),
457 I40E_PTT_UNUSED_ENTRY(188),
458 I40E_PTT_UNUSED_ENTRY(189),
459
460 I40E_PTT_UNUSED_ENTRY(190),
461 I40E_PTT_UNUSED_ENTRY(191),
462 I40E_PTT_UNUSED_ENTRY(192),
463 I40E_PTT_UNUSED_ENTRY(193),
464 I40E_PTT_UNUSED_ENTRY(194),
465 I40E_PTT_UNUSED_ENTRY(195),
466 I40E_PTT_UNUSED_ENTRY(196),
467 I40E_PTT_UNUSED_ENTRY(197),
468 I40E_PTT_UNUSED_ENTRY(198),
469 I40E_PTT_UNUSED_ENTRY(199),
470
471 I40E_PTT_UNUSED_ENTRY(200),
472 I40E_PTT_UNUSED_ENTRY(201),
473 I40E_PTT_UNUSED_ENTRY(202),
474 I40E_PTT_UNUSED_ENTRY(203),
475 I40E_PTT_UNUSED_ENTRY(204),
476 I40E_PTT_UNUSED_ENTRY(205),
477 I40E_PTT_UNUSED_ENTRY(206),
478 I40E_PTT_UNUSED_ENTRY(207),
479 I40E_PTT_UNUSED_ENTRY(208),
480 I40E_PTT_UNUSED_ENTRY(209),
481
482 I40E_PTT_UNUSED_ENTRY(210),
483 I40E_PTT_UNUSED_ENTRY(211),
484 I40E_PTT_UNUSED_ENTRY(212),
485 I40E_PTT_UNUSED_ENTRY(213),
486 I40E_PTT_UNUSED_ENTRY(214),
487 I40E_PTT_UNUSED_ENTRY(215),
488 I40E_PTT_UNUSED_ENTRY(216),
489 I40E_PTT_UNUSED_ENTRY(217),
490 I40E_PTT_UNUSED_ENTRY(218),
491 I40E_PTT_UNUSED_ENTRY(219),
492
493 I40E_PTT_UNUSED_ENTRY(220),
494 I40E_PTT_UNUSED_ENTRY(221),
495 I40E_PTT_UNUSED_ENTRY(222),
496 I40E_PTT_UNUSED_ENTRY(223),
497 I40E_PTT_UNUSED_ENTRY(224),
498 I40E_PTT_UNUSED_ENTRY(225),
499 I40E_PTT_UNUSED_ENTRY(226),
500 I40E_PTT_UNUSED_ENTRY(227),
501 I40E_PTT_UNUSED_ENTRY(228),
502 I40E_PTT_UNUSED_ENTRY(229),
503
504 I40E_PTT_UNUSED_ENTRY(230),
505 I40E_PTT_UNUSED_ENTRY(231),
506 I40E_PTT_UNUSED_ENTRY(232),
507 I40E_PTT_UNUSED_ENTRY(233),
508 I40E_PTT_UNUSED_ENTRY(234),
509 I40E_PTT_UNUSED_ENTRY(235),
510 I40E_PTT_UNUSED_ENTRY(236),
511 I40E_PTT_UNUSED_ENTRY(237),
512 I40E_PTT_UNUSED_ENTRY(238),
513 I40E_PTT_UNUSED_ENTRY(239),
514
515 I40E_PTT_UNUSED_ENTRY(240),
516 I40E_PTT_UNUSED_ENTRY(241),
517 I40E_PTT_UNUSED_ENTRY(242),
518 I40E_PTT_UNUSED_ENTRY(243),
519 I40E_PTT_UNUSED_ENTRY(244),
520 I40E_PTT_UNUSED_ENTRY(245),
521 I40E_PTT_UNUSED_ENTRY(246),
522 I40E_PTT_UNUSED_ENTRY(247),
523 I40E_PTT_UNUSED_ENTRY(248),
524 I40E_PTT_UNUSED_ENTRY(249),
525
526 I40E_PTT_UNUSED_ENTRY(250),
527 I40E_PTT_UNUSED_ENTRY(251),
528 I40E_PTT_UNUSED_ENTRY(252),
529 I40E_PTT_UNUSED_ENTRY(253),
530 I40E_PTT_UNUSED_ENTRY(254),
531 I40E_PTT_UNUSED_ENTRY(255)
532 };
533
534
535 /**
536 * i40e_init_shared_code - Initialize the shared code
537 * @hw: pointer to hardware structure
538 *
539 * This assigns the MAC type and PHY code and inits the NVM.
540 * Does not touch the hardware. This function must be called prior to any
541 * other function in the shared code. The i40e_hw structure should be
542 * memset to 0 prior to calling this function. The following fields in
543 * hw structure should be filled in prior to calling this function:
544 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
545 * subsystem_vendor_id, and revision_id
546 **/
547 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
548 {
549 i40e_status status = 0;
550 u32 reg;
551
552 i40e_set_mac_type(hw);
553
554 switch (hw->mac.type) {
555 case I40E_MAC_XL710:
556 break;
557 default:
558 return I40E_ERR_DEVICE_NOT_SUPPORTED;
559 break;
560 }
561
562 hw->phy.get_link_info = true;
563
564 /* Determine port number */
565 reg = rd32(hw, I40E_PFGEN_PORTNUM);
566 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
567 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
568 hw->port = (u8)reg;
569
570 /* Determine the PF number based on the PCI fn */
571 reg = rd32(hw, I40E_GLPCI_CAPSUP);
572 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
573 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
574 else
575 hw->pf_id = (u8)hw->bus.func;
576
577 status = i40e_init_nvm(hw);
578 return status;
579 }
580
581 /**
582 * i40e_aq_mac_address_read - Retrieve the MAC addresses
583 * @hw: pointer to the hw struct
584 * @flags: a return indicator of what addresses were added to the addr store
585 * @addrs: the requestor's mac addr store
586 * @cmd_details: pointer to command details structure or NULL
587 **/
588 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
589 u16 *flags,
590 struct i40e_aqc_mac_address_read_data *addrs,
591 struct i40e_asq_cmd_details *cmd_details)
592 {
593 struct i40e_aq_desc desc;
594 struct i40e_aqc_mac_address_read *cmd_data =
595 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
596 i40e_status status;
597
598 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
599 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
600
601 status = i40e_asq_send_command(hw, &desc, addrs,
602 sizeof(*addrs), cmd_details);
603 *flags = le16_to_cpu(cmd_data->command_flags);
604
605 return status;
606 }
607
608 /**
609 * i40e_aq_mac_address_write - Change the MAC addresses
610 * @hw: pointer to the hw struct
611 * @flags: indicates which MAC to be written
612 * @mac_addr: address to write
613 * @cmd_details: pointer to command details structure or NULL
614 **/
615 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
616 u16 flags, u8 *mac_addr,
617 struct i40e_asq_cmd_details *cmd_details)
618 {
619 struct i40e_aq_desc desc;
620 struct i40e_aqc_mac_address_write *cmd_data =
621 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
622 i40e_status status;
623
624 i40e_fill_default_direct_cmd_desc(&desc,
625 i40e_aqc_opc_mac_address_write);
626 cmd_data->command_flags = cpu_to_le16(flags);
627 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
628 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
629 ((u32)mac_addr[3] << 16) |
630 ((u32)mac_addr[4] << 8) |
631 mac_addr[5]);
632
633 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
634
635 return status;
636 }
637
638 /**
639 * i40e_get_mac_addr - get MAC address
640 * @hw: pointer to the HW structure
641 * @mac_addr: pointer to MAC address
642 *
643 * Reads the adapter's MAC address from register
644 **/
645 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
646 {
647 struct i40e_aqc_mac_address_read_data addrs;
648 i40e_status status;
649 u16 flags = 0;
650
651 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
652
653 if (flags & I40E_AQC_LAN_ADDR_VALID)
654 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
655
656 return status;
657 }
658
659 /**
660 * i40e_pre_tx_queue_cfg - pre tx queue configure
661 * @hw: pointer to the HW structure
662 * @queue: target pf queue index
663 * @enable: state change request
664 *
665 * Handles hw requirement to indicate intention to enable
666 * or disable target queue.
667 **/
668 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
669 {
670 u32 reg_val = rd32(hw, I40E_PFLAN_QALLOC);
671 u32 first_queue = (reg_val & I40E_PFLAN_QALLOC_FIRSTQ_MASK);
672 u32 abs_queue_idx = first_queue + queue;
673 u32 reg_block = 0;
674
675 if (abs_queue_idx >= 128)
676 reg_block = abs_queue_idx / 128;
677
678 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
679 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
680 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
681
682 if (enable)
683 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
684 else
685 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
686
687 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
688 }
689
690 /**
691 * i40e_get_media_type - Gets media type
692 * @hw: pointer to the hardware structure
693 **/
694 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
695 {
696 enum i40e_media_type media;
697
698 switch (hw->phy.link_info.phy_type) {
699 case I40E_PHY_TYPE_10GBASE_SR:
700 case I40E_PHY_TYPE_10GBASE_LR:
701 case I40E_PHY_TYPE_40GBASE_SR4:
702 case I40E_PHY_TYPE_40GBASE_LR4:
703 media = I40E_MEDIA_TYPE_FIBER;
704 break;
705 case I40E_PHY_TYPE_100BASE_TX:
706 case I40E_PHY_TYPE_1000BASE_T:
707 case I40E_PHY_TYPE_10GBASE_T:
708 media = I40E_MEDIA_TYPE_BASET;
709 break;
710 case I40E_PHY_TYPE_10GBASE_CR1_CU:
711 case I40E_PHY_TYPE_40GBASE_CR4_CU:
712 case I40E_PHY_TYPE_10GBASE_CR1:
713 case I40E_PHY_TYPE_40GBASE_CR4:
714 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
715 media = I40E_MEDIA_TYPE_DA;
716 break;
717 case I40E_PHY_TYPE_1000BASE_KX:
718 case I40E_PHY_TYPE_10GBASE_KX4:
719 case I40E_PHY_TYPE_10GBASE_KR:
720 case I40E_PHY_TYPE_40GBASE_KR4:
721 media = I40E_MEDIA_TYPE_BACKPLANE;
722 break;
723 case I40E_PHY_TYPE_SGMII:
724 case I40E_PHY_TYPE_XAUI:
725 case I40E_PHY_TYPE_XFI:
726 case I40E_PHY_TYPE_XLAUI:
727 case I40E_PHY_TYPE_XLPPI:
728 default:
729 media = I40E_MEDIA_TYPE_UNKNOWN;
730 break;
731 }
732
733 return media;
734 }
735
736 #define I40E_PF_RESET_WAIT_COUNT_A0 200
737 #define I40E_PF_RESET_WAIT_COUNT 100
738 /**
739 * i40e_pf_reset - Reset the PF
740 * @hw: pointer to the hardware structure
741 *
742 * Assuming someone else has triggered a global reset,
743 * assure the global reset is complete and then reset the PF
744 **/
745 i40e_status i40e_pf_reset(struct i40e_hw *hw)
746 {
747 u32 cnt = 0;
748 u32 cnt1 = 0;
749 u32 reg = 0;
750 u32 grst_del;
751
752 /* Poll for Global Reset steady state in case of recent GRST.
753 * The grst delay value is in 100ms units, and we'll wait a
754 * couple counts longer to be sure we don't just miss the end.
755 */
756 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
757 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
758 for (cnt = 0; cnt < grst_del + 2; cnt++) {
759 reg = rd32(hw, I40E_GLGEN_RSTAT);
760 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
761 break;
762 msleep(100);
763 }
764 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
765 hw_dbg(hw, "Global reset polling failed to complete.\n");
766 return I40E_ERR_RESET_FAILED;
767 }
768
769 /* Now Wait for the FW to be ready */
770 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
771 reg = rd32(hw, I40E_GLNVM_ULD);
772 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
773 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
774 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
775 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
776 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
777 break;
778 }
779 usleep_range(10000, 20000);
780 }
781 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
782 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
783 hw_dbg(hw, "wait for FW Reset complete timedout\n");
784 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
785 return I40E_ERR_RESET_FAILED;
786 }
787
788 /* If there was a Global Reset in progress when we got here,
789 * we don't need to do the PF Reset
790 */
791 if (!cnt) {
792 if (hw->revision_id == 0)
793 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
794 else
795 cnt = I40E_PF_RESET_WAIT_COUNT;
796 reg = rd32(hw, I40E_PFGEN_CTRL);
797 wr32(hw, I40E_PFGEN_CTRL,
798 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
799 for (; cnt; cnt--) {
800 reg = rd32(hw, I40E_PFGEN_CTRL);
801 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
802 break;
803 usleep_range(1000, 2000);
804 }
805 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
806 hw_dbg(hw, "PF reset polling failed to complete.\n");
807 return I40E_ERR_RESET_FAILED;
808 }
809 }
810
811 i40e_clear_pxe_mode(hw);
812
813 return 0;
814 }
815
816 /**
817 * i40e_clear_pxe_mode - clear pxe operations mode
818 * @hw: pointer to the hw struct
819 *
820 * Make sure all PXE mode settings are cleared, including things
821 * like descriptor fetch/write-back mode.
822 **/
823 void i40e_clear_pxe_mode(struct i40e_hw *hw)
824 {
825 u32 reg;
826
827 if (i40e_check_asq_alive(hw))
828 i40e_aq_clear_pxe_mode(hw, NULL);
829
830 /* Clear single descriptor fetch/write-back mode */
831 reg = rd32(hw, I40E_GLLAN_RCTL_0);
832
833 if (hw->revision_id == 0) {
834 /* As a work around clear PXE_MODE instead of setting it */
835 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
836 } else {
837 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
838 }
839 }
840
841 /**
842 * i40e_led_is_mine - helper to find matching led
843 * @hw: pointer to the hw struct
844 * @idx: index into GPIO registers
845 *
846 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
847 */
848 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
849 {
850 u32 gpio_val = 0;
851 u32 port;
852
853 if (!hw->func_caps.led[idx])
854 return 0;
855
856 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
857 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
858 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
859
860 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
861 * if it is not our port then ignore
862 */
863 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
864 (port != hw->port))
865 return 0;
866
867 return gpio_val;
868 }
869
870 #define I40E_LED0 22
871 #define I40E_LINK_ACTIVITY 0xC
872
873 /**
874 * i40e_led_get - return current on/off mode
875 * @hw: pointer to the hw struct
876 *
877 * The value returned is the 'mode' field as defined in the
878 * GPIO register definitions: 0x0 = off, 0xf = on, and other
879 * values are variations of possible behaviors relating to
880 * blink, link, and wire.
881 **/
882 u32 i40e_led_get(struct i40e_hw *hw)
883 {
884 u32 mode = 0;
885 int i;
886
887 /* as per the documentation GPIO 22-29 are the LED
888 * GPIO pins named LED0..LED7
889 */
890 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
891 u32 gpio_val = i40e_led_is_mine(hw, i);
892
893 if (!gpio_val)
894 continue;
895
896 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
897 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
898 break;
899 }
900
901 return mode;
902 }
903
904 /**
905 * i40e_led_set - set new on/off mode
906 * @hw: pointer to the hw struct
907 * @mode: 0=off, 0xf=on (else see manual for mode details)
908 * @blink: true if the LED should blink when on, false if steady
909 *
910 * if this function is used to turn on the blink it should
911 * be used to disable the blink when restoring the original state.
912 **/
913 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
914 {
915 int i;
916
917 if (mode & 0xfffffff0)
918 hw_dbg(hw, "invalid mode passed in %X\n", mode);
919
920 /* as per the documentation GPIO 22-29 are the LED
921 * GPIO pins named LED0..LED7
922 */
923 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
924 u32 gpio_val = i40e_led_is_mine(hw, i);
925
926 if (!gpio_val)
927 continue;
928
929 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
930 /* this & is a bit of paranoia, but serves as a range check */
931 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
932 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
933
934 if (mode == I40E_LINK_ACTIVITY)
935 blink = false;
936
937 gpio_val |= (blink ? 1 : 0) <<
938 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
939
940 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
941 break;
942 }
943 }
944
945 /* Admin command wrappers */
946
947 /**
948 * i40e_aq_clear_pxe_mode
949 * @hw: pointer to the hw struct
950 * @cmd_details: pointer to command details structure or NULL
951 *
952 * Tell the firmware that the driver is taking over from PXE
953 **/
954 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
955 struct i40e_asq_cmd_details *cmd_details)
956 {
957 i40e_status status;
958 struct i40e_aq_desc desc;
959 struct i40e_aqc_clear_pxe *cmd =
960 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
961
962 i40e_fill_default_direct_cmd_desc(&desc,
963 i40e_aqc_opc_clear_pxe_mode);
964
965 cmd->rx_cnt = 0x2;
966
967 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
968
969 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
970
971 return status;
972 }
973
974 /**
975 * i40e_aq_set_link_restart_an
976 * @hw: pointer to the hw struct
977 * @cmd_details: pointer to command details structure or NULL
978 *
979 * Sets up the link and restarts the Auto-Negotiation over the link.
980 **/
981 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
982 struct i40e_asq_cmd_details *cmd_details)
983 {
984 struct i40e_aq_desc desc;
985 struct i40e_aqc_set_link_restart_an *cmd =
986 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
987 i40e_status status;
988
989 i40e_fill_default_direct_cmd_desc(&desc,
990 i40e_aqc_opc_set_link_restart_an);
991
992 cmd->command = I40E_AQ_PHY_RESTART_AN;
993
994 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
995
996 return status;
997 }
998
999 /**
1000 * i40e_aq_get_link_info
1001 * @hw: pointer to the hw struct
1002 * @enable_lse: enable/disable LinkStatusEvent reporting
1003 * @link: pointer to link status structure - optional
1004 * @cmd_details: pointer to command details structure or NULL
1005 *
1006 * Returns the link status of the adapter.
1007 **/
1008 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1009 bool enable_lse, struct i40e_link_status *link,
1010 struct i40e_asq_cmd_details *cmd_details)
1011 {
1012 struct i40e_aq_desc desc;
1013 struct i40e_aqc_get_link_status *resp =
1014 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1015 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1016 i40e_status status;
1017 u16 command_flags;
1018
1019 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1020
1021 if (enable_lse)
1022 command_flags = I40E_AQ_LSE_ENABLE;
1023 else
1024 command_flags = I40E_AQ_LSE_DISABLE;
1025 resp->command_flags = cpu_to_le16(command_flags);
1026
1027 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1028
1029 if (status)
1030 goto aq_get_link_info_exit;
1031
1032 /* save off old link status information */
1033 hw->phy.link_info_old = *hw_link_info;
1034
1035 /* update link status */
1036 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1037 hw->phy.media_type = i40e_get_media_type(hw);
1038 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1039 hw_link_info->link_info = resp->link_info;
1040 hw_link_info->an_info = resp->an_info;
1041 hw_link_info->ext_info = resp->ext_info;
1042 hw_link_info->loopback = resp->loopback;
1043 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1044 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1045
1046 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1047 hw_link_info->crc_enable = true;
1048 else
1049 hw_link_info->crc_enable = false;
1050
1051 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1052 hw_link_info->lse_enable = true;
1053 else
1054 hw_link_info->lse_enable = false;
1055
1056 /* save link status information */
1057 if (link)
1058 *link = *hw_link_info;
1059
1060 /* flag cleared so helper functions don't call AQ again */
1061 hw->phy.get_link_info = false;
1062
1063 aq_get_link_info_exit:
1064 return status;
1065 }
1066
1067 /**
1068 * i40e_aq_add_vsi
1069 * @hw: pointer to the hw struct
1070 * @vsi_ctx: pointer to a vsi context struct
1071 * @cmd_details: pointer to command details structure or NULL
1072 *
1073 * Add a VSI context to the hardware.
1074 **/
1075 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1076 struct i40e_vsi_context *vsi_ctx,
1077 struct i40e_asq_cmd_details *cmd_details)
1078 {
1079 struct i40e_aq_desc desc;
1080 struct i40e_aqc_add_get_update_vsi *cmd =
1081 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1082 struct i40e_aqc_add_get_update_vsi_completion *resp =
1083 (struct i40e_aqc_add_get_update_vsi_completion *)
1084 &desc.params.raw;
1085 i40e_status status;
1086
1087 i40e_fill_default_direct_cmd_desc(&desc,
1088 i40e_aqc_opc_add_vsi);
1089
1090 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1091 cmd->connection_type = vsi_ctx->connection_type;
1092 cmd->vf_id = vsi_ctx->vf_num;
1093 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1094
1095 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1096
1097 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1098 sizeof(vsi_ctx->info), cmd_details);
1099
1100 if (status)
1101 goto aq_add_vsi_exit;
1102
1103 vsi_ctx->seid = le16_to_cpu(resp->seid);
1104 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1105 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1106 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1107
1108 aq_add_vsi_exit:
1109 return status;
1110 }
1111
1112 /**
1113 * i40e_aq_set_vsi_unicast_promiscuous
1114 * @hw: pointer to the hw struct
1115 * @seid: vsi number
1116 * @set: set unicast promiscuous enable/disable
1117 * @cmd_details: pointer to command details structure or NULL
1118 **/
1119 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1120 u16 seid, bool set,
1121 struct i40e_asq_cmd_details *cmd_details)
1122 {
1123 struct i40e_aq_desc desc;
1124 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1125 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1126 i40e_status status;
1127 u16 flags = 0;
1128
1129 i40e_fill_default_direct_cmd_desc(&desc,
1130 i40e_aqc_opc_set_vsi_promiscuous_modes);
1131
1132 if (set)
1133 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1134
1135 cmd->promiscuous_flags = cpu_to_le16(flags);
1136
1137 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1138
1139 cmd->seid = cpu_to_le16(seid);
1140 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1141
1142 return status;
1143 }
1144
1145 /**
1146 * i40e_aq_set_vsi_multicast_promiscuous
1147 * @hw: pointer to the hw struct
1148 * @seid: vsi number
1149 * @set: set multicast promiscuous enable/disable
1150 * @cmd_details: pointer to command details structure or NULL
1151 **/
1152 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1153 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1154 {
1155 struct i40e_aq_desc desc;
1156 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1157 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1158 i40e_status status;
1159 u16 flags = 0;
1160
1161 i40e_fill_default_direct_cmd_desc(&desc,
1162 i40e_aqc_opc_set_vsi_promiscuous_modes);
1163
1164 if (set)
1165 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1166
1167 cmd->promiscuous_flags = cpu_to_le16(flags);
1168
1169 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1170
1171 cmd->seid = cpu_to_le16(seid);
1172 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1173
1174 return status;
1175 }
1176
1177 /**
1178 * i40e_aq_set_vsi_broadcast
1179 * @hw: pointer to the hw struct
1180 * @seid: vsi number
1181 * @set_filter: true to set filter, false to clear filter
1182 * @cmd_details: pointer to command details structure or NULL
1183 *
1184 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1185 **/
1186 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1187 u16 seid, bool set_filter,
1188 struct i40e_asq_cmd_details *cmd_details)
1189 {
1190 struct i40e_aq_desc desc;
1191 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1192 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1193 i40e_status status;
1194
1195 i40e_fill_default_direct_cmd_desc(&desc,
1196 i40e_aqc_opc_set_vsi_promiscuous_modes);
1197
1198 if (set_filter)
1199 cmd->promiscuous_flags
1200 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1201 else
1202 cmd->promiscuous_flags
1203 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1204
1205 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1206 cmd->seid = cpu_to_le16(seid);
1207 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1208
1209 return status;
1210 }
1211
1212 /**
1213 * i40e_get_vsi_params - get VSI configuration info
1214 * @hw: pointer to the hw struct
1215 * @vsi_ctx: pointer to a vsi context struct
1216 * @cmd_details: pointer to command details structure or NULL
1217 **/
1218 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1219 struct i40e_vsi_context *vsi_ctx,
1220 struct i40e_asq_cmd_details *cmd_details)
1221 {
1222 struct i40e_aq_desc desc;
1223 struct i40e_aqc_add_get_update_vsi *cmd =
1224 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1225 struct i40e_aqc_add_get_update_vsi_completion *resp =
1226 (struct i40e_aqc_add_get_update_vsi_completion *)
1227 &desc.params.raw;
1228 i40e_status status;
1229
1230 i40e_fill_default_direct_cmd_desc(&desc,
1231 i40e_aqc_opc_get_vsi_parameters);
1232
1233 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1234
1235 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1236
1237 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1238 sizeof(vsi_ctx->info), NULL);
1239
1240 if (status)
1241 goto aq_get_vsi_params_exit;
1242
1243 vsi_ctx->seid = le16_to_cpu(resp->seid);
1244 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1245 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1246 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1247
1248 aq_get_vsi_params_exit:
1249 return status;
1250 }
1251
1252 /**
1253 * i40e_aq_update_vsi_params
1254 * @hw: pointer to the hw struct
1255 * @vsi_ctx: pointer to a vsi context struct
1256 * @cmd_details: pointer to command details structure or NULL
1257 *
1258 * Update a VSI context.
1259 **/
1260 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1261 struct i40e_vsi_context *vsi_ctx,
1262 struct i40e_asq_cmd_details *cmd_details)
1263 {
1264 struct i40e_aq_desc desc;
1265 struct i40e_aqc_add_get_update_vsi *cmd =
1266 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1267 i40e_status status;
1268
1269 i40e_fill_default_direct_cmd_desc(&desc,
1270 i40e_aqc_opc_update_vsi_parameters);
1271 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1272
1273 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1274
1275 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1276 sizeof(vsi_ctx->info), cmd_details);
1277
1278 return status;
1279 }
1280
1281 /**
1282 * i40e_aq_get_switch_config
1283 * @hw: pointer to the hardware structure
1284 * @buf: pointer to the result buffer
1285 * @buf_size: length of input buffer
1286 * @start_seid: seid to start for the report, 0 == beginning
1287 * @cmd_details: pointer to command details structure or NULL
1288 *
1289 * Fill the buf with switch configuration returned from AdminQ command
1290 **/
1291 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1292 struct i40e_aqc_get_switch_config_resp *buf,
1293 u16 buf_size, u16 *start_seid,
1294 struct i40e_asq_cmd_details *cmd_details)
1295 {
1296 struct i40e_aq_desc desc;
1297 struct i40e_aqc_switch_seid *scfg =
1298 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1299 i40e_status status;
1300
1301 i40e_fill_default_direct_cmd_desc(&desc,
1302 i40e_aqc_opc_get_switch_config);
1303 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1304 if (buf_size > I40E_AQ_LARGE_BUF)
1305 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1306 scfg->seid = cpu_to_le16(*start_seid);
1307
1308 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1309 *start_seid = le16_to_cpu(scfg->seid);
1310
1311 return status;
1312 }
1313
1314 /**
1315 * i40e_aq_get_firmware_version
1316 * @hw: pointer to the hw struct
1317 * @fw_major_version: firmware major version
1318 * @fw_minor_version: firmware minor version
1319 * @api_major_version: major queue version
1320 * @api_minor_version: minor queue version
1321 * @cmd_details: pointer to command details structure or NULL
1322 *
1323 * Get the firmware version from the admin queue commands
1324 **/
1325 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1326 u16 *fw_major_version, u16 *fw_minor_version,
1327 u16 *api_major_version, u16 *api_minor_version,
1328 struct i40e_asq_cmd_details *cmd_details)
1329 {
1330 struct i40e_aq_desc desc;
1331 struct i40e_aqc_get_version *resp =
1332 (struct i40e_aqc_get_version *)&desc.params.raw;
1333 i40e_status status;
1334
1335 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1336
1337 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1338
1339 if (!status) {
1340 if (fw_major_version != NULL)
1341 *fw_major_version = le16_to_cpu(resp->fw_major);
1342 if (fw_minor_version != NULL)
1343 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1344 if (api_major_version != NULL)
1345 *api_major_version = le16_to_cpu(resp->api_major);
1346 if (api_minor_version != NULL)
1347 *api_minor_version = le16_to_cpu(resp->api_minor);
1348 }
1349
1350 return status;
1351 }
1352
1353 /**
1354 * i40e_aq_send_driver_version
1355 * @hw: pointer to the hw struct
1356 * @dv: driver's major, minor version
1357 * @cmd_details: pointer to command details structure or NULL
1358 *
1359 * Send the driver version to the firmware
1360 **/
1361 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1362 struct i40e_driver_version *dv,
1363 struct i40e_asq_cmd_details *cmd_details)
1364 {
1365 struct i40e_aq_desc desc;
1366 struct i40e_aqc_driver_version *cmd =
1367 (struct i40e_aqc_driver_version *)&desc.params.raw;
1368 i40e_status status;
1369 u16 len;
1370
1371 if (dv == NULL)
1372 return I40E_ERR_PARAM;
1373
1374 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1375
1376 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1377 cmd->driver_major_ver = dv->major_version;
1378 cmd->driver_minor_ver = dv->minor_version;
1379 cmd->driver_build_ver = dv->build_version;
1380 cmd->driver_subbuild_ver = dv->subbuild_version;
1381
1382 len = 0;
1383 while (len < sizeof(dv->driver_string) &&
1384 (dv->driver_string[len] < 0x80) &&
1385 dv->driver_string[len])
1386 len++;
1387 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1388 len, cmd_details);
1389
1390 return status;
1391 }
1392
1393 /**
1394 * i40e_get_link_status - get status of the HW network link
1395 * @hw: pointer to the hw struct
1396 *
1397 * Returns true if link is up, false if link is down.
1398 *
1399 * Side effect: LinkStatusEvent reporting becomes enabled
1400 **/
1401 bool i40e_get_link_status(struct i40e_hw *hw)
1402 {
1403 i40e_status status = 0;
1404 bool link_status = false;
1405
1406 if (hw->phy.get_link_info) {
1407 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1408
1409 if (status)
1410 goto i40e_get_link_status_exit;
1411 }
1412
1413 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1414
1415 i40e_get_link_status_exit:
1416 return link_status;
1417 }
1418
1419 /**
1420 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1421 * @hw: pointer to the hw struct
1422 * @uplink_seid: the MAC or other gizmo SEID
1423 * @downlink_seid: the VSI SEID
1424 * @enabled_tc: bitmap of TCs to be enabled
1425 * @default_port: true for default port VSI, false for control port
1426 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
1427 * @veb_seid: pointer to where to put the resulting VEB SEID
1428 * @cmd_details: pointer to command details structure or NULL
1429 *
1430 * This asks the FW to add a VEB between the uplink and downlink
1431 * elements. If the uplink SEID is 0, this will be a floating VEB.
1432 **/
1433 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1434 u16 downlink_seid, u8 enabled_tc,
1435 bool default_port, bool enable_l2_filtering,
1436 u16 *veb_seid,
1437 struct i40e_asq_cmd_details *cmd_details)
1438 {
1439 struct i40e_aq_desc desc;
1440 struct i40e_aqc_add_veb *cmd =
1441 (struct i40e_aqc_add_veb *)&desc.params.raw;
1442 struct i40e_aqc_add_veb_completion *resp =
1443 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1444 i40e_status status;
1445 u16 veb_flags = 0;
1446
1447 /* SEIDs need to either both be set or both be 0 for floating VEB */
1448 if (!!uplink_seid != !!downlink_seid)
1449 return I40E_ERR_PARAM;
1450
1451 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1452
1453 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1454 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1455 cmd->enable_tcs = enabled_tc;
1456 if (!uplink_seid)
1457 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1458 if (default_port)
1459 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1460 else
1461 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
1462
1463 if (enable_l2_filtering)
1464 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1465
1466 cmd->veb_flags = cpu_to_le16(veb_flags);
1467
1468 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1469
1470 if (!status && veb_seid)
1471 *veb_seid = le16_to_cpu(resp->veb_seid);
1472
1473 return status;
1474 }
1475
1476 /**
1477 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1478 * @hw: pointer to the hw struct
1479 * @veb_seid: the SEID of the VEB to query
1480 * @switch_id: the uplink switch id
1481 * @floating: set to true if the VEB is floating
1482 * @statistic_index: index of the stats counter block for this VEB
1483 * @vebs_used: number of VEB's used by function
1484 * @vebs_free: total VEB's not reserved by any function
1485 * @cmd_details: pointer to command details structure or NULL
1486 *
1487 * This retrieves the parameters for a particular VEB, specified by
1488 * uplink_seid, and returns them to the caller.
1489 **/
1490 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1491 u16 veb_seid, u16 *switch_id,
1492 bool *floating, u16 *statistic_index,
1493 u16 *vebs_used, u16 *vebs_free,
1494 struct i40e_asq_cmd_details *cmd_details)
1495 {
1496 struct i40e_aq_desc desc;
1497 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1498 (struct i40e_aqc_get_veb_parameters_completion *)
1499 &desc.params.raw;
1500 i40e_status status;
1501
1502 if (veb_seid == 0)
1503 return I40E_ERR_PARAM;
1504
1505 i40e_fill_default_direct_cmd_desc(&desc,
1506 i40e_aqc_opc_get_veb_parameters);
1507 cmd_resp->seid = cpu_to_le16(veb_seid);
1508
1509 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1510 if (status)
1511 goto get_veb_exit;
1512
1513 if (switch_id)
1514 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1515 if (statistic_index)
1516 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1517 if (vebs_used)
1518 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1519 if (vebs_free)
1520 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1521 if (floating) {
1522 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1523 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1524 *floating = true;
1525 else
1526 *floating = false;
1527 }
1528
1529 get_veb_exit:
1530 return status;
1531 }
1532
1533 /**
1534 * i40e_aq_add_macvlan
1535 * @hw: pointer to the hw struct
1536 * @seid: VSI for the mac address
1537 * @mv_list: list of macvlans to be added
1538 * @count: length of the list
1539 * @cmd_details: pointer to command details structure or NULL
1540 *
1541 * Add MAC/VLAN addresses to the HW filtering
1542 **/
1543 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1544 struct i40e_aqc_add_macvlan_element_data *mv_list,
1545 u16 count, struct i40e_asq_cmd_details *cmd_details)
1546 {
1547 struct i40e_aq_desc desc;
1548 struct i40e_aqc_macvlan *cmd =
1549 (struct i40e_aqc_macvlan *)&desc.params.raw;
1550 i40e_status status;
1551 u16 buf_size;
1552
1553 if (count == 0 || !mv_list || !hw)
1554 return I40E_ERR_PARAM;
1555
1556 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1557
1558 /* prep the rest of the request */
1559 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1560 cmd->num_addresses = cpu_to_le16(count);
1561 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1562 cmd->seid[1] = 0;
1563 cmd->seid[2] = 0;
1564
1565 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1566 if (buf_size > I40E_AQ_LARGE_BUF)
1567 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1568
1569 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1570 cmd_details);
1571
1572 return status;
1573 }
1574
1575 /**
1576 * i40e_aq_remove_macvlan
1577 * @hw: pointer to the hw struct
1578 * @seid: VSI for the mac address
1579 * @mv_list: list of macvlans to be removed
1580 * @count: length of the list
1581 * @cmd_details: pointer to command details structure or NULL
1582 *
1583 * Remove MAC/VLAN addresses from the HW filtering
1584 **/
1585 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1586 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1587 u16 count, struct i40e_asq_cmd_details *cmd_details)
1588 {
1589 struct i40e_aq_desc desc;
1590 struct i40e_aqc_macvlan *cmd =
1591 (struct i40e_aqc_macvlan *)&desc.params.raw;
1592 i40e_status status;
1593 u16 buf_size;
1594
1595 if (count == 0 || !mv_list || !hw)
1596 return I40E_ERR_PARAM;
1597
1598 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1599
1600 /* prep the rest of the request */
1601 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1602 cmd->num_addresses = cpu_to_le16(count);
1603 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1604 cmd->seid[1] = 0;
1605 cmd->seid[2] = 0;
1606
1607 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1608 if (buf_size > I40E_AQ_LARGE_BUF)
1609 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1610
1611 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1612 cmd_details);
1613
1614 return status;
1615 }
1616
1617 /**
1618 * i40e_aq_send_msg_to_vf
1619 * @hw: pointer to the hardware structure
1620 * @vfid: vf id to send msg
1621 * @v_opcode: opcodes for VF-PF communication
1622 * @v_retval: return error code
1623 * @msg: pointer to the msg buffer
1624 * @msglen: msg length
1625 * @cmd_details: pointer to command details
1626 *
1627 * send msg to vf
1628 **/
1629 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1630 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1631 struct i40e_asq_cmd_details *cmd_details)
1632 {
1633 struct i40e_aq_desc desc;
1634 struct i40e_aqc_pf_vf_message *cmd =
1635 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1636 i40e_status status;
1637
1638 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1639 cmd->id = cpu_to_le32(vfid);
1640 desc.cookie_high = cpu_to_le32(v_opcode);
1641 desc.cookie_low = cpu_to_le32(v_retval);
1642 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1643 if (msglen) {
1644 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1645 I40E_AQ_FLAG_RD));
1646 if (msglen > I40E_AQ_LARGE_BUF)
1647 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1648 desc.datalen = cpu_to_le16(msglen);
1649 }
1650 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1651
1652 return status;
1653 }
1654
1655 /**
1656 * i40e_aq_set_hmc_resource_profile
1657 * @hw: pointer to the hw struct
1658 * @profile: type of profile the HMC is to be set as
1659 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1660 * @cmd_details: pointer to command details structure or NULL
1661 *
1662 * set the HMC profile of the device.
1663 **/
1664 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1665 enum i40e_aq_hmc_profile profile,
1666 u8 pe_vf_enabled_count,
1667 struct i40e_asq_cmd_details *cmd_details)
1668 {
1669 struct i40e_aq_desc desc;
1670 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1671 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1672 i40e_status status;
1673
1674 i40e_fill_default_direct_cmd_desc(&desc,
1675 i40e_aqc_opc_set_hmc_resource_profile);
1676
1677 cmd->pm_profile = (u8)profile;
1678 cmd->pe_vf_enabled = pe_vf_enabled_count;
1679
1680 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1681
1682 return status;
1683 }
1684
1685 /**
1686 * i40e_aq_request_resource
1687 * @hw: pointer to the hw struct
1688 * @resource: resource id
1689 * @access: access type
1690 * @sdp_number: resource number
1691 * @timeout: the maximum time in ms that the driver may hold the resource
1692 * @cmd_details: pointer to command details structure or NULL
1693 *
1694 * requests common resource using the admin queue commands
1695 **/
1696 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1697 enum i40e_aq_resources_ids resource,
1698 enum i40e_aq_resource_access_type access,
1699 u8 sdp_number, u64 *timeout,
1700 struct i40e_asq_cmd_details *cmd_details)
1701 {
1702 struct i40e_aq_desc desc;
1703 struct i40e_aqc_request_resource *cmd_resp =
1704 (struct i40e_aqc_request_resource *)&desc.params.raw;
1705 i40e_status status;
1706
1707 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1708
1709 cmd_resp->resource_id = cpu_to_le16(resource);
1710 cmd_resp->access_type = cpu_to_le16(access);
1711 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1712
1713 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1714 /* The completion specifies the maximum time in ms that the driver
1715 * may hold the resource in the Timeout field.
1716 * If the resource is held by someone else, the command completes with
1717 * busy return value and the timeout field indicates the maximum time
1718 * the current owner of the resource has to free it.
1719 */
1720 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1721 *timeout = le32_to_cpu(cmd_resp->timeout);
1722
1723 return status;
1724 }
1725
1726 /**
1727 * i40e_aq_release_resource
1728 * @hw: pointer to the hw struct
1729 * @resource: resource id
1730 * @sdp_number: resource number
1731 * @cmd_details: pointer to command details structure or NULL
1732 *
1733 * release common resource using the admin queue commands
1734 **/
1735 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1736 enum i40e_aq_resources_ids resource,
1737 u8 sdp_number,
1738 struct i40e_asq_cmd_details *cmd_details)
1739 {
1740 struct i40e_aq_desc desc;
1741 struct i40e_aqc_request_resource *cmd =
1742 (struct i40e_aqc_request_resource *)&desc.params.raw;
1743 i40e_status status;
1744
1745 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1746
1747 cmd->resource_id = cpu_to_le16(resource);
1748 cmd->resource_number = cpu_to_le32(sdp_number);
1749
1750 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1751
1752 return status;
1753 }
1754
1755 /**
1756 * i40e_aq_read_nvm
1757 * @hw: pointer to the hw struct
1758 * @module_pointer: module pointer location in words from the NVM beginning
1759 * @offset: byte offset from the module beginning
1760 * @length: length of the section to be read (in bytes from the offset)
1761 * @data: command buffer (size [bytes] = length)
1762 * @last_command: tells if this is the last command in a series
1763 * @cmd_details: pointer to command details structure or NULL
1764 *
1765 * Read the NVM using the admin queue commands
1766 **/
1767 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1768 u32 offset, u16 length, void *data,
1769 bool last_command,
1770 struct i40e_asq_cmd_details *cmd_details)
1771 {
1772 struct i40e_aq_desc desc;
1773 struct i40e_aqc_nvm_update *cmd =
1774 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1775 i40e_status status;
1776
1777 /* In offset the highest byte must be zeroed. */
1778 if (offset & 0xFF000000) {
1779 status = I40E_ERR_PARAM;
1780 goto i40e_aq_read_nvm_exit;
1781 }
1782
1783 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1784
1785 /* If this is the last command in a series, set the proper flag. */
1786 if (last_command)
1787 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1788 cmd->module_pointer = module_pointer;
1789 cmd->offset = cpu_to_le32(offset);
1790 cmd->length = cpu_to_le16(length);
1791
1792 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1793 if (length > I40E_AQ_LARGE_BUF)
1794 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1795
1796 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1797
1798 i40e_aq_read_nvm_exit:
1799 return status;
1800 }
1801
1802 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1803 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1804 #define I40E_DEV_FUNC_CAP_NPAR 0x03
1805 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1806 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1807 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1808 #define I40E_DEV_FUNC_CAP_VF 0x13
1809 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
1810 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1811 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1812 #define I40E_DEV_FUNC_CAP_VSI 0x17
1813 #define I40E_DEV_FUNC_CAP_DCB 0x18
1814 #define I40E_DEV_FUNC_CAP_FCOE 0x21
1815 #define I40E_DEV_FUNC_CAP_RSS 0x40
1816 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1817 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1818 #define I40E_DEV_FUNC_CAP_MSIX 0x43
1819 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1820 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1821 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1822 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1823 #define I40E_DEV_FUNC_CAP_CEM 0xF2
1824 #define I40E_DEV_FUNC_CAP_IWARP 0x51
1825 #define I40E_DEV_FUNC_CAP_LED 0x61
1826 #define I40E_DEV_FUNC_CAP_SDP 0x62
1827 #define I40E_DEV_FUNC_CAP_MDIO 0x63
1828
1829 /**
1830 * i40e_parse_discover_capabilities
1831 * @hw: pointer to the hw struct
1832 * @buff: pointer to a buffer containing device/function capability records
1833 * @cap_count: number of capability records in the list
1834 * @list_type_opc: type of capabilities list to parse
1835 *
1836 * Parse the device/function capabilities list.
1837 **/
1838 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1839 u32 cap_count,
1840 enum i40e_admin_queue_opc list_type_opc)
1841 {
1842 struct i40e_aqc_list_capabilities_element_resp *cap;
1843 u32 number, logical_id, phys_id;
1844 struct i40e_hw_capabilities *p;
1845 u32 reg_val;
1846 u32 i = 0;
1847 u16 id;
1848
1849 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1850
1851 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
1852 p = &hw->dev_caps;
1853 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
1854 p = &hw->func_caps;
1855 else
1856 return;
1857
1858 for (i = 0; i < cap_count; i++, cap++) {
1859 id = le16_to_cpu(cap->id);
1860 number = le32_to_cpu(cap->number);
1861 logical_id = le32_to_cpu(cap->logical_id);
1862 phys_id = le32_to_cpu(cap->phys_id);
1863
1864 switch (id) {
1865 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1866 p->switch_mode = number;
1867 break;
1868 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1869 p->management_mode = number;
1870 break;
1871 case I40E_DEV_FUNC_CAP_NPAR:
1872 p->npar_enable = number;
1873 break;
1874 case I40E_DEV_FUNC_CAP_OS2BMC:
1875 p->os2bmc = number;
1876 break;
1877 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1878 p->valid_functions = number;
1879 break;
1880 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1881 if (number == 1)
1882 p->sr_iov_1_1 = true;
1883 break;
1884 case I40E_DEV_FUNC_CAP_VF:
1885 p->num_vfs = number;
1886 p->vf_base_id = logical_id;
1887 break;
1888 case I40E_DEV_FUNC_CAP_VMDQ:
1889 if (number == 1)
1890 p->vmdq = true;
1891 break;
1892 case I40E_DEV_FUNC_CAP_802_1_QBG:
1893 if (number == 1)
1894 p->evb_802_1_qbg = true;
1895 break;
1896 case I40E_DEV_FUNC_CAP_802_1_QBH:
1897 if (number == 1)
1898 p->evb_802_1_qbh = true;
1899 break;
1900 case I40E_DEV_FUNC_CAP_VSI:
1901 p->num_vsis = number;
1902 break;
1903 case I40E_DEV_FUNC_CAP_DCB:
1904 if (number == 1) {
1905 p->dcb = true;
1906 p->enabled_tcmap = logical_id;
1907 p->maxtc = phys_id;
1908 }
1909 break;
1910 case I40E_DEV_FUNC_CAP_FCOE:
1911 if (number == 1)
1912 p->fcoe = true;
1913 break;
1914 case I40E_DEV_FUNC_CAP_RSS:
1915 p->rss = true;
1916 reg_val = rd32(hw, I40E_PFQF_CTL_0);
1917 if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
1918 p->rss_table_size = number;
1919 else
1920 p->rss_table_size = 128;
1921 p->rss_table_entry_width = logical_id;
1922 break;
1923 case I40E_DEV_FUNC_CAP_RX_QUEUES:
1924 p->num_rx_qp = number;
1925 p->base_queue = phys_id;
1926 break;
1927 case I40E_DEV_FUNC_CAP_TX_QUEUES:
1928 p->num_tx_qp = number;
1929 p->base_queue = phys_id;
1930 break;
1931 case I40E_DEV_FUNC_CAP_MSIX:
1932 p->num_msix_vectors = number;
1933 break;
1934 case I40E_DEV_FUNC_CAP_MSIX_VF:
1935 p->num_msix_vectors_vf = number;
1936 break;
1937 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
1938 if (number == 1)
1939 p->mfp_mode_1 = true;
1940 break;
1941 case I40E_DEV_FUNC_CAP_CEM:
1942 if (number == 1)
1943 p->mgmt_cem = true;
1944 break;
1945 case I40E_DEV_FUNC_CAP_IWARP:
1946 if (number == 1)
1947 p->iwarp = true;
1948 break;
1949 case I40E_DEV_FUNC_CAP_LED:
1950 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1951 p->led[phys_id] = true;
1952 break;
1953 case I40E_DEV_FUNC_CAP_SDP:
1954 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1955 p->sdp[phys_id] = true;
1956 break;
1957 case I40E_DEV_FUNC_CAP_MDIO:
1958 if (number == 1) {
1959 p->mdio_port_num = phys_id;
1960 p->mdio_port_mode = logical_id;
1961 }
1962 break;
1963 case I40E_DEV_FUNC_CAP_IEEE_1588:
1964 if (number == 1)
1965 p->ieee_1588 = true;
1966 break;
1967 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
1968 p->fd = true;
1969 p->fd_filters_guaranteed = number;
1970 p->fd_filters_best_effort = logical_id;
1971 break;
1972 default:
1973 break;
1974 }
1975 }
1976
1977 /* Software override ensuring FCoE is disabled if npar or mfp
1978 * mode because it is not supported in these modes.
1979 */
1980 if (p->npar_enable || p->mfp_mode_1)
1981 p->fcoe = false;
1982
1983 /* additional HW specific goodies that might
1984 * someday be HW version specific
1985 */
1986 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
1987 }
1988
1989 /**
1990 * i40e_aq_discover_capabilities
1991 * @hw: pointer to the hw struct
1992 * @buff: a virtual buffer to hold the capabilities
1993 * @buff_size: Size of the virtual buffer
1994 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
1995 * @list_type_opc: capabilities type to discover - pass in the command opcode
1996 * @cmd_details: pointer to command details structure or NULL
1997 *
1998 * Get the device capabilities descriptions from the firmware
1999 **/
2000 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2001 void *buff, u16 buff_size, u16 *data_size,
2002 enum i40e_admin_queue_opc list_type_opc,
2003 struct i40e_asq_cmd_details *cmd_details)
2004 {
2005 struct i40e_aqc_list_capabilites *cmd;
2006 struct i40e_aq_desc desc;
2007 i40e_status status = 0;
2008
2009 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2010
2011 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2012 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2013 status = I40E_ERR_PARAM;
2014 goto exit;
2015 }
2016
2017 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2018
2019 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2020 if (buff_size > I40E_AQ_LARGE_BUF)
2021 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2022
2023 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2024 *data_size = le16_to_cpu(desc.datalen);
2025
2026 if (status)
2027 goto exit;
2028
2029 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2030 list_type_opc);
2031
2032 exit:
2033 return status;
2034 }
2035
2036 /**
2037 * i40e_aq_get_lldp_mib
2038 * @hw: pointer to the hw struct
2039 * @bridge_type: type of bridge requested
2040 * @mib_type: Local, Remote or both Local and Remote MIBs
2041 * @buff: pointer to a user supplied buffer to store the MIB block
2042 * @buff_size: size of the buffer (in bytes)
2043 * @local_len : length of the returned Local LLDP MIB
2044 * @remote_len: length of the returned Remote LLDP MIB
2045 * @cmd_details: pointer to command details structure or NULL
2046 *
2047 * Requests the complete LLDP MIB (entire packet).
2048 **/
2049 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2050 u8 mib_type, void *buff, u16 buff_size,
2051 u16 *local_len, u16 *remote_len,
2052 struct i40e_asq_cmd_details *cmd_details)
2053 {
2054 struct i40e_aq_desc desc;
2055 struct i40e_aqc_lldp_get_mib *cmd =
2056 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2057 struct i40e_aqc_lldp_get_mib *resp =
2058 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2059 i40e_status status;
2060
2061 if (buff_size == 0 || !buff)
2062 return I40E_ERR_PARAM;
2063
2064 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2065 /* Indirect Command */
2066 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2067
2068 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2069 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2070 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2071
2072 desc.datalen = cpu_to_le16(buff_size);
2073
2074 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2075 if (buff_size > I40E_AQ_LARGE_BUF)
2076 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2077
2078 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2079 if (!status) {
2080 if (local_len != NULL)
2081 *local_len = le16_to_cpu(resp->local_len);
2082 if (remote_len != NULL)
2083 *remote_len = le16_to_cpu(resp->remote_len);
2084 }
2085
2086 return status;
2087 }
2088
2089 /**
2090 * i40e_aq_cfg_lldp_mib_change_event
2091 * @hw: pointer to the hw struct
2092 * @enable_update: Enable or Disable event posting
2093 * @cmd_details: pointer to command details structure or NULL
2094 *
2095 * Enable or Disable posting of an event on ARQ when LLDP MIB
2096 * associated with the interface changes
2097 **/
2098 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2099 bool enable_update,
2100 struct i40e_asq_cmd_details *cmd_details)
2101 {
2102 struct i40e_aq_desc desc;
2103 struct i40e_aqc_lldp_update_mib *cmd =
2104 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2105 i40e_status status;
2106
2107 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2108
2109 if (!enable_update)
2110 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2111
2112 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2113
2114 return status;
2115 }
2116
2117 /**
2118 * i40e_aq_stop_lldp
2119 * @hw: pointer to the hw struct
2120 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2121 * @cmd_details: pointer to command details structure or NULL
2122 *
2123 * Stop or Shutdown the embedded LLDP Agent
2124 **/
2125 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2126 struct i40e_asq_cmd_details *cmd_details)
2127 {
2128 struct i40e_aq_desc desc;
2129 struct i40e_aqc_lldp_stop *cmd =
2130 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2131 i40e_status status;
2132
2133 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2134
2135 if (shutdown_agent)
2136 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2137
2138 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2139
2140 return status;
2141 }
2142
2143 /**
2144 * i40e_aq_start_lldp
2145 * @hw: pointer to the hw struct
2146 * @cmd_details: pointer to command details structure or NULL
2147 *
2148 * Start the embedded LLDP Agent on all ports.
2149 **/
2150 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2151 struct i40e_asq_cmd_details *cmd_details)
2152 {
2153 struct i40e_aq_desc desc;
2154 struct i40e_aqc_lldp_start *cmd =
2155 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2156 i40e_status status;
2157
2158 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2159
2160 cmd->command = I40E_AQ_LLDP_AGENT_START;
2161
2162 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2163
2164 return status;
2165 }
2166
2167 /**
2168 * i40e_aq_add_udp_tunnel
2169 * @hw: pointer to the hw struct
2170 * @udp_port: the UDP port to add
2171 * @header_len: length of the tunneling header length in DWords
2172 * @protocol_index: protocol index type
2173 * @filter_index: pointer to filter index
2174 * @cmd_details: pointer to command details structure or NULL
2175 **/
2176 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
2177 u16 udp_port, u8 protocol_index,
2178 u8 *filter_index,
2179 struct i40e_asq_cmd_details *cmd_details)
2180 {
2181 struct i40e_aq_desc desc;
2182 struct i40e_aqc_add_udp_tunnel *cmd =
2183 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2184 struct i40e_aqc_del_udp_tunnel_completion *resp =
2185 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2186 i40e_status status;
2187
2188 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2189
2190 cmd->udp_port = cpu_to_le16(udp_port);
2191 cmd->protocol_type = protocol_index;
2192
2193 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2194
2195 if (!status)
2196 *filter_index = resp->index;
2197
2198 return status;
2199 }
2200
2201 /**
2202 * i40e_aq_del_udp_tunnel
2203 * @hw: pointer to the hw struct
2204 * @index: filter index
2205 * @cmd_details: pointer to command details structure or NULL
2206 **/
2207 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2208 struct i40e_asq_cmd_details *cmd_details)
2209 {
2210 struct i40e_aq_desc desc;
2211 struct i40e_aqc_remove_udp_tunnel *cmd =
2212 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2213 i40e_status status;
2214
2215 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2216
2217 cmd->index = index;
2218
2219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2220
2221 return status;
2222 }
2223
2224 /**
2225 * i40e_aq_delete_element - Delete switch element
2226 * @hw: pointer to the hw struct
2227 * @seid: the SEID to delete from the switch
2228 * @cmd_details: pointer to command details structure or NULL
2229 *
2230 * This deletes a switch element from the switch.
2231 **/
2232 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2233 struct i40e_asq_cmd_details *cmd_details)
2234 {
2235 struct i40e_aq_desc desc;
2236 struct i40e_aqc_switch_seid *cmd =
2237 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2238 i40e_status status;
2239
2240 if (seid == 0)
2241 return I40E_ERR_PARAM;
2242
2243 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2244
2245 cmd->seid = cpu_to_le16(seid);
2246
2247 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2248
2249 return status;
2250 }
2251
2252 /**
2253 * i40e_aq_dcb_updated - DCB Updated Command
2254 * @hw: pointer to the hw struct
2255 * @cmd_details: pointer to command details structure or NULL
2256 *
2257 * EMP will return when the shared RPB settings have been
2258 * recomputed and modified. The retval field in the descriptor
2259 * will be set to 0 when RPB is modified.
2260 **/
2261 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2262 struct i40e_asq_cmd_details *cmd_details)
2263 {
2264 struct i40e_aq_desc desc;
2265 i40e_status status;
2266
2267 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2268
2269 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2270
2271 return status;
2272 }
2273
2274 /**
2275 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2276 * @hw: pointer to the hw struct
2277 * @seid: seid for the physical port/switching component/vsi
2278 * @buff: Indirect buffer to hold data parameters and response
2279 * @buff_size: Indirect buffer size
2280 * @opcode: Tx scheduler AQ command opcode
2281 * @cmd_details: pointer to command details structure or NULL
2282 *
2283 * Generic command handler for Tx scheduler AQ commands
2284 **/
2285 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2286 void *buff, u16 buff_size,
2287 enum i40e_admin_queue_opc opcode,
2288 struct i40e_asq_cmd_details *cmd_details)
2289 {
2290 struct i40e_aq_desc desc;
2291 struct i40e_aqc_tx_sched_ind *cmd =
2292 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2293 i40e_status status;
2294 bool cmd_param_flag = false;
2295
2296 switch (opcode) {
2297 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2298 case i40e_aqc_opc_configure_vsi_tc_bw:
2299 case i40e_aqc_opc_enable_switching_comp_ets:
2300 case i40e_aqc_opc_modify_switching_comp_ets:
2301 case i40e_aqc_opc_disable_switching_comp_ets:
2302 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2303 case i40e_aqc_opc_configure_switching_comp_bw_config:
2304 cmd_param_flag = true;
2305 break;
2306 case i40e_aqc_opc_query_vsi_bw_config:
2307 case i40e_aqc_opc_query_vsi_ets_sla_config:
2308 case i40e_aqc_opc_query_switching_comp_ets_config:
2309 case i40e_aqc_opc_query_port_ets_config:
2310 case i40e_aqc_opc_query_switching_comp_bw_config:
2311 cmd_param_flag = false;
2312 break;
2313 default:
2314 return I40E_ERR_PARAM;
2315 }
2316
2317 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2318
2319 /* Indirect command */
2320 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2321 if (cmd_param_flag)
2322 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2323 if (buff_size > I40E_AQ_LARGE_BUF)
2324 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2325
2326 desc.datalen = cpu_to_le16(buff_size);
2327
2328 cmd->vsi_seid = cpu_to_le16(seid);
2329
2330 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2331
2332 return status;
2333 }
2334
2335 /**
2336 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2337 * @hw: pointer to the hw struct
2338 * @seid: VSI seid
2339 * @credit: BW limit credits (0 = disabled)
2340 * @max_credit: Max BW limit credits
2341 * @cmd_details: pointer to command details structure or NULL
2342 **/
2343 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2344 u16 seid, u16 credit, u8 max_credit,
2345 struct i40e_asq_cmd_details *cmd_details)
2346 {
2347 struct i40e_aq_desc desc;
2348 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2349 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2350 i40e_status status;
2351
2352 i40e_fill_default_direct_cmd_desc(&desc,
2353 i40e_aqc_opc_configure_vsi_bw_limit);
2354
2355 cmd->vsi_seid = cpu_to_le16(seid);
2356 cmd->credit = cpu_to_le16(credit);
2357 cmd->max_credit = max_credit;
2358
2359 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2360
2361 return status;
2362 }
2363
2364 /**
2365 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2366 * @hw: pointer to the hw struct
2367 * @seid: VSI seid
2368 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2369 * @cmd_details: pointer to command details structure or NULL
2370 **/
2371 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2372 u16 seid,
2373 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2374 struct i40e_asq_cmd_details *cmd_details)
2375 {
2376 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2377 i40e_aqc_opc_configure_vsi_tc_bw,
2378 cmd_details);
2379 }
2380
2381 /**
2382 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2383 * @hw: pointer to the hw struct
2384 * @seid: seid of the switching component connected to Physical Port
2385 * @ets_data: Buffer holding ETS parameters
2386 * @cmd_details: pointer to command details structure or NULL
2387 **/
2388 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2389 u16 seid,
2390 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2391 enum i40e_admin_queue_opc opcode,
2392 struct i40e_asq_cmd_details *cmd_details)
2393 {
2394 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2395 sizeof(*ets_data), opcode, cmd_details);
2396 }
2397
2398 /**
2399 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2400 * @hw: pointer to the hw struct
2401 * @seid: seid of the switching component
2402 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2403 * @cmd_details: pointer to command details structure or NULL
2404 **/
2405 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2406 u16 seid,
2407 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2408 struct i40e_asq_cmd_details *cmd_details)
2409 {
2410 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2411 i40e_aqc_opc_configure_switching_comp_bw_config,
2412 cmd_details);
2413 }
2414
2415 /**
2416 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2417 * @hw: pointer to the hw struct
2418 * @seid: seid of the VSI
2419 * @bw_data: Buffer to hold VSI BW configuration
2420 * @cmd_details: pointer to command details structure or NULL
2421 **/
2422 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2423 u16 seid,
2424 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2425 struct i40e_asq_cmd_details *cmd_details)
2426 {
2427 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2428 i40e_aqc_opc_query_vsi_bw_config,
2429 cmd_details);
2430 }
2431
2432 /**
2433 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2434 * @hw: pointer to the hw struct
2435 * @seid: seid of the VSI
2436 * @bw_data: Buffer to hold VSI BW configuration per TC
2437 * @cmd_details: pointer to command details structure or NULL
2438 **/
2439 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2440 u16 seid,
2441 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2442 struct i40e_asq_cmd_details *cmd_details)
2443 {
2444 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2445 i40e_aqc_opc_query_vsi_ets_sla_config,
2446 cmd_details);
2447 }
2448
2449 /**
2450 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2451 * @hw: pointer to the hw struct
2452 * @seid: seid of the switching component
2453 * @bw_data: Buffer to hold switching component's per TC BW config
2454 * @cmd_details: pointer to command details structure or NULL
2455 **/
2456 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2457 u16 seid,
2458 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2459 struct i40e_asq_cmd_details *cmd_details)
2460 {
2461 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2462 i40e_aqc_opc_query_switching_comp_ets_config,
2463 cmd_details);
2464 }
2465
2466 /**
2467 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2468 * @hw: pointer to the hw struct
2469 * @seid: seid of the VSI or switching component connected to Physical Port
2470 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2471 * @cmd_details: pointer to command details structure or NULL
2472 **/
2473 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2474 u16 seid,
2475 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2476 struct i40e_asq_cmd_details *cmd_details)
2477 {
2478 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2479 i40e_aqc_opc_query_port_ets_config,
2480 cmd_details);
2481 }
2482
2483 /**
2484 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2485 * @hw: pointer to the hw struct
2486 * @seid: seid of the switching component
2487 * @bw_data: Buffer to hold switching component's BW configuration
2488 * @cmd_details: pointer to command details structure or NULL
2489 **/
2490 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2491 u16 seid,
2492 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2493 struct i40e_asq_cmd_details *cmd_details)
2494 {
2495 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2496 i40e_aqc_opc_query_switching_comp_bw_config,
2497 cmd_details);
2498 }
2499
2500 /**
2501 * i40e_validate_filter_settings
2502 * @hw: pointer to the hardware structure
2503 * @settings: Filter control settings
2504 *
2505 * Check and validate the filter control settings passed.
2506 * The function checks for the valid filter/context sizes being
2507 * passed for FCoE and PE.
2508 *
2509 * Returns 0 if the values passed are valid and within
2510 * range else returns an error.
2511 **/
2512 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
2513 struct i40e_filter_control_settings *settings)
2514 {
2515 u32 fcoe_cntx_size, fcoe_filt_size;
2516 u32 pe_cntx_size, pe_filt_size;
2517 u32 fcoe_fmax, pe_fmax;
2518 u32 val;
2519
2520 /* Validate FCoE settings passed */
2521 switch (settings->fcoe_filt_num) {
2522 case I40E_HASH_FILTER_SIZE_1K:
2523 case I40E_HASH_FILTER_SIZE_2K:
2524 case I40E_HASH_FILTER_SIZE_4K:
2525 case I40E_HASH_FILTER_SIZE_8K:
2526 case I40E_HASH_FILTER_SIZE_16K:
2527 case I40E_HASH_FILTER_SIZE_32K:
2528 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2529 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
2530 break;
2531 default:
2532 return I40E_ERR_PARAM;
2533 }
2534
2535 switch (settings->fcoe_cntx_num) {
2536 case I40E_DMA_CNTX_SIZE_512:
2537 case I40E_DMA_CNTX_SIZE_1K:
2538 case I40E_DMA_CNTX_SIZE_2K:
2539 case I40E_DMA_CNTX_SIZE_4K:
2540 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2541 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2542 break;
2543 default:
2544 return I40E_ERR_PARAM;
2545 }
2546
2547 /* Validate PE settings passed */
2548 switch (settings->pe_filt_num) {
2549 case I40E_HASH_FILTER_SIZE_1K:
2550 case I40E_HASH_FILTER_SIZE_2K:
2551 case I40E_HASH_FILTER_SIZE_4K:
2552 case I40E_HASH_FILTER_SIZE_8K:
2553 case I40E_HASH_FILTER_SIZE_16K:
2554 case I40E_HASH_FILTER_SIZE_32K:
2555 case I40E_HASH_FILTER_SIZE_64K:
2556 case I40E_HASH_FILTER_SIZE_128K:
2557 case I40E_HASH_FILTER_SIZE_256K:
2558 case I40E_HASH_FILTER_SIZE_512K:
2559 case I40E_HASH_FILTER_SIZE_1M:
2560 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2561 pe_filt_size <<= (u32)settings->pe_filt_num;
2562 break;
2563 default:
2564 return I40E_ERR_PARAM;
2565 }
2566
2567 switch (settings->pe_cntx_num) {
2568 case I40E_DMA_CNTX_SIZE_512:
2569 case I40E_DMA_CNTX_SIZE_1K:
2570 case I40E_DMA_CNTX_SIZE_2K:
2571 case I40E_DMA_CNTX_SIZE_4K:
2572 case I40E_DMA_CNTX_SIZE_8K:
2573 case I40E_DMA_CNTX_SIZE_16K:
2574 case I40E_DMA_CNTX_SIZE_32K:
2575 case I40E_DMA_CNTX_SIZE_64K:
2576 case I40E_DMA_CNTX_SIZE_128K:
2577 case I40E_DMA_CNTX_SIZE_256K:
2578 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2579 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2580 break;
2581 default:
2582 return I40E_ERR_PARAM;
2583 }
2584
2585 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2586 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2587 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2588 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2589 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2590 return I40E_ERR_INVALID_SIZE;
2591
2592 /* PEHSIZE + PEDSIZE should not be greater than PMPEXFMAX */
2593 val = rd32(hw, I40E_GLHMC_PEXFMAX);
2594 pe_fmax = (val & I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK)
2595 >> I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT;
2596 if (pe_filt_size + pe_cntx_size > pe_fmax)
2597 return I40E_ERR_INVALID_SIZE;
2598
2599 return 0;
2600 }
2601
2602 /**
2603 * i40e_set_filter_control
2604 * @hw: pointer to the hardware structure
2605 * @settings: Filter control settings
2606 *
2607 * Set the Queue Filters for PE/FCoE and enable filters required
2608 * for a single PF. It is expected that these settings are programmed
2609 * at the driver initialization time.
2610 **/
2611 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2612 struct i40e_filter_control_settings *settings)
2613 {
2614 i40e_status ret = 0;
2615 u32 hash_lut_size = 0;
2616 u32 val;
2617
2618 if (!settings)
2619 return I40E_ERR_PARAM;
2620
2621 /* Validate the input settings */
2622 ret = i40e_validate_filter_settings(hw, settings);
2623 if (ret)
2624 return ret;
2625
2626 /* Read the PF Queue Filter control register */
2627 val = rd32(hw, I40E_PFQF_CTL_0);
2628
2629 /* Program required PE hash buckets for the PF */
2630 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2631 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2632 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2633 /* Program required PE contexts for the PF */
2634 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2635 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2636 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2637
2638 /* Program required FCoE hash buckets for the PF */
2639 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2640 val |= ((u32)settings->fcoe_filt_num <<
2641 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2642 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2643 /* Program required FCoE DDP contexts for the PF */
2644 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2645 val |= ((u32)settings->fcoe_cntx_num <<
2646 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2647 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2648
2649 /* Program Hash LUT size for the PF */
2650 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2651 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2652 hash_lut_size = 1;
2653 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2654 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2655
2656 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2657 if (settings->enable_fdir)
2658 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2659 if (settings->enable_ethtype)
2660 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2661 if (settings->enable_macvlan)
2662 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2663
2664 wr32(hw, I40E_PFQF_CTL_0, val);
2665
2666 return 0;
2667 }
2668
2669 /**
2670 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
2671 * @hw: pointer to the hw struct
2672 * @mac_addr: MAC address to use in the filter
2673 * @ethtype: Ethertype to use in the filter
2674 * @flags: Flags that needs to be applied to the filter
2675 * @vsi_seid: seid of the control VSI
2676 * @queue: VSI queue number to send the packet to
2677 * @is_add: Add control packet filter if True else remove
2678 * @stats: Structure to hold information on control filter counts
2679 * @cmd_details: pointer to command details structure or NULL
2680 *
2681 * This command will Add or Remove control packet filter for a control VSI.
2682 * In return it will update the total number of perfect filter count in
2683 * the stats member.
2684 **/
2685 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
2686 u8 *mac_addr, u16 ethtype, u16 flags,
2687 u16 vsi_seid, u16 queue, bool is_add,
2688 struct i40e_control_filter_stats *stats,
2689 struct i40e_asq_cmd_details *cmd_details)
2690 {
2691 struct i40e_aq_desc desc;
2692 struct i40e_aqc_add_remove_control_packet_filter *cmd =
2693 (struct i40e_aqc_add_remove_control_packet_filter *)
2694 &desc.params.raw;
2695 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
2696 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
2697 &desc.params.raw;
2698 i40e_status status;
2699
2700 if (vsi_seid == 0)
2701 return I40E_ERR_PARAM;
2702
2703 if (is_add) {
2704 i40e_fill_default_direct_cmd_desc(&desc,
2705 i40e_aqc_opc_add_control_packet_filter);
2706 cmd->queue = cpu_to_le16(queue);
2707 } else {
2708 i40e_fill_default_direct_cmd_desc(&desc,
2709 i40e_aqc_opc_remove_control_packet_filter);
2710 }
2711
2712 if (mac_addr)
2713 memcpy(cmd->mac, mac_addr, ETH_ALEN);
2714
2715 cmd->etype = cpu_to_le16(ethtype);
2716 cmd->flags = cpu_to_le16(flags);
2717 cmd->seid = cpu_to_le16(vsi_seid);
2718
2719 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2720
2721 if (!status && stats) {
2722 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
2723 stats->etype_used = le16_to_cpu(resp->etype_used);
2724 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
2725 stats->etype_free = le16_to_cpu(resp->etype_free);
2726 }
2727
2728 return status;
2729 }
2730
2731 /**
2732 * i40e_set_pci_config_data - store PCI bus info
2733 * @hw: pointer to hardware structure
2734 * @link_status: the link status word from PCI config space
2735 *
2736 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2737 **/
2738 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2739 {
2740 hw->bus.type = i40e_bus_type_pci_express;
2741
2742 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2743 case PCI_EXP_LNKSTA_NLW_X1:
2744 hw->bus.width = i40e_bus_width_pcie_x1;
2745 break;
2746 case PCI_EXP_LNKSTA_NLW_X2:
2747 hw->bus.width = i40e_bus_width_pcie_x2;
2748 break;
2749 case PCI_EXP_LNKSTA_NLW_X4:
2750 hw->bus.width = i40e_bus_width_pcie_x4;
2751 break;
2752 case PCI_EXP_LNKSTA_NLW_X8:
2753 hw->bus.width = i40e_bus_width_pcie_x8;
2754 break;
2755 default:
2756 hw->bus.width = i40e_bus_width_unknown;
2757 break;
2758 }
2759
2760 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2761 case PCI_EXP_LNKSTA_CLS_2_5GB:
2762 hw->bus.speed = i40e_bus_speed_2500;
2763 break;
2764 case PCI_EXP_LNKSTA_CLS_5_0GB:
2765 hw->bus.speed = i40e_bus_speed_5000;
2766 break;
2767 case PCI_EXP_LNKSTA_CLS_8_0GB:
2768 hw->bus.speed = i40e_bus_speed_8000;
2769 break;
2770 default:
2771 hw->bus.speed = i40e_bus_speed_unknown;
2772 break;
2773 }
2774 }
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