| blob | 72bf1b5737885cc0f8e7ae26595bc86a05d5031f |
1 /*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include "skeleton.dtsi"
21 #include <dt-bindings/clock/exynos3250.h>
23 / {
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
27 aliases {
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 mshc0 = &mshc_0;
31 mshc1 = &mshc_1;
32 spi0 = &spi_0;
33 spi1 = &spi_1;
34 i2c0 = &i2c_0;
35 i2c1 = &i2c_1;
36 i2c2 = &i2c_2;
37 i2c3 = &i2c_3;
38 i2c4 = &i2c_4;
39 i2c5 = &i2c_5;
40 i2c6 = &i2c_6;
41 i2c7 = &i2c_7;
42 serial0 = &serial_0;
43 serial1 = &serial_1;
44 };
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a7";
53 reg = <0>;
54 clock-frequency = <1000000000>;
55 };
57 cpu1: cpu@1 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a7";
60 reg = <1>;
61 clock-frequency = <1000000000>;
62 };
63 };
65 soc: soc {
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
71 fixed-rate-clocks {
72 #address-cells = <1>;
73 #size-cells = <0>;
75 xusbxti: clock@0 {
76 compatible = "fixed-clock";
77 #address-cells = <1>;
78 #size-cells = <0>;
79 reg = <0>;
80 clock-frequency = <0>;
81 #clock-cells = <0>;
82 clock-output-names = "xusbxti";
83 };
85 xxti: clock@1 {
86 compatible = "fixed-clock";
87 reg = <1>;
88 clock-frequency = <0>;
89 #clock-cells = <0>;
90 clock-output-names = "xxti";
91 };
93 xtcxo: clock@2 {
94 compatible = "fixed-clock";
95 reg = <2>;
96 clock-frequency = <0>;
97 #clock-cells = <0>;
98 clock-output-names = "xtcxo";
99 };
100 };
102 sysram@02020000 {
103 compatible = "mmio-sram";
104 reg = <0x02020000 0x40000>;
105 #address-cells = <1>;
106 #size-cells = <1>;
107 ranges = <0 0x02020000 0x40000>;
109 smp-sysram@0 {
110 compatible = "samsung,exynos4210-sysram";
111 reg = <0x0 0x1000>;
112 };
114 smp-sysram@3f000 {
115 compatible = "samsung,exynos4210-sysram-ns";
116 reg = <0x3f000 0x1000>;
117 };
118 };
120 chipid@10000000 {
121 compatible = "samsung,exynos4210-chipid";
122 reg = <0x10000000 0x100>;
123 };
125 sys_reg: syscon@10010000 {
126 compatible = "samsung,exynos3-sysreg", "syscon";
127 reg = <0x10010000 0x400>;
128 };
130 pmu_system_controller: system-controller@10020000 {
131 compatible = "samsung,exynos3250-pmu", "syscon";
132 reg = <0x10020000 0x4000>;
133 };
135 pd_cam: cam-power-domain@10023C00 {
136 compatible = "samsung,exynos4210-pd";
137 reg = <0x10023C00 0x20>;
138 };
140 pd_mfc: mfc-power-domain@10023C40 {
141 compatible = "samsung,exynos4210-pd";
142 reg = <0x10023C40 0x20>;
143 };
145 pd_g3d: g3d-power-domain@10023C60 {
146 compatible = "samsung,exynos4210-pd";
147 reg = <0x10023C60 0x20>;
148 };
150 pd_lcd0: lcd0-power-domain@10023C80 {
151 compatible = "samsung,exynos4210-pd";
152 reg = <0x10023C80 0x20>;
153 };
155 pd_isp: isp-power-domain@10023CA0 {
156 compatible = "samsung,exynos4210-pd";
157 reg = <0x10023CA0 0x20>;
158 };
160 cmu: clock-controller@10030000 {
161 compatible = "samsung,exynos3250-cmu";
162 reg = <0x10030000 0x20000>;
163 #clock-cells = <1>;
164 };
166 cmu_dmc: clock-controller@105C0000 {
167 compatible = "samsung,exynos3250-cmu-dmc";
168 reg = <0x105C0000 0x2000>;
169 #clock-cells = <1>;
170 };
172 rtc: rtc@10070000 {
173 compatible = "samsung,s3c6410-rtc";
174 reg = <0x10070000 0x100>;
175 interrupts = <0 73 0>, <0 74 0>;
176 status = "disabled";
177 };
179 tmu: tmu@100C0000 {
180 compatible = "samsung,exynos3250-tmu";
181 reg = <0x100C0000 0x100>;
182 interrupts = <0 216 0>;
183 clocks = <&cmu CLK_TMU_APBIF>;
184 clock-names = "tmu_apbif";
185 status = "disabled";
186 };
188 gic: interrupt-controller@10481000 {
189 compatible = "arm,cortex-a15-gic";
190 #interrupt-cells = <3>;
191 interrupt-controller;
192 reg = <0x10481000 0x1000>,
193 <0x10482000 0x1000>,
194 <0x10484000 0x2000>,
195 <0x10486000 0x2000>;
196 interrupts = <1 9 0xf04>;
197 };
199 mct@10050000 {
200 compatible = "samsung,exynos4210-mct";
201 reg = <0x10050000 0x800>;
202 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
203 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
204 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
205 clock-names = "fin_pll", "mct";
206 };
208 pinctrl_1: pinctrl@11000000 {
209 compatible = "samsung,exynos3250-pinctrl";
210 reg = <0x11000000 0x1000>;
211 interrupts = <0 225 0>;
213 wakeup-interrupt-controller {
214 compatible = "samsung,exynos4210-wakeup-eint";
215 interrupts = <0 48 0>;
216 };
217 };
219 pinctrl_0: pinctrl@11400000 {
220 compatible = "samsung,exynos3250-pinctrl";
221 reg = <0x11400000 0x1000>;
222 interrupts = <0 240 0>;
223 };
225 mshc_0: mshc@12510000 {
226 compatible = "samsung,exynos5250-dw-mshc";
227 reg = <0x12510000 0x1000>;
228 interrupts = <0 142 0>;
229 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
230 clock-names = "biu", "ciu";
231 fifo-depth = <0x80>;
232 #address-cells = <1>;
233 #size-cells = <0>;
234 status = "disabled";
235 };
237 mshc_1: mshc@12520000 {
238 compatible = "samsung,exynos5250-dw-mshc";
239 reg = <0x12520000 0x1000>;
240 interrupts = <0 143 0>;
241 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
242 clock-names = "biu", "ciu";
243 fifo-depth = <0x80>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 status = "disabled";
247 };
249 amba {
250 compatible = "arm,amba-bus";
251 #address-cells = <1>;
252 #size-cells = <1>;
253 ranges;
255 pdma0: pdma@12680000 {
256 compatible = "arm,pl330", "arm,primecell";
257 reg = <0x12680000 0x1000>;
258 interrupts = <0 138 0>;
259 clocks = <&cmu CLK_PDMA0>;
260 clock-names = "apb_pclk";
261 #dma-cells = <1>;
262 #dma-channels = <8>;
263 #dma-requests = <32>;
264 };
266 pdma1: pdma@12690000 {
267 compatible = "arm,pl330", "arm,primecell";
268 reg = <0x12690000 0x1000>;
269 interrupts = <0 139 0>;
270 clocks = <&cmu CLK_PDMA1>;
271 clock-names = "apb_pclk";
272 #dma-cells = <1>;
273 #dma-channels = <8>;
274 #dma-requests = <32>;
275 };
276 };
278 adc: adc@126C0000 {
279 compatible = "samsung,exynos3250-adc",
280 "samsung,exynos-adc-v2";
281 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
282 interrupts = <0 137 0>;
283 clock-names = "adc", "sclk";
284 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
285 #io-channel-cells = <1>;
286 io-channel-ranges;
287 status = "disabled";
288 };
290 serial_0: serial@13800000 {
291 compatible = "samsung,exynos4210-uart";
292 reg = <0x13800000 0x100>;
293 interrupts = <0 109 0>;
294 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
295 clock-names = "uart", "clk_uart_baud0";
296 pinctrl-names = "default";
297 pinctrl-0 = <&uart0_data &uart0_fctl>;
298 status = "disabled";
299 };
301 serial_1: serial@13810000 {
302 compatible = "samsung,exynos4210-uart";
303 reg = <0x13810000 0x100>;
304 interrupts = <0 110 0>;
305 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
306 clock-names = "uart", "clk_uart_baud0";
307 pinctrl-names = "default";
308 pinctrl-0 = <&uart1_data>;
309 status = "disabled";
310 };
312 i2c_0: i2c@13860000 {
313 #address-cells = <1>;
314 #size-cells = <0>;
315 compatible = "samsung,s3c2440-i2c";
316 reg = <0x13860000 0x100>;
317 interrupts = <0 113 0>;
318 clocks = <&cmu CLK_I2C0>;
319 clock-names = "i2c";
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c0_bus>;
322 status = "disabled";
323 };
325 i2c_1: i2c@13870000 {
326 #address-cells = <1>;
327 #size-cells = <0>;
328 compatible = "samsung,s3c2440-i2c";
329 reg = <0x13870000 0x100>;
330 interrupts = <0 114 0>;
331 clocks = <&cmu CLK_I2C1>;
332 clock-names = "i2c";
333 pinctrl-names = "default";
334 pinctrl-0 = <&i2c1_bus>;
335 status = "disabled";
336 };
338 i2c_2: i2c@13880000 {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 compatible = "samsung,s3c2440-i2c";
342 reg = <0x13880000 0x100>;
343 interrupts = <0 115 0>;
344 clocks = <&cmu CLK_I2C2>;
345 clock-names = "i2c";
346 pinctrl-names = "default";
347 pinctrl-0 = <&i2c2_bus>;
348 status = "disabled";
349 };
351 i2c_3: i2c@13890000 {
352 #address-cells = <1>;
353 #size-cells = <0>;
354 compatible = "samsung,s3c2440-i2c";
355 reg = <0x13890000 0x100>;
356 interrupts = <0 116 0>;
357 clocks = <&cmu CLK_I2C3>;
358 clock-names = "i2c";
359 pinctrl-names = "default";
360 pinctrl-0 = <&i2c3_bus>;
361 status = "disabled";
362 };
364 i2c_4: i2c@138A0000 {
365 #address-cells = <1>;
366 #size-cells = <0>;
367 compatible = "samsung,s3c2440-i2c";
368 reg = <0x138A0000 0x100>;
369 interrupts = <0 117 0>;
370 clocks = <&cmu CLK_I2C4>;
371 clock-names = "i2c";
372 pinctrl-names = "default";
373 pinctrl-0 = <&i2c4_bus>;
374 status = "disabled";
375 };
377 i2c_5: i2c@138B0000 {
378 #address-cells = <1>;
379 #size-cells = <0>;
380 compatible = "samsung,s3c2440-i2c";
381 reg = <0x138B0000 0x100>;
382 interrupts = <0 118 0>;
383 clocks = <&cmu CLK_I2C5>;
384 clock-names = "i2c";
385 pinctrl-names = "default";
386 pinctrl-0 = <&i2c5_bus>;
387 status = "disabled";
388 };
390 i2c_6: i2c@138C0000 {
391 #address-cells = <1>;
392 #size-cells = <0>;
393 compatible = "samsung,s3c2440-i2c";
394 reg = <0x138C0000 0x100>;
395 interrupts = <0 119 0>;
396 clocks = <&cmu CLK_I2C6>;
397 clock-names = "i2c";
398 pinctrl-names = "default";
399 pinctrl-0 = <&i2c6_bus>;
400 status = "disabled";
401 };
403 i2c_7: i2c@138D0000 {
404 #address-cells = <1>;
405 #size-cells = <0>;
406 compatible = "samsung,s3c2440-i2c";
407 reg = <0x138D0000 0x100>;
408 interrupts = <0 120 0>;
409 clocks = <&cmu CLK_I2C7>;
410 clock-names = "i2c";
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2c7_bus>;
413 status = "disabled";
414 };
416 spi_0: spi@13920000 {
417 compatible = "samsung,exynos4210-spi";
418 reg = <0x13920000 0x100>;
419 interrupts = <0 121 0>;
420 dmas = <&pdma0 7>, <&pdma0 6>;
421 dma-names = "tx", "rx";
422 #address-cells = <1>;
423 #size-cells = <0>;
424 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
425 clock-names = "spi", "spi_busclk0";
426 samsung,spi-src-clk = <0>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&spi0_bus>;
429 status = "disabled";
430 };
432 spi_1: spi@13930000 {
433 compatible = "samsung,exynos4210-spi";
434 reg = <0x13930000 0x100>;
435 interrupts = <0 122 0>;
436 dmas = <&pdma1 7>, <&pdma1 6>;
437 dma-names = "tx", "rx";
438 #address-cells = <1>;
439 #size-cells = <0>;
440 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
441 clock-names = "spi", "spi_busclk0";
442 samsung,spi-src-clk = <0>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&spi1_bus>;
445 status = "disabled";
446 };
448 i2s2: i2s@13970000 {
449 compatible = "samsung,s3c6410-i2s";
450 reg = <0x13970000 0x100>;
451 interrupts = <0 126 0>;
452 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
453 clock-names = "iis", "i2s_opclk0";
454 dmas = <&pdma0 14>, <&pdma0 13>;
455 dma-names = "tx", "rx";
456 pinctrl-0 = <&i2s2_bus>;
457 pinctrl-names = "default";
458 status = "disabled";
459 };
461 pwm: pwm@139D0000 {
462 compatible = "samsung,exynos4210-pwm";
463 reg = <0x139D0000 0x1000>;
464 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
465 <0 107 0>, <0 108 0>;
466 #pwm-cells = <3>;
467 status = "disabled";
468 };
470 pmu {
471 compatible = "arm,cortex-a7-pmu";
472 interrupts = <0 18 0>, <0 19 0>;
473 };
474 };
475 };
477 #include "exynos3250-pinctrl.dtsi"