2 * Specific bus support for PMC-TWI compliant implementation on MSP71xx.
4 * Copyright 2005-2007 PMC-Sierra, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/platform_device.h>
31 #include <linux/i2c.h>
32 #include <linux/interrupt.h>
33 #include <linux/completion.h>
34 #include <linux/mutex.h>
35 #include <linux/delay.h>
38 #define DRV_NAME "pmcmsptwi"
40 #define MSP_TWI_SF_CLK_REG_OFFSET 0x00
41 #define MSP_TWI_HS_CLK_REG_OFFSET 0x04
42 #define MSP_TWI_CFG_REG_OFFSET 0x08
43 #define MSP_TWI_CMD_REG_OFFSET 0x0c
44 #define MSP_TWI_ADD_REG_OFFSET 0x10
45 #define MSP_TWI_DAT_0_REG_OFFSET 0x14
46 #define MSP_TWI_DAT_1_REG_OFFSET 0x18
47 #define MSP_TWI_INT_STS_REG_OFFSET 0x1c
48 #define MSP_TWI_INT_MSK_REG_OFFSET 0x20
49 #define MSP_TWI_BUSY_REG_OFFSET 0x24
51 #define MSP_TWI_INT_STS_DONE (1 << 0)
52 #define MSP_TWI_INT_STS_LOST_ARBITRATION (1 << 1)
53 #define MSP_TWI_INT_STS_NO_RESPONSE (1 << 2)
54 #define MSP_TWI_INT_STS_DATA_COLLISION (1 << 3)
55 #define MSP_TWI_INT_STS_BUSY (1 << 4)
56 #define MSP_TWI_INT_STS_ALL 0x1f
58 #define MSP_MAX_BYTES_PER_RW 8
59 #define MSP_MAX_POLL 5
60 #define MSP_POLL_DELAY 10
61 #define MSP_IRQ_TIMEOUT (MSP_MAX_POLL * MSP_POLL_DELAY)
63 /* IO Operation macros */
64 #define pmcmsptwi_readl __raw_readl
65 #define pmcmsptwi_writel __raw_writel
67 /* TWI command type */
68 enum pmcmsptwi_cmd_type
{
69 MSP_TWI_CMD_WRITE
= 0, /* Write only */
70 MSP_TWI_CMD_READ
= 1, /* Read only */
71 MSP_TWI_CMD_WRITE_READ
= 2, /* Write then Read */
74 /* The possible results of the xferCmd */
75 enum pmcmsptwi_xfer_result
{
79 MSP_TWI_XFER_DATA_COLLISION
,
80 MSP_TWI_XFER_NO_RESPONSE
,
81 MSP_TWI_XFER_LOST_ARBITRATION
,
84 /* Corresponds to a PMCTWI clock configuration register */
85 struct pmcmsptwi_clock
{
86 u8 filter
; /* Bits 15:12, default = 0x03 */
87 u16 clock
; /* Bits 9:0, default = 0x001f */
90 struct pmcmsptwi_clockcfg
{
91 struct pmcmsptwi_clock standard
; /* The standard/fast clock config */
92 struct pmcmsptwi_clock highspeed
; /* The highspeed clock config */
95 /* Corresponds to the main TWI configuration register */
96 struct pmcmsptwi_cfg
{
97 u8 arbf
; /* Bits 15:12, default=0x03 */
98 u8 nak
; /* Bits 11:8, default=0x03 */
99 u8 add10
; /* Bit 7, default=0x00 */
100 u8 mst_code
; /* Bits 6:4, default=0x00 */
101 u8 arb
; /* Bit 1, default=0x01 */
102 u8 highspeed
; /* Bit 0, default=0x00 */
105 /* A single pmctwi command to issue */
106 struct pmcmsptwi_cmd
{
107 u16 addr
; /* The slave address (7 or 10 bits) */
108 enum pmcmsptwi_cmd_type type
; /* The command type */
109 u8 write_len
; /* Number of bytes in the write buffer */
110 u8 read_len
; /* Number of bytes in the read buffer */
111 u8
*write_data
; /* Buffer of characters to send */
112 u8
*read_data
; /* Buffer to fill with incoming data */
115 /* The private data */
116 struct pmcmsptwi_data
{
117 void __iomem
*iobase
; /* iomapped base for IO */
118 int irq
; /* IRQ to use (0 disables) */
119 struct completion wait
; /* Completion for xfer */
120 struct mutex lock
; /* Used for threadsafeness */
121 enum pmcmsptwi_xfer_result last_result
; /* result of last xfer */
124 /* The default settings */
125 static const struct pmcmsptwi_clockcfg pmcmsptwi_defclockcfg
= {
136 static const struct pmcmsptwi_cfg pmcmsptwi_defcfg
= {
145 static struct pmcmsptwi_data pmcmsptwi_data
;
147 static struct i2c_adapter pmcmsptwi_adapter
;
149 /* inline helper functions */
150 static inline u32
pmcmsptwi_clock_to_reg(
151 const struct pmcmsptwi_clock
*clock
)
153 return ((clock
->filter
& 0xf) << 12) | (clock
->clock
& 0x03ff);
156 static inline void pmcmsptwi_reg_to_clock(
157 u32 reg
, struct pmcmsptwi_clock
*clock
)
159 clock
->filter
= (reg
>> 12) & 0xf;
160 clock
->clock
= reg
& 0x03ff;
163 static inline u32
pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg
*cfg
)
165 return ((cfg
->arbf
& 0xf) << 12) |
166 ((cfg
->nak
& 0xf) << 8) |
167 ((cfg
->add10
& 0x1) << 7) |
168 ((cfg
->mst_code
& 0x7) << 4) |
169 ((cfg
->arb
& 0x1) << 1) |
170 (cfg
->highspeed
& 0x1);
173 static inline void pmcmsptwi_reg_to_cfg(u32 reg
, struct pmcmsptwi_cfg
*cfg
)
175 cfg
->arbf
= (reg
>> 12) & 0xf;
176 cfg
->nak
= (reg
>> 8) & 0xf;
177 cfg
->add10
= (reg
>> 7) & 0x1;
178 cfg
->mst_code
= (reg
>> 4) & 0x7;
179 cfg
->arb
= (reg
>> 1) & 0x1;
180 cfg
->highspeed
= reg
& 0x1;
184 * Sets the current clock configuration
186 static void pmcmsptwi_set_clock_config(const struct pmcmsptwi_clockcfg
*cfg
,
187 struct pmcmsptwi_data
*data
)
189 mutex_lock(&data
->lock
);
190 pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg
->standard
),
191 data
->iobase
+ MSP_TWI_SF_CLK_REG_OFFSET
);
192 pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg
->highspeed
),
193 data
->iobase
+ MSP_TWI_HS_CLK_REG_OFFSET
);
194 mutex_unlock(&data
->lock
);
198 * Gets the current TWI bus configuration
200 static void pmcmsptwi_get_twi_config(struct pmcmsptwi_cfg
*cfg
,
201 struct pmcmsptwi_data
*data
)
203 mutex_lock(&data
->lock
);
204 pmcmsptwi_reg_to_cfg(pmcmsptwi_readl(
205 data
->iobase
+ MSP_TWI_CFG_REG_OFFSET
), cfg
);
206 mutex_unlock(&data
->lock
);
210 * Sets the current TWI bus configuration
212 static void pmcmsptwi_set_twi_config(const struct pmcmsptwi_cfg
*cfg
,
213 struct pmcmsptwi_data
*data
)
215 mutex_lock(&data
->lock
);
216 pmcmsptwi_writel(pmcmsptwi_cfg_to_reg(cfg
),
217 data
->iobase
+ MSP_TWI_CFG_REG_OFFSET
);
218 mutex_unlock(&data
->lock
);
222 * Parses the 'int_sts' register and returns a well-defined error code
224 static enum pmcmsptwi_xfer_result
pmcmsptwi_get_result(u32 reg
)
226 if (reg
& MSP_TWI_INT_STS_LOST_ARBITRATION
) {
227 dev_dbg(&pmcmsptwi_adapter
.dev
,
228 "Result: Lost arbitration\n");
229 return MSP_TWI_XFER_LOST_ARBITRATION
;
230 } else if (reg
& MSP_TWI_INT_STS_NO_RESPONSE
) {
231 dev_dbg(&pmcmsptwi_adapter
.dev
,
232 "Result: No response\n");
233 return MSP_TWI_XFER_NO_RESPONSE
;
234 } else if (reg
& MSP_TWI_INT_STS_DATA_COLLISION
) {
235 dev_dbg(&pmcmsptwi_adapter
.dev
,
236 "Result: Data collision\n");
237 return MSP_TWI_XFER_DATA_COLLISION
;
238 } else if (reg
& MSP_TWI_INT_STS_BUSY
) {
239 dev_dbg(&pmcmsptwi_adapter
.dev
,
240 "Result: Bus busy\n");
241 return MSP_TWI_XFER_BUSY
;
244 dev_dbg(&pmcmsptwi_adapter
.dev
, "Result: Operation succeeded\n");
245 return MSP_TWI_XFER_OK
;
249 * In interrupt mode, handle the interrupt.
250 * NOTE: Assumes data->lock is held.
252 static irqreturn_t
pmcmsptwi_interrupt(int irq
, void *ptr
)
254 struct pmcmsptwi_data
*data
= ptr
;
256 u32 reason
= pmcmsptwi_readl(data
->iobase
+
257 MSP_TWI_INT_STS_REG_OFFSET
);
258 pmcmsptwi_writel(reason
, data
->iobase
+ MSP_TWI_INT_STS_REG_OFFSET
);
260 dev_dbg(&pmcmsptwi_adapter
.dev
, "Got interrupt 0x%08x\n", reason
);
261 if (!(reason
& MSP_TWI_INT_STS_DONE
))
264 data
->last_result
= pmcmsptwi_get_result(reason
);
265 complete(&data
->wait
);
271 * Probe for and register the device and return 0 if there is one.
273 static int __devinit
pmcmsptwi_probe(struct platform_device
*pldev
)
275 struct resource
*res
;
278 /* get the static platform resources */
279 res
= platform_get_resource(pldev
, IORESOURCE_MEM
, 0);
281 dev_err(&pldev
->dev
, "IOMEM resource not found\n");
285 /* reserve the memory region */
286 if (!request_mem_region(res
->start
, resource_size(res
),
289 "Unable to get memory/io address region 0x%08x\n",
295 /* remap the memory */
296 pmcmsptwi_data
.iobase
= ioremap_nocache(res
->start
,
298 if (!pmcmsptwi_data
.iobase
) {
300 "Unable to ioremap address 0x%08x\n", res
->start
);
305 /* request the irq */
306 pmcmsptwi_data
.irq
= platform_get_irq(pldev
, 0);
307 if (pmcmsptwi_data
.irq
) {
308 rc
= request_irq(pmcmsptwi_data
.irq
, &pmcmsptwi_interrupt
,
309 IRQF_SHARED
, pldev
->name
, &pmcmsptwi_data
);
312 * Enable 'DONE' interrupt only.
314 * If you enable all interrupts, you will get one on
315 * error and another when the operation completes.
316 * This way you only have to handle one interrupt,
317 * but you can still check all result flags.
319 pmcmsptwi_writel(MSP_TWI_INT_STS_DONE
,
320 pmcmsptwi_data
.iobase
+
321 MSP_TWI_INT_MSK_REG_OFFSET
);
323 dev_warn(&pldev
->dev
,
324 "Could not assign TWI IRQ handler "
325 "to irq %d (continuing with poll)\n",
327 pmcmsptwi_data
.irq
= 0;
331 init_completion(&pmcmsptwi_data
.wait
);
332 mutex_init(&pmcmsptwi_data
.lock
);
334 pmcmsptwi_set_clock_config(&pmcmsptwi_defclockcfg
, &pmcmsptwi_data
);
335 pmcmsptwi_set_twi_config(&pmcmsptwi_defcfg
, &pmcmsptwi_data
);
337 printk(KERN_INFO DRV_NAME
": Registering MSP71xx I2C adapter\n");
339 pmcmsptwi_adapter
.dev
.parent
= &pldev
->dev
;
340 platform_set_drvdata(pldev
, &pmcmsptwi_adapter
);
341 i2c_set_adapdata(&pmcmsptwi_adapter
, &pmcmsptwi_data
);
343 rc
= i2c_add_adapter(&pmcmsptwi_adapter
);
345 dev_err(&pldev
->dev
, "Unable to register I2C adapter\n");
352 platform_set_drvdata(pldev
, NULL
);
353 if (pmcmsptwi_data
.irq
) {
355 pmcmsptwi_data
.iobase
+ MSP_TWI_INT_MSK_REG_OFFSET
);
356 free_irq(pmcmsptwi_data
.irq
, &pmcmsptwi_data
);
359 iounmap(pmcmsptwi_data
.iobase
);
362 release_mem_region(res
->start
, resource_size(res
));
369 * Release the device and return 0 if there is one.
371 static int __devexit
pmcmsptwi_remove(struct platform_device
*pldev
)
373 struct resource
*res
;
375 i2c_del_adapter(&pmcmsptwi_adapter
);
377 platform_set_drvdata(pldev
, NULL
);
378 if (pmcmsptwi_data
.irq
) {
380 pmcmsptwi_data
.iobase
+ MSP_TWI_INT_MSK_REG_OFFSET
);
381 free_irq(pmcmsptwi_data
.irq
, &pmcmsptwi_data
);
384 iounmap(pmcmsptwi_data
.iobase
);
386 res
= platform_get_resource(pldev
, IORESOURCE_MEM
, 0);
387 release_mem_region(res
->start
, resource_size(res
));
393 * Polls the 'busy' register until the command is complete.
394 * NOTE: Assumes data->lock is held.
396 static void pmcmsptwi_poll_complete(struct pmcmsptwi_data
*data
)
400 for (i
= 0; i
< MSP_MAX_POLL
; i
++) {
401 u32 val
= pmcmsptwi_readl(data
->iobase
+
402 MSP_TWI_BUSY_REG_OFFSET
);
404 u32 reason
= pmcmsptwi_readl(data
->iobase
+
405 MSP_TWI_INT_STS_REG_OFFSET
);
406 pmcmsptwi_writel(reason
, data
->iobase
+
407 MSP_TWI_INT_STS_REG_OFFSET
);
408 data
->last_result
= pmcmsptwi_get_result(reason
);
411 udelay(MSP_POLL_DELAY
);
414 dev_dbg(&pmcmsptwi_adapter
.dev
, "Result: Poll timeout\n");
415 data
->last_result
= MSP_TWI_XFER_TIMEOUT
;
419 * Do the transfer (low level):
420 * May use interrupt-driven or polling, depending on if an IRQ is
421 * presently registered.
422 * NOTE: Assumes data->lock is held.
424 static enum pmcmsptwi_xfer_result
pmcmsptwi_do_xfer(
425 u32 reg
, struct pmcmsptwi_data
*data
)
427 dev_dbg(&pmcmsptwi_adapter
.dev
, "Writing cmd reg 0x%08x\n", reg
);
428 pmcmsptwi_writel(reg
, data
->iobase
+ MSP_TWI_CMD_REG_OFFSET
);
430 unsigned long timeleft
= wait_for_completion_timeout(
431 &data
->wait
, MSP_IRQ_TIMEOUT
);
433 dev_dbg(&pmcmsptwi_adapter
.dev
,
434 "Result: IRQ timeout\n");
435 complete(&data
->wait
);
436 data
->last_result
= MSP_TWI_XFER_TIMEOUT
;
439 pmcmsptwi_poll_complete(data
);
441 return data
->last_result
;
445 * Helper routine, converts 'pmctwi_cmd' struct to register format
447 static inline u32
pmcmsptwi_cmd_to_reg(const struct pmcmsptwi_cmd
*cmd
)
449 return ((cmd
->type
& 0x3) << 8) |
450 (((cmd
->write_len
- 1) & 0x7) << 4) |
451 ((cmd
->read_len
- 1) & 0x7);
455 * Do the transfer (high level)
457 static enum pmcmsptwi_xfer_result
pmcmsptwi_xfer_cmd(
458 struct pmcmsptwi_cmd
*cmd
,
459 struct pmcmsptwi_data
*data
)
461 enum pmcmsptwi_xfer_result retval
;
463 if ((cmd
->type
== MSP_TWI_CMD_WRITE
&& cmd
->write_len
== 0) ||
464 (cmd
->type
== MSP_TWI_CMD_READ
&& cmd
->read_len
== 0) ||
465 (cmd
->type
== MSP_TWI_CMD_WRITE_READ
&&
466 (cmd
->read_len
== 0 || cmd
->write_len
== 0))) {
467 dev_err(&pmcmsptwi_adapter
.dev
,
468 "%s: Cannot transfer less than 1 byte\n",
473 if (cmd
->read_len
> MSP_MAX_BYTES_PER_RW
||
474 cmd
->write_len
> MSP_MAX_BYTES_PER_RW
) {
475 dev_err(&pmcmsptwi_adapter
.dev
,
476 "%s: Cannot transfer more than %d bytes\n",
477 __func__
, MSP_MAX_BYTES_PER_RW
);
481 mutex_lock(&data
->lock
);
482 dev_dbg(&pmcmsptwi_adapter
.dev
,
483 "Setting address to 0x%04x\n", cmd
->addr
);
484 pmcmsptwi_writel(cmd
->addr
, data
->iobase
+ MSP_TWI_ADD_REG_OFFSET
);
486 if (cmd
->type
== MSP_TWI_CMD_WRITE
||
487 cmd
->type
== MSP_TWI_CMD_WRITE_READ
) {
488 u64 tmp
= be64_to_cpup((__be64
*)cmd
->write_data
);
489 tmp
>>= (MSP_MAX_BYTES_PER_RW
- cmd
->write_len
) * 8;
490 dev_dbg(&pmcmsptwi_adapter
.dev
, "Writing 0x%016llx\n", tmp
);
491 pmcmsptwi_writel(tmp
& 0x00000000ffffffffLL
,
492 data
->iobase
+ MSP_TWI_DAT_0_REG_OFFSET
);
493 if (cmd
->write_len
> 4)
494 pmcmsptwi_writel(tmp
>> 32,
495 data
->iobase
+ MSP_TWI_DAT_1_REG_OFFSET
);
498 retval
= pmcmsptwi_do_xfer(pmcmsptwi_cmd_to_reg(cmd
), data
);
499 if (retval
!= MSP_TWI_XFER_OK
)
502 if (cmd
->type
== MSP_TWI_CMD_READ
||
503 cmd
->type
== MSP_TWI_CMD_WRITE_READ
) {
505 u64 rmsk
= ~(0xffffffffffffffffLL
<< (cmd
->read_len
* 8));
506 u64 tmp
= (u64
)pmcmsptwi_readl(data
->iobase
+
507 MSP_TWI_DAT_0_REG_OFFSET
);
508 if (cmd
->read_len
> 4)
509 tmp
|= (u64
)pmcmsptwi_readl(data
->iobase
+
510 MSP_TWI_DAT_1_REG_OFFSET
) << 32;
512 dev_dbg(&pmcmsptwi_adapter
.dev
, "Read 0x%016llx\n", tmp
);
514 for (i
= 0; i
< cmd
->read_len
; i
++)
515 cmd
->read_data
[i
] = tmp
>> i
;
519 mutex_unlock(&data
->lock
);
524 /* -- Algorithm functions -- */
527 * Sends an i2c command out on the adapter
529 static int pmcmsptwi_master_xfer(struct i2c_adapter
*adap
,
530 struct i2c_msg
*msg
, int num
)
532 struct pmcmsptwi_data
*data
= i2c_get_adapdata(adap
);
533 struct pmcmsptwi_cmd cmd
;
534 struct pmcmsptwi_cfg oldcfg
, newcfg
;
538 dev_dbg(&adap
->dev
, "%d messages unsupported\n", num
);
540 } else if (num
== 2) {
541 /* Check for a dual write-then-read command */
542 struct i2c_msg
*nextmsg
= msg
+ 1;
543 if (!(msg
->flags
& I2C_M_RD
) &&
544 (nextmsg
->flags
& I2C_M_RD
) &&
545 msg
->addr
== nextmsg
->addr
) {
546 cmd
.type
= MSP_TWI_CMD_WRITE_READ
;
547 cmd
.write_len
= msg
->len
;
548 cmd
.write_data
= msg
->buf
;
549 cmd
.read_len
= nextmsg
->len
;
550 cmd
.read_data
= nextmsg
->buf
;
553 "Non write-read dual messages unsupported\n");
556 } else if (msg
->flags
& I2C_M_RD
) {
557 cmd
.type
= MSP_TWI_CMD_READ
;
558 cmd
.read_len
= msg
->len
;
559 cmd
.read_data
= msg
->buf
;
561 cmd
.write_data
= NULL
;
563 cmd
.type
= MSP_TWI_CMD_WRITE
;
565 cmd
.read_data
= NULL
;
566 cmd
.write_len
= msg
->len
;
567 cmd
.write_data
= msg
->buf
;
571 dev_err(&adap
->dev
, "Zero-byte messages unsupported\n");
575 cmd
.addr
= msg
->addr
;
577 if (msg
->flags
& I2C_M_TEN
) {
578 pmcmsptwi_get_twi_config(&newcfg
, data
);
579 memcpy(&oldcfg
, &newcfg
, sizeof(oldcfg
));
581 /* Set the special 10-bit address flag */
584 pmcmsptwi_set_twi_config(&newcfg
, data
);
587 /* Execute the command */
588 ret
= pmcmsptwi_xfer_cmd(&cmd
, data
);
590 if (msg
->flags
& I2C_M_TEN
)
591 pmcmsptwi_set_twi_config(&oldcfg
, data
);
593 dev_dbg(&adap
->dev
, "I2C %s of %d bytes %s\n",
594 (msg
->flags
& I2C_M_RD
) ? "read" : "write", msg
->len
,
595 (ret
== MSP_TWI_XFER_OK
) ? "succeeded" : "failed");
597 if (ret
!= MSP_TWI_XFER_OK
) {
599 * TODO: We could potentially loop and retry in the case
600 * of MSP_TWI_XFER_TIMEOUT.
608 static u32
pmcmsptwi_i2c_func(struct i2c_adapter
*adapter
)
610 return I2C_FUNC_I2C
| I2C_FUNC_10BIT_ADDR
|
611 I2C_FUNC_SMBUS_BYTE
| I2C_FUNC_SMBUS_BYTE_DATA
|
612 I2C_FUNC_SMBUS_WORD_DATA
| I2C_FUNC_SMBUS_PROC_CALL
;
615 /* -- Initialization -- */
617 static struct i2c_algorithm pmcmsptwi_algo
= {
618 .master_xfer
= pmcmsptwi_master_xfer
,
619 .functionality
= pmcmsptwi_i2c_func
,
622 static struct i2c_adapter pmcmsptwi_adapter
= {
623 .owner
= THIS_MODULE
,
624 .class = I2C_CLASS_HWMON
| I2C_CLASS_SPD
,
625 .algo
= &pmcmsptwi_algo
,
629 static struct platform_driver pmcmsptwi_driver
= {
630 .probe
= pmcmsptwi_probe
,
631 .remove
= __devexit_p(pmcmsptwi_remove
),
634 .owner
= THIS_MODULE
,
638 module_platform_driver(pmcmsptwi_driver
);
640 MODULE_DESCRIPTION("PMC MSP TWI/SMBus/I2C driver");
641 MODULE_LICENSE("GPL");
642 MODULE_ALIAS("platform:" DRV_NAME
);