2 * Synopsys DesignWare I2C adapter driver (master only).
4 * Based on the TI DAVINCI I2C adapter driver.
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
10 * ----------------------------------------------------------------------------
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/errno.h>
31 #include <linux/err.h>
32 #include <linux/i2c.h>
33 #include <linux/interrupt.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/delay.h>
37 #include "i2c-designware-core.h"
44 #define DW_IC_DATA_CMD 0x10
45 #define DW_IC_SS_SCL_HCNT 0x14
46 #define DW_IC_SS_SCL_LCNT 0x18
47 #define DW_IC_FS_SCL_HCNT 0x1c
48 #define DW_IC_FS_SCL_LCNT 0x20
49 #define DW_IC_INTR_STAT 0x2c
50 #define DW_IC_INTR_MASK 0x30
51 #define DW_IC_RAW_INTR_STAT 0x34
52 #define DW_IC_RX_TL 0x38
53 #define DW_IC_TX_TL 0x3c
54 #define DW_IC_CLR_INTR 0x40
55 #define DW_IC_CLR_RX_UNDER 0x44
56 #define DW_IC_CLR_RX_OVER 0x48
57 #define DW_IC_CLR_TX_OVER 0x4c
58 #define DW_IC_CLR_RD_REQ 0x50
59 #define DW_IC_CLR_TX_ABRT 0x54
60 #define DW_IC_CLR_RX_DONE 0x58
61 #define DW_IC_CLR_ACTIVITY 0x5c
62 #define DW_IC_CLR_STOP_DET 0x60
63 #define DW_IC_CLR_START_DET 0x64
64 #define DW_IC_CLR_GEN_CALL 0x68
65 #define DW_IC_ENABLE 0x6c
66 #define DW_IC_STATUS 0x70
67 #define DW_IC_TXFLR 0x74
68 #define DW_IC_RXFLR 0x78
69 #define DW_IC_TX_ABRT_SOURCE 0x80
70 #define DW_IC_COMP_PARAM_1 0xf4
71 #define DW_IC_COMP_TYPE 0xfc
72 #define DW_IC_COMP_TYPE_VALUE 0x44570140
74 #define DW_IC_INTR_RX_UNDER 0x001
75 #define DW_IC_INTR_RX_OVER 0x002
76 #define DW_IC_INTR_RX_FULL 0x004
77 #define DW_IC_INTR_TX_OVER 0x008
78 #define DW_IC_INTR_TX_EMPTY 0x010
79 #define DW_IC_INTR_RD_REQ 0x020
80 #define DW_IC_INTR_TX_ABRT 0x040
81 #define DW_IC_INTR_RX_DONE 0x080
82 #define DW_IC_INTR_ACTIVITY 0x100
83 #define DW_IC_INTR_STOP_DET 0x200
84 #define DW_IC_INTR_START_DET 0x400
85 #define DW_IC_INTR_GEN_CALL 0x800
87 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
88 DW_IC_INTR_TX_EMPTY | \
89 DW_IC_INTR_TX_ABRT | \
92 #define DW_IC_STATUS_ACTIVITY 0x1
94 #define DW_IC_ERR_TX_ABRT 0x1
99 #define STATUS_IDLE 0x0
100 #define STATUS_WRITE_IN_PROGRESS 0x1
101 #define STATUS_READ_IN_PROGRESS 0x2
103 #define TIMEOUT 20 /* ms */
106 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
108 * only expected abort codes are listed here
109 * refer to the datasheet for the full list
111 #define ABRT_7B_ADDR_NOACK 0
112 #define ABRT_10ADDR1_NOACK 1
113 #define ABRT_10ADDR2_NOACK 2
114 #define ABRT_TXDATA_NOACK 3
115 #define ABRT_GCALL_NOACK 4
116 #define ABRT_GCALL_READ 5
117 #define ABRT_SBYTE_ACKDET 7
118 #define ABRT_SBYTE_NORSTRT 9
119 #define ABRT_10B_RD_NORSTRT 10
120 #define ABRT_MASTER_DIS 11
123 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
124 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
125 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
126 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
127 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
128 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
129 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
130 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
131 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
132 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
133 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
135 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
136 DW_IC_TX_ABRT_10ADDR1_NOACK | \
137 DW_IC_TX_ABRT_10ADDR2_NOACK | \
138 DW_IC_TX_ABRT_TXDATA_NOACK | \
139 DW_IC_TX_ABRT_GCALL_NOACK)
141 static char *abort_sources
[] = {
142 [ABRT_7B_ADDR_NOACK
] =
143 "slave address not acknowledged (7bit mode)",
144 [ABRT_10ADDR1_NOACK
] =
145 "first address byte not acknowledged (10bit mode)",
146 [ABRT_10ADDR2_NOACK
] =
147 "second address byte not acknowledged (10bit mode)",
148 [ABRT_TXDATA_NOACK
] =
149 "data not acknowledged",
151 "no acknowledgement for a general call",
153 "read after general call",
154 [ABRT_SBYTE_ACKDET
] =
155 "start byte acknowledged",
156 [ABRT_SBYTE_NORSTRT
] =
157 "trying to send start byte when restart is disabled",
158 [ABRT_10B_RD_NORSTRT
] =
159 "trying to read when restart is disabled (10bit mode)",
161 "trying to use disabled adapter",
166 u32
dw_readl(struct dw_i2c_dev
*dev
, int offset
)
170 if (dev
->accessor_flags
& ACCESS_16BIT
)
171 value
= readw(dev
->base
+ offset
) |
172 (readw(dev
->base
+ offset
+ 2) << 16);
174 value
= readl(dev
->base
+ offset
);
176 if (dev
->accessor_flags
& ACCESS_SWAP
)
177 return swab32(value
);
182 void dw_writel(struct dw_i2c_dev
*dev
, u32 b
, int offset
)
184 if (dev
->accessor_flags
& ACCESS_SWAP
)
187 if (dev
->accessor_flags
& ACCESS_16BIT
) {
188 writew((u16
)b
, dev
->base
+ offset
);
189 writew((u16
)(b
>> 16), dev
->base
+ offset
+ 2);
191 writel(b
, dev
->base
+ offset
);
196 i2c_dw_scl_hcnt(u32 ic_clk
, u32 tSYMBOL
, u32 tf
, int cond
, int offset
)
199 * DesignWare I2C core doesn't seem to have solid strategy to meet
200 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
201 * will result in violation of the tHD;STA spec.
205 * Conditional expression:
207 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
209 * This is based on the DW manuals, and represents an ideal
210 * configuration. The resulting I2C bus speed will be
211 * faster than any of the others.
213 * If your hardware is free from tHD;STA issue, try this one.
215 return (ic_clk
* tSYMBOL
+ 5000) / 10000 - 8 + offset
;
218 * Conditional expression:
220 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
222 * This is just experimental rule; the tHD;STA period turned
223 * out to be proportinal to (_HCNT + 3). With this setting,
224 * we could meet both tHIGH and tHD;STA timing specs.
226 * If unsure, you'd better to take this alternative.
228 * The reason why we need to take into account "tf" here,
229 * is the same as described in i2c_dw_scl_lcnt().
231 return (ic_clk
* (tSYMBOL
+ tf
) + 5000) / 10000 - 3 + offset
;
234 static u32
i2c_dw_scl_lcnt(u32 ic_clk
, u32 tLOW
, u32 tf
, int offset
)
237 * Conditional expression:
239 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
241 * DW I2C core starts counting the SCL CNTs for the LOW period
242 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
243 * In order to meet the tLOW timing spec, we need to take into
244 * account the fall time of SCL signal (tf). Default tf value
245 * should be 0.3 us, for safety.
247 return ((ic_clk
* (tLOW
+ tf
) + 5000) / 10000) - 1 + offset
;
251 * i2c_dw_init() - initialize the designware i2c master hardware
252 * @dev: device private data
254 * This functions configures and enables the I2C master.
255 * This function is called during I2C init function, and in case of timeout at
258 int i2c_dw_init(struct dw_i2c_dev
*dev
)
264 input_clock_khz
= dev
->get_clk_rate_khz(dev
);
266 reg
= dw_readl(dev
, DW_IC_COMP_TYPE
);
267 if (reg
== ___constant_swab32(DW_IC_COMP_TYPE_VALUE
)) {
268 /* Configure register endianess access */
269 dev
->accessor_flags
|= ACCESS_SWAP
;
270 } else if (reg
== (DW_IC_COMP_TYPE_VALUE
& 0x0000ffff)) {
271 /* Configure register access mode 16bit */
272 dev
->accessor_flags
|= ACCESS_16BIT
;
273 } else if (reg
!= DW_IC_COMP_TYPE_VALUE
) {
274 dev_err(dev
->dev
, "Unknown Synopsys component type: "
279 /* Disable the adapter */
280 dw_writel(dev
, 0, DW_IC_ENABLE
);
282 /* set standard and fast speed deviders for high/low periods */
285 hcnt
= i2c_dw_scl_hcnt(input_clock_khz
,
286 40, /* tHD;STA = tHIGH = 4.0 us */
288 0, /* 0: DW default, 1: Ideal */
290 lcnt
= i2c_dw_scl_lcnt(input_clock_khz
,
291 47, /* tLOW = 4.7 us */
294 dw_writel(dev
, hcnt
, DW_IC_SS_SCL_HCNT
);
295 dw_writel(dev
, lcnt
, DW_IC_SS_SCL_LCNT
);
296 dev_dbg(dev
->dev
, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt
, lcnt
);
299 hcnt
= i2c_dw_scl_hcnt(input_clock_khz
,
300 6, /* tHD;STA = tHIGH = 0.6 us */
302 0, /* 0: DW default, 1: Ideal */
304 lcnt
= i2c_dw_scl_lcnt(input_clock_khz
,
305 13, /* tLOW = 1.3 us */
308 dw_writel(dev
, hcnt
, DW_IC_FS_SCL_HCNT
);
309 dw_writel(dev
, lcnt
, DW_IC_FS_SCL_LCNT
);
310 dev_dbg(dev
->dev
, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt
, lcnt
);
312 /* Configure Tx/Rx FIFO threshold levels */
313 dw_writel(dev
, dev
->tx_fifo_depth
- 1, DW_IC_TX_TL
);
314 dw_writel(dev
, 0, DW_IC_RX_TL
);
316 /* configure the i2c master */
317 dw_writel(dev
, dev
->master_cfg
, DW_IC_CON
);
320 EXPORT_SYMBOL_GPL(i2c_dw_init
);
323 * Waiting for bus not busy
325 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev
*dev
)
327 int timeout
= TIMEOUT
;
329 while (dw_readl(dev
, DW_IC_STATUS
) & DW_IC_STATUS_ACTIVITY
) {
331 dev_warn(dev
->dev
, "timeout waiting for bus ready\n");
341 static void i2c_dw_xfer_init(struct dw_i2c_dev
*dev
)
343 struct i2c_msg
*msgs
= dev
->msgs
;
346 /* Disable the adapter */
347 dw_writel(dev
, 0, DW_IC_ENABLE
);
349 /* set the slave (target) address */
350 dw_writel(dev
, msgs
[dev
->msg_write_idx
].addr
, DW_IC_TAR
);
352 /* if the slave address is ten bit address, enable 10BITADDR */
353 ic_con
= dw_readl(dev
, DW_IC_CON
);
354 if (msgs
[dev
->msg_write_idx
].flags
& I2C_M_TEN
)
355 ic_con
|= DW_IC_CON_10BITADDR_MASTER
;
357 ic_con
&= ~DW_IC_CON_10BITADDR_MASTER
;
358 dw_writel(dev
, ic_con
, DW_IC_CON
);
360 /* Enable the adapter */
361 dw_writel(dev
, 1, DW_IC_ENABLE
);
363 /* Enable interrupts */
364 dw_writel(dev
, DW_IC_INTR_DEFAULT_MASK
, DW_IC_INTR_MASK
);
368 * Initiate (and continue) low level master read/write transaction.
369 * This function is only called from i2c_dw_isr, and pumping i2c_msg
370 * messages into the tx buffer. Even if the size of i2c_msg data is
371 * longer than the size of the tx buffer, it handles everything.
374 i2c_dw_xfer_msg(struct dw_i2c_dev
*dev
)
376 struct i2c_msg
*msgs
= dev
->msgs
;
378 int tx_limit
, rx_limit
;
379 u32 addr
= msgs
[dev
->msg_write_idx
].addr
;
380 u32 buf_len
= dev
->tx_buf_len
;
381 u8
*buf
= dev
->tx_buf
;
383 intr_mask
= DW_IC_INTR_DEFAULT_MASK
;
385 for (; dev
->msg_write_idx
< dev
->msgs_num
; dev
->msg_write_idx
++) {
387 * if target address has changed, we need to
388 * reprogram the target address in the i2c
389 * adapter when we are done with this transfer
391 if (msgs
[dev
->msg_write_idx
].addr
!= addr
) {
393 "%s: invalid target address\n", __func__
);
394 dev
->msg_err
= -EINVAL
;
398 if (msgs
[dev
->msg_write_idx
].len
== 0) {
400 "%s: invalid message length\n", __func__
);
401 dev
->msg_err
= -EINVAL
;
405 if (!(dev
->status
& STATUS_WRITE_IN_PROGRESS
)) {
407 buf
= msgs
[dev
->msg_write_idx
].buf
;
408 buf_len
= msgs
[dev
->msg_write_idx
].len
;
411 tx_limit
= dev
->tx_fifo_depth
- dw_readl(dev
, DW_IC_TXFLR
);
412 rx_limit
= dev
->rx_fifo_depth
- dw_readl(dev
, DW_IC_RXFLR
);
414 while (buf_len
> 0 && tx_limit
> 0 && rx_limit
> 0) {
415 if (msgs
[dev
->msg_write_idx
].flags
& I2C_M_RD
) {
416 dw_writel(dev
, 0x100, DW_IC_DATA_CMD
);
419 dw_writel(dev
, *buf
++, DW_IC_DATA_CMD
);
420 tx_limit
--; buf_len
--;
424 dev
->tx_buf_len
= buf_len
;
427 /* more bytes to be written */
428 dev
->status
|= STATUS_WRITE_IN_PROGRESS
;
431 dev
->status
&= ~STATUS_WRITE_IN_PROGRESS
;
435 * If i2c_msg index search is completed, we don't need TX_EMPTY
436 * interrupt any more.
438 if (dev
->msg_write_idx
== dev
->msgs_num
)
439 intr_mask
&= ~DW_IC_INTR_TX_EMPTY
;
444 dw_writel(dev
, intr_mask
, DW_IC_INTR_MASK
);
448 i2c_dw_read(struct dw_i2c_dev
*dev
)
450 struct i2c_msg
*msgs
= dev
->msgs
;
453 for (; dev
->msg_read_idx
< dev
->msgs_num
; dev
->msg_read_idx
++) {
457 if (!(msgs
[dev
->msg_read_idx
].flags
& I2C_M_RD
))
460 if (!(dev
->status
& STATUS_READ_IN_PROGRESS
)) {
461 len
= msgs
[dev
->msg_read_idx
].len
;
462 buf
= msgs
[dev
->msg_read_idx
].buf
;
464 len
= dev
->rx_buf_len
;
468 rx_valid
= dw_readl(dev
, DW_IC_RXFLR
);
470 for (; len
> 0 && rx_valid
> 0; len
--, rx_valid
--)
471 *buf
++ = dw_readl(dev
, DW_IC_DATA_CMD
);
474 dev
->status
|= STATUS_READ_IN_PROGRESS
;
475 dev
->rx_buf_len
= len
;
479 dev
->status
&= ~STATUS_READ_IN_PROGRESS
;
483 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev
*dev
)
485 unsigned long abort_source
= dev
->abort_source
;
488 if (abort_source
& DW_IC_TX_ABRT_NOACK
) {
489 for_each_set_bit(i
, &abort_source
, ARRAY_SIZE(abort_sources
))
491 "%s: %s\n", __func__
, abort_sources
[i
]);
495 for_each_set_bit(i
, &abort_source
, ARRAY_SIZE(abort_sources
))
496 dev_err(dev
->dev
, "%s: %s\n", __func__
, abort_sources
[i
]);
498 if (abort_source
& DW_IC_TX_ARB_LOST
)
500 else if (abort_source
& DW_IC_TX_ABRT_GCALL_READ
)
501 return -EINVAL
; /* wrong msgs[] data */
507 * Prepare controller for a transaction and call i2c_dw_xfer_msg
510 i2c_dw_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[], int num
)
512 struct dw_i2c_dev
*dev
= i2c_get_adapdata(adap
);
515 dev_dbg(dev
->dev
, "%s: msgs: %d\n", __func__
, num
);
517 mutex_lock(&dev
->lock
);
518 pm_runtime_get_sync(dev
->dev
);
520 INIT_COMPLETION(dev
->cmd_complete
);
524 dev
->msg_write_idx
= 0;
525 dev
->msg_read_idx
= 0;
527 dev
->status
= STATUS_IDLE
;
528 dev
->abort_source
= 0;
530 ret
= i2c_dw_wait_bus_not_busy(dev
);
534 /* start the transfers */
535 i2c_dw_xfer_init(dev
);
537 /* wait for tx to complete */
538 ret
= wait_for_completion_interruptible_timeout(&dev
->cmd_complete
, HZ
);
540 dev_err(dev
->dev
, "controller timed out\n");
553 if (likely(!dev
->cmd_err
)) {
554 /* Disable the adapter */
555 dw_writel(dev
, 0, DW_IC_ENABLE
);
560 /* We have an error */
561 if (dev
->cmd_err
== DW_IC_ERR_TX_ABRT
) {
562 ret
= i2c_dw_handle_tx_abort(dev
);
568 pm_runtime_put(dev
->dev
);
569 mutex_unlock(&dev
->lock
);
573 EXPORT_SYMBOL_GPL(i2c_dw_xfer
);
575 u32
i2c_dw_func(struct i2c_adapter
*adap
)
577 struct dw_i2c_dev
*dev
= i2c_get_adapdata(adap
);
578 return dev
->functionality
;
580 EXPORT_SYMBOL_GPL(i2c_dw_func
);
582 static u32
i2c_dw_read_clear_intrbits(struct dw_i2c_dev
*dev
)
587 * The IC_INTR_STAT register just indicates "enabled" interrupts.
588 * Ths unmasked raw version of interrupt status bits are available
589 * in the IC_RAW_INTR_STAT register.
592 * stat = dw_readl(IC_INTR_STAT);
594 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
596 * The raw version might be useful for debugging purposes.
598 stat
= dw_readl(dev
, DW_IC_INTR_STAT
);
601 * Do not use the IC_CLR_INTR register to clear interrupts, or
602 * you'll miss some interrupts, triggered during the period from
603 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
605 * Instead, use the separately-prepared IC_CLR_* registers.
607 if (stat
& DW_IC_INTR_RX_UNDER
)
608 dw_readl(dev
, DW_IC_CLR_RX_UNDER
);
609 if (stat
& DW_IC_INTR_RX_OVER
)
610 dw_readl(dev
, DW_IC_CLR_RX_OVER
);
611 if (stat
& DW_IC_INTR_TX_OVER
)
612 dw_readl(dev
, DW_IC_CLR_TX_OVER
);
613 if (stat
& DW_IC_INTR_RD_REQ
)
614 dw_readl(dev
, DW_IC_CLR_RD_REQ
);
615 if (stat
& DW_IC_INTR_TX_ABRT
) {
617 * The IC_TX_ABRT_SOURCE register is cleared whenever
618 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
620 dev
->abort_source
= dw_readl(dev
, DW_IC_TX_ABRT_SOURCE
);
621 dw_readl(dev
, DW_IC_CLR_TX_ABRT
);
623 if (stat
& DW_IC_INTR_RX_DONE
)
624 dw_readl(dev
, DW_IC_CLR_RX_DONE
);
625 if (stat
& DW_IC_INTR_ACTIVITY
)
626 dw_readl(dev
, DW_IC_CLR_ACTIVITY
);
627 if (stat
& DW_IC_INTR_STOP_DET
)
628 dw_readl(dev
, DW_IC_CLR_STOP_DET
);
629 if (stat
& DW_IC_INTR_START_DET
)
630 dw_readl(dev
, DW_IC_CLR_START_DET
);
631 if (stat
& DW_IC_INTR_GEN_CALL
)
632 dw_readl(dev
, DW_IC_CLR_GEN_CALL
);
638 * Interrupt service routine. This gets called whenever an I2C interrupt
641 irqreturn_t
i2c_dw_isr(int this_irq
, void *dev_id
)
643 struct dw_i2c_dev
*dev
= dev_id
;
646 enabled
= dw_readl(dev
, DW_IC_ENABLE
);
647 stat
= dw_readl(dev
, DW_IC_RAW_INTR_STAT
);
648 dev_dbg(dev
->dev
, "%s: %s enabled= 0x%x stat=0x%x\n", __func__
,
649 dev
->adapter
.name
, enabled
, stat
);
650 if (!enabled
|| !(stat
& ~DW_IC_INTR_ACTIVITY
))
653 stat
= i2c_dw_read_clear_intrbits(dev
);
655 if (stat
& DW_IC_INTR_TX_ABRT
) {
656 dev
->cmd_err
|= DW_IC_ERR_TX_ABRT
;
657 dev
->status
= STATUS_IDLE
;
660 * Anytime TX_ABRT is set, the contents of the tx/rx
661 * buffers are flushed. Make sure to skip them.
663 dw_writel(dev
, 0, DW_IC_INTR_MASK
);
667 if (stat
& DW_IC_INTR_RX_FULL
)
670 if (stat
& DW_IC_INTR_TX_EMPTY
)
671 i2c_dw_xfer_msg(dev
);
674 * No need to modify or disable the interrupt mask here.
675 * i2c_dw_xfer_msg() will take care of it according to
676 * the current transmit status.
680 if ((stat
& (DW_IC_INTR_TX_ABRT
| DW_IC_INTR_STOP_DET
)) || dev
->msg_err
)
681 complete(&dev
->cmd_complete
);
685 EXPORT_SYMBOL_GPL(i2c_dw_isr
);
687 void i2c_dw_enable(struct dw_i2c_dev
*dev
)
689 /* Enable the adapter */
690 dw_writel(dev
, 1, DW_IC_ENABLE
);
692 EXPORT_SYMBOL_GPL(i2c_dw_enable
);
694 u32
i2c_dw_is_enabled(struct dw_i2c_dev
*dev
)
696 return dw_readl(dev
, DW_IC_ENABLE
);
698 EXPORT_SYMBOL_GPL(i2c_dw_is_enabled
);
700 void i2c_dw_disable(struct dw_i2c_dev
*dev
)
702 /* Disable controller */
703 dw_writel(dev
, 0, DW_IC_ENABLE
);
705 /* Disable all interupts */
706 dw_writel(dev
, 0, DW_IC_INTR_MASK
);
707 dw_readl(dev
, DW_IC_CLR_INTR
);
709 EXPORT_SYMBOL_GPL(i2c_dw_disable
);
711 void i2c_dw_clear_int(struct dw_i2c_dev
*dev
)
713 dw_readl(dev
, DW_IC_CLR_INTR
);
715 EXPORT_SYMBOL_GPL(i2c_dw_clear_int
);
717 void i2c_dw_disable_int(struct dw_i2c_dev
*dev
)
719 dw_writel(dev
, 0, DW_IC_INTR_MASK
);
721 EXPORT_SYMBOL_GPL(i2c_dw_disable_int
);
723 u32
i2c_dw_read_comp_param(struct dw_i2c_dev
*dev
)
725 return dw_readl(dev
, DW_IC_COMP_PARAM_1
);
727 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param
);