2 * OMAP3xxx PRM module functions
4 * Copyright (C) 2010-2012 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
8 * Rajendra Nayak <rnayak@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
19 #include <linux/irq.h>
23 #include <plat/prcm.h>
26 #include "powerdomain.h"
28 #include "prm2xxx_3xxx.h"
29 #include "cm2xxx_3xxx.h"
30 #include "prm-regbits-34xx.h"
32 static const struct omap_prcm_irq omap3_prcm_irqs
[] = {
33 OMAP_PRCM_IRQ("wkup", 0, 0),
34 OMAP_PRCM_IRQ("io", 9, 1),
37 static struct omap_prcm_irq_setup omap3_prcm_irq_setup
= {
38 .ack
= OMAP3_PRM_IRQSTATUS_MPU_OFFSET
,
39 .mask
= OMAP3_PRM_IRQENABLE_MPU_OFFSET
,
41 .irqs
= omap3_prcm_irqs
,
42 .nr_irqs
= ARRAY_SIZE(omap3_prcm_irqs
),
43 .irq
= 11 + OMAP_INTC_START
,
44 .read_pending_irqs
= &omap3xxx_prm_read_pending_irqs
,
45 .ocp_barrier
= &omap3xxx_prm_ocp_barrier
,
46 .save_and_clear_irqen
= &omap3xxx_prm_save_and_clear_irqen
,
47 .restore_irqen
= &omap3xxx_prm_restore_irqen
,
51 * omap3_prm_reset_src_map - map from bits in the PRM_RSTST hardware
52 * register (which are specific to OMAP3xxx SoCs) to reset source ID
53 * bit shifts (which is an OMAP SoC-independent enumeration)
55 static struct prm_reset_src_map omap3xxx_prm_reset_src_map
[] = {
56 { OMAP3430_GLOBAL_COLD_RST_SHIFT
, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT
},
57 { OMAP3430_GLOBAL_SW_RST_SHIFT
, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT
},
58 { OMAP3430_SECURITY_VIOL_RST_SHIFT
, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT
},
59 { OMAP3430_MPU_WD_RST_SHIFT
, OMAP_MPU_WD_RST_SRC_ID_SHIFT
},
60 { OMAP3430_SECURE_WD_RST_SHIFT
, OMAP_MPU_WD_RST_SRC_ID_SHIFT
},
61 { OMAP3430_EXTERNAL_WARM_RST_SHIFT
, OMAP_EXTWARM_RST_SRC_ID_SHIFT
},
62 { OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT
,
63 OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT
},
64 { OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT
,
65 OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT
},
66 { OMAP3430_ICEPICK_RST_SHIFT
, OMAP_ICEPICK_RST_SRC_ID_SHIFT
},
67 { OMAP3430_ICECRUSHER_RST_SHIFT
, OMAP_ICECRUSHER_RST_SRC_ID_SHIFT
},
74 * struct omap3_vp - OMAP3 VP register access description.
75 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
81 static struct omap3_vp omap3_vp
[] = {
82 [OMAP3_VP_VDD_MPU_ID
] = {
83 .tranxdone_status
= OMAP3430_VP1_TRANXDONE_ST_MASK
,
85 [OMAP3_VP_VDD_CORE_ID
] = {
86 .tranxdone_status
= OMAP3430_VP2_TRANXDONE_ST_MASK
,
90 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
92 u32
omap3_prm_vp_check_txdone(u8 vp_id
)
94 struct omap3_vp
*vp
= &omap3_vp
[vp_id
];
97 irqstatus
= omap2_prm_read_mod_reg(OCP_MOD
,
98 OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
99 return irqstatus
& vp
->tranxdone_status
;
102 void omap3_prm_vp_clear_txdone(u8 vp_id
)
104 struct omap3_vp
*vp
= &omap3_vp
[vp_id
];
106 omap2_prm_write_mod_reg(vp
->tranxdone_status
,
107 OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
110 u32
omap3_prm_vcvp_read(u8 offset
)
112 return omap2_prm_read_mod_reg(OMAP3430_GR_MOD
, offset
);
115 void omap3_prm_vcvp_write(u32 val
, u8 offset
)
117 omap2_prm_write_mod_reg(val
, OMAP3430_GR_MOD
, offset
);
120 u32
omap3_prm_vcvp_rmw(u32 mask
, u32 bits
, u8 offset
)
122 return omap2_prm_rmw_mod_reg_bits(mask
, bits
, OMAP3430_GR_MOD
, offset
);
126 * omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC
128 * Set the DPLL3 reset bit, which should reboot the SoC. This is the
129 * recommended way to restart the SoC, considering Errata i520. No
132 void omap3xxx_prm_dpll3_reset(void)
134 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK
, OMAP3430_GR_MOD
,
137 omap2_prm_read_mod_reg(OMAP3430_GR_MOD
, OMAP2_RM_RSTCTRL
);
141 * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
142 * @events: ptr to a u32, preallocated by caller
144 * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
145 * MPU IRQs, and store the result into the u32 pointed to by @events.
148 void omap3xxx_prm_read_pending_irqs(unsigned long *events
)
152 /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
153 mask
= omap2_prm_read_mod_reg(OCP_MOD
, OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
154 st
= omap2_prm_read_mod_reg(OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
156 events
[0] = mask
& st
;
160 * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
162 * Force any buffered writes to the PRM IP block to complete. Needed
163 * by the PRM IRQ handler, which reads and writes directly to the IP
164 * block, to avoid race conditions after acknowledging or clearing IRQ
165 * bits. No return value.
167 void omap3xxx_prm_ocp_barrier(void)
169 omap2_prm_read_mod_reg(OCP_MOD
, OMAP3_PRM_REVISION_OFFSET
);
173 * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
174 * @saved_mask: ptr to a u32 array to save IRQENABLE bits
176 * Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask
177 * must be allocated by the caller. Intended to be used in the PRM
178 * interrupt handler suspend callback. The OCP barrier is needed to
179 * ensure the write to disable PRM interrupts reaches the PRM before
180 * returning; otherwise, spurious interrupts might occur. No return
183 void omap3xxx_prm_save_and_clear_irqen(u32
*saved_mask
)
185 saved_mask
[0] = omap2_prm_read_mod_reg(OCP_MOD
,
186 OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
187 omap2_prm_write_mod_reg(0, OCP_MOD
, OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
190 omap2_prm_read_mod_reg(OCP_MOD
, OMAP3_PRM_REVISION_OFFSET
);
194 * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
195 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
197 * Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended
198 * to be used in the PRM interrupt handler resume callback to restore
199 * values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP
200 * barrier should be needed here; any pending PRM interrupts will fire
201 * once the writes reach the PRM. No return value.
203 void omap3xxx_prm_restore_irqen(u32
*saved_mask
)
205 omap2_prm_write_mod_reg(saved_mask
[0], OCP_MOD
,
206 OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
210 * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
212 * Clear any previously-latched I/O wakeup events and ensure that the
213 * I/O wakeup gates are aligned with the current mux settings. Works
214 * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
215 * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No
218 void omap3xxx_prm_reconfigure_io_chain(void)
222 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK
, WKUP_MOD
,
225 omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD
, PM_WKST
) &
226 OMAP3430_ST_IO_CHAIN_MASK
,
227 MAX_IOPAD_LATCH_TIME
, i
);
228 if (i
== MAX_IOPAD_LATCH_TIME
)
229 pr_warn("PRM: I/O chain clock line assertion timed out\n");
231 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK
, WKUP_MOD
,
234 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK
, WKUP_MOD
,
237 omap2_prm_read_mod_reg(WKUP_MOD
, PM_WKST
);
241 * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
243 * Activates the I/O wakeup event latches and allows events logged by
244 * those latches to signal a wakeup event to the PRCM. For I/O
245 * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
246 * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
249 static void __init
omap3xxx_prm_enable_io_wakeup(void)
251 if (omap3_has_io_wakeup())
252 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK
, WKUP_MOD
,
257 * omap3xxx_prm_read_reset_sources - return the last SoC reset source
259 * Return a u32 representing the last reset sources of the SoC. The
260 * returned reset source bits are standardized across OMAP SoCs.
262 static u32
omap3xxx_prm_read_reset_sources(void)
264 struct prm_reset_src_map
*p
;
268 v
= omap2_prm_read_mod_reg(WKUP_MOD
, OMAP2_RM_RSTST
);
270 p
= omap3xxx_prm_reset_src_map
;
271 while (p
->reg_shift
>= 0 && p
->std_shift
>= 0) {
272 if (v
& (1 << p
->reg_shift
))
273 r
|= 1 << p
->std_shift
;
280 /* Powerdomain low-level functions */
282 /* Applicable only for OMAP3. Not supported on OMAP2 */
283 static int omap3_pwrdm_read_prev_pwrst(struct powerdomain
*pwrdm
)
285 return omap2_prm_read_mod_bits_shift(pwrdm
->prcm_offs
,
286 OMAP3430_PM_PREPWSTST
,
287 OMAP3430_LASTPOWERSTATEENTERED_MASK
);
290 static int omap3_pwrdm_read_logic_pwrst(struct powerdomain
*pwrdm
)
292 return omap2_prm_read_mod_bits_shift(pwrdm
->prcm_offs
,
294 OMAP3430_LOGICSTATEST_MASK
);
297 static int omap3_pwrdm_read_logic_retst(struct powerdomain
*pwrdm
)
299 return omap2_prm_read_mod_bits_shift(pwrdm
->prcm_offs
,
301 OMAP3430_LOGICSTATEST_MASK
);
304 static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain
*pwrdm
)
306 return omap2_prm_read_mod_bits_shift(pwrdm
->prcm_offs
,
307 OMAP3430_PM_PREPWSTST
,
308 OMAP3430_LASTLOGICSTATEENTERED_MASK
);
311 static int omap3_get_mem_bank_lastmemst_mask(u8 bank
)
315 return OMAP3430_LASTMEM1STATEENTERED_MASK
;
317 return OMAP3430_LASTMEM2STATEENTERED_MASK
;
319 return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK
;
321 return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK
;
323 WARN_ON(1); /* should never happen */
329 static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain
*pwrdm
, u8 bank
)
333 m
= omap3_get_mem_bank_lastmemst_mask(bank
);
335 return omap2_prm_read_mod_bits_shift(pwrdm
->prcm_offs
,
336 OMAP3430_PM_PREPWSTST
, m
);
339 static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain
*pwrdm
)
341 omap2_prm_write_mod_reg(0, pwrdm
->prcm_offs
, OMAP3430_PM_PREPWSTST
);
345 static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain
*pwrdm
)
347 return omap2_prm_rmw_mod_reg_bits(0,
348 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT
,
349 pwrdm
->prcm_offs
, OMAP2_PM_PWSTCTRL
);
352 static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain
*pwrdm
)
354 return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT
,
359 struct pwrdm_ops omap3_pwrdm_operations
= {
360 .pwrdm_set_next_pwrst
= omap2_pwrdm_set_next_pwrst
,
361 .pwrdm_read_next_pwrst
= omap2_pwrdm_read_next_pwrst
,
362 .pwrdm_read_pwrst
= omap2_pwrdm_read_pwrst
,
363 .pwrdm_read_prev_pwrst
= omap3_pwrdm_read_prev_pwrst
,
364 .pwrdm_set_logic_retst
= omap2_pwrdm_set_logic_retst
,
365 .pwrdm_read_logic_pwrst
= omap3_pwrdm_read_logic_pwrst
,
366 .pwrdm_read_logic_retst
= omap3_pwrdm_read_logic_retst
,
367 .pwrdm_read_prev_logic_pwrst
= omap3_pwrdm_read_prev_logic_pwrst
,
368 .pwrdm_set_mem_onst
= omap2_pwrdm_set_mem_onst
,
369 .pwrdm_set_mem_retst
= omap2_pwrdm_set_mem_retst
,
370 .pwrdm_read_mem_pwrst
= omap2_pwrdm_read_mem_pwrst
,
371 .pwrdm_read_mem_retst
= omap2_pwrdm_read_mem_retst
,
372 .pwrdm_read_prev_mem_pwrst
= omap3_pwrdm_read_prev_mem_pwrst
,
373 .pwrdm_clear_all_prev_pwrst
= omap3_pwrdm_clear_all_prev_pwrst
,
374 .pwrdm_enable_hdwr_sar
= omap3_pwrdm_enable_hdwr_sar
,
375 .pwrdm_disable_hdwr_sar
= omap3_pwrdm_disable_hdwr_sar
,
376 .pwrdm_wait_transition
= omap2_pwrdm_wait_transition
,
383 static struct prm_ll_data omap3xxx_prm_ll_data
= {
384 .read_reset_sources
= &omap3xxx_prm_read_reset_sources
,
387 static int __init
omap3xxx_prm_init(void)
391 if (!cpu_is_omap34xx())
394 ret
= prm_register(&omap3xxx_prm_ll_data
);
398 omap3xxx_prm_enable_io_wakeup();
399 ret
= omap_prcm_register_chain_handler(&omap3_prcm_irq_setup
);
401 irq_set_status_flags(omap_prcm_event_to_irq("io"),
407 subsys_initcall(omap3xxx_prm_init
);
409 static void __exit
omap3xxx_prm_exit(void)
411 if (!cpu_is_omap34xx())
414 /* Should never happen */
415 WARN(prm_unregister(&omap3xxx_prm_ll_data
),
416 "%s: prm_ll_data function pointer mismatch\n", __func__
);
418 __exitcall(omap3xxx_prm_exit
);