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OMAPDSS: HDMI5: use common AVI infoframe support
[linux-2.6/btrfs-unstable.git] / drivers / video / fbdev / omap2 / dss / hdmi5_core.c
blobd46cb13b06bfd5561d362ee1f59a4cc05b0d7298
1 /*
2 * OMAP5 HDMI CORE IP driver library
3 *
4 * Copyright (C) 2014 Texas Instruments Incorporated
5 *
6 * Authors:
7 * Yong Zhi
8 * Mythri pk
9 * Archit Taneja <archit@ti.com>
10 * Tomi Valkeinen <tomi.valkeinen@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published by
14 * the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program. If not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/err.h>
28 #include <linux/io.h>
29 #include <linux/delay.h>
30 #include <linux/string.h>
31 #include <linux/seq_file.h>
32 #include <drm/drm_edid.h>
33 #if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
34 #include <sound/asound.h>
35 #include <sound/asoundef.h>
36 #endif
37
38 #include "hdmi5_core.h"
39
40 /* only 24 bit color depth used for now */
41 static const struct csc_table csc_table_deepcolor[] = {
42 /* HDMI_DEEP_COLOR_24BIT */
43 [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
44 /* HDMI_DEEP_COLOR_30BIT */
45 [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
46 /* HDMI_DEEP_COLOR_36BIT */
47 [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
48 /* FULL RANGE */
49 [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
50 };
51
52 static void hdmi_core_ddc_init(struct hdmi_core_data *core)
53 {
54 void __iomem *base = core->base;
55 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
56 const unsigned ss_scl_high = 4000; /* ns */
57 const unsigned ss_scl_low = 4700; /* ns */
58 const unsigned fs_scl_high = 600; /* ns */
59 const unsigned fs_scl_low = 1300; /* ns */
60 const unsigned sda_hold = 300; /* ns */
61 const unsigned sfr_div = 10;
62 unsigned long long sfr;
63 unsigned v;
64
65 sfr = iclk / sfr_div; /* SFR_DIV */
66 sfr /= 1000; /* SFR clock in kHz */
67
68 /* Reset */
69 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
70 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
71 0, 0, 1) != 1)
72 DSSERR("HDMI I2CM reset failed\n");
73
74 /* Standard (0) or Fast (1) Mode */
75 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
76
77 /* Standard Mode SCL High counter */
78 v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
79 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
80 (v >> 8) & 0xff, 7, 0);
81 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
82 v & 0xff, 7, 0);
83
84 /* Standard Mode SCL Low counter */
85 v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
86 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
87 (v >> 8) & 0xff, 7, 0);
88 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
89 v & 0xff, 7, 0);
90
91 /* Fast Mode SCL High Counter */
92 v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
93 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
94 (v >> 8) & 0xff, 7, 0);
95 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
96 v & 0xff, 7, 0);
97
98 /* Fast Mode SCL Low Counter */
99 v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
100 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
101 (v >> 8) & 0xff, 7, 0);
102 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
103 v & 0xff, 7, 0);
104
105 /* SDA Hold Time */
106 v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
107 REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
108
109 REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
110 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
111
112 /* NACK_POL to high */
113 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
114
115 /* NACK_MASK to unmasked */
116 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
117
118 /* ARBITRATION_POL to high */
119 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
120
121 /* ARBITRATION_MASK to unmasked */
122 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
123
124 /* DONE_POL to high */
125 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
126
127 /* DONE_MASK to unmasked */
128 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
129 }
130
131 static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
132 {
133 void __iomem *base = core->base;
134
135 /* Mask I2C interrupts */
136 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
137 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
138 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
139 }
140
141 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
142 {
143 void __iomem *base = core->base;
144 u8 cur_addr;
145 char checksum = 0;
146 const int retries = 1000;
147 u8 seg_ptr = ext / 2;
148 u8 edidbase = ((ext % 2) * 0x80);
149
150 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
151
152 /*
153 * TODO: We use polling here, although we probably should use proper
154 * interrupts.
155 */
156 for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
157 int i;
158
159 /* clear ERROR and DONE */
160 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
161
162 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
163 edidbase + cur_addr, 7, 0);
164
165 if (seg_ptr)
166 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
167 else
168 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
169
170 for (i = 0; i < retries; ++i) {
171 u32 stat;
172
173 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
174
175 /* I2CM_ERROR */
176 if (stat & 1) {
177 DSSERR("HDMI I2C Master Error\n");
178 return -EIO;
179 }
180
181 /* I2CM_DONE */
182 if (stat & (1 << 1))
183 break;
184
185 usleep_range(250, 1000);
186 }
187
188 if (i == retries) {
189 DSSERR("HDMI I2C timeout reading EDID\n");
190 return -EIO;
191 }
192
193 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
194 checksum += pedid[cur_addr];
195 }
196
197 return 0;
198
199 }
200
201 int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
202 {
203 int r, n, i;
204 int max_ext_blocks = (len / 128) - 1;
205
206 if (len < 128)
207 return -EINVAL;
208
209 hdmi_core_ddc_init(core);
210
211 r = hdmi_core_ddc_edid(core, edid, 0);
212 if (r)
213 goto out;
214
215 n = edid[0x7e];
216
217 if (n > max_ext_blocks)
218 n = max_ext_blocks;
219
220 for (i = 1; i <= n; i++) {
221 r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
222 if (r)
223 goto out;
224 }
225
226 out:
227 hdmi_core_ddc_uninit(core);
228
229 return r ? r : len;
230 }
231
232 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
233 {
234
235 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
236 hdmi_read_reg(core->base, r))
237
238 DUMPCORE(HDMI_CORE_FC_INVIDCONF);
239 DUMPCORE(HDMI_CORE_FC_INHACTIV0);
240 DUMPCORE(HDMI_CORE_FC_INHACTIV1);
241 DUMPCORE(HDMI_CORE_FC_INHBLANK0);
242 DUMPCORE(HDMI_CORE_FC_INHBLANK1);
243 DUMPCORE(HDMI_CORE_FC_INVACTIV0);
244 DUMPCORE(HDMI_CORE_FC_INVACTIV1);
245 DUMPCORE(HDMI_CORE_FC_INVBLANK);
246 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
247 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
248 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
249 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
250 DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
251 DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
252 DUMPCORE(HDMI_CORE_FC_CTRLDUR);
253 DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
254 DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
255 DUMPCORE(HDMI_CORE_FC_CH0PREAM);
256 DUMPCORE(HDMI_CORE_FC_CH1PREAM);
257 DUMPCORE(HDMI_CORE_FC_CH2PREAM);
258 DUMPCORE(HDMI_CORE_FC_AVICONF0);
259 DUMPCORE(HDMI_CORE_FC_AVICONF1);
260 DUMPCORE(HDMI_CORE_FC_AVICONF2);
261 DUMPCORE(HDMI_CORE_FC_AVIVID);
262 DUMPCORE(HDMI_CORE_FC_PRCONF);
263
264 DUMPCORE(HDMI_CORE_MC_CLKDIS);
265 DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
266 DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
267 DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
268 DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
269
270 DUMPCORE(HDMI_CORE_I2CM_SLAVE);
271 DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
272 DUMPCORE(HDMI_CORE_I2CM_DATAO);
273 DUMPCORE(HDMI_CORE_I2CM_DATAI);
274 DUMPCORE(HDMI_CORE_I2CM_OPERATION);
275 DUMPCORE(HDMI_CORE_I2CM_INT);
276 DUMPCORE(HDMI_CORE_I2CM_CTLINT);
277 DUMPCORE(HDMI_CORE_I2CM_DIV);
278 DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
279 DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
280 DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
281 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
282 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
283 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
284 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
285 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
286 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
287 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
288 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
289 DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
290 }
291
292 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
293 struct hdmi_config *cfg)
294 {
295 DSSDBG("hdmi_core_init\n");
296
297 /* video core */
298 video_cfg->data_enable_pol = 1; /* It is always 1*/
299 video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level;
300 video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res;
301 video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1;
302 video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp;
303 video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp;
304 video_cfg->hblank = cfg->timings.hfp +
305 cfg->timings.hbp + cfg->timings.hsw - 1;
306 video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level;
307 video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res;
308 video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw;
309 video_cfg->v_fc_config.timings.vfp = cfg->timings.vfp;
310 video_cfg->v_fc_config.timings.vbp = cfg->timings.vbp;
311 video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */
312 video_cfg->vblank = cfg->timings.vsw +
313 cfg->timings.vfp + cfg->timings.vbp;
314 video_cfg->v_fc_config.cm.mode = cfg->cm.mode;
315 video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace;
316 }
317
318 /* DSS_HDMI_CORE_VIDEO_CONFIG */
319 static void hdmi_core_video_config(struct hdmi_core_data *core,
320 struct hdmi_core_vid_config *cfg)
321 {
322 void __iomem *base = core->base;
323 unsigned char r = 0;
324 bool vsync_pol, hsync_pol;
325
326 vsync_pol =
327 cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
328 hsync_pol =
329 cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
330
331 /* Set hsync, vsync and data-enable polarity */
332 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
333 r = FLD_MOD(r, vsync_pol, 6, 6);
334 r = FLD_MOD(r, hsync_pol, 5, 5);
335 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
336 r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
337 r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0);
338 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
339
340 /* set x resolution */
341 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1,
342 cfg->v_fc_config.timings.x_res >> 8, 4, 0);
343 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0,
344 cfg->v_fc_config.timings.x_res & 0xFF, 7, 0);
345
346 /* set y resolution */
347 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1,
348 cfg->v_fc_config.timings.y_res >> 8, 4, 0);
349 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0,
350 cfg->v_fc_config.timings.y_res & 0xFF, 7, 0);
351
352 /* set horizontal blanking pixels */
353 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
354 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
355
356 /* set vertial blanking pixels */
357 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
358
359 /* set horizontal sync offset */
360 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1,
361 cfg->v_fc_config.timings.hfp >> 8, 4, 0);
362 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0,
363 cfg->v_fc_config.timings.hfp & 0xFF, 7, 0);
364
365 /* set vertical sync offset */
366 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY,
367 cfg->v_fc_config.timings.vfp, 7, 0);
368
369 /* set horizontal sync pulse width */
370 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1,
371 (cfg->v_fc_config.timings.hsw >> 8), 1, 0);
372 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0,
373 cfg->v_fc_config.timings.hsw & 0xFF, 7, 0);
374
375 /* set vertical sync pulse width */
376 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
377 cfg->v_fc_config.timings.vsw, 5, 0);
378
379 /* select DVI mode */
380 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
381 cfg->v_fc_config.cm.mode, 3, 3);
382 }
383
384 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
385 {
386 void __iomem *base = core->base;
387 int clr_depth = 0; /* 24 bit color depth */
388
389 /* COLOR_DEPTH */
390 REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
391 /* BYPASS_EN */
392 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
393 /* PP_EN */
394 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
395 /* YCC422_EN */
396 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
397 /* PP_STUFFING */
398 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
399 /* YCC422_STUFFING */
400 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
401 /* OUTPUT_SELECTOR */
402 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
403 }
404
405 static void hdmi_core_config_csc(struct hdmi_core_data *core)
406 {
407 int clr_depth = 0; /* 24 bit color depth */
408
409 /* CSC_COLORDEPTH */
410 REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
411 }
412
413 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
414 {
415 int video_mapping = 1; /* for 24 bit color depth */
416
417 /* VIDEO_MAPPING */
418 REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
419 }
420
421 static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core)
422 {
423 struct hdmi_avi_infoframe *frame = &core->avi_infoframe;
424 void __iomem *base = core->base;
425 u8 data[HDMI_INFOFRAME_SIZE(AVI)];
426 u8 *ptr;
427 unsigned y, a, b, s;
428 unsigned c, m, r;
429 unsigned itc, ec, q, sc;
430 unsigned vic;
431 unsigned yq, cn, pr;
432
433 hdmi_avi_infoframe_pack(frame, data, sizeof(data));
434
435 ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
436
437 y = (ptr[0] >> 5) & 0x3;
438 a = (ptr[0] >> 4) & 0x1;
439 b = (ptr[0] >> 2) & 0x3;
440 s = (ptr[0] >> 0) & 0x3;
441
442 c = (ptr[1] >> 6) & 0x3;
443 m = (ptr[1] >> 4) & 0x3;
444 r = (ptr[1] >> 0) & 0x3;
445
446 itc = (ptr[2] >> 7) & 0x1;
447 ec = (ptr[2] >> 4) & 0x7;
448 q = (ptr[2] >> 2) & 0x3;
449 sc = (ptr[2] >> 0) & 0x3;
450
451 vic = ptr[3];
452
453 yq = (ptr[4] >> 6) & 0x3;
454 cn = (ptr[4] >> 4) & 0x3;
455 pr = (ptr[4] >> 0) & 0xf;
456
457 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
458 (a << 6) | (s << 4) | (b << 2) | (y << 0));
459
460 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
461 (c << 6) | (m << 4) | (r << 0));
462
463 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
464 (itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
465
466 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
467
468 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
469 (yq << 2) | (cn << 0));
470
471 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
472 }
473
474 static void hdmi_core_csc_config(struct hdmi_core_data *core,
475 struct csc_table csc_coeff)
476 {
477 void __iomem *base = core->base;
478
479 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
480 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
481 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
482 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
483 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
484 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
485 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
486 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
487 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
488 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
489 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
490 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
491 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
492 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
493 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
494 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
495 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
496 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
497 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
498 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
499 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
500 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
501 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
502 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
503
504 REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
505 }
506
507 static void hdmi_core_configure_range(struct hdmi_core_data *core)
508 {
509 struct csc_table csc_coeff = { 0 };
510
511 /* support limited range with 24 bit color depth for now */
512 csc_coeff = csc_table_deepcolor[0];
513 core->avi_infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
514
515 hdmi_core_csc_config(core, csc_coeff);
516 hdmi_core_aux_infoframe_avi_config(core);
517 }
518
519 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
520 {
521 void __iomem *base = core->base;
522
523 DSSDBG("hdmi_core_enable_video_path\n");
524
525 REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
526 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
527 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
528 REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
529 REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
530 REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
531 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
532 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
533 }
534
535 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
536 {
537 void __iomem *base = core->base;
538
539 /* Master IRQ mask */
540 REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
541
542 /* Mask all the interrupts in HDMI core */
543
544 REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
545 REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
546 REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
547 REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
548
549 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
550 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
551
552 REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
553
554 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
555 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
556 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
557
558 REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
559
560 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
561
562 /* Clear all the current interrupt bits */
563
564 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
565 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
566 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
567 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
568
569 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
570
571 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
572
573 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
574
575 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
576 }
577
578 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
579 {
580 /* Unmute interrupts */
581 REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
582 }
583
584 int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
585 {
586 void __iomem *base = core->base;
587
588 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
589 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
590 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
591 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
592 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
593 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
594 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
595 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
596 REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
597
598 return 0;
599 }
600
601 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
602 struct hdmi_config *cfg)
603 {
604 struct omap_video_timings video_timing;
605 struct hdmi_video_format video_format;
606 struct hdmi_core_vid_config v_core_cfg;
607 struct hdmi_avi_infoframe *avi_infoframe = &core->avi_infoframe;
608
609 hdmi_core_mask_interrupts(core);
610
611 hdmi_core_init(&v_core_cfg, cfg);
612
613 hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
614
615 hdmi_wp_video_config_timing(wp, &video_timing);
616
617 /* video config */
618 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
619
620 hdmi_wp_video_config_format(wp, &video_format);
621
622 hdmi_wp_video_config_interface(wp, &video_timing);
623
624 hdmi_core_configure_range(core);
625
626 /*
627 * configure core video part, set software reset in the core
628 */
629 v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
630
631 hdmi_core_video_config(core, &v_core_cfg);
632
633 hdmi_core_config_video_packetizer(core);
634 hdmi_core_config_csc(core);
635 hdmi_core_config_video_sampler(core);
636
637 /*
638 * configure packet info frame video see doc CEA861-D page 65
639 */
640 hdmi_avi_infoframe_init(avi_infoframe);
641 avi_infoframe->colorspace = HDMI_COLORSPACE_RGB;
642 avi_infoframe->scan_mode = HDMI_SCAN_MODE_NONE;
643 avi_infoframe->colorimetry = HDMI_COLORIMETRY_NONE;
644 avi_infoframe->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
645 avi_infoframe->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
646 avi_infoframe->itc = 0;
647 avi_infoframe->extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
648 avi_infoframe->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
649 avi_infoframe->nups = HDMI_NUPS_UNKNOWN;
650 avi_infoframe->video_code = cfg->cm.code;
651 avi_infoframe->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
652 avi_infoframe->content_type = HDMI_CONTENT_TYPE_NONE;
653 avi_infoframe->pixel_repeat = 0;
654 hdmi_core_aux_infoframe_avi_config(core);
655
656 hdmi_core_enable_video_path(core);
657
658 hdmi_core_enable_interrupts(core);
659 }
660
661
662 #if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
663
664 static void hdmi5_core_audio_config(struct hdmi_core_data *core,
665 struct hdmi_core_audio_config *cfg)
666 {
667 void __iomem *base = core->base;
668 u8 val;
669
670 /* Mute audio before configuring */
671 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
672
673 /* Set the N parameter */
674 REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
675 REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
676 REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
677
678 /*
679 * CTS manual mode. Automatic mode is not supported when using audio
680 * parallel interface.
681 */
682 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
683 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
684 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
685 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
686
687 /* Layout of Audio Sample Packets: 2-channel or multichannels */
688 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
689 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
690 else
691 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
692
693 /* Configure IEC-609580 Validity bits */
694 /* Channel 0 is valid */
695 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
696 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
697
698 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
699 val = 1;
700 else
701 val = 0;
702
703 /* Channels 1, 2 setting */
704 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
705 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
706 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
707 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
708 /* Channel 3 setting */
709 if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
710 val = 1;
711 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
712 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
713
714 /* Configure IEC-60958 User bits */
715 /* TODO: should be set by user. */
716 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
717
718 /* Configure IEC-60958 Channel Status word */
719 /* CGMSA */
720 val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
721 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
722
723 /* Copyright */
724 val = (cfg->iec60958_cfg->status[0] &
725 IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
726 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
727
728 /* Category */
729 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
730 cfg->iec60958_cfg->status[1]);
731
732 /* PCM audio mode */
733 val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
734 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
735
736 /* Source number */
737 val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
738 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 4);
739
740 /* Channel number right 0 */
741 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
742 /* Channel number right 1*/
743 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
744 /* Channel number right 2 */
745 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
746 /* Channel number right 3*/
747 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
748 /* Channel number left 0 */
749 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
750 /* Channel number left 1*/
751 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
752 /* Channel number left 2 */
753 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
754 /* Channel number left 3*/
755 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
756
757 /* Clock accuracy and sample rate */
758 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
759 cfg->iec60958_cfg->status[3]);
760
761 /* Original sample rate and word length */
762 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
763 cfg->iec60958_cfg->status[4]);
764
765 /* Enable FIFO empty and full interrupts */
766 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
767
768 /* Configure GPA */
769 /* select HBR/SPDIF interfaces */
770 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
771 /* select HBR/SPDIF interfaces */
772 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
773 /* enable two channels in GPA */
774 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
775 } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
776 /* select HBR/SPDIF interfaces */
777 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
778 /* enable six channels in GPA */
779 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
780 } else {
781 /* select HBR/SPDIF interfaces */
782 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
783 /* enable eight channels in GPA */
784 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
785 }
786
787 /* disable HBR */
788 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
789 /* enable PCUV */
790 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
791 /* enable GPA FIFO full and empty mask */
792 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
793 /* set polarity of GPA FIFO empty interrupts */
794 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
795
796 /* unmute audio */
797 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
798 }
799
800 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
801 struct snd_cea_861_aud_if *info_aud)
802 {
803 void __iomem *base = core->base;
804
805 /* channel count and coding type fields in AUDICONF0 are swapped */
806 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
807 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
808 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
809
810 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
811 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
812 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, info_aud->db5_dminh_lsv);
813 }
814
815 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
816 struct omap_dss_audio *audio, u32 pclk)
817 {
818 struct hdmi_audio_format audio_format;
819 struct hdmi_audio_dma audio_dma;
820 struct hdmi_core_audio_config core_cfg;
821 int err, n, cts, channel_count;
822 unsigned int fs_nr;
823 bool word_length_16b = false;
824
825 if (!audio || !audio->iec || !audio->cea || !core)
826 return -EINVAL;
827
828 core_cfg.iec60958_cfg = audio->iec;
829
830 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
831 (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
832 word_length_16b = true;
833
834 /* only 16-bit word length supported atm */
835 if (!word_length_16b)
836 return -EINVAL;
837
838 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
839 case IEC958_AES3_CON_FS_32000:
840 fs_nr = 32000;
841 break;
842 case IEC958_AES3_CON_FS_44100:
843 fs_nr = 44100;
844 break;
845 case IEC958_AES3_CON_FS_48000:
846 fs_nr = 48000;
847 break;
848 case IEC958_AES3_CON_FS_88200:
849 fs_nr = 88200;
850 break;
851 case IEC958_AES3_CON_FS_96000:
852 fs_nr = 96000;
853 break;
854 case IEC958_AES3_CON_FS_176400:
855 fs_nr = 176400;
856 break;
857 case IEC958_AES3_CON_FS_192000:
858 fs_nr = 192000;
859 break;
860 default:
861 return -EINVAL;
862 }
863
864 err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
865 core_cfg.n = n;
866 core_cfg.cts = cts;
867
868 /* Audio channels settings */
869 channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
870 + 1;
871
872 if (channel_count == 2)
873 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
874 else if (channel_count == 6)
875 core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
876 else
877 core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
878
879 /* DMA settings */
880 if (word_length_16b)
881 audio_dma.transfer_size = 0x10;
882 else
883 audio_dma.transfer_size = 0x20;
884 audio_dma.block_size = 0xC0;
885 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
886 audio_dma.fifo_threshold = 0x20; /* in number of samples */
887
888 /* audio FIFO format settings for 16-bit samples*/
889 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
890 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
891 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
892
893 /* only LPCM atm */
894 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
895
896 /* disable start/stop signals of IEC 60958 blocks */
897 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
898
899 /* configure DMA and audio FIFO format*/
900 hdmi_wp_audio_config_dma(wp, &audio_dma);
901 hdmi_wp_audio_config_format(wp, &audio_format);
902
903 /* configure the core */
904 hdmi5_core_audio_config(core, &core_cfg);
905
906 /* configure CEA 861 audio infoframe */
907 hdmi5_core_audio_infoframe_cfg(core, audio->cea);
908
909 return 0;
910 }
911 #endif
912
913 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
914 {
915 struct resource *res;
916
917 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
918 if (!res) {
919 DSSERR("can't get CORE IORESOURCE_MEM HDMI\n");
920 return -EINVAL;
921 }
922
923 core->base = devm_ioremap_resource(&pdev->dev, res);
924 if (IS_ERR(core->base)) {
925 DSSERR("can't ioremap HDMI core\n");
926 return PTR_ERR(core->base);
927 }
928
929 return 0;
930 }
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