drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/net_tstamp.h>
  44 #ifdef CONFIG_MLX4_EN_DCB
  45 #include <linux/dcbnl.h>
  46 #endif
  47 #include <linux/cpu_rmap.h>
  48 #include <linux/ptp_clock_kernel.h>
  49
  50 #include <linux/mlx4/device.h>
  51 #include <linux/mlx4/qp.h>
  52 #include <linux/mlx4/cq.h>
  53 #include <linux/mlx4/srq.h>
  54 #include <linux/mlx4/doorbell.h>
  55 #include <linux/mlx4/cmd.h>
  56
  57 #include "en_port.h"
  58 #include "mlx4_stats.h"
  59
  60 #define DRV_NAME        "mlx4_en"
  61 #define DRV_VERSION     "4.0-0"
  62
  63 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  64
  65 /*
  66  * Device constants
  67  */
  68
  69
  70 #define MLX4_EN_PAGE_SHIFT      12
  71 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  72 #define DEF_RX_RINGS            16
  73 #define MAX_RX_RINGS            128
  74 #define MIN_RX_RINGS            4
  75 #define TXBB_SIZE               64
  76 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  77 #define STAMP_STRIDE            64
  78 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  79 #define STAMP_SHIFT             31
  80 #define STAMP_VAL               0x7fffffff
  81 #define STATS_DELAY             (HZ / 4)
  82 #define SERVICE_TASK_DELAY      (HZ / 4)
  83 #define MAX_NUM_OF_FS_RULES     256
  84
  85 #define MLX4_EN_FILTER_HASH_SHIFT 4
  86 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
  87
  88 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  89 #define MAX_DESC_SIZE           512
  90 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  91
  92 /*
  93  * OS related constants and tunables
  94  */
  95
  96 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
  97 #define MLX4_EN_PRIV_FLAGS_PHV       2
  98
  99 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
 100
 101 /* Use the maximum between 16384 and a single page */
 102 #define MLX4_EN_ALLOC_SIZE      PAGE_ALIGN(16384)
 103
 104 #define MLX4_EN_MAX_RX_FRAGS    4
 105
 106 /* Maximum ring sizes */
 107 #define MLX4_EN_MAX_TX_SIZE     8192
 108 #define MLX4_EN_MAX_RX_SIZE     8192
 109
 110 /* Minimum ring size for our page-allocation scheme to work */
 111 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 112 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 113
 114 #define MLX4_EN_SMALL_PKT_SIZE          64
 115 #define MLX4_EN_MIN_TX_RING_P_UP        1
 116 #define MLX4_EN_MAX_TX_RING_P_UP        32
 117 #define MLX4_EN_NUM_UP                  8
 118 #define MLX4_EN_DEF_TX_RING_SIZE        512
 119 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 120 #define MAX_TX_RINGS                    (MLX4_EN_MAX_TX_RING_P_UP * \
 121                                          MLX4_EN_NUM_UP)
 122
 123 #define MLX4_EN_DEFAULT_TX_WORK         256
 124 #define MLX4_EN_DOORBELL_BUDGET         8
 125
 126 /* Target number of packets to coalesce with interrupt moderation */
 127 #define MLX4_EN_RX_COAL_TARGET  44
 128 #define MLX4_EN_RX_COAL_TIME    0x10
 129
 130 #define MLX4_EN_TX_COAL_PKTS    16
 131 #define MLX4_EN_TX_COAL_TIME    0x10
 132
 133 #define MLX4_EN_RX_RATE_LOW             400000
 134 #define MLX4_EN_RX_COAL_TIME_LOW        0
 135 #define MLX4_EN_RX_RATE_HIGH            450000
 136 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 137 #define MLX4_EN_RX_SIZE_THRESH          1024
 138 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 139 #define MLX4_EN_SAMPLE_INTERVAL         0
 140 #define MLX4_EN_AVG_PKT_SMALL           256
 141
 142 #define MLX4_EN_AUTO_CONF       0xffff
 143
 144 #define MLX4_EN_DEF_RX_PAUSE    1
 145 #define MLX4_EN_DEF_TX_PAUSE    1
 146
 147 /* Interval between successive polls in the Tx routine when polling is used
 148    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 149 #define MLX4_EN_TX_POLL_MODER   16
 150 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 151
 152 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 153 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 154 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 155
 156 #define MLX4_EN_MIN_MTU         46
 157 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
 158  * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
 159  */
 160 #define MLX4_EN_EFF_MTU(mtu)    ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
 161 #define ETH_BCAST               0xffffffffffffULL
 162
 163 #define MLX4_EN_LOOPBACK_RETRIES        5
 164 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 165
 166 #ifdef MLX4_EN_PERF_STAT
 167 /* Number of samples to 'average' */
 168 #define AVG_SIZE                        128
 169 #define AVG_FACTOR                      1024
 170
 171 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 172 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 173 #define AVG_PERF_COUNTER(cnt, sample) \
 174         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 175 #define GET_PERF_COUNTER(cnt)           (cnt)
 176 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 177
 178 #else
 179
 180 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 181 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 182 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 183 #define GET_PERF_COUNTER(cnt)           (0)
 184 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 185 #endif /* MLX4_EN_PERF_STAT */
 186
 187 /* Constants for TX flow */
 188 enum {
 189         MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
 190         MAX_BF = 256,
 191         MIN_PKT_LEN = 17,
 192 };
 193
 194 /*
 195  * Configurables
 196  */
 197
 198 enum cq_type {
 199         /* keep tx types first */
 200         TX,
 201         TX_XDP,
 202 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
 203         RX,
 204 };
 205
 206
 207 /*
 208  * Useful macros
 209  */
 210 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 211 #define XNOR(x, y)              (!(x) == !(y))
 212
 213
 214 struct mlx4_en_tx_info {
 215         union {
 216                 struct sk_buff *skb;
 217                 struct page *page;
 218         };
 219         dma_addr_t      map0_dma;
 220         u32             map0_byte_count;
 221         u32             nr_txbb;
 222         u32             nr_bytes;
 223         u8              linear;
 224         u8              data_offset;
 225         u8              inl;
 226         u8              ts_requested;
 227         u8              nr_maps;
 228 } ____cacheline_aligned_in_smp;
 229
 230
 231 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 232 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 233 #define MLX4_EN_MEMTYPE_PAD     0x100
 234 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 235
 236
 237 struct mlx4_en_tx_desc {
 238         struct mlx4_wqe_ctrl_seg ctrl;
 239         union {
 240                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 241                 struct mlx4_wqe_lso_seg lso;
 242                 struct mlx4_wqe_inline_seg inl;
 243         };
 244 };
 245
 246 #define MLX4_EN_USE_SRQ         0x01000000
 247
 248 #define MLX4_EN_CX3_LOW_ID      0x1000
 249 #define MLX4_EN_CX3_HIGH_ID     0x1005
 250
 251 struct mlx4_en_rx_alloc {
 252         struct page     *page;
 253         dma_addr_t      dma;
 254         u32             page_offset;
 255 };
 256
 257 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
 258
 259 struct mlx4_en_page_cache {
 260         u32 index;
 261         struct {
 262                 struct page     *page;
 263                 dma_addr_t      dma;
 264         } buf[MLX4_EN_CACHE_SIZE];
 265 };
 266
 267 struct mlx4_en_priv;
 268
 269 struct mlx4_en_tx_ring {
 270         /* cache line used and dirtied in tx completion
 271          * (mlx4_en_free_tx_buf())
 272          */
 273         u32                     last_nr_txbb;
 274         u32                     cons;
 275         unsigned long           wake_queue;
 276         struct netdev_queue     *tx_queue;
 277         u32                     (*free_tx_desc)(struct mlx4_en_priv *priv,
 278                                                 struct mlx4_en_tx_ring *ring,
 279                                                 int index,
 280                                                 u64 timestamp, int napi_mode);
 281         struct mlx4_en_rx_ring  *recycle_ring;
 282
 283         /* cache line used and dirtied in mlx4_en_xmit() */
 284         u32                     prod ____cacheline_aligned_in_smp;
 285         unsigned int            tx_dropped;
 286         unsigned long           bytes;
 287         unsigned long           packets;
 288         unsigned long           tx_csum;
 289         unsigned long           tso_packets;
 290         unsigned long           xmit_more;
 291         struct mlx4_bf          bf;
 292
 293         /* Following part should be mostly read */
 294         __be32                  doorbell_qpn;
 295         __be32                  mr_key;
 296         u32                     size; /* number of TXBBs */
 297         u32                     size_mask;
 298         u32                     full_size;
 299         u32                     buf_size;
 300         void                    *buf;
 301         struct mlx4_en_tx_info  *tx_info;
 302         int                     qpn;
 303         u8                      queue_index;
 304         bool                    bf_enabled;
 305         bool                    bf_alloced;
 306         u8                      hwtstamp_tx_type;
 307         u8                      *bounce_buf;
 308
 309         /* Not used in fast path
 310          * Only queue_stopped might be used if BQL is not properly working.
 311          */
 312         unsigned long           queue_stopped;
 313         struct mlx4_hwq_resources sp_wqres;
 314         struct mlx4_qp          sp_qp;
 315         struct mlx4_qp_context  sp_context;
 316         cpumask_t               sp_affinity_mask;
 317         enum mlx4_qp_state      sp_qp_state;
 318         u16                     sp_stride;
 319         u16                     sp_cqn; /* index of port CQ associated with this ring */
 320 } ____cacheline_aligned_in_smp;
 321
 322 struct mlx4_en_rx_desc {
 323         /* actual number of entries depends on rx ring stride */
 324         struct mlx4_wqe_data_seg data[0];
 325 };
 326
 327 struct mlx4_en_rx_ring {
 328         struct mlx4_hwq_resources wqres;
 329         u32 size ;      /* number of Rx descs*/
 330         u32 actual_size;
 331         u32 size_mask;
 332         u16 stride;
 333         u16 log_stride;
 334         u16 cqn;        /* index of port CQ associated with this ring */
 335         u32 prod;
 336         u32 cons;
 337         u32 buf_size;
 338         u8  fcs_del;
 339         void *buf;
 340         void *rx_info;
 341         struct bpf_prog __rcu *xdp_prog;
 342         struct mlx4_en_page_cache page_cache;
 343         unsigned long bytes;
 344         unsigned long packets;
 345         unsigned long csum_ok;
 346         unsigned long csum_none;
 347         unsigned long csum_complete;
 348         unsigned long rx_alloc_pages;
 349         unsigned long xdp_drop;
 350         unsigned long xdp_tx;
 351         unsigned long xdp_tx_full;
 352         unsigned long dropped;
 353         int hwtstamp_rx_filter;
 354         cpumask_var_t affinity_mask;
 355 };
 356
 357 struct mlx4_en_cq {
 358         struct mlx4_cq          mcq;
 359         struct mlx4_hwq_resources wqres;
 360         int                     ring;
 361         struct net_device      *dev;
 362         struct napi_struct      napi;
 363         int size;
 364         int buf_size;
 365         int vector;
 366         enum cq_type type;
 367         u16 moder_time;
 368         u16 moder_cnt;
 369         struct mlx4_cqe *buf;
 370 #define MLX4_EN_OPCODE_ERROR    0x1e
 371
 372         struct irq_desc *irq_desc;
 373 };
 374
 375 struct mlx4_en_port_profile {
 376         u32 flags;
 377         u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
 378         u32 rx_ring_num;
 379         u32 tx_ring_size;
 380         u32 rx_ring_size;
 381         u8 num_tx_rings_p_up;
 382         u8 rx_pause;
 383         u8 rx_ppp;
 384         u8 tx_pause;
 385         u8 tx_ppp;
 386         int rss_rings;
 387         int inline_thold;
 388         struct hwtstamp_config hwtstamp_config;
 389 };
 390
 391 struct mlx4_en_profile {
 392         int udp_rss;
 393         u8 rss_mask;
 394         u32 active_ports;
 395         u32 small_pkt_int;
 396         u8 no_reset;
 397         u8 num_tx_rings_p_up;
 398         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 399 };
 400
 401 struct mlx4_en_dev {
 402         struct mlx4_dev         *dev;
 403         struct pci_dev          *pdev;
 404         struct mutex            state_lock;
 405         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 406         struct net_device       *upper[MLX4_MAX_PORTS + 1];
 407         u32                     port_cnt;
 408         bool                    device_up;
 409         struct mlx4_en_profile  profile;
 410         u32                     LSO_support;
 411         struct workqueue_struct *workqueue;
 412         struct device           *dma_device;
 413         void __iomem            *uar_map;
 414         struct mlx4_uar         priv_uar;
 415         struct mlx4_mr          mr;
 416         u32                     priv_pdn;
 417         spinlock_t              uar_lock;
 418         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 419         u32                     nominal_c_mult;
 420         struct cyclecounter     cycles;
 421         seqlock_t               clock_lock;
 422         struct timecounter      clock;
 423         unsigned long           last_overflow_check;
 424         struct ptp_clock        *ptp_clock;
 425         struct ptp_clock_info   ptp_clock_info;
 426         struct notifier_block   nb;
 427 };
 428
 429
 430 struct mlx4_en_rss_map {
 431         int base_qpn;
 432         struct mlx4_qp qps[MAX_RX_RINGS];
 433         enum mlx4_qp_state state[MAX_RX_RINGS];
 434         struct mlx4_qp indir_qp;
 435         enum mlx4_qp_state indir_state;
 436 };
 437
 438 enum mlx4_en_port_flag {
 439         MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
 440         MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
 441 };
 442
 443 struct mlx4_en_port_state {
 444         int link_state;
 445         int link_speed;
 446         int transceiver;
 447         u32 flags;
 448 };
 449
 450 enum mlx4_en_mclist_act {
 451         MCLIST_NONE,
 452         MCLIST_REM,
 453         MCLIST_ADD,
 454 };
 455
 456 struct mlx4_en_mc_list {
 457         struct list_head        list;
 458         enum mlx4_en_mclist_act action;
 459         u8                      addr[ETH_ALEN];
 460         u64                     reg_id;
 461         u64                     tunnel_reg_id;
 462 };
 463
 464 struct mlx4_en_frag_info {
 465         u16 frag_size;
 466         u32 frag_stride;
 467 };
 468
 469 #ifdef CONFIG_MLX4_EN_DCB
 470 /* Minimal TC BW - setting to 0 will block traffic */
 471 #define MLX4_EN_BW_MIN 1
 472 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
 473
 474 #define MLX4_EN_TC_ETS 7
 475
 476 enum dcb_pfc_type {
 477         pfc_disabled = 0,
 478         pfc_enabled_full,
 479         pfc_enabled_tx,
 480         pfc_enabled_rx
 481 };
 482
 483 struct mlx4_en_cee_config {
 484         bool    pfc_state;
 485         enum    dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP];
 486 };
 487 #endif
 488
 489 struct ethtool_flow_id {
 490         struct list_head list;
 491         struct ethtool_rx_flow_spec flow_spec;
 492         u64 id;
 493 };
 494
 495 enum {
 496         MLX4_EN_FLAG_PROMISC            = (1 << 0),
 497         MLX4_EN_FLAG_MC_PROMISC         = (1 << 1),
 498         /* whether we need to enable hardware loopback by putting dmac
 499          * in Tx WQE
 500          */
 501         MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
 502         /* whether we need to drop packets that hardware loopback-ed */
 503         MLX4_EN_FLAG_RX_FILTER_NEEDED   = (1 << 3),
 504         MLX4_EN_FLAG_FORCE_PROMISC      = (1 << 4),
 505         MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP        = (1 << 5),
 506 #ifdef CONFIG_MLX4_EN_DCB
 507         MLX4_EN_FLAG_DCB_ENABLED        = (1 << 6),
 508 #endif
 509 };
 510
 511 #define PORT_BEACON_MAX_LIMIT (65535)
 512 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
 513 #define MLX4_EN_MAC_HASH_IDX 5
 514
 515 struct mlx4_en_stats_bitmap {
 516         DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
 517         struct mutex mutex; /* for mutual access to stats bitmap */
 518 };
 519
 520 struct mlx4_en_priv {
 521         struct mlx4_en_dev *mdev;
 522         struct mlx4_en_port_profile *prof;
 523         struct net_device *dev;
 524         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 525         struct mlx4_en_port_state port_state;
 526         spinlock_t stats_lock;
 527         struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
 528         /* To allow rules removal while port is going down */
 529         struct list_head ethtool_list;
 530
 531         unsigned long last_moder_packets[MAX_RX_RINGS];
 532         unsigned long last_moder_tx_packets;
 533         unsigned long last_moder_bytes[MAX_RX_RINGS];
 534         unsigned long last_moder_jiffies;
 535         int last_moder_time[MAX_RX_RINGS];
 536         u16 rx_usecs;
 537         u16 rx_frames;
 538         u16 tx_usecs;
 539         u16 tx_frames;
 540         u32 pkt_rate_low;
 541         u16 rx_usecs_low;
 542         u32 pkt_rate_high;
 543         u16 rx_usecs_high;
 544         u16 sample_interval;
 545         u16 adaptive_rx_coal;
 546         u32 msg_enable;
 547         u32 loopback_ok;
 548         u32 validate_loopback;
 549
 550         struct mlx4_hwq_resources res;
 551         int link_state;
 552         int last_link_state;
 553         bool port_up;
 554         int port;
 555         int registered;
 556         int allocated;
 557         int stride;
 558         unsigned char current_mac[ETH_ALEN + 2];
 559         int mac_index;
 560         unsigned max_mtu;
 561         int base_qpn;
 562         int cqe_factor;
 563         int cqe_size;
 564
 565         struct mlx4_en_rss_map rss_map;
 566         __be32 ctrl_flags;
 567         u32 flags;
 568         u8 num_tx_rings_p_up;
 569         u32 tx_work_limit;
 570         u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
 571         u32 rx_ring_num;
 572         u32 rx_skb_size;
 573         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 574         u8 num_frags;
 575         u8 log_rx_info;
 576         u8 dma_dir;
 577         u16 rx_headroom;
 578
 579         struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
 580         struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
 581         struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
 582         struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
 583         struct mlx4_qp drop_qp;
 584         struct work_struct rx_mode_task;
 585         struct work_struct watchdog_task;
 586         struct work_struct linkstate_task;
 587         struct delayed_work stats_task;
 588         struct delayed_work service_task;
 589         struct work_struct vxlan_add_task;
 590         struct work_struct vxlan_del_task;
 591         struct mlx4_en_perf_stats pstats;
 592         struct mlx4_en_pkt_stats pkstats;
 593         struct mlx4_en_counter_stats pf_stats;
 594         struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
 595         struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
 596         struct mlx4_en_flow_stats_rx rx_flowstats;
 597         struct mlx4_en_flow_stats_tx tx_flowstats;
 598         struct mlx4_en_port_stats port_stats;
 599         struct mlx4_en_xdp_stats xdp_stats;
 600         struct mlx4_en_stats_bitmap stats_bitmap;
 601         struct list_head mc_list;
 602         struct list_head curr_list;
 603         u64 broadcast_id;
 604         struct mlx4_en_stat_out_mbox hw_stats;
 605         int vids[128];
 606         bool wol;
 607         struct device *ddev;
 608         struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
 609         struct hwtstamp_config hwtstamp_config;
 610         u32 counter_index;
 611
 612 #ifdef CONFIG_MLX4_EN_DCB
 613 #define MLX4_EN_DCB_ENABLED     0x3
 614         struct ieee_ets ets;
 615         u16 maxrate[IEEE_8021QAZ_MAX_TCS];
 616         enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
 617         struct mlx4_en_cee_config cee_config;
 618         u8 dcbx_cap;
 619 #endif
 620 #ifdef CONFIG_RFS_ACCEL
 621         spinlock_t filters_lock;
 622         int last_filter_id;
 623         struct list_head filters;
 624         struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
 625 #endif
 626         u64 tunnel_reg_id;
 627         __be16 vxlan_port;
 628
 629         u32 pflags;
 630         u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
 631         u8 rss_hash_fn;
 632 };
 633
 634 enum mlx4_en_wol {
 635         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 636         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 637 };
 638
 639 struct mlx4_mac_entry {
 640         struct hlist_node hlist;
 641         unsigned char mac[ETH_ALEN + 2];
 642         u64 reg_id;
 643         struct rcu_head rcu;
 644 };
 645
 646 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
 647 {
 648         return buf + idx * cqe_sz;
 649 }
 650
 651 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
 652
 653 void mlx4_en_init_ptys2ethtool_map(void);
 654 void mlx4_en_update_loopback_state(struct net_device *dev,
 655                                    netdev_features_t features);
 656
 657 void mlx4_en_destroy_netdev(struct net_device *dev);
 658 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 659                         struct mlx4_en_port_profile *prof);
 660
 661 int mlx4_en_start_port(struct net_device *dev);
 662 void mlx4_en_stop_port(struct net_device *dev, int detach);
 663
 664 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
 665                               struct mlx4_en_stats_bitmap *stats_bitmap,
 666                               u8 rx_ppp, u8 rx_pause,
 667                               u8 tx_ppp, u8 tx_pause);
 668
 669 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
 670                                 struct mlx4_en_priv *tmp,
 671                                 struct mlx4_en_port_profile *prof,
 672                                 bool carry_xdp_prog);
 673 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
 674                                     struct mlx4_en_priv *tmp);
 675
 676 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
 677                       int entries, int ring, enum cq_type mode, int node);
 678 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
 679 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 680                         int cq_idx);
 681 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 682 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 683 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 684
 685 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 686 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 687                          void *accel_priv, select_queue_fallback_t fallback);
 688 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 689 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
 690                                struct mlx4_en_rx_alloc *frame,
 691                                struct net_device *dev, unsigned int length,
 692                                int tx_ind, int *doorbell_pending);
 693 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
 694 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
 695                         struct mlx4_en_rx_alloc *frame);
 696
 697 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
 698                            struct mlx4_en_tx_ring **pring,
 699                            u32 size, u16 stride,
 700                            int node, int queue_index);
 701 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 702                              struct mlx4_en_tx_ring **pring);
 703 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 704                              struct mlx4_en_tx_ring *ring,
 705                              int cq, int user_prio);
 706 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 707                                 struct mlx4_en_tx_ring *ring);
 708 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
 709 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
 710 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 711                            struct mlx4_en_rx_ring **pring,
 712                            u32 size, u16 stride, int node);
 713 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 714                              struct mlx4_en_rx_ring **pring,
 715                              u32 size, u16 stride);
 716 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 717 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 718                                 struct mlx4_en_rx_ring *ring);
 719 int mlx4_en_process_rx_cq(struct net_device *dev,
 720                           struct mlx4_en_cq *cq,
 721                           int budget);
 722 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 723 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
 724 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 725                          struct mlx4_en_tx_ring *ring,
 726                          int index, u64 timestamp,
 727                          int napi_mode);
 728 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
 729                             struct mlx4_en_tx_ring *ring,
 730                             int index, u64 timestamp,
 731                             int napi_mode);
 732 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 733                 int is_tx, int rss, int qpn, int cqn, int user_prio,
 734                 struct mlx4_qp_context *context);
 735 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 736 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
 737                             int loopback);
 738 void mlx4_en_calc_rx_buf(struct net_device *dev);
 739 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 740 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 741 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
 742 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
 743 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 744 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 745
 746 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 747 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 748
 749 void mlx4_en_fold_software_stats(struct net_device *dev);
 750 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 751 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 752
 753 #ifdef CONFIG_MLX4_EN_DCB
 754 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
 755 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
 756 #endif
 757
 758 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
 759
 760 #ifdef CONFIG_RFS_ACCEL
 761 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
 762 #endif
 763
 764 #define MLX4_EN_NUM_SELF_TEST   5
 765 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 766 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
 767
 768 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
 769         ((dev->features & feature) ^ (new_features & feature))
 770
 771 int mlx4_en_reset_config(struct net_device *dev,
 772                          struct hwtstamp_config ts_config,
 773                          netdev_features_t new_features);
 774 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
 775                                      struct mlx4_en_stats_bitmap *stats_bitmap,
 776                                      u8 rx_ppp, u8 rx_pause,
 777                                      u8 tx_ppp, u8 tx_pause);
 778 int mlx4_en_netdev_event(struct notifier_block *this,
 779                          unsigned long event, void *ptr);
 780
 781 /*
 782  * Functions for time stamping
 783  */
 784 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
 785 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
 786                             struct skb_shared_hwtstamps *hwts,
 787                             u64 timestamp);
 788 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
 789 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
 790
 791 /* Globals
 792  */
 793 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 794
 795
 796
 797 /*
 798  * printk / logging functions
 799  */
 800
 801 __printf(3, 4)
 802 void en_print(const char *level, const struct mlx4_en_priv *priv,
 803               const char *format, ...);
 804
 805 #define en_dbg(mlevel, priv, format, ...)                               \
 806 do {                                                                    \
 807         if (NETIF_MSG_##mlevel & (priv)->msg_enable)                    \
 808                 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__);      \
 809 } while (0)
 810 #define en_warn(priv, format, ...)                                      \
 811         en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
 812 #define en_err(priv, format, ...)                                       \
 813         en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
 814 #define en_info(priv, format, ...)                                      \
 815         en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
 816
 817 #define mlx4_err(mdev, format, ...)                                     \
 818         pr_err(DRV_NAME " %s: " format,                                 \
 819                dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 820 #define mlx4_info(mdev, format, ...)                                    \
 821         pr_info(DRV_NAME " %s: " format,                                \
 822                 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 823 #define mlx4_warn(mdev, format, ...)                                    \
 824         pr_warn(DRV_NAME " %s: " format,                                \
 825                 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 826
 827 #endif