2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol
[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
51 struct ath_atx_tid
*tid
, struct sk_buff
*skb
);
52 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
53 int tx_flags
, struct ath_txq
*txq
);
54 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
55 struct ath_txq
*txq
, struct list_head
*bf_q
,
56 struct ath_tx_status
*ts
, int txok
);
57 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
58 struct list_head
*head
, bool internal
);
59 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
60 struct ath_tx_status
*ts
, int nframes
, int nbad
,
62 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
64 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
66 struct ath_atx_tid
*tid
,
76 static int ath_max_4ms_framelen
[4][32] = {
78 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
79 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
80 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
81 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
84 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
85 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
86 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
87 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
90 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
91 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
92 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
93 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
96 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
97 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
98 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
99 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
103 /*********************/
104 /* Aggregation logic */
105 /*********************/
107 static void ath_txq_lock(struct ath_softc
*sc
, struct ath_txq
*txq
)
108 __acquires(&txq
->axq_lock
)
110 spin_lock_bh(&txq
->axq_lock
);
113 static void ath_txq_unlock(struct ath_softc
*sc
, struct ath_txq
*txq
)
114 __releases(&txq
->axq_lock
)
116 spin_unlock_bh(&txq
->axq_lock
);
119 static void ath_txq_unlock_complete(struct ath_softc
*sc
, struct ath_txq
*txq
)
120 __releases(&txq
->axq_lock
)
122 struct sk_buff_head q
;
125 __skb_queue_head_init(&q
);
126 skb_queue_splice_init(&txq
->complete_q
, &q
);
127 spin_unlock_bh(&txq
->axq_lock
);
129 while ((skb
= __skb_dequeue(&q
)))
130 ieee80211_tx_status(sc
->hw
, skb
);
133 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
135 struct ath_atx_ac
*ac
= tid
->ac
;
144 list_add_tail(&tid
->list
, &ac
->tid_q
);
150 list_add_tail(&ac
->list
, &txq
->axq_acq
);
153 static void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
155 struct ath_txq
*txq
= tid
->ac
->txq
;
157 WARN_ON(!tid
->paused
);
159 ath_txq_lock(sc
, txq
);
162 if (skb_queue_empty(&tid
->buf_q
))
165 ath_tx_queue_tid(txq
, tid
);
166 ath_txq_schedule(sc
, txq
);
168 ath_txq_unlock_complete(sc
, txq
);
171 static struct ath_frame_info
*get_frame_info(struct sk_buff
*skb
)
173 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
174 BUILD_BUG_ON(sizeof(struct ath_frame_info
) >
175 sizeof(tx_info
->rate_driver_data
));
176 return (struct ath_frame_info
*) &tx_info
->rate_driver_data
[0];
179 static void ath_send_bar(struct ath_atx_tid
*tid
, u16 seqno
)
181 ieee80211_send_bar(tid
->an
->vif
, tid
->an
->sta
->addr
, tid
->tidno
,
182 seqno
<< IEEE80211_SEQ_SEQ_SHIFT
);
185 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
187 struct ath_txq
*txq
= tid
->ac
->txq
;
190 struct list_head bf_head
;
191 struct ath_tx_status ts
;
192 struct ath_frame_info
*fi
;
193 bool sendbar
= false;
195 INIT_LIST_HEAD(&bf_head
);
197 memset(&ts
, 0, sizeof(ts
));
199 while ((skb
= __skb_dequeue(&tid
->buf_q
))) {
200 fi
= get_frame_info(skb
);
203 if (bf
&& fi
->retries
) {
204 list_add_tail(&bf
->list
, &bf_head
);
205 ath_tx_update_baw(sc
, tid
, bf
->bf_state
.seqno
);
206 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
209 ath_tx_send_normal(sc
, txq
, NULL
, skb
);
213 if (tid
->baw_head
== tid
->baw_tail
) {
214 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
215 tid
->state
&= ~AGGR_CLEANUP
;
219 ath_txq_unlock(sc
, txq
);
220 ath_send_bar(tid
, tid
->seq_start
);
221 ath_txq_lock(sc
, txq
);
225 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
230 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
231 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
233 __clear_bit(cindex
, tid
->tx_buf
);
235 while (tid
->baw_head
!= tid
->baw_tail
&& !test_bit(tid
->baw_head
, tid
->tx_buf
)) {
236 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
237 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
238 if (tid
->bar_index
>= 0)
243 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
248 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
249 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
250 __set_bit(cindex
, tid
->tx_buf
);
252 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
253 (ATH_TID_MAX_BUFS
- 1))) {
254 tid
->baw_tail
= cindex
;
255 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
260 * TODO: For frame(s) that are in the retry state, we will reuse the
261 * sequence number(s) without setting the retry bit. The
262 * alternative is to give up on these and BAR the receiver's window
265 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
266 struct ath_atx_tid
*tid
)
271 struct list_head bf_head
;
272 struct ath_tx_status ts
;
273 struct ath_frame_info
*fi
;
275 memset(&ts
, 0, sizeof(ts
));
276 INIT_LIST_HEAD(&bf_head
);
278 while ((skb
= __skb_dequeue(&tid
->buf_q
))) {
279 fi
= get_frame_info(skb
);
283 ath_tx_complete(sc
, skb
, ATH_TX_ERROR
, txq
);
287 list_add_tail(&bf
->list
, &bf_head
);
290 ath_tx_update_baw(sc
, tid
, bf
->bf_state
.seqno
);
292 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
295 tid
->seq_next
= tid
->seq_start
;
296 tid
->baw_tail
= tid
->baw_head
;
300 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_txq
*txq
,
301 struct sk_buff
*skb
, int count
)
303 struct ath_frame_info
*fi
= get_frame_info(skb
);
304 struct ath_buf
*bf
= fi
->bf
;
305 struct ieee80211_hdr
*hdr
;
306 int prev
= fi
->retries
;
308 TX_STAT_INC(txq
->axq_qnum
, a_retries
);
309 fi
->retries
+= count
;
314 hdr
= (struct ieee80211_hdr
*)skb
->data
;
315 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
316 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
317 sizeof(*hdr
), DMA_TO_DEVICE
);
320 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
322 struct ath_buf
*bf
= NULL
;
324 spin_lock_bh(&sc
->tx
.txbuflock
);
326 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
327 spin_unlock_bh(&sc
->tx
.txbuflock
);
331 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
334 spin_unlock_bh(&sc
->tx
.txbuflock
);
339 static void ath_tx_return_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
)
341 spin_lock_bh(&sc
->tx
.txbuflock
);
342 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
343 spin_unlock_bh(&sc
->tx
.txbuflock
);
346 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
350 tbf
= ath_tx_get_buffer(sc
);
354 ATH_TXBUF_RESET(tbf
);
356 tbf
->bf_mpdu
= bf
->bf_mpdu
;
357 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
358 memcpy(tbf
->bf_desc
, bf
->bf_desc
, sc
->sc_ah
->caps
.tx_desc_len
);
359 tbf
->bf_state
= bf
->bf_state
;
364 static void ath_tx_count_frames(struct ath_softc
*sc
, struct ath_buf
*bf
,
365 struct ath_tx_status
*ts
, int txok
,
366 int *nframes
, int *nbad
)
368 struct ath_frame_info
*fi
;
370 u32 ba
[WME_BA_BMP_SIZE
>> 5];
377 isaggr
= bf_isaggr(bf
);
379 seq_st
= ts
->ts_seqnum
;
380 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
384 fi
= get_frame_info(bf
->bf_mpdu
);
385 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_state
.seqno
);
388 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
396 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
397 struct ath_buf
*bf
, struct list_head
*bf_q
,
398 struct ath_tx_status
*ts
, int txok
, bool retry
)
400 struct ath_node
*an
= NULL
;
402 struct ieee80211_sta
*sta
;
403 struct ieee80211_hw
*hw
= sc
->hw
;
404 struct ieee80211_hdr
*hdr
;
405 struct ieee80211_tx_info
*tx_info
;
406 struct ath_atx_tid
*tid
= NULL
;
407 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
408 struct list_head bf_head
;
409 struct sk_buff_head bf_pending
;
410 u16 seq_st
= 0, acked_cnt
= 0, txfail_cnt
= 0, seq_first
;
411 u32 ba
[WME_BA_BMP_SIZE
>> 5];
412 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0, nbad
= 0;
413 bool rc_update
= true;
414 struct ieee80211_tx_rate rates
[4];
415 struct ath_frame_info
*fi
;
418 bool flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
423 hdr
= (struct ieee80211_hdr
*)skb
->data
;
425 tx_info
= IEEE80211_SKB_CB(skb
);
427 memcpy(rates
, tx_info
->control
.rates
, sizeof(rates
));
429 retries
= ts
->ts_longretry
+ 1;
430 for (i
= 0; i
< ts
->ts_rateindex
; i
++)
431 retries
+= rates
[i
].count
;
435 sta
= ieee80211_find_sta_by_ifaddr(hw
, hdr
->addr1
, hdr
->addr2
);
439 INIT_LIST_HEAD(&bf_head
);
441 bf_next
= bf
->bf_next
;
443 if (!bf
->bf_stale
|| bf_next
!= NULL
)
444 list_move_tail(&bf
->list
, &bf_head
);
446 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
, 0);
453 an
= (struct ath_node
*)sta
->drv_priv
;
454 tidno
= ieee80211_get_qos_ctl(hdr
)[0] & IEEE80211_QOS_CTL_TID_MASK
;
455 tid
= ATH_AN_2_TID(an
, tidno
);
456 seq_first
= tid
->seq_start
;
459 * The hardware occasionally sends a tx status for the wrong TID.
460 * In this case, the BA status cannot be considered valid and all
461 * subframes need to be retransmitted
463 if (tidno
!= ts
->tid
)
466 isaggr
= bf_isaggr(bf
);
467 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
469 if (isaggr
&& txok
) {
470 if (ts
->ts_flags
& ATH9K_TX_BA
) {
471 seq_st
= ts
->ts_seqnum
;
472 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
475 * AR5416 can become deaf/mute when BA
476 * issue happens. Chip needs to be reset.
477 * But AP code may have sychronization issues
478 * when perform internal reset in this routine.
479 * Only enable reset in STA mode for now.
481 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
)
486 __skb_queue_head_init(&bf_pending
);
488 ath_tx_count_frames(sc
, bf
, ts
, txok
, &nframes
, &nbad
);
490 u16 seqno
= bf
->bf_state
.seqno
;
492 txfail
= txpending
= sendbar
= 0;
493 bf_next
= bf
->bf_next
;
496 tx_info
= IEEE80211_SKB_CB(skb
);
497 fi
= get_frame_info(skb
);
499 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, seqno
))) {
500 /* transmit completion, subframe is
501 * acked by block ack */
503 } else if (!isaggr
&& txok
) {
504 /* transmit completion */
506 } else if ((tid
->state
& AGGR_CLEANUP
) || !retry
) {
508 * cleanup in progress, just fail
509 * the un-acked sub-frames
514 } else if (fi
->retries
< ATH_MAX_SW_RETRIES
) {
515 if (txok
|| !an
->sleeping
)
516 ath_tx_set_retry(sc
, txq
, bf
->bf_mpdu
,
523 bar_index
= max_t(int, bar_index
,
524 ATH_BA_INDEX(seq_first
, seqno
));
528 * Make sure the last desc is reclaimed if it
529 * not a holding desc.
531 INIT_LIST_HEAD(&bf_head
);
532 if ((sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) ||
533 bf_next
!= NULL
|| !bf_last
->bf_stale
)
534 list_move_tail(&bf
->list
, &bf_head
);
536 if (!txpending
|| (tid
->state
& AGGR_CLEANUP
)) {
538 * complete the acked-ones/xretried ones; update
541 ath_tx_update_baw(sc
, tid
, seqno
);
543 if (rc_update
&& (acked_cnt
== 1 || txfail_cnt
== 1)) {
544 memcpy(tx_info
->control
.rates
, rates
, sizeof(rates
));
545 ath_tx_rc_status(sc
, bf
, ts
, nframes
, nbad
, txok
);
549 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
,
552 /* retry the un-acked ones */
553 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) &&
554 bf
->bf_next
== NULL
&& bf_last
->bf_stale
) {
557 tbf
= ath_clone_txbuf(sc
, bf_last
);
559 * Update tx baw and complete the
560 * frame with failed status if we
564 ath_tx_update_baw(sc
, tid
, seqno
);
566 ath_tx_complete_buf(sc
, bf
, txq
,
568 bar_index
= max_t(int, bar_index
,
569 ATH_BA_INDEX(seq_first
, seqno
));
577 * Put this buffer to the temporary pending
578 * queue to retain ordering
580 __skb_queue_tail(&bf_pending
, skb
);
586 /* prepend un-acked frames to the beginning of the pending frame queue */
587 if (!skb_queue_empty(&bf_pending
)) {
589 ieee80211_sta_set_buffered(sta
, tid
->tidno
, true);
591 skb_queue_splice(&bf_pending
, &tid
->buf_q
);
593 ath_tx_queue_tid(txq
, tid
);
595 if (ts
->ts_status
& ATH9K_TXERR_FILT
)
596 tid
->ac
->clear_ps_filter
= true;
600 if (bar_index
>= 0) {
601 u16 bar_seq
= ATH_BA_INDEX2SEQ(seq_first
, bar_index
);
603 if (BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bar_seq
))
604 tid
->bar_index
= ATH_BA_INDEX(tid
->seq_start
, bar_seq
);
606 ath_txq_unlock(sc
, txq
);
607 ath_send_bar(tid
, ATH_BA_INDEX2SEQ(seq_first
, bar_index
+ 1));
608 ath_txq_lock(sc
, txq
);
611 if (tid
->state
& AGGR_CLEANUP
)
612 ath_tx_flush_tid(sc
, tid
);
617 RESET_STAT_INC(sc
, RESET_TYPE_TX_ERROR
);
618 ieee80211_queue_work(sc
->hw
, &sc
->hw_reset_work
);
622 static bool ath_lookup_legacy(struct ath_buf
*bf
)
625 struct ieee80211_tx_info
*tx_info
;
626 struct ieee80211_tx_rate
*rates
;
630 tx_info
= IEEE80211_SKB_CB(skb
);
631 rates
= tx_info
->control
.rates
;
633 for (i
= 0; i
< 4; i
++) {
634 if (!rates
[i
].count
|| rates
[i
].idx
< 0)
637 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
))
644 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
645 struct ath_atx_tid
*tid
)
648 struct ieee80211_tx_info
*tx_info
;
649 struct ieee80211_tx_rate
*rates
;
650 u32 max_4ms_framelen
, frmlen
;
651 u16 aggr_limit
, bt_aggr_limit
, legacy
= 0;
655 tx_info
= IEEE80211_SKB_CB(skb
);
656 rates
= tx_info
->control
.rates
;
659 * Find the lowest frame length among the rate series that will have a
660 * 4ms transmit duration.
661 * TODO - TXOP limit needs to be considered.
663 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
665 for (i
= 0; i
< 4; i
++) {
671 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
)) {
676 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
681 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
684 frmlen
= ath_max_4ms_framelen
[modeidx
][rates
[i
].idx
];
685 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
689 * limit aggregate size by the minimum rate if rate selected is
690 * not a probe rate, if rate selected is a probe rate then
691 * avoid aggregation of this packet.
693 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
696 aggr_limit
= min(max_4ms_framelen
, (u32
)ATH_AMPDU_LIMIT_MAX
);
699 * Override the default aggregation limit for BTCOEX.
701 bt_aggr_limit
= ath9k_btcoex_aggr_limit(sc
, max_4ms_framelen
);
703 aggr_limit
= bt_aggr_limit
;
706 * h/w can accept aggregates up to 16 bit lengths (65535).
707 * The IE, however can hold up to 65536, which shows up here
708 * as zero. Ignore 65536 since we are constrained by hw.
710 if (tid
->an
->maxampdu
)
711 aggr_limit
= min(aggr_limit
, tid
->an
->maxampdu
);
717 * Returns the number of delimiters to be added to
718 * meet the minimum required mpdudensity.
720 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
721 struct ath_buf
*bf
, u16 frmlen
,
724 #define FIRST_DESC_NDELIMS 60
725 struct sk_buff
*skb
= bf
->bf_mpdu
;
726 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
727 u32 nsymbits
, nsymbols
;
730 int width
, streams
, half_gi
, ndelim
, mindelim
;
731 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
733 /* Select standard number of delimiters based on frame length alone */
734 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
737 * If encryption enabled, hardware requires some more padding between
739 * TODO - this could be improved to be dependent on the rate.
740 * The hardware can keep up at lower rates, but not higher rates
742 if ((fi
->keyix
!= ATH9K_TXKEYIX_INVALID
) &&
743 !(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
))
744 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
747 * Add delimiter when using RTS/CTS with aggregation
748 * and non enterprise AR9003 card
750 if (first_subfrm
&& !AR_SREV_9580_10_OR_LATER(sc
->sc_ah
) &&
751 (sc
->sc_ah
->ent_mode
& AR_ENT_OTP_MIN_PKT_SIZE_DISABLE
))
752 ndelim
= max(ndelim
, FIRST_DESC_NDELIMS
);
755 * Convert desired mpdu density from microeconds to bytes based
756 * on highest rate in rate series (i.e. first rate) to determine
757 * required minimum length for subframe. Take into account
758 * whether high rate is 20 or 40Mhz and half or full GI.
760 * If there is no mpdu density restriction, no further calculation
764 if (tid
->an
->mpdudensity
== 0)
767 rix
= tx_info
->control
.rates
[0].idx
;
768 flags
= tx_info
->control
.rates
[0].flags
;
769 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
770 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
773 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(tid
->an
->mpdudensity
);
775 nsymbols
= NUM_SYMBOLS_PER_USEC(tid
->an
->mpdudensity
);
780 streams
= HT_RC_2_STREAMS(rix
);
781 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
782 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
784 if (frmlen
< minlen
) {
785 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
786 ndelim
= max(mindelim
, ndelim
);
792 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
794 struct ath_atx_tid
*tid
,
795 struct list_head
*bf_q
,
798 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
799 struct ath_buf
*bf
, *bf_first
= NULL
, *bf_prev
= NULL
;
800 int rl
= 0, nframes
= 0, ndelim
, prev_al
= 0;
801 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
802 al_delta
, h_baw
= tid
->baw_size
/ 2;
803 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
804 struct ieee80211_tx_info
*tx_info
;
805 struct ath_frame_info
*fi
;
810 skb
= skb_peek(&tid
->buf_q
);
811 fi
= get_frame_info(skb
);
814 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
819 bf
->bf_state
.bf_type
= BUF_AMPDU
| BUF_AGGR
;
820 seqno
= bf
->bf_state
.seqno
;
822 /* do not step over block-ack window */
823 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
)) {
824 status
= ATH_AGGR_BAW_CLOSED
;
828 if (tid
->bar_index
> ATH_BA_INDEX(tid
->seq_start
, seqno
)) {
829 struct ath_tx_status ts
= {};
830 struct list_head bf_head
;
832 INIT_LIST_HEAD(&bf_head
);
833 list_add(&bf
->list
, &bf_head
);
834 __skb_unlink(skb
, &tid
->buf_q
);
835 ath_tx_update_baw(sc
, tid
, seqno
);
836 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
844 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
848 /* do not exceed aggregation limit */
849 al_delta
= ATH_AGGR_DELIM_SZ
+ fi
->framelen
;
852 ((aggr_limit
< (al
+ bpad
+ al_delta
+ prev_al
)) ||
853 ath_lookup_legacy(bf
))) {
854 status
= ATH_AGGR_LIMITED
;
858 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
859 if (nframes
&& (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
))
862 /* do not exceed subframe limit */
863 if (nframes
>= min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
864 status
= ATH_AGGR_LIMITED
;
868 /* add padding for previous frame to aggregation length */
869 al
+= bpad
+ al_delta
;
872 * Get the delimiters needed to meet the MPDU
873 * density for this node.
875 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, fi
->framelen
,
877 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
882 /* link buffers of this frame to the aggregate */
884 ath_tx_addto_baw(sc
, tid
, seqno
);
885 bf
->bf_state
.ndelim
= ndelim
;
887 __skb_unlink(skb
, &tid
->buf_q
);
888 list_add_tail(&bf
->list
, bf_q
);
890 bf_prev
->bf_next
= bf
;
894 } while (!skb_queue_empty(&tid
->buf_q
));
904 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
905 * width - 0 for 20 MHz, 1 for 40 MHz
906 * half_gi - to use 4us v/s 3.6 us for symbol time
908 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, int pktlen
,
909 int width
, int half_gi
, bool shortPreamble
)
911 u32 nbits
, nsymbits
, duration
, nsymbols
;
914 /* find number of symbols: PLCP + data */
915 streams
= HT_RC_2_STREAMS(rix
);
916 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
917 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
918 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
921 duration
= SYMBOL_TIME(nsymbols
);
923 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
925 /* addup duration for legacy/ht training and signal fields */
926 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
931 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
932 struct ath_tx_info
*info
, int len
)
934 struct ath_hw
*ah
= sc
->sc_ah
;
936 struct ieee80211_tx_info
*tx_info
;
937 struct ieee80211_tx_rate
*rates
;
938 const struct ieee80211_rate
*rate
;
939 struct ieee80211_hdr
*hdr
;
944 tx_info
= IEEE80211_SKB_CB(skb
);
945 rates
= tx_info
->control
.rates
;
946 hdr
= (struct ieee80211_hdr
*)skb
->data
;
948 /* set dur_update_en for l-sig computation except for PS-Poll frames */
949 info
->dur_update
= !ieee80211_is_pspoll(hdr
->frame_control
);
952 * We check if Short Preamble is needed for the CTS rate by
953 * checking the BSS's global flag.
954 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
956 rate
= ieee80211_get_rts_cts_rate(sc
->hw
, tx_info
);
957 info
->rtscts_rate
= rate
->hw_value
;
959 if (tx_info
->control
.vif
&&
960 tx_info
->control
.vif
->bss_conf
.use_short_preamble
)
961 info
->rtscts_rate
|= rate
->hw_value_short
;
963 for (i
= 0; i
< 4; i
++) {
964 bool is_40
, is_sgi
, is_sp
;
967 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
971 info
->rates
[i
].Tries
= rates
[i
].count
;
973 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
974 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
975 info
->flags
|= ATH9K_TXDESC_RTSENA
;
976 } else if (rates
[i
].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
977 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
978 info
->flags
|= ATH9K_TXDESC_CTSENA
;
981 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
982 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
983 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
984 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
986 is_sgi
= !!(rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
);
987 is_40
= !!(rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
);
988 is_sp
= !!(rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
);
990 if (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) {
992 info
->rates
[i
].Rate
= rix
| 0x80;
993 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
994 ah
->txchainmask
, info
->rates
[i
].Rate
);
995 info
->rates
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, len
,
996 is_40
, is_sgi
, is_sp
);
997 if (rix
< 8 && (tx_info
->flags
& IEEE80211_TX_CTL_STBC
))
998 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_STBC
;
1003 if ((tx_info
->band
== IEEE80211_BAND_2GHZ
) &&
1004 !(rate
->flags
& IEEE80211_RATE_ERP_G
))
1005 phy
= WLAN_RC_PHY_CCK
;
1007 phy
= WLAN_RC_PHY_OFDM
;
1009 rate
= &sc
->sbands
[tx_info
->band
].bitrates
[rates
[i
].idx
];
1010 info
->rates
[i
].Rate
= rate
->hw_value
;
1011 if (rate
->hw_value_short
) {
1012 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
1013 info
->rates
[i
].Rate
|= rate
->hw_value_short
;
1018 if (bf
->bf_state
.bfs_paprd
)
1019 info
->rates
[i
].ChSel
= ah
->txchainmask
;
1021 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1022 ah
->txchainmask
, info
->rates
[i
].Rate
);
1024 info
->rates
[i
].PktDuration
= ath9k_hw_computetxtime(sc
->sc_ah
,
1025 phy
, rate
->bitrate
* 100, len
, rix
, is_sp
);
1028 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1029 if (bf_isaggr(bf
) && (len
> sc
->sc_ah
->caps
.rts_aggr_limit
))
1030 info
->flags
&= ~ATH9K_TXDESC_RTSENA
;
1032 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1033 if (info
->flags
& ATH9K_TXDESC_RTSENA
)
1034 info
->flags
&= ~ATH9K_TXDESC_CTSENA
;
1037 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1039 struct ieee80211_hdr
*hdr
;
1040 enum ath9k_pkt_type htype
;
1043 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1044 fc
= hdr
->frame_control
;
1046 if (ieee80211_is_beacon(fc
))
1047 htype
= ATH9K_PKT_TYPE_BEACON
;
1048 else if (ieee80211_is_probe_resp(fc
))
1049 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
1050 else if (ieee80211_is_atim(fc
))
1051 htype
= ATH9K_PKT_TYPE_ATIM
;
1052 else if (ieee80211_is_pspoll(fc
))
1053 htype
= ATH9K_PKT_TYPE_PSPOLL
;
1055 htype
= ATH9K_PKT_TYPE_NORMAL
;
1060 static void ath_tx_fill_desc(struct ath_softc
*sc
, struct ath_buf
*bf
,
1061 struct ath_txq
*txq
, int len
)
1063 struct ath_hw
*ah
= sc
->sc_ah
;
1064 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1065 struct ath_buf
*bf_first
= bf
;
1066 struct ath_tx_info info
;
1067 bool aggr
= !!(bf
->bf_state
.bf_type
& BUF_AGGR
);
1069 memset(&info
, 0, sizeof(info
));
1070 info
.is_first
= true;
1071 info
.is_last
= true;
1072 info
.txpower
= MAX_RATE_POWER
;
1073 info
.qcu
= txq
->axq_qnum
;
1075 info
.flags
= ATH9K_TXDESC_INTREQ
;
1076 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1077 info
.flags
|= ATH9K_TXDESC_NOACK
;
1078 if (tx_info
->flags
& IEEE80211_TX_CTL_LDPC
)
1079 info
.flags
|= ATH9K_TXDESC_LDPC
;
1081 ath_buf_set_rate(sc
, bf
, &info
, len
);
1083 if (tx_info
->flags
& IEEE80211_TX_CTL_CLEAR_PS_FILT
)
1084 info
.flags
|= ATH9K_TXDESC_CLRDMASK
;
1086 if (bf
->bf_state
.bfs_paprd
)
1087 info
.flags
|= (u32
) bf
->bf_state
.bfs_paprd
<< ATH9K_TXDESC_PAPRD_S
;
1091 struct sk_buff
*skb
= bf
->bf_mpdu
;
1092 struct ath_frame_info
*fi
= get_frame_info(skb
);
1094 info
.type
= get_hw_packet_type(skb
);
1096 info
.link
= bf
->bf_next
->bf_daddr
;
1100 info
.buf_addr
[0] = bf
->bf_buf_addr
;
1101 info
.buf_len
[0] = skb
->len
;
1102 info
.pkt_len
= fi
->framelen
;
1103 info
.keyix
= fi
->keyix
;
1104 info
.keytype
= fi
->keytype
;
1108 info
.aggr
= AGGR_BUF_FIRST
;
1109 else if (!bf
->bf_next
)
1110 info
.aggr
= AGGR_BUF_LAST
;
1112 info
.aggr
= AGGR_BUF_MIDDLE
;
1114 info
.ndelim
= bf
->bf_state
.ndelim
;
1115 info
.aggr_len
= len
;
1118 ath9k_hw_set_txdesc(ah
, bf
->bf_desc
, &info
);
1123 static void ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
1124 struct ath_atx_tid
*tid
)
1127 enum ATH_AGGR_STATUS status
;
1128 struct ieee80211_tx_info
*tx_info
;
1129 struct list_head bf_q
;
1133 if (skb_queue_empty(&tid
->buf_q
))
1136 INIT_LIST_HEAD(&bf_q
);
1138 status
= ath_tx_form_aggr(sc
, txq
, tid
, &bf_q
, &aggr_len
);
1141 * no frames picked up to be aggregated;
1142 * block-ack window is not open.
1144 if (list_empty(&bf_q
))
1147 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1148 bf
->bf_lastbf
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1149 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1151 if (tid
->ac
->clear_ps_filter
) {
1152 tid
->ac
->clear_ps_filter
= false;
1153 tx_info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1155 tx_info
->flags
&= ~IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1158 /* if only one frame, send as non-aggregate */
1159 if (bf
== bf
->bf_lastbf
) {
1160 aggr_len
= get_frame_info(bf
->bf_mpdu
)->framelen
;
1161 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1163 TX_STAT_INC(txq
->axq_qnum
, a_aggr
);
1166 ath_tx_fill_desc(sc
, bf
, txq
, aggr_len
);
1167 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1168 } while (txq
->axq_ampdu_depth
< ATH_AGGR_MIN_QDEPTH
&&
1169 status
!= ATH_AGGR_BAW_CLOSED
);
1172 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
1175 struct ath_atx_tid
*txtid
;
1176 struct ath_node
*an
;
1178 an
= (struct ath_node
*)sta
->drv_priv
;
1179 txtid
= ATH_AN_2_TID(an
, tid
);
1181 if (txtid
->state
& (AGGR_CLEANUP
| AGGR_ADDBA_COMPLETE
))
1184 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
1185 txtid
->paused
= true;
1186 *ssn
= txtid
->seq_start
= txtid
->seq_next
;
1187 txtid
->bar_index
= -1;
1189 memset(txtid
->tx_buf
, 0, sizeof(txtid
->tx_buf
));
1190 txtid
->baw_head
= txtid
->baw_tail
= 0;
1195 void ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
1197 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1198 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
1199 struct ath_txq
*txq
= txtid
->ac
->txq
;
1201 if (txtid
->state
& AGGR_CLEANUP
)
1204 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
1205 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
1209 ath_txq_lock(sc
, txq
);
1210 txtid
->paused
= true;
1213 * If frames are still being transmitted for this TID, they will be
1214 * cleaned up during tx completion. To prevent race conditions, this
1215 * TID can only be reused after all in-progress subframes have been
1218 if (txtid
->baw_head
!= txtid
->baw_tail
)
1219 txtid
->state
|= AGGR_CLEANUP
;
1221 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
1223 ath_tx_flush_tid(sc
, txtid
);
1224 ath_txq_unlock_complete(sc
, txq
);
1227 void ath_tx_aggr_sleep(struct ieee80211_sta
*sta
, struct ath_softc
*sc
,
1228 struct ath_node
*an
)
1230 struct ath_atx_tid
*tid
;
1231 struct ath_atx_ac
*ac
;
1232 struct ath_txq
*txq
;
1236 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1237 tidno
< WME_NUM_TID
; tidno
++, tid
++) {
1245 ath_txq_lock(sc
, txq
);
1247 buffered
= !skb_queue_empty(&tid
->buf_q
);
1250 list_del(&tid
->list
);
1254 list_del(&ac
->list
);
1257 ath_txq_unlock(sc
, txq
);
1259 ieee80211_sta_set_buffered(sta
, tidno
, buffered
);
1263 void ath_tx_aggr_wakeup(struct ath_softc
*sc
, struct ath_node
*an
)
1265 struct ath_atx_tid
*tid
;
1266 struct ath_atx_ac
*ac
;
1267 struct ath_txq
*txq
;
1270 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1271 tidno
< WME_NUM_TID
; tidno
++, tid
++) {
1276 ath_txq_lock(sc
, txq
);
1277 ac
->clear_ps_filter
= true;
1279 if (!skb_queue_empty(&tid
->buf_q
) && !tid
->paused
) {
1280 ath_tx_queue_tid(txq
, tid
);
1281 ath_txq_schedule(sc
, txq
);
1284 ath_txq_unlock_complete(sc
, txq
);
1288 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
1290 struct ath_atx_tid
*txtid
;
1291 struct ath_node
*an
;
1293 an
= (struct ath_node
*)sta
->drv_priv
;
1295 txtid
= ATH_AN_2_TID(an
, tid
);
1296 txtid
->baw_size
= IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
1297 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
1298 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
1299 ath_tx_resume_tid(sc
, txtid
);
1302 /********************/
1303 /* Queue Management */
1304 /********************/
1306 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
1307 struct ath_txq
*txq
)
1309 struct ath_atx_ac
*ac
, *ac_tmp
;
1310 struct ath_atx_tid
*tid
, *tid_tmp
;
1312 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1313 list_del(&ac
->list
);
1315 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
1316 list_del(&tid
->list
);
1318 ath_tid_drain(sc
, txq
, tid
);
1323 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1325 struct ath_hw
*ah
= sc
->sc_ah
;
1326 struct ath9k_tx_queue_info qi
;
1327 static const int subtype_txq_to_hwq
[] = {
1328 [WME_AC_BE
] = ATH_TXQ_AC_BE
,
1329 [WME_AC_BK
] = ATH_TXQ_AC_BK
,
1330 [WME_AC_VI
] = ATH_TXQ_AC_VI
,
1331 [WME_AC_VO
] = ATH_TXQ_AC_VO
,
1335 memset(&qi
, 0, sizeof(qi
));
1336 qi
.tqi_subtype
= subtype_txq_to_hwq
[subtype
];
1337 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1338 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1339 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1340 qi
.tqi_physCompBuf
= 0;
1343 * Enable interrupts only for EOL and DESC conditions.
1344 * We mark tx descriptors to receive a DESC interrupt
1345 * when a tx queue gets deep; otherwise waiting for the
1346 * EOL to reap descriptors. Note that this is done to
1347 * reduce interrupt load and this only defers reaping
1348 * descriptors, never transmitting frames. Aside from
1349 * reducing interrupts this also permits more concurrency.
1350 * The only potential downside is if the tx queue backs
1351 * up in which case the top half of the kernel may backup
1352 * due to a lack of tx descriptors.
1354 * The UAPSD queue is an exception, since we take a desc-
1355 * based intr on the EOSP frames.
1357 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1358 qi
.tqi_qflags
= TXQ_FLAG_TXINT_ENABLE
;
1360 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1361 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1363 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1364 TXQ_FLAG_TXDESCINT_ENABLE
;
1366 axq_qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1367 if (axq_qnum
== -1) {
1369 * NB: don't print a message, this happens
1370 * normally on parts with too few tx queues
1374 if (!ATH_TXQ_SETUP(sc
, axq_qnum
)) {
1375 struct ath_txq
*txq
= &sc
->tx
.txq
[axq_qnum
];
1377 txq
->axq_qnum
= axq_qnum
;
1378 txq
->mac80211_qnum
= -1;
1379 txq
->axq_link
= NULL
;
1380 __skb_queue_head_init(&txq
->complete_q
);
1381 INIT_LIST_HEAD(&txq
->axq_q
);
1382 INIT_LIST_HEAD(&txq
->axq_acq
);
1383 spin_lock_init(&txq
->axq_lock
);
1385 txq
->axq_ampdu_depth
= 0;
1386 txq
->axq_tx_inprogress
= false;
1387 sc
->tx
.txqsetup
|= 1<<axq_qnum
;
1389 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
1390 for (i
= 0; i
< ATH_TXFIFO_DEPTH
; i
++)
1391 INIT_LIST_HEAD(&txq
->txq_fifo
[i
]);
1393 return &sc
->tx
.txq
[axq_qnum
];
1396 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
1397 struct ath9k_tx_queue_info
*qinfo
)
1399 struct ath_hw
*ah
= sc
->sc_ah
;
1401 struct ath9k_tx_queue_info qi
;
1403 if (qnum
== sc
->beacon
.beaconq
) {
1405 * XXX: for beacon queue, we just save the parameter.
1406 * It will be picked up by ath_beaconq_config when
1409 sc
->beacon
.beacon_qi
= *qinfo
;
1413 BUG_ON(sc
->tx
.txq
[qnum
].axq_qnum
!= qnum
);
1415 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
1416 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
1417 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
1418 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
1419 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
1420 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
1422 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
1423 ath_err(ath9k_hw_common(sc
->sc_ah
),
1424 "Unable to update hardware queue %u!\n", qnum
);
1427 ath9k_hw_resettxqueue(ah
, qnum
);
1433 int ath_cabq_update(struct ath_softc
*sc
)
1435 struct ath9k_tx_queue_info qi
;
1436 struct ath_beacon_config
*cur_conf
= &sc
->cur_beacon_conf
;
1437 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
1439 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
1441 * Ensure the readytime % is within the bounds.
1443 if (sc
->config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
1444 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
1445 else if (sc
->config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
1446 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
1448 qi
.tqi_readyTime
= (cur_conf
->beacon_interval
*
1449 sc
->config
.cabqReadytime
) / 100;
1450 ath_txq_update(sc
, qnum
, &qi
);
1455 static bool bf_is_ampdu_not_probing(struct ath_buf
*bf
)
1457 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1458 return bf_isampdu(bf
) && !(info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
);
1461 static void ath_drain_txq_list(struct ath_softc
*sc
, struct ath_txq
*txq
,
1462 struct list_head
*list
, bool retry_tx
)
1464 struct ath_buf
*bf
, *lastbf
;
1465 struct list_head bf_head
;
1466 struct ath_tx_status ts
;
1468 memset(&ts
, 0, sizeof(ts
));
1469 ts
.ts_status
= ATH9K_TX_FLUSH
;
1470 INIT_LIST_HEAD(&bf_head
);
1472 while (!list_empty(list
)) {
1473 bf
= list_first_entry(list
, struct ath_buf
, list
);
1476 list_del(&bf
->list
);
1478 ath_tx_return_buffer(sc
, bf
);
1482 lastbf
= bf
->bf_lastbf
;
1483 list_cut_position(&bf_head
, list
, &lastbf
->list
);
1486 if (bf_is_ampdu_not_probing(bf
))
1487 txq
->axq_ampdu_depth
--;
1490 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, &ts
, 0,
1493 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
1498 * Drain a given TX queue (could be Beacon or Data)
1500 * This assumes output has been stopped and
1501 * we do not need to block ath_tx_tasklet.
1503 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
, bool retry_tx
)
1505 ath_txq_lock(sc
, txq
);
1507 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1508 int idx
= txq
->txq_tailidx
;
1510 while (!list_empty(&txq
->txq_fifo
[idx
])) {
1511 ath_drain_txq_list(sc
, txq
, &txq
->txq_fifo
[idx
],
1514 INCR(idx
, ATH_TXFIFO_DEPTH
);
1516 txq
->txq_tailidx
= idx
;
1519 txq
->axq_link
= NULL
;
1520 txq
->axq_tx_inprogress
= false;
1521 ath_drain_txq_list(sc
, txq
, &txq
->axq_q
, retry_tx
);
1523 /* flush any pending frames if aggregation is enabled */
1524 if ((sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) && !retry_tx
)
1525 ath_txq_drain_pending_buffers(sc
, txq
);
1527 ath_txq_unlock_complete(sc
, txq
);
1530 bool ath_drain_all_txq(struct ath_softc
*sc
, bool retry_tx
)
1532 struct ath_hw
*ah
= sc
->sc_ah
;
1533 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1534 struct ath_txq
*txq
;
1538 if (sc
->sc_flags
& SC_OP_INVALID
)
1541 ath9k_hw_abort_tx_dma(ah
);
1543 /* Check if any queue remains active */
1544 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1545 if (!ATH_TXQ_SETUP(sc
, i
))
1548 if (ath9k_hw_numtxpending(ah
, sc
->tx
.txq
[i
].axq_qnum
))
1553 ath_err(common
, "Failed to stop TX DMA, queues=0x%03x!\n", npend
);
1555 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1556 if (!ATH_TXQ_SETUP(sc
, i
))
1560 * The caller will resume queues with ieee80211_wake_queues.
1561 * Mark the queue as not stopped to prevent ath_tx_complete
1562 * from waking the queue too early.
1564 txq
= &sc
->tx
.txq
[i
];
1565 txq
->stopped
= false;
1566 ath_draintxq(sc
, txq
, retry_tx
);
1572 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1574 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1575 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1578 /* For each axq_acq entry, for each tid, try to schedule packets
1579 * for transmit until ampdu_depth has reached min Q depth.
1581 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1583 struct ath_atx_ac
*ac
, *ac_tmp
, *last_ac
;
1584 struct ath_atx_tid
*tid
, *last_tid
;
1586 if (work_pending(&sc
->hw_reset_work
) || list_empty(&txq
->axq_acq
) ||
1587 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1590 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
1591 last_ac
= list_entry(txq
->axq_acq
.prev
, struct ath_atx_ac
, list
);
1593 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1594 last_tid
= list_entry(ac
->tid_q
.prev
, struct ath_atx_tid
, list
);
1595 list_del(&ac
->list
);
1598 while (!list_empty(&ac
->tid_q
)) {
1599 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
,
1601 list_del(&tid
->list
);
1607 ath_tx_sched_aggr(sc
, txq
, tid
);
1610 * add tid to round-robin queue if more frames
1611 * are pending for the tid
1613 if (!skb_queue_empty(&tid
->buf_q
))
1614 ath_tx_queue_tid(txq
, tid
);
1616 if (tid
== last_tid
||
1617 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1621 if (!list_empty(&ac
->tid_q
) && !ac
->sched
) {
1623 list_add_tail(&ac
->list
, &txq
->axq_acq
);
1626 if (ac
== last_ac
||
1627 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1637 * Insert a chain of ath_buf (descriptors) on a txq and
1638 * assume the descriptors are already chained together by caller.
1640 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1641 struct list_head
*head
, bool internal
)
1643 struct ath_hw
*ah
= sc
->sc_ah
;
1644 struct ath_common
*common
= ath9k_hw_common(ah
);
1645 struct ath_buf
*bf
, *bf_last
;
1646 bool puttxbuf
= false;
1650 * Insert the frame on the outbound list and
1651 * pass it on to the hardware.
1654 if (list_empty(head
))
1657 edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1658 bf
= list_first_entry(head
, struct ath_buf
, list
);
1659 bf_last
= list_entry(head
->prev
, struct ath_buf
, list
);
1661 ath_dbg(common
, QUEUE
, "qnum: %d, txq depth: %d\n",
1662 txq
->axq_qnum
, txq
->axq_depth
);
1664 if (edma
&& list_empty(&txq
->txq_fifo
[txq
->txq_headidx
])) {
1665 list_splice_tail_init(head
, &txq
->txq_fifo
[txq
->txq_headidx
]);
1666 INCR(txq
->txq_headidx
, ATH_TXFIFO_DEPTH
);
1669 list_splice_tail_init(head
, &txq
->axq_q
);
1671 if (txq
->axq_link
) {
1672 ath9k_hw_set_desc_link(ah
, txq
->axq_link
, bf
->bf_daddr
);
1673 ath_dbg(common
, XMIT
, "link[%u] (%p)=%llx (%p)\n",
1674 txq
->axq_qnum
, txq
->axq_link
,
1675 ito64(bf
->bf_daddr
), bf
->bf_desc
);
1679 txq
->axq_link
= bf_last
->bf_desc
;
1683 TX_STAT_INC(txq
->axq_qnum
, puttxbuf
);
1684 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1685 ath_dbg(common
, XMIT
, "TXDP[%u] = %llx (%p)\n",
1686 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
1690 TX_STAT_INC(txq
->axq_qnum
, txstart
);
1691 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
1696 if (bf_is_ampdu_not_probing(bf
))
1697 txq
->axq_ampdu_depth
++;
1701 static void ath_tx_send_ampdu(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
1702 struct sk_buff
*skb
, struct ath_tx_control
*txctl
)
1704 struct ath_frame_info
*fi
= get_frame_info(skb
);
1705 struct list_head bf_head
;
1709 * Do not queue to h/w when any of the following conditions is true:
1710 * - there are pending frames in software queue
1711 * - the TID is currently paused for ADDBA/BAR request
1712 * - seqno is not within block-ack window
1713 * - h/w queue depth exceeds low water mark
1715 if (!skb_queue_empty(&tid
->buf_q
) || tid
->paused
||
1716 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, tid
->seq_next
) ||
1717 txctl
->txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1719 * Add this frame to software queue for scheduling later
1722 TX_STAT_INC(txctl
->txq
->axq_qnum
, a_queued_sw
);
1723 __skb_queue_tail(&tid
->buf_q
, skb
);
1724 if (!txctl
->an
|| !txctl
->an
->sleeping
)
1725 ath_tx_queue_tid(txctl
->txq
, tid
);
1729 bf
= ath_tx_setup_buffer(sc
, txctl
->txq
, tid
, skb
);
1733 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1734 INIT_LIST_HEAD(&bf_head
);
1735 list_add(&bf
->list
, &bf_head
);
1737 /* Add sub-frame to BAW */
1738 ath_tx_addto_baw(sc
, tid
, bf
->bf_state
.seqno
);
1740 /* Queue to h/w without aggregation */
1741 TX_STAT_INC(txctl
->txq
->axq_qnum
, a_queued_hw
);
1743 ath_tx_fill_desc(sc
, bf
, txctl
->txq
, fi
->framelen
);
1744 ath_tx_txqaddbuf(sc
, txctl
->txq
, &bf_head
, false);
1747 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1748 struct ath_atx_tid
*tid
, struct sk_buff
*skb
)
1750 struct ath_frame_info
*fi
= get_frame_info(skb
);
1751 struct list_head bf_head
;
1756 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
1761 INIT_LIST_HEAD(&bf_head
);
1762 list_add_tail(&bf
->list
, &bf_head
);
1763 bf
->bf_state
.bf_type
= 0;
1766 ath_tx_fill_desc(sc
, bf
, txq
, fi
->framelen
);
1767 ath_tx_txqaddbuf(sc
, txq
, &bf_head
, false);
1768 TX_STAT_INC(txq
->axq_qnum
, queued
);
1771 static void setup_frame_info(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1774 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1775 struct ieee80211_sta
*sta
= tx_info
->control
.sta
;
1776 struct ieee80211_key_conf
*hw_key
= tx_info
->control
.hw_key
;
1777 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1778 struct ath_frame_info
*fi
= get_frame_info(skb
);
1779 struct ath_node
*an
= NULL
;
1780 enum ath9k_key_type keytype
;
1782 keytype
= ath9k_cmn_get_hw_crypto_keytype(skb
);
1785 an
= (struct ath_node
*) sta
->drv_priv
;
1787 memset(fi
, 0, sizeof(*fi
));
1789 fi
->keyix
= hw_key
->hw_key_idx
;
1790 else if (an
&& ieee80211_is_data(hdr
->frame_control
) && an
->ps_key
> 0)
1791 fi
->keyix
= an
->ps_key
;
1793 fi
->keyix
= ATH9K_TXKEYIX_INVALID
;
1794 fi
->keytype
= keytype
;
1795 fi
->framelen
= framelen
;
1798 u8
ath_txchainmask_reduction(struct ath_softc
*sc
, u8 chainmask
, u32 rate
)
1800 struct ath_hw
*ah
= sc
->sc_ah
;
1801 struct ath9k_channel
*curchan
= ah
->curchan
;
1802 if ((ah
->caps
.hw_caps
& ATH9K_HW_CAP_APM
) &&
1803 (curchan
->channelFlags
& CHANNEL_5GHZ
) &&
1804 (chainmask
== 0x7) && (rate
< 0x90))
1811 * Assign a descriptor (and sequence number if necessary,
1812 * and map buffer for DMA. Frees skb on error
1814 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
1815 struct ath_txq
*txq
,
1816 struct ath_atx_tid
*tid
,
1817 struct sk_buff
*skb
)
1819 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1820 struct ath_frame_info
*fi
= get_frame_info(skb
);
1821 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1825 bf
= ath_tx_get_buffer(sc
);
1827 ath_dbg(common
, XMIT
, "TX buffers are full\n");
1831 ATH_TXBUF_RESET(bf
);
1834 seqno
= tid
->seq_next
;
1835 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<< IEEE80211_SEQ_SEQ_SHIFT
);
1836 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
1837 bf
->bf_state
.seqno
= seqno
;
1842 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
1843 skb
->len
, DMA_TO_DEVICE
);
1844 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_buf_addr
))) {
1846 bf
->bf_buf_addr
= 0;
1847 ath_err(ath9k_hw_common(sc
->sc_ah
),
1848 "dma_mapping_error() on TX\n");
1849 ath_tx_return_buffer(sc
, bf
);
1858 dev_kfree_skb_any(skb
);
1862 /* FIXME: tx power */
1863 static void ath_tx_start_dma(struct ath_softc
*sc
, struct sk_buff
*skb
,
1864 struct ath_tx_control
*txctl
)
1866 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1867 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1868 struct ath_atx_tid
*tid
= NULL
;
1872 if ((sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) && txctl
->an
&&
1873 ieee80211_is_data_qos(hdr
->frame_control
)) {
1874 tidno
= ieee80211_get_qos_ctl(hdr
)[0] &
1875 IEEE80211_QOS_CTL_TID_MASK
;
1876 tid
= ATH_AN_2_TID(txctl
->an
, tidno
);
1878 WARN_ON(tid
->ac
->txq
!= txctl
->txq
);
1881 if ((tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) && tid
) {
1883 * Try aggregation if it's a unicast data frame
1884 * and the destination is HT capable.
1886 ath_tx_send_ampdu(sc
, tid
, skb
, txctl
);
1888 bf
= ath_tx_setup_buffer(sc
, txctl
->txq
, tid
, skb
);
1892 bf
->bf_state
.bfs_paprd
= txctl
->paprd
;
1895 bf
->bf_state
.bfs_paprd_timestamp
= jiffies
;
1897 ath_tx_send_normal(sc
, txctl
->txq
, tid
, skb
);
1901 /* Upon failure caller should free skb */
1902 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1903 struct ath_tx_control
*txctl
)
1905 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
1906 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1907 struct ieee80211_sta
*sta
= info
->control
.sta
;
1908 struct ieee80211_vif
*vif
= info
->control
.vif
;
1909 struct ath_softc
*sc
= hw
->priv
;
1910 struct ath_txq
*txq
= txctl
->txq
;
1911 int padpos
, padsize
;
1912 int frmlen
= skb
->len
+ FCS_LEN
;
1915 /* NOTE: sta can be NULL according to net/mac80211.h */
1917 txctl
->an
= (struct ath_node
*)sta
->drv_priv
;
1919 if (info
->control
.hw_key
)
1920 frmlen
+= info
->control
.hw_key
->icv_len
;
1923 * As a temporary workaround, assign seq# here; this will likely need
1924 * to be cleaned up to work better with Beacon transmission and virtual
1927 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
1928 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
1929 sc
->tx
.seq_no
+= 0x10;
1930 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
1931 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
1934 /* Add the padding after the header if this is not already done */
1935 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1936 padsize
= padpos
& 3;
1937 if (padsize
&& skb
->len
> padpos
) {
1938 if (skb_headroom(skb
) < padsize
)
1941 skb_push(skb
, padsize
);
1942 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
1943 hdr
= (struct ieee80211_hdr
*) skb
->data
;
1946 if ((vif
&& vif
->type
!= NL80211_IFTYPE_AP
&&
1947 vif
->type
!= NL80211_IFTYPE_AP_VLAN
) ||
1948 !ieee80211_is_data(hdr
->frame_control
))
1949 info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1951 setup_frame_info(hw
, skb
, frmlen
);
1954 * At this point, the vif, hw_key and sta pointers in the tx control
1955 * info are no longer valid (overwritten by the ath_frame_info data.
1958 q
= skb_get_queue_mapping(skb
);
1960 ath_txq_lock(sc
, txq
);
1961 if (txq
== sc
->tx
.txq_map
[q
] &&
1962 ++txq
->pending_frames
> ATH_MAX_QDEPTH
&& !txq
->stopped
) {
1963 ieee80211_stop_queue(sc
->hw
, q
);
1964 txq
->stopped
= true;
1967 ath_tx_start_dma(sc
, skb
, txctl
);
1969 ath_txq_unlock(sc
, txq
);
1978 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
1979 int tx_flags
, struct ath_txq
*txq
)
1981 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1982 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1983 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
1984 int q
, padpos
, padsize
;
1986 ath_dbg(common
, XMIT
, "TX complete: skb: %p\n", skb
);
1988 if (!(tx_flags
& ATH_TX_ERROR
))
1989 /* Frame was ACKed */
1990 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
1992 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1993 padsize
= padpos
& 3;
1994 if (padsize
&& skb
->len
>padpos
+padsize
) {
1996 * Remove MAC header padding before giving the frame back to
1999 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
2000 skb_pull(skb
, padsize
);
2003 if ((sc
->ps_flags
& PS_WAIT_FOR_TX_ACK
) && !txq
->axq_depth
) {
2004 sc
->ps_flags
&= ~PS_WAIT_FOR_TX_ACK
;
2006 "Going back to sleep after having received TX status (0x%lx)\n",
2007 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
2009 PS_WAIT_FOR_PSPOLL_DATA
|
2010 PS_WAIT_FOR_TX_ACK
));
2013 q
= skb_get_queue_mapping(skb
);
2014 if (txq
== sc
->tx
.txq_map
[q
]) {
2015 if (WARN_ON(--txq
->pending_frames
< 0))
2016 txq
->pending_frames
= 0;
2018 if (txq
->stopped
&& txq
->pending_frames
< ATH_MAX_QDEPTH
) {
2019 ieee80211_wake_queue(sc
->hw
, q
);
2020 txq
->stopped
= false;
2024 __skb_queue_tail(&txq
->complete_q
, skb
);
2027 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
2028 struct ath_txq
*txq
, struct list_head
*bf_q
,
2029 struct ath_tx_status
*ts
, int txok
)
2031 struct sk_buff
*skb
= bf
->bf_mpdu
;
2032 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2033 unsigned long flags
;
2037 tx_flags
|= ATH_TX_ERROR
;
2039 if (ts
->ts_status
& ATH9K_TXERR_FILT
)
2040 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
2042 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
, skb
->len
, DMA_TO_DEVICE
);
2043 bf
->bf_buf_addr
= 0;
2045 if (bf
->bf_state
.bfs_paprd
) {
2046 if (time_after(jiffies
,
2047 bf
->bf_state
.bfs_paprd_timestamp
+
2048 msecs_to_jiffies(ATH_PAPRD_TIMEOUT
)))
2049 dev_kfree_skb_any(skb
);
2051 complete(&sc
->paprd_complete
);
2053 ath_debug_stat_tx(sc
, bf
, ts
, txq
, tx_flags
);
2054 ath_tx_complete(sc
, skb
, tx_flags
, txq
);
2056 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2057 * accidentally reference it later.
2062 * Return the list of ath_buf of this mpdu to free queue
2064 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
2065 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
2066 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
2069 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
2070 struct ath_tx_status
*ts
, int nframes
, int nbad
,
2073 struct sk_buff
*skb
= bf
->bf_mpdu
;
2074 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2075 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2076 struct ieee80211_hw
*hw
= sc
->hw
;
2077 struct ath_hw
*ah
= sc
->sc_ah
;
2081 tx_info
->status
.ack_signal
= ts
->ts_rssi
;
2083 tx_rateindex
= ts
->ts_rateindex
;
2084 WARN_ON(tx_rateindex
>= hw
->max_rates
);
2086 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
2087 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
2089 BUG_ON(nbad
> nframes
);
2091 tx_info
->status
.ampdu_len
= nframes
;
2092 tx_info
->status
.ampdu_ack_len
= nframes
- nbad
;
2094 if ((ts
->ts_status
& ATH9K_TXERR_FILT
) == 0 &&
2095 (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
) == 0) {
2097 * If an underrun error is seen assume it as an excessive
2098 * retry only if max frame trigger level has been reached
2099 * (2 KB for single stream, and 4 KB for dual stream).
2100 * Adjust the long retry as if the frame was tried
2101 * hw->max_rate_tries times to affect how rate control updates
2102 * PER for the failed rate.
2103 * In case of congestion on the bus penalizing this type of
2104 * underruns should help hardware actually transmit new frames
2105 * successfully by eventually preferring slower rates.
2106 * This itself should also alleviate congestion on the bus.
2108 if (unlikely(ts
->ts_flags
& (ATH9K_TX_DATA_UNDERRUN
|
2109 ATH9K_TX_DELIM_UNDERRUN
)) &&
2110 ieee80211_is_data(hdr
->frame_control
) &&
2111 ah
->tx_trig_level
>= sc
->sc_ah
->config
.max_txtrig_level
)
2112 tx_info
->status
.rates
[tx_rateindex
].count
=
2116 for (i
= tx_rateindex
+ 1; i
< hw
->max_rates
; i
++) {
2117 tx_info
->status
.rates
[i
].count
= 0;
2118 tx_info
->status
.rates
[i
].idx
= -1;
2121 tx_info
->status
.rates
[tx_rateindex
].count
= ts
->ts_longretry
+ 1;
2124 static void ath_tx_process_buffer(struct ath_softc
*sc
, struct ath_txq
*txq
,
2125 struct ath_tx_status
*ts
, struct ath_buf
*bf
,
2126 struct list_head
*bf_head
)
2131 txok
= !(ts
->ts_status
& ATH9K_TXERR_MASK
);
2132 txq
->axq_tx_inprogress
= false;
2133 if (bf_is_ampdu_not_probing(bf
))
2134 txq
->axq_ampdu_depth
--;
2136 if (!bf_isampdu(bf
)) {
2137 ath_tx_rc_status(sc
, bf
, ts
, 1, txok
? 0 : 1, txok
);
2138 ath_tx_complete_buf(sc
, bf
, txq
, bf_head
, ts
, txok
);
2140 ath_tx_complete_aggr(sc
, txq
, bf
, bf_head
, ts
, txok
, true);
2142 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
)
2143 ath_txq_schedule(sc
, txq
);
2146 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2148 struct ath_hw
*ah
= sc
->sc_ah
;
2149 struct ath_common
*common
= ath9k_hw_common(ah
);
2150 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
2151 struct list_head bf_head
;
2152 struct ath_desc
*ds
;
2153 struct ath_tx_status ts
;
2156 ath_dbg(common
, QUEUE
, "tx queue %d (%x), link %p\n",
2157 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
2160 ath_txq_lock(sc
, txq
);
2162 if (work_pending(&sc
->hw_reset_work
))
2165 if (list_empty(&txq
->axq_q
)) {
2166 txq
->axq_link
= NULL
;
2167 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
)
2168 ath_txq_schedule(sc
, txq
);
2171 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2174 * There is a race condition that a BH gets scheduled
2175 * after sw writes TxE and before hw re-load the last
2176 * descriptor to get the newly chained one.
2177 * Software must keep the last DONE descriptor as a
2178 * holding descriptor - software does so by marking
2179 * it with the STALE flag.
2184 if (list_is_last(&bf_held
->list
, &txq
->axq_q
))
2187 bf
= list_entry(bf_held
->list
.next
, struct ath_buf
,
2191 lastbf
= bf
->bf_lastbf
;
2192 ds
= lastbf
->bf_desc
;
2194 memset(&ts
, 0, sizeof(ts
));
2195 status
= ath9k_hw_txprocdesc(ah
, ds
, &ts
);
2196 if (status
== -EINPROGRESS
)
2199 TX_STAT_INC(txq
->axq_qnum
, txprocdesc
);
2202 * Remove ath_buf's of the same transmit unit from txq,
2203 * however leave the last descriptor back as the holding
2204 * descriptor for hw.
2206 lastbf
->bf_stale
= true;
2207 INIT_LIST_HEAD(&bf_head
);
2208 if (!list_is_singular(&lastbf
->list
))
2209 list_cut_position(&bf_head
,
2210 &txq
->axq_q
, lastbf
->list
.prev
);
2213 list_del(&bf_held
->list
);
2214 ath_tx_return_buffer(sc
, bf_held
);
2217 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2219 ath_txq_unlock_complete(sc
, txq
);
2222 static void ath_tx_complete_poll_work(struct work_struct
*work
)
2224 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
2225 tx_complete_work
.work
);
2226 struct ath_txq
*txq
;
2228 bool needreset
= false;
2229 #ifdef CONFIG_ATH9K_DEBUGFS
2230 sc
->tx_complete_poll_work_seen
++;
2233 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
2234 if (ATH_TXQ_SETUP(sc
, i
)) {
2235 txq
= &sc
->tx
.txq
[i
];
2236 ath_txq_lock(sc
, txq
);
2237 if (txq
->axq_depth
) {
2238 if (txq
->axq_tx_inprogress
) {
2240 ath_txq_unlock(sc
, txq
);
2243 txq
->axq_tx_inprogress
= true;
2246 ath_txq_unlock_complete(sc
, txq
);
2250 ath_dbg(ath9k_hw_common(sc
->sc_ah
), RESET
,
2251 "tx hung, resetting the chip\n");
2252 RESET_STAT_INC(sc
, RESET_TYPE_TX_HANG
);
2253 ieee80211_queue_work(sc
->hw
, &sc
->hw_reset_work
);
2256 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2257 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT
));
2262 void ath_tx_tasklet(struct ath_softc
*sc
)
2265 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2267 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2269 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2270 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2271 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2275 void ath_tx_edma_tasklet(struct ath_softc
*sc
)
2277 struct ath_tx_status ts
;
2278 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2279 struct ath_hw
*ah
= sc
->sc_ah
;
2280 struct ath_txq
*txq
;
2281 struct ath_buf
*bf
, *lastbf
;
2282 struct list_head bf_head
;
2286 if (work_pending(&sc
->hw_reset_work
))
2289 status
= ath9k_hw_txprocdesc(ah
, NULL
, (void *)&ts
);
2290 if (status
== -EINPROGRESS
)
2292 if (status
== -EIO
) {
2293 ath_dbg(common
, XMIT
, "Error processing tx status\n");
2297 /* Process beacon completions separately */
2298 if (ts
.qid
== sc
->beacon
.beaconq
) {
2299 sc
->beacon
.tx_processed
= true;
2300 sc
->beacon
.tx_last
= !(ts
.ts_status
& ATH9K_TXERR_MASK
);
2304 txq
= &sc
->tx
.txq
[ts
.qid
];
2306 ath_txq_lock(sc
, txq
);
2308 if (list_empty(&txq
->txq_fifo
[txq
->txq_tailidx
])) {
2309 ath_txq_unlock(sc
, txq
);
2313 bf
= list_first_entry(&txq
->txq_fifo
[txq
->txq_tailidx
],
2314 struct ath_buf
, list
);
2315 lastbf
= bf
->bf_lastbf
;
2317 INIT_LIST_HEAD(&bf_head
);
2318 list_cut_position(&bf_head
, &txq
->txq_fifo
[txq
->txq_tailidx
],
2321 if (list_empty(&txq
->txq_fifo
[txq
->txq_tailidx
])) {
2322 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
2324 if (!list_empty(&txq
->axq_q
)) {
2325 struct list_head bf_q
;
2327 INIT_LIST_HEAD(&bf_q
);
2328 txq
->axq_link
= NULL
;
2329 list_splice_tail_init(&txq
->axq_q
, &bf_q
);
2330 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, true);
2334 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2335 ath_txq_unlock_complete(sc
, txq
);
2343 static int ath_txstatus_setup(struct ath_softc
*sc
, int size
)
2345 struct ath_descdma
*dd
= &sc
->txsdma
;
2346 u8 txs_len
= sc
->sc_ah
->caps
.txs_len
;
2348 dd
->dd_desc_len
= size
* txs_len
;
2349 dd
->dd_desc
= dma_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
2350 &dd
->dd_desc_paddr
, GFP_KERNEL
);
2357 static int ath_tx_edma_init(struct ath_softc
*sc
)
2361 err
= ath_txstatus_setup(sc
, ATH_TXSTATUS_RING_SIZE
);
2363 ath9k_hw_setup_statusring(sc
->sc_ah
, sc
->txsdma
.dd_desc
,
2364 sc
->txsdma
.dd_desc_paddr
,
2365 ATH_TXSTATUS_RING_SIZE
);
2370 static void ath_tx_edma_cleanup(struct ath_softc
*sc
)
2372 struct ath_descdma
*dd
= &sc
->txsdma
;
2374 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
2378 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2380 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2383 spin_lock_init(&sc
->tx
.txbuflock
);
2385 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2389 "Failed to allocate tx descriptors: %d\n", error
);
2393 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2394 "beacon", ATH_BCBUF
, 1, 1);
2397 "Failed to allocate beacon descriptors: %d\n", error
);
2401 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath_tx_complete_poll_work
);
2403 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
2404 error
= ath_tx_edma_init(sc
);
2416 void ath_tx_cleanup(struct ath_softc
*sc
)
2418 if (sc
->beacon
.bdma
.dd_desc_len
!= 0)
2419 ath_descdma_cleanup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
);
2421 if (sc
->tx
.txdma
.dd_desc_len
!= 0)
2422 ath_descdma_cleanup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
);
2424 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
2425 ath_tx_edma_cleanup(sc
);
2428 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2430 struct ath_atx_tid
*tid
;
2431 struct ath_atx_ac
*ac
;
2434 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2435 tidno
< WME_NUM_TID
;
2439 tid
->seq_start
= tid
->seq_next
= 0;
2440 tid
->baw_size
= WME_MAX_BA
;
2441 tid
->baw_head
= tid
->baw_tail
= 0;
2443 tid
->paused
= false;
2444 tid
->state
&= ~AGGR_CLEANUP
;
2445 __skb_queue_head_init(&tid
->buf_q
);
2446 acno
= TID_TO_WME_AC(tidno
);
2447 tid
->ac
= &an
->ac
[acno
];
2448 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2449 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2452 for (acno
= 0, ac
= &an
->ac
[acno
];
2453 acno
< WME_NUM_AC
; acno
++, ac
++) {
2455 ac
->txq
= sc
->tx
.txq_map
[acno
];
2456 INIT_LIST_HEAD(&ac
->tid_q
);
2460 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2462 struct ath_atx_ac
*ac
;
2463 struct ath_atx_tid
*tid
;
2464 struct ath_txq
*txq
;
2467 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2468 tidno
< WME_NUM_TID
; tidno
++, tid
++) {
2473 ath_txq_lock(sc
, txq
);
2476 list_del(&tid
->list
);
2481 list_del(&ac
->list
);
2482 tid
->ac
->sched
= false;
2485 ath_tid_drain(sc
, txq
, tid
);
2486 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2487 tid
->state
&= ~AGGR_CLEANUP
;
2489 ath_txq_unlock(sc
, txq
);