2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
105 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
107 switch (obj
->tiling_mode
) {
109 case I915_TILING_NONE
: return " ";
110 case I915_TILING_X
: return "X";
111 case I915_TILING_Y
: return "Y";
115 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
117 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
121 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
123 struct i915_vma
*vma
;
126 seq_printf(m
, "%pK: %s%s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
128 obj
->active
? "*" : " ",
130 get_tiling_flag(obj
),
131 get_global_flag(obj
),
132 obj
->base
.size
/ 1024,
133 obj
->base
.read_domains
,
134 obj
->base
.write_domain
,
135 i915_gem_request_get_seqno(obj
->last_read_req
),
136 i915_gem_request_get_seqno(obj
->last_write_req
),
137 i915_gem_request_get_seqno(obj
->last_fenced_req
),
138 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
139 obj
->dirty
? " dirty" : "",
140 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
142 seq_printf(m
, " (name: %d)", obj
->base
.name
);
143 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
144 if (vma
->pin_count
> 0)
147 seq_printf(m
, " (pinned x %d)", pin_count
);
148 if (obj
->pin_display
)
149 seq_printf(m
, " (display)");
150 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
151 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
152 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
153 if (!i915_is_ggtt(vma
->vm
))
157 seq_printf(m
, "gtt offset: %08llx, size: %08llx, type: %u)",
158 vma
->node
.start
, vma
->node
.size
,
159 vma
->ggtt_view
.type
);
162 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
163 if (obj
->pin_display
|| obj
->fault_mappable
) {
165 if (obj
->pin_display
)
167 if (obj
->fault_mappable
)
170 seq_printf(m
, " (%s mappable)", s
);
172 if (obj
->last_read_req
!= NULL
)
173 seq_printf(m
, " (%s)",
174 i915_gem_request_get_ring(obj
->last_read_req
)->name
);
175 if (obj
->frontbuffer_bits
)
176 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
179 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
181 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
182 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
186 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
188 struct drm_info_node
*node
= m
->private;
189 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
190 struct list_head
*head
;
191 struct drm_device
*dev
= node
->minor
->dev
;
192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
193 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
194 struct i915_vma
*vma
;
195 size_t total_obj_size
, total_gtt_size
;
198 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
202 /* FIXME: the user of this interface might want more than just GGTT */
205 seq_puts(m
, "Active:\n");
206 head
= &vm
->active_list
;
209 seq_puts(m
, "Inactive:\n");
210 head
= &vm
->inactive_list
;
213 mutex_unlock(&dev
->struct_mutex
);
217 total_obj_size
= total_gtt_size
= count
= 0;
218 list_for_each_entry(vma
, head
, mm_list
) {
220 describe_obj(m
, vma
->obj
);
222 total_obj_size
+= vma
->obj
->base
.size
;
223 total_gtt_size
+= vma
->node
.size
;
226 mutex_unlock(&dev
->struct_mutex
);
228 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
229 count
, total_obj_size
, total_gtt_size
);
233 static int obj_rank_by_stolen(void *priv
,
234 struct list_head
*A
, struct list_head
*B
)
236 struct drm_i915_gem_object
*a
=
237 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
238 struct drm_i915_gem_object
*b
=
239 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
241 return a
->stolen
->start
- b
->stolen
->start
;
244 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
246 struct drm_info_node
*node
= m
->private;
247 struct drm_device
*dev
= node
->minor
->dev
;
248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
249 struct drm_i915_gem_object
*obj
;
250 size_t total_obj_size
, total_gtt_size
;
254 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
258 total_obj_size
= total_gtt_size
= count
= 0;
259 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
260 if (obj
->stolen
== NULL
)
263 list_add(&obj
->obj_exec_link
, &stolen
);
265 total_obj_size
+= obj
->base
.size
;
266 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
269 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
270 if (obj
->stolen
== NULL
)
273 list_add(&obj
->obj_exec_link
, &stolen
);
275 total_obj_size
+= obj
->base
.size
;
278 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
279 seq_puts(m
, "Stolen:\n");
280 while (!list_empty(&stolen
)) {
281 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
283 describe_obj(m
, obj
);
285 list_del_init(&obj
->obj_exec_link
);
287 mutex_unlock(&dev
->struct_mutex
);
289 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
290 count
, total_obj_size
, total_gtt_size
);
294 #define count_objects(list, member) do { \
295 list_for_each_entry(obj, list, member) { \
296 size += i915_gem_obj_ggtt_size(obj); \
298 if (obj->map_and_fenceable) { \
299 mappable_size += i915_gem_obj_ggtt_size(obj); \
306 struct drm_i915_file_private
*file_priv
;
308 size_t total
, unbound
;
309 size_t global
, shared
;
310 size_t active
, inactive
;
313 static int per_file_stats(int id
, void *ptr
, void *data
)
315 struct drm_i915_gem_object
*obj
= ptr
;
316 struct file_stats
*stats
= data
;
317 struct i915_vma
*vma
;
320 stats
->total
+= obj
->base
.size
;
322 if (obj
->base
.name
|| obj
->base
.dma_buf
)
323 stats
->shared
+= obj
->base
.size
;
325 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
326 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
327 struct i915_hw_ppgtt
*ppgtt
;
329 if (!drm_mm_node_allocated(&vma
->node
))
332 if (i915_is_ggtt(vma
->vm
)) {
333 stats
->global
+= obj
->base
.size
;
337 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
338 if (ppgtt
->file_priv
!= stats
->file_priv
)
341 if (obj
->active
) /* XXX per-vma statistic */
342 stats
->active
+= obj
->base
.size
;
344 stats
->inactive
+= obj
->base
.size
;
349 if (i915_gem_obj_ggtt_bound(obj
)) {
350 stats
->global
+= obj
->base
.size
;
352 stats
->active
+= obj
->base
.size
;
354 stats
->inactive
+= obj
->base
.size
;
359 if (!list_empty(&obj
->global_list
))
360 stats
->unbound
+= obj
->base
.size
;
365 #define print_file_stats(m, name, stats) do { \
367 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
378 static void print_batch_pool_stats(struct seq_file
*m
,
379 struct drm_i915_private
*dev_priv
)
381 struct drm_i915_gem_object
*obj
;
382 struct file_stats stats
;
383 struct intel_engine_cs
*ring
;
386 memset(&stats
, 0, sizeof(stats
));
388 for_each_ring(ring
, dev_priv
, i
) {
389 for (j
= 0; j
< ARRAY_SIZE(ring
->batch_pool
.cache_list
); j
++) {
390 list_for_each_entry(obj
,
391 &ring
->batch_pool
.cache_list
[j
],
393 per_file_stats(0, obj
, &stats
);
397 print_file_stats(m
, "[k]batch pool", stats
);
400 #define count_vmas(list, member) do { \
401 list_for_each_entry(vma, list, member) { \
402 size += i915_gem_obj_ggtt_size(vma->obj); \
404 if (vma->obj->map_and_fenceable) { \
405 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
411 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
413 struct drm_info_node
*node
= m
->private;
414 struct drm_device
*dev
= node
->minor
->dev
;
415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
416 u32 count
, mappable_count
, purgeable_count
;
417 size_t size
, mappable_size
, purgeable_size
;
418 struct drm_i915_gem_object
*obj
;
419 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
420 struct drm_file
*file
;
421 struct i915_vma
*vma
;
424 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
428 seq_printf(m
, "%u objects, %zu bytes\n",
429 dev_priv
->mm
.object_count
,
430 dev_priv
->mm
.object_memory
);
432 size
= count
= mappable_size
= mappable_count
= 0;
433 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
434 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
435 count
, mappable_count
, size
, mappable_size
);
437 size
= count
= mappable_size
= mappable_count
= 0;
438 count_vmas(&vm
->active_list
, mm_list
);
439 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
440 count
, mappable_count
, size
, mappable_size
);
442 size
= count
= mappable_size
= mappable_count
= 0;
443 count_vmas(&vm
->inactive_list
, mm_list
);
444 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
445 count
, mappable_count
, size
, mappable_size
);
447 size
= count
= purgeable_size
= purgeable_count
= 0;
448 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
449 size
+= obj
->base
.size
, ++count
;
450 if (obj
->madv
== I915_MADV_DONTNEED
)
451 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
453 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
455 size
= count
= mappable_size
= mappable_count
= 0;
456 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
457 if (obj
->fault_mappable
) {
458 size
+= i915_gem_obj_ggtt_size(obj
);
461 if (obj
->pin_display
) {
462 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
465 if (obj
->madv
== I915_MADV_DONTNEED
) {
466 purgeable_size
+= obj
->base
.size
;
470 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
471 purgeable_count
, purgeable_size
);
472 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
473 mappable_count
, mappable_size
);
474 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
477 seq_printf(m
, "%zu [%lu] gtt total\n",
478 dev_priv
->gtt
.base
.total
,
479 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
482 print_batch_pool_stats(m
, dev_priv
);
483 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
484 struct file_stats stats
;
485 struct task_struct
*task
;
487 memset(&stats
, 0, sizeof(stats
));
488 stats
.file_priv
= file
->driver_priv
;
489 spin_lock(&file
->table_lock
);
490 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
491 spin_unlock(&file
->table_lock
);
493 * Although we have a valid reference on file->pid, that does
494 * not guarantee that the task_struct who called get_pid() is
495 * still alive (e.g. get_pid(current) => fork() => exit()).
496 * Therefore, we need to protect this ->comm access using RCU.
499 task
= pid_task(file
->pid
, PIDTYPE_PID
);
500 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
504 mutex_unlock(&dev
->struct_mutex
);
509 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
511 struct drm_info_node
*node
= m
->private;
512 struct drm_device
*dev
= node
->minor
->dev
;
513 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
515 struct drm_i915_gem_object
*obj
;
516 size_t total_obj_size
, total_gtt_size
;
519 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
523 total_obj_size
= total_gtt_size
= count
= 0;
524 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
525 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
529 describe_obj(m
, obj
);
531 total_obj_size
+= obj
->base
.size
;
532 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
536 mutex_unlock(&dev
->struct_mutex
);
538 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
539 count
, total_obj_size
, total_gtt_size
);
544 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
546 struct drm_info_node
*node
= m
->private;
547 struct drm_device
*dev
= node
->minor
->dev
;
548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
549 struct intel_crtc
*crtc
;
552 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
556 for_each_intel_crtc(dev
, crtc
) {
557 const char pipe
= pipe_name(crtc
->pipe
);
558 const char plane
= plane_name(crtc
->plane
);
559 struct intel_unpin_work
*work
;
561 spin_lock_irq(&dev
->event_lock
);
562 work
= crtc
->unpin_work
;
564 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
569 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
570 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
573 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
576 if (work
->flip_queued_req
) {
577 struct intel_engine_cs
*ring
=
578 i915_gem_request_get_ring(work
->flip_queued_req
);
580 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
582 i915_gem_request_get_seqno(work
->flip_queued_req
),
583 dev_priv
->next_seqno
,
584 ring
->get_seqno(ring
, true),
585 i915_gem_request_completed(work
->flip_queued_req
, true));
587 seq_printf(m
, "Flip not associated with any ring\n");
588 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
589 work
->flip_queued_vblank
,
590 work
->flip_ready_vblank
,
591 drm_crtc_vblank_count(&crtc
->base
));
592 if (work
->enable_stall_check
)
593 seq_puts(m
, "Stall check enabled, ");
595 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
596 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
598 if (INTEL_INFO(dev
)->gen
>= 4)
599 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
601 addr
= I915_READ(DSPADDR(crtc
->plane
));
602 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
604 if (work
->pending_flip_obj
) {
605 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
606 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
609 spin_unlock_irq(&dev
->event_lock
);
612 mutex_unlock(&dev
->struct_mutex
);
617 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
619 struct drm_info_node
*node
= m
->private;
620 struct drm_device
*dev
= node
->minor
->dev
;
621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
622 struct drm_i915_gem_object
*obj
;
623 struct intel_engine_cs
*ring
;
627 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
631 for_each_ring(ring
, dev_priv
, i
) {
632 for (j
= 0; j
< ARRAY_SIZE(ring
->batch_pool
.cache_list
); j
++) {
636 list_for_each_entry(obj
,
637 &ring
->batch_pool
.cache_list
[j
],
640 seq_printf(m
, "%s cache[%d]: %d objects\n",
641 ring
->name
, j
, count
);
643 list_for_each_entry(obj
,
644 &ring
->batch_pool
.cache_list
[j
],
647 describe_obj(m
, obj
);
655 seq_printf(m
, "total: %d\n", total
);
657 mutex_unlock(&dev
->struct_mutex
);
662 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
664 struct drm_info_node
*node
= m
->private;
665 struct drm_device
*dev
= node
->minor
->dev
;
666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
667 struct intel_engine_cs
*ring
;
668 struct drm_i915_gem_request
*rq
;
671 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
676 for_each_ring(ring
, dev_priv
, i
) {
680 list_for_each_entry(rq
, &ring
->request_list
, list
)
685 seq_printf(m
, "%s requests: %d\n", ring
->name
, count
);
686 list_for_each_entry(rq
, &ring
->request_list
, list
) {
687 struct task_struct
*task
;
692 task
= pid_task(rq
->pid
, PIDTYPE_PID
);
693 seq_printf(m
, " %x @ %d: %s [%d]\n",
695 (int) (jiffies
- rq
->emitted_jiffies
),
696 task
? task
->comm
: "<unknown>",
697 task
? task
->pid
: -1);
703 mutex_unlock(&dev
->struct_mutex
);
706 seq_puts(m
, "No requests\n");
711 static void i915_ring_seqno_info(struct seq_file
*m
,
712 struct intel_engine_cs
*ring
)
714 if (ring
->get_seqno
) {
715 seq_printf(m
, "Current sequence (%s): %x\n",
716 ring
->name
, ring
->get_seqno(ring
, false));
720 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
722 struct drm_info_node
*node
= m
->private;
723 struct drm_device
*dev
= node
->minor
->dev
;
724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
725 struct intel_engine_cs
*ring
;
728 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
731 intel_runtime_pm_get(dev_priv
);
733 for_each_ring(ring
, dev_priv
, i
)
734 i915_ring_seqno_info(m
, ring
);
736 intel_runtime_pm_put(dev_priv
);
737 mutex_unlock(&dev
->struct_mutex
);
743 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
745 struct drm_info_node
*node
= m
->private;
746 struct drm_device
*dev
= node
->minor
->dev
;
747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
748 struct intel_engine_cs
*ring
;
751 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
754 intel_runtime_pm_get(dev_priv
);
756 if (IS_CHERRYVIEW(dev
)) {
757 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
758 I915_READ(GEN8_MASTER_IRQ
));
760 seq_printf(m
, "Display IER:\t%08x\n",
762 seq_printf(m
, "Display IIR:\t%08x\n",
764 seq_printf(m
, "Display IIR_RW:\t%08x\n",
765 I915_READ(VLV_IIR_RW
));
766 seq_printf(m
, "Display IMR:\t%08x\n",
768 for_each_pipe(dev_priv
, pipe
)
769 seq_printf(m
, "Pipe %c stat:\t%08x\n",
771 I915_READ(PIPESTAT(pipe
)));
773 seq_printf(m
, "Port hotplug:\t%08x\n",
774 I915_READ(PORT_HOTPLUG_EN
));
775 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
776 I915_READ(VLV_DPFLIPSTAT
));
777 seq_printf(m
, "DPINVGTT:\t%08x\n",
778 I915_READ(DPINVGTT
));
780 for (i
= 0; i
< 4; i
++) {
781 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
782 i
, I915_READ(GEN8_GT_IMR(i
)));
783 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
784 i
, I915_READ(GEN8_GT_IIR(i
)));
785 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
786 i
, I915_READ(GEN8_GT_IER(i
)));
789 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
790 I915_READ(GEN8_PCU_IMR
));
791 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
792 I915_READ(GEN8_PCU_IIR
));
793 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
794 I915_READ(GEN8_PCU_IER
));
795 } else if (INTEL_INFO(dev
)->gen
>= 8) {
796 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
797 I915_READ(GEN8_MASTER_IRQ
));
799 for (i
= 0; i
< 4; i
++) {
800 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
801 i
, I915_READ(GEN8_GT_IMR(i
)));
802 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
803 i
, I915_READ(GEN8_GT_IIR(i
)));
804 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
805 i
, I915_READ(GEN8_GT_IER(i
)));
808 for_each_pipe(dev_priv
, pipe
) {
809 if (!intel_display_power_is_enabled(dev_priv
,
810 POWER_DOMAIN_PIPE(pipe
))) {
811 seq_printf(m
, "Pipe %c power disabled\n",
815 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
817 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
818 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
820 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
821 seq_printf(m
, "Pipe %c IER:\t%08x\n",
823 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
826 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
827 I915_READ(GEN8_DE_PORT_IMR
));
828 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
829 I915_READ(GEN8_DE_PORT_IIR
));
830 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
831 I915_READ(GEN8_DE_PORT_IER
));
833 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
834 I915_READ(GEN8_DE_MISC_IMR
));
835 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
836 I915_READ(GEN8_DE_MISC_IIR
));
837 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
838 I915_READ(GEN8_DE_MISC_IER
));
840 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
841 I915_READ(GEN8_PCU_IMR
));
842 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
843 I915_READ(GEN8_PCU_IIR
));
844 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
845 I915_READ(GEN8_PCU_IER
));
846 } else if (IS_VALLEYVIEW(dev
)) {
847 seq_printf(m
, "Display IER:\t%08x\n",
849 seq_printf(m
, "Display IIR:\t%08x\n",
851 seq_printf(m
, "Display IIR_RW:\t%08x\n",
852 I915_READ(VLV_IIR_RW
));
853 seq_printf(m
, "Display IMR:\t%08x\n",
855 for_each_pipe(dev_priv
, pipe
)
856 seq_printf(m
, "Pipe %c stat:\t%08x\n",
858 I915_READ(PIPESTAT(pipe
)));
860 seq_printf(m
, "Master IER:\t%08x\n",
861 I915_READ(VLV_MASTER_IER
));
863 seq_printf(m
, "Render IER:\t%08x\n",
865 seq_printf(m
, "Render IIR:\t%08x\n",
867 seq_printf(m
, "Render IMR:\t%08x\n",
870 seq_printf(m
, "PM IER:\t\t%08x\n",
871 I915_READ(GEN6_PMIER
));
872 seq_printf(m
, "PM IIR:\t\t%08x\n",
873 I915_READ(GEN6_PMIIR
));
874 seq_printf(m
, "PM IMR:\t\t%08x\n",
875 I915_READ(GEN6_PMIMR
));
877 seq_printf(m
, "Port hotplug:\t%08x\n",
878 I915_READ(PORT_HOTPLUG_EN
));
879 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
880 I915_READ(VLV_DPFLIPSTAT
));
881 seq_printf(m
, "DPINVGTT:\t%08x\n",
882 I915_READ(DPINVGTT
));
884 } else if (!HAS_PCH_SPLIT(dev
)) {
885 seq_printf(m
, "Interrupt enable: %08x\n",
887 seq_printf(m
, "Interrupt identity: %08x\n",
889 seq_printf(m
, "Interrupt mask: %08x\n",
891 for_each_pipe(dev_priv
, pipe
)
892 seq_printf(m
, "Pipe %c stat: %08x\n",
894 I915_READ(PIPESTAT(pipe
)));
896 seq_printf(m
, "North Display Interrupt enable: %08x\n",
898 seq_printf(m
, "North Display Interrupt identity: %08x\n",
900 seq_printf(m
, "North Display Interrupt mask: %08x\n",
902 seq_printf(m
, "South Display Interrupt enable: %08x\n",
904 seq_printf(m
, "South Display Interrupt identity: %08x\n",
906 seq_printf(m
, "South Display Interrupt mask: %08x\n",
908 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
910 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
912 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
915 for_each_ring(ring
, dev_priv
, i
) {
916 if (INTEL_INFO(dev
)->gen
>= 6) {
918 "Graphics Interrupt mask (%s): %08x\n",
919 ring
->name
, I915_READ_IMR(ring
));
921 i915_ring_seqno_info(m
, ring
);
923 intel_runtime_pm_put(dev_priv
);
924 mutex_unlock(&dev
->struct_mutex
);
929 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
931 struct drm_info_node
*node
= m
->private;
932 struct drm_device
*dev
= node
->minor
->dev
;
933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
936 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
940 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
941 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
942 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
943 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
945 seq_printf(m
, "Fence %d, pin count = %d, object = ",
946 i
, dev_priv
->fence_regs
[i
].pin_count
);
948 seq_puts(m
, "unused");
950 describe_obj(m
, obj
);
954 mutex_unlock(&dev
->struct_mutex
);
958 static int i915_hws_info(struct seq_file
*m
, void *data
)
960 struct drm_info_node
*node
= m
->private;
961 struct drm_device
*dev
= node
->minor
->dev
;
962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
963 struct intel_engine_cs
*ring
;
967 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
968 hws
= ring
->status_page
.page_addr
;
972 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
973 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
975 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
981 i915_error_state_write(struct file
*filp
,
982 const char __user
*ubuf
,
986 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
987 struct drm_device
*dev
= error_priv
->dev
;
990 DRM_DEBUG_DRIVER("Resetting error state\n");
992 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
996 i915_destroy_error_state(dev
);
997 mutex_unlock(&dev
->struct_mutex
);
1002 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1004 struct drm_device
*dev
= inode
->i_private
;
1005 struct i915_error_state_file_priv
*error_priv
;
1007 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1011 error_priv
->dev
= dev
;
1013 i915_error_state_get(dev
, error_priv
);
1015 file
->private_data
= error_priv
;
1020 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1022 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1024 i915_error_state_put(error_priv
);
1030 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1031 size_t count
, loff_t
*pos
)
1033 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1034 struct drm_i915_error_state_buf error_str
;
1036 ssize_t ret_count
= 0;
1039 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1043 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1047 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1054 *pos
= error_str
.start
+ ret_count
;
1056 i915_error_state_buf_release(&error_str
);
1057 return ret
?: ret_count
;
1060 static const struct file_operations i915_error_state_fops
= {
1061 .owner
= THIS_MODULE
,
1062 .open
= i915_error_state_open
,
1063 .read
= i915_error_state_read
,
1064 .write
= i915_error_state_write
,
1065 .llseek
= default_llseek
,
1066 .release
= i915_error_state_release
,
1070 i915_next_seqno_get(void *data
, u64
*val
)
1072 struct drm_device
*dev
= data
;
1073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1076 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1080 *val
= dev_priv
->next_seqno
;
1081 mutex_unlock(&dev
->struct_mutex
);
1087 i915_next_seqno_set(void *data
, u64 val
)
1089 struct drm_device
*dev
= data
;
1092 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1096 ret
= i915_gem_set_seqno(dev
, val
);
1097 mutex_unlock(&dev
->struct_mutex
);
1102 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1103 i915_next_seqno_get
, i915_next_seqno_set
,
1106 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1108 struct drm_info_node
*node
= m
->private;
1109 struct drm_device
*dev
= node
->minor
->dev
;
1110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1113 intel_runtime_pm_get(dev_priv
);
1115 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1118 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1119 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1121 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1122 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1123 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1125 seq_printf(m
, "Current P-state: %d\n",
1126 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1127 } else if (IS_GEN6(dev
) || (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) ||
1128 IS_BROADWELL(dev
) || IS_GEN9(dev
)) {
1129 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1130 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1131 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1132 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1133 u32 rpstat
, cagf
, reqf
;
1134 u32 rpupei
, rpcurup
, rpprevup
;
1135 u32 rpdownei
, rpcurdown
, rpprevdown
;
1136 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1139 /* RPSTAT1 is in the GT power well */
1140 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1144 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1146 reqf
= I915_READ(GEN6_RPNSWREQ
);
1150 reqf
&= ~GEN6_TURBO_DISABLE
;
1151 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1156 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1158 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1159 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1160 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1162 rpstat
= I915_READ(GEN6_RPSTAT1
);
1163 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1164 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1165 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1166 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1167 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1168 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1170 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1171 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1172 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1174 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1175 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1177 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1178 mutex_unlock(&dev
->struct_mutex
);
1180 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1181 pm_ier
= I915_READ(GEN6_PMIER
);
1182 pm_imr
= I915_READ(GEN6_PMIMR
);
1183 pm_isr
= I915_READ(GEN6_PMISR
);
1184 pm_iir
= I915_READ(GEN6_PMIIR
);
1185 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1187 pm_ier
= I915_READ(GEN8_GT_IER(2));
1188 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1189 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1190 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1191 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1193 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1194 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1195 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1196 seq_printf(m
, "Render p-state ratio: %d\n",
1197 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1198 seq_printf(m
, "Render p-state VID: %d\n",
1199 gt_perf_status
& 0xff);
1200 seq_printf(m
, "Render p-state limit: %d\n",
1201 rp_state_limits
& 0xff);
1202 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1203 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1204 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1205 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1206 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1207 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1208 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1209 GEN6_CURICONT_MASK
);
1210 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1211 GEN6_CURBSYTAVG_MASK
);
1212 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1213 GEN6_CURBSYTAVG_MASK
);
1214 seq_printf(m
, "Up threshold: %d%%\n",
1215 dev_priv
->rps
.up_threshold
);
1217 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1219 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1220 GEN6_CURBSYTAVG_MASK
);
1221 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1222 GEN6_CURBSYTAVG_MASK
);
1223 seq_printf(m
, "Down threshold: %d%%\n",
1224 dev_priv
->rps
.down_threshold
);
1226 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1227 max_freq
*= (IS_SKYLAKE(dev
) ? GEN9_FREQ_SCALER
: 1);
1228 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1229 intel_gpu_freq(dev_priv
, max_freq
));
1231 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1232 max_freq
*= (IS_SKYLAKE(dev
) ? GEN9_FREQ_SCALER
: 1);
1233 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1234 intel_gpu_freq(dev_priv
, max_freq
));
1236 max_freq
= rp_state_cap
& 0xff;
1237 max_freq
*= (IS_SKYLAKE(dev
) ? GEN9_FREQ_SCALER
: 1);
1238 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1239 intel_gpu_freq(dev_priv
, max_freq
));
1240 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1241 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1243 seq_printf(m
, "Current freq: %d MHz\n",
1244 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1245 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1246 seq_printf(m
, "Idle freq: %d MHz\n",
1247 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1248 seq_printf(m
, "Min freq: %d MHz\n",
1249 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1250 seq_printf(m
, "Max freq: %d MHz\n",
1251 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1253 "efficient (RPe) frequency: %d MHz\n",
1254 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1255 } else if (IS_VALLEYVIEW(dev
)) {
1258 mutex_lock(&dev_priv
->rps
.hw_lock
);
1259 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1260 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1261 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1263 seq_printf(m
, "actual GPU freq: %d MHz\n",
1264 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1266 seq_printf(m
, "current GPU freq: %d MHz\n",
1267 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1269 seq_printf(m
, "max GPU freq: %d MHz\n",
1270 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1272 seq_printf(m
, "min GPU freq: %d MHz\n",
1273 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1275 seq_printf(m
, "idle GPU freq: %d MHz\n",
1276 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1279 "efficient (RPe) frequency: %d MHz\n",
1280 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1281 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1283 seq_puts(m
, "no P-state info available\n");
1287 intel_runtime_pm_put(dev_priv
);
1291 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1293 struct drm_info_node
*node
= m
->private;
1294 struct drm_device
*dev
= node
->minor
->dev
;
1295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1296 struct intel_engine_cs
*ring
;
1297 u64 acthd
[I915_NUM_RINGS
];
1298 u32 seqno
[I915_NUM_RINGS
];
1301 if (!i915
.enable_hangcheck
) {
1302 seq_printf(m
, "Hangcheck disabled\n");
1306 intel_runtime_pm_get(dev_priv
);
1308 for_each_ring(ring
, dev_priv
, i
) {
1309 seqno
[i
] = ring
->get_seqno(ring
, false);
1310 acthd
[i
] = intel_ring_get_active_head(ring
);
1313 intel_runtime_pm_put(dev_priv
);
1315 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1316 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1317 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1320 seq_printf(m
, "Hangcheck inactive\n");
1322 for_each_ring(ring
, dev_priv
, i
) {
1323 seq_printf(m
, "%s:\n", ring
->name
);
1324 seq_printf(m
, "\tseqno = %x [current %x]\n",
1325 ring
->hangcheck
.seqno
, seqno
[i
]);
1326 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1327 (long long)ring
->hangcheck
.acthd
,
1328 (long long)acthd
[i
]);
1329 seq_printf(m
, "\tmax ACTHD = 0x%08llx\n",
1330 (long long)ring
->hangcheck
.max_acthd
);
1331 seq_printf(m
, "\tscore = %d\n", ring
->hangcheck
.score
);
1332 seq_printf(m
, "\taction = %d\n", ring
->hangcheck
.action
);
1338 static int ironlake_drpc_info(struct seq_file
*m
)
1340 struct drm_info_node
*node
= m
->private;
1341 struct drm_device
*dev
= node
->minor
->dev
;
1342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1343 u32 rgvmodectl
, rstdbyctl
;
1347 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1350 intel_runtime_pm_get(dev_priv
);
1352 rgvmodectl
= I915_READ(MEMMODECTL
);
1353 rstdbyctl
= I915_READ(RSTDBYCTL
);
1354 crstandvid
= I915_READ16(CRSTANDVID
);
1356 intel_runtime_pm_put(dev_priv
);
1357 mutex_unlock(&dev
->struct_mutex
);
1359 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1361 seq_printf(m
, "Boost freq: %d\n",
1362 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1363 MEMMODE_BOOST_FREQ_SHIFT
);
1364 seq_printf(m
, "HW control enabled: %s\n",
1365 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1366 seq_printf(m
, "SW control enabled: %s\n",
1367 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1368 seq_printf(m
, "Gated voltage change: %s\n",
1369 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1370 seq_printf(m
, "Starting frequency: P%d\n",
1371 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1372 seq_printf(m
, "Max P-state: P%d\n",
1373 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1374 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1375 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1376 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1377 seq_printf(m
, "Render standby enabled: %s\n",
1378 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1379 seq_puts(m
, "Current RS state: ");
1380 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1382 seq_puts(m
, "on\n");
1384 case RSX_STATUS_RC1
:
1385 seq_puts(m
, "RC1\n");
1387 case RSX_STATUS_RC1E
:
1388 seq_puts(m
, "RC1E\n");
1390 case RSX_STATUS_RS1
:
1391 seq_puts(m
, "RS1\n");
1393 case RSX_STATUS_RS2
:
1394 seq_puts(m
, "RS2 (RC6)\n");
1396 case RSX_STATUS_RS3
:
1397 seq_puts(m
, "RC3 (RC6+)\n");
1400 seq_puts(m
, "unknown\n");
1407 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1409 struct drm_info_node
*node
= m
->private;
1410 struct drm_device
*dev
= node
->minor
->dev
;
1411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1412 struct intel_uncore_forcewake_domain
*fw_domain
;
1415 spin_lock_irq(&dev_priv
->uncore
.lock
);
1416 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1417 seq_printf(m
, "%s.wake_count = %u\n",
1418 intel_uncore_forcewake_domain_to_str(i
),
1419 fw_domain
->wake_count
);
1421 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1426 static int vlv_drpc_info(struct seq_file
*m
)
1428 struct drm_info_node
*node
= m
->private;
1429 struct drm_device
*dev
= node
->minor
->dev
;
1430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1431 u32 rpmodectl1
, rcctl1
, pw_status
;
1433 intel_runtime_pm_get(dev_priv
);
1435 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1436 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1437 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1439 intel_runtime_pm_put(dev_priv
);
1441 seq_printf(m
, "Video Turbo Mode: %s\n",
1442 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1443 seq_printf(m
, "Turbo enabled: %s\n",
1444 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1445 seq_printf(m
, "HW control enabled: %s\n",
1446 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1447 seq_printf(m
, "SW control enabled: %s\n",
1448 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1449 GEN6_RP_MEDIA_SW_MODE
));
1450 seq_printf(m
, "RC6 Enabled: %s\n",
1451 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1452 GEN6_RC_CTL_EI_MODE(1))));
1453 seq_printf(m
, "Render Power Well: %s\n",
1454 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1455 seq_printf(m
, "Media Power Well: %s\n",
1456 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1458 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1459 I915_READ(VLV_GT_RENDER_RC6
));
1460 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1461 I915_READ(VLV_GT_MEDIA_RC6
));
1463 return i915_forcewake_domains(m
, NULL
);
1466 static int gen6_drpc_info(struct seq_file
*m
)
1468 struct drm_info_node
*node
= m
->private;
1469 struct drm_device
*dev
= node
->minor
->dev
;
1470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1471 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1472 unsigned forcewake_count
;
1475 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1478 intel_runtime_pm_get(dev_priv
);
1480 spin_lock_irq(&dev_priv
->uncore
.lock
);
1481 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1482 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1484 if (forcewake_count
) {
1485 seq_puts(m
, "RC information inaccurate because somebody "
1486 "holds a forcewake reference \n");
1488 /* NB: we cannot use forcewake, else we read the wrong values */
1489 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1491 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1494 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1495 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1497 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1498 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1499 mutex_unlock(&dev
->struct_mutex
);
1500 mutex_lock(&dev_priv
->rps
.hw_lock
);
1501 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1502 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1504 intel_runtime_pm_put(dev_priv
);
1506 seq_printf(m
, "Video Turbo Mode: %s\n",
1507 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1508 seq_printf(m
, "HW control enabled: %s\n",
1509 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1510 seq_printf(m
, "SW control enabled: %s\n",
1511 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1512 GEN6_RP_MEDIA_SW_MODE
));
1513 seq_printf(m
, "RC1e Enabled: %s\n",
1514 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1515 seq_printf(m
, "RC6 Enabled: %s\n",
1516 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1517 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1518 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1519 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1520 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1521 seq_puts(m
, "Current RC state: ");
1522 switch (gt_core_status
& GEN6_RCn_MASK
) {
1524 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1525 seq_puts(m
, "Core Power Down\n");
1527 seq_puts(m
, "on\n");
1530 seq_puts(m
, "RC3\n");
1533 seq_puts(m
, "RC6\n");
1536 seq_puts(m
, "RC7\n");
1539 seq_puts(m
, "Unknown\n");
1543 seq_printf(m
, "Core Power Down: %s\n",
1544 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1546 /* Not exactly sure what this is */
1547 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1548 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1549 seq_printf(m
, "RC6 residency since boot: %u\n",
1550 I915_READ(GEN6_GT_GFX_RC6
));
1551 seq_printf(m
, "RC6+ residency since boot: %u\n",
1552 I915_READ(GEN6_GT_GFX_RC6p
));
1553 seq_printf(m
, "RC6++ residency since boot: %u\n",
1554 I915_READ(GEN6_GT_GFX_RC6pp
));
1556 seq_printf(m
, "RC6 voltage: %dmV\n",
1557 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1558 seq_printf(m
, "RC6+ voltage: %dmV\n",
1559 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1560 seq_printf(m
, "RC6++ voltage: %dmV\n",
1561 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1565 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1567 struct drm_info_node
*node
= m
->private;
1568 struct drm_device
*dev
= node
->minor
->dev
;
1570 if (IS_VALLEYVIEW(dev
))
1571 return vlv_drpc_info(m
);
1572 else if (INTEL_INFO(dev
)->gen
>= 6)
1573 return gen6_drpc_info(m
);
1575 return ironlake_drpc_info(m
);
1578 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1580 struct drm_info_node
*node
= m
->private;
1581 struct drm_device
*dev
= node
->minor
->dev
;
1582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1584 if (!HAS_FBC(dev
)) {
1585 seq_puts(m
, "FBC unsupported on this chipset\n");
1589 intel_runtime_pm_get(dev_priv
);
1591 if (intel_fbc_enabled(dev
)) {
1592 seq_puts(m
, "FBC enabled\n");
1594 seq_puts(m
, "FBC disabled: ");
1595 switch (dev_priv
->fbc
.no_fbc_reason
) {
1597 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1599 case FBC_UNSUPPORTED
:
1600 seq_puts(m
, "unsupported by this chipset");
1603 seq_puts(m
, "no outputs");
1605 case FBC_STOLEN_TOO_SMALL
:
1606 seq_puts(m
, "not enough stolen memory");
1608 case FBC_UNSUPPORTED_MODE
:
1609 seq_puts(m
, "mode not supported");
1611 case FBC_MODE_TOO_LARGE
:
1612 seq_puts(m
, "mode too large");
1615 seq_puts(m
, "FBC unsupported on plane");
1618 seq_puts(m
, "scanout buffer not tiled");
1620 case FBC_MULTIPLE_PIPES
:
1621 seq_puts(m
, "multiple pipes are enabled");
1623 case FBC_MODULE_PARAM
:
1624 seq_puts(m
, "disabled per module param (default off)");
1626 case FBC_CHIP_DEFAULT
:
1627 seq_puts(m
, "disabled per chip default");
1630 seq_puts(m
, "unknown reason");
1635 intel_runtime_pm_put(dev_priv
);
1640 static int i915_fbc_fc_get(void *data
, u64
*val
)
1642 struct drm_device
*dev
= data
;
1643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1645 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1648 drm_modeset_lock_all(dev
);
1649 *val
= dev_priv
->fbc
.false_color
;
1650 drm_modeset_unlock_all(dev
);
1655 static int i915_fbc_fc_set(void *data
, u64 val
)
1657 struct drm_device
*dev
= data
;
1658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1661 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1664 drm_modeset_lock_all(dev
);
1666 reg
= I915_READ(ILK_DPFC_CONTROL
);
1667 dev_priv
->fbc
.false_color
= val
;
1669 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1670 (reg
| FBC_CTL_FALSE_COLOR
) :
1671 (reg
& ~FBC_CTL_FALSE_COLOR
));
1673 drm_modeset_unlock_all(dev
);
1677 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1678 i915_fbc_fc_get
, i915_fbc_fc_set
,
1681 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1683 struct drm_info_node
*node
= m
->private;
1684 struct drm_device
*dev
= node
->minor
->dev
;
1685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1687 if (!HAS_IPS(dev
)) {
1688 seq_puts(m
, "not supported\n");
1692 intel_runtime_pm_get(dev_priv
);
1694 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1695 yesno(i915
.enable_ips
));
1697 if (INTEL_INFO(dev
)->gen
>= 8) {
1698 seq_puts(m
, "Currently: unknown\n");
1700 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1701 seq_puts(m
, "Currently: enabled\n");
1703 seq_puts(m
, "Currently: disabled\n");
1706 intel_runtime_pm_put(dev_priv
);
1711 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1713 struct drm_info_node
*node
= m
->private;
1714 struct drm_device
*dev
= node
->minor
->dev
;
1715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1716 bool sr_enabled
= false;
1718 intel_runtime_pm_get(dev_priv
);
1720 if (HAS_PCH_SPLIT(dev
))
1721 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1722 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1723 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1724 else if (IS_I915GM(dev
))
1725 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1726 else if (IS_PINEVIEW(dev
))
1727 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1729 intel_runtime_pm_put(dev_priv
);
1731 seq_printf(m
, "self-refresh: %s\n",
1732 sr_enabled
? "enabled" : "disabled");
1737 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1739 struct drm_info_node
*node
= m
->private;
1740 struct drm_device
*dev
= node
->minor
->dev
;
1741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1742 unsigned long temp
, chipset
, gfx
;
1748 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1752 temp
= i915_mch_val(dev_priv
);
1753 chipset
= i915_chipset_val(dev_priv
);
1754 gfx
= i915_gfx_val(dev_priv
);
1755 mutex_unlock(&dev
->struct_mutex
);
1757 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1758 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1759 seq_printf(m
, "GFX power: %ld\n", gfx
);
1760 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1765 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1767 struct drm_info_node
*node
= m
->private;
1768 struct drm_device
*dev
= node
->minor
->dev
;
1769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1771 int gpu_freq
, ia_freq
;
1773 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1774 seq_puts(m
, "unsupported on this chipset\n");
1778 intel_runtime_pm_get(dev_priv
);
1780 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1782 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1786 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1788 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1789 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1792 sandybridge_pcode_read(dev_priv
,
1793 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1795 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1796 intel_gpu_freq(dev_priv
, gpu_freq
),
1797 ((ia_freq
>> 0) & 0xff) * 100,
1798 ((ia_freq
>> 8) & 0xff) * 100);
1801 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1804 intel_runtime_pm_put(dev_priv
);
1808 static int i915_opregion(struct seq_file
*m
, void *unused
)
1810 struct drm_info_node
*node
= m
->private;
1811 struct drm_device
*dev
= node
->minor
->dev
;
1812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1813 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1814 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1820 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1824 if (opregion
->header
) {
1825 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1826 seq_write(m
, data
, OPREGION_SIZE
);
1829 mutex_unlock(&dev
->struct_mutex
);
1836 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1838 struct drm_info_node
*node
= m
->private;
1839 struct drm_device
*dev
= node
->minor
->dev
;
1840 struct intel_fbdev
*ifbdev
= NULL
;
1841 struct intel_framebuffer
*fb
;
1843 #ifdef CONFIG_DRM_I915_FBDEV
1844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1846 ifbdev
= dev_priv
->fbdev
;
1847 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1849 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1853 fb
->base
.bits_per_pixel
,
1854 fb
->base
.modifier
[0],
1855 atomic_read(&fb
->base
.refcount
.refcount
));
1856 describe_obj(m
, fb
->obj
);
1860 mutex_lock(&dev
->mode_config
.fb_lock
);
1861 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1862 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1865 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1869 fb
->base
.bits_per_pixel
,
1870 fb
->base
.modifier
[0],
1871 atomic_read(&fb
->base
.refcount
.refcount
));
1872 describe_obj(m
, fb
->obj
);
1875 mutex_unlock(&dev
->mode_config
.fb_lock
);
1880 static void describe_ctx_ringbuf(struct seq_file
*m
,
1881 struct intel_ringbuffer
*ringbuf
)
1883 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1884 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1885 ringbuf
->last_retired_head
);
1888 static int i915_context_status(struct seq_file
*m
, void *unused
)
1890 struct drm_info_node
*node
= m
->private;
1891 struct drm_device
*dev
= node
->minor
->dev
;
1892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1893 struct intel_engine_cs
*ring
;
1894 struct intel_context
*ctx
;
1897 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1901 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1902 if (!i915
.enable_execlists
&&
1903 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1906 seq_puts(m
, "HW context ");
1907 describe_ctx(m
, ctx
);
1908 for_each_ring(ring
, dev_priv
, i
) {
1909 if (ring
->default_context
== ctx
)
1910 seq_printf(m
, "(default context %s) ",
1914 if (i915
.enable_execlists
) {
1916 for_each_ring(ring
, dev_priv
, i
) {
1917 struct drm_i915_gem_object
*ctx_obj
=
1918 ctx
->engine
[i
].state
;
1919 struct intel_ringbuffer
*ringbuf
=
1920 ctx
->engine
[i
].ringbuf
;
1922 seq_printf(m
, "%s: ", ring
->name
);
1924 describe_obj(m
, ctx_obj
);
1926 describe_ctx_ringbuf(m
, ringbuf
);
1930 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1936 mutex_unlock(&dev
->struct_mutex
);
1941 static void i915_dump_lrc_obj(struct seq_file
*m
,
1942 struct intel_engine_cs
*ring
,
1943 struct drm_i915_gem_object
*ctx_obj
)
1946 uint32_t *reg_state
;
1948 unsigned long ggtt_offset
= 0;
1950 if (ctx_obj
== NULL
) {
1951 seq_printf(m
, "Context on %s with no gem object\n",
1956 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1957 intel_execlists_ctx_id(ctx_obj
));
1959 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
1960 seq_puts(m
, "\tNot bound in GGTT\n");
1962 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
1964 if (i915_gem_object_get_pages(ctx_obj
)) {
1965 seq_puts(m
, "\tFailed to get pages for context object\n");
1969 page
= i915_gem_object_get_page(ctx_obj
, 1);
1970 if (!WARN_ON(page
== NULL
)) {
1971 reg_state
= kmap_atomic(page
);
1973 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
1974 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1975 ggtt_offset
+ 4096 + (j
* 4),
1976 reg_state
[j
], reg_state
[j
+ 1],
1977 reg_state
[j
+ 2], reg_state
[j
+ 3]);
1979 kunmap_atomic(reg_state
);
1985 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
1987 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1988 struct drm_device
*dev
= node
->minor
->dev
;
1989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1990 struct intel_engine_cs
*ring
;
1991 struct intel_context
*ctx
;
1994 if (!i915
.enable_execlists
) {
1995 seq_printf(m
, "Logical Ring Contexts are disabled\n");
1999 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2003 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
2004 for_each_ring(ring
, dev_priv
, i
) {
2005 if (ring
->default_context
!= ctx
)
2006 i915_dump_lrc_obj(m
, ring
,
2007 ctx
->engine
[i
].state
);
2011 mutex_unlock(&dev
->struct_mutex
);
2016 static int i915_execlists(struct seq_file
*m
, void *data
)
2018 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2019 struct drm_device
*dev
= node
->minor
->dev
;
2020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2021 struct intel_engine_cs
*ring
;
2027 struct list_head
*cursor
;
2031 if (!i915
.enable_execlists
) {
2032 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2036 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2040 intel_runtime_pm_get(dev_priv
);
2042 for_each_ring(ring
, dev_priv
, ring_id
) {
2043 struct drm_i915_gem_request
*head_req
= NULL
;
2045 unsigned long flags
;
2047 seq_printf(m
, "%s\n", ring
->name
);
2049 status
= I915_READ(RING_EXECLIST_STATUS(ring
));
2050 ctx_id
= I915_READ(RING_EXECLIST_STATUS(ring
) + 4);
2051 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2054 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
2055 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2057 read_pointer
= ring
->next_context_status_buffer
;
2058 write_pointer
= status_pointer
& 0x07;
2059 if (read_pointer
> write_pointer
)
2061 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2062 read_pointer
, write_pointer
);
2064 for (i
= 0; i
< 6; i
++) {
2065 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
);
2066 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
+ 4);
2068 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2072 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2073 list_for_each(cursor
, &ring
->execlist_queue
)
2075 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
2076 struct drm_i915_gem_request
, execlist_link
);
2077 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2079 seq_printf(m
, "\t%d requests in queue\n", count
);
2081 struct drm_i915_gem_object
*ctx_obj
;
2083 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
2084 seq_printf(m
, "\tHead request id: %u\n",
2085 intel_execlists_ctx_id(ctx_obj
));
2086 seq_printf(m
, "\tHead request tail: %u\n",
2093 intel_runtime_pm_put(dev_priv
);
2094 mutex_unlock(&dev
->struct_mutex
);
2099 static const char *swizzle_string(unsigned swizzle
)
2102 case I915_BIT_6_SWIZZLE_NONE
:
2104 case I915_BIT_6_SWIZZLE_9
:
2106 case I915_BIT_6_SWIZZLE_9_10
:
2107 return "bit9/bit10";
2108 case I915_BIT_6_SWIZZLE_9_11
:
2109 return "bit9/bit11";
2110 case I915_BIT_6_SWIZZLE_9_10_11
:
2111 return "bit9/bit10/bit11";
2112 case I915_BIT_6_SWIZZLE_9_17
:
2113 return "bit9/bit17";
2114 case I915_BIT_6_SWIZZLE_9_10_17
:
2115 return "bit9/bit10/bit17";
2116 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2123 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2125 struct drm_info_node
*node
= m
->private;
2126 struct drm_device
*dev
= node
->minor
->dev
;
2127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2130 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2133 intel_runtime_pm_get(dev_priv
);
2135 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2136 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2137 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2138 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2140 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2141 seq_printf(m
, "DDC = 0x%08x\n",
2143 seq_printf(m
, "DDC2 = 0x%08x\n",
2145 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2146 I915_READ16(C0DRB3
));
2147 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2148 I915_READ16(C1DRB3
));
2149 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2150 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2151 I915_READ(MAD_DIMM_C0
));
2152 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2153 I915_READ(MAD_DIMM_C1
));
2154 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2155 I915_READ(MAD_DIMM_C2
));
2156 seq_printf(m
, "TILECTL = 0x%08x\n",
2157 I915_READ(TILECTL
));
2158 if (INTEL_INFO(dev
)->gen
>= 8)
2159 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2160 I915_READ(GAMTARBMODE
));
2162 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2163 I915_READ(ARB_MODE
));
2164 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2165 I915_READ(DISP_ARB_CTL
));
2168 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2169 seq_puts(m
, "L-shaped memory detected\n");
2171 intel_runtime_pm_put(dev_priv
);
2172 mutex_unlock(&dev
->struct_mutex
);
2177 static int per_file_ctx(int id
, void *ptr
, void *data
)
2179 struct intel_context
*ctx
= ptr
;
2180 struct seq_file
*m
= data
;
2181 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2184 seq_printf(m
, " no ppgtt for context %d\n",
2189 if (i915_gem_context_is_default(ctx
))
2190 seq_puts(m
, " default context:\n");
2192 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2193 ppgtt
->debug_dump(ppgtt
, m
);
2198 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2201 struct intel_engine_cs
*ring
;
2202 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2208 for_each_ring(ring
, dev_priv
, unused
) {
2209 seq_printf(m
, "%s\n", ring
->name
);
2210 for (i
= 0; i
< 4; i
++) {
2211 u32 offset
= 0x270 + i
* 8;
2212 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
2214 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
2215 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2220 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2223 struct intel_engine_cs
*ring
;
2224 struct drm_file
*file
;
2227 if (INTEL_INFO(dev
)->gen
== 6)
2228 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2230 for_each_ring(ring
, dev_priv
, i
) {
2231 seq_printf(m
, "%s\n", ring
->name
);
2232 if (INTEL_INFO(dev
)->gen
== 7)
2233 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2234 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2235 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2236 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2238 if (dev_priv
->mm
.aliasing_ppgtt
) {
2239 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2241 seq_puts(m
, "aliasing PPGTT:\n");
2242 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.pd_offset
);
2244 ppgtt
->debug_dump(ppgtt
, m
);
2247 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2248 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2250 seq_printf(m
, "proc: %s\n",
2251 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
2252 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
2254 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2257 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2259 struct drm_info_node
*node
= m
->private;
2260 struct drm_device
*dev
= node
->minor
->dev
;
2261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2263 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2266 intel_runtime_pm_get(dev_priv
);
2268 if (INTEL_INFO(dev
)->gen
>= 8)
2269 gen8_ppgtt_info(m
, dev
);
2270 else if (INTEL_INFO(dev
)->gen
>= 6)
2271 gen6_ppgtt_info(m
, dev
);
2273 intel_runtime_pm_put(dev_priv
);
2274 mutex_unlock(&dev
->struct_mutex
);
2279 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2281 struct drm_info_node
*node
= m
->private;
2282 struct drm_device
*dev
= node
->minor
->dev
;
2283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2284 struct drm_file
*file
;
2287 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2291 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
2295 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2296 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2297 struct task_struct
*task
;
2300 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2301 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2302 task
? task
->comm
: "<unknown>",
2303 task
? task
->pid
: -1,
2304 file_priv
->rps_boosts
,
2305 list_empty(&file_priv
->rps_boost
) ? "" : ", active");
2308 seq_printf(m
, "Kernel boosts: %d\n", dev_priv
->rps
.boosts
);
2310 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2312 mutex_unlock(&dev
->struct_mutex
);
2317 static int i915_llc(struct seq_file
*m
, void *data
)
2319 struct drm_info_node
*node
= m
->private;
2320 struct drm_device
*dev
= node
->minor
->dev
;
2321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2323 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2324 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2325 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2330 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2332 struct drm_info_node
*node
= m
->private;
2333 struct drm_device
*dev
= node
->minor
->dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2338 bool enabled
= false;
2340 if (!HAS_PSR(dev
)) {
2341 seq_puts(m
, "PSR not supported\n");
2345 intel_runtime_pm_get(dev_priv
);
2347 mutex_lock(&dev_priv
->psr
.lock
);
2348 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2349 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2350 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2351 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2352 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2353 dev_priv
->psr
.busy_frontbuffer_bits
);
2354 seq_printf(m
, "Re-enable work scheduled: %s\n",
2355 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2358 enabled
= I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2360 for_each_pipe(dev_priv
, pipe
) {
2361 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2362 VLV_EDP_PSR_CURR_STATE_MASK
;
2363 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2364 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2368 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2371 for_each_pipe(dev_priv
, pipe
) {
2372 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2373 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2374 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2378 /* CHV PSR has no kind of performance counter */
2380 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
2381 EDP_PSR_PERF_CNT_MASK
;
2383 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2385 mutex_unlock(&dev_priv
->psr
.lock
);
2387 intel_runtime_pm_put(dev_priv
);
2391 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2393 struct drm_info_node
*node
= m
->private;
2394 struct drm_device
*dev
= node
->minor
->dev
;
2395 struct intel_encoder
*encoder
;
2396 struct intel_connector
*connector
;
2397 struct intel_dp
*intel_dp
= NULL
;
2401 drm_modeset_lock_all(dev
);
2402 for_each_intel_connector(dev
, connector
) {
2404 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2407 if (!connector
->base
.encoder
)
2410 encoder
= to_intel_encoder(connector
->base
.encoder
);
2411 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2414 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2416 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2420 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2421 crc
[0], crc
[1], crc
[2],
2422 crc
[3], crc
[4], crc
[5]);
2427 drm_modeset_unlock_all(dev
);
2431 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2433 struct drm_info_node
*node
= m
->private;
2434 struct drm_device
*dev
= node
->minor
->dev
;
2435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2439 if (INTEL_INFO(dev
)->gen
< 6)
2442 intel_runtime_pm_get(dev_priv
);
2444 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2445 power
= (power
& 0x1f00) >> 8;
2446 units
= 1000000 / (1 << power
); /* convert to uJ */
2447 power
= I915_READ(MCH_SECP_NRG_STTS
);
2450 intel_runtime_pm_put(dev_priv
);
2452 seq_printf(m
, "%llu", (long long unsigned)power
);
2457 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2459 struct drm_info_node
*node
= m
->private;
2460 struct drm_device
*dev
= node
->minor
->dev
;
2461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2463 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2464 seq_puts(m
, "not supported\n");
2468 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2469 seq_printf(m
, "IRQs disabled: %s\n",
2470 yesno(!intel_irqs_enabled(dev_priv
)));
2475 static const char *power_domain_str(enum intel_display_power_domain domain
)
2478 case POWER_DOMAIN_PIPE_A
:
2480 case POWER_DOMAIN_PIPE_B
:
2482 case POWER_DOMAIN_PIPE_C
:
2484 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2485 return "PIPE_A_PANEL_FITTER";
2486 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2487 return "PIPE_B_PANEL_FITTER";
2488 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2489 return "PIPE_C_PANEL_FITTER";
2490 case POWER_DOMAIN_TRANSCODER_A
:
2491 return "TRANSCODER_A";
2492 case POWER_DOMAIN_TRANSCODER_B
:
2493 return "TRANSCODER_B";
2494 case POWER_DOMAIN_TRANSCODER_C
:
2495 return "TRANSCODER_C";
2496 case POWER_DOMAIN_TRANSCODER_EDP
:
2497 return "TRANSCODER_EDP";
2498 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2499 return "PORT_DDI_A_2_LANES";
2500 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2501 return "PORT_DDI_A_4_LANES";
2502 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2503 return "PORT_DDI_B_2_LANES";
2504 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2505 return "PORT_DDI_B_4_LANES";
2506 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2507 return "PORT_DDI_C_2_LANES";
2508 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2509 return "PORT_DDI_C_4_LANES";
2510 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2511 return "PORT_DDI_D_2_LANES";
2512 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2513 return "PORT_DDI_D_4_LANES";
2514 case POWER_DOMAIN_PORT_DSI
:
2516 case POWER_DOMAIN_PORT_CRT
:
2518 case POWER_DOMAIN_PORT_OTHER
:
2519 return "PORT_OTHER";
2520 case POWER_DOMAIN_VGA
:
2522 case POWER_DOMAIN_AUDIO
:
2524 case POWER_DOMAIN_PLLS
:
2526 case POWER_DOMAIN_AUX_A
:
2528 case POWER_DOMAIN_AUX_B
:
2530 case POWER_DOMAIN_AUX_C
:
2532 case POWER_DOMAIN_AUX_D
:
2534 case POWER_DOMAIN_INIT
:
2537 MISSING_CASE(domain
);
2542 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2544 struct drm_info_node
*node
= m
->private;
2545 struct drm_device
*dev
= node
->minor
->dev
;
2546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2547 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2550 mutex_lock(&power_domains
->lock
);
2552 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2553 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2554 struct i915_power_well
*power_well
;
2555 enum intel_display_power_domain power_domain
;
2557 power_well
= &power_domains
->power_wells
[i
];
2558 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2561 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2563 if (!(BIT(power_domain
) & power_well
->domains
))
2566 seq_printf(m
, " %-23s %d\n",
2567 power_domain_str(power_domain
),
2568 power_domains
->domain_use_count
[power_domain
]);
2572 mutex_unlock(&power_domains
->lock
);
2577 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2578 struct drm_display_mode
*mode
)
2582 for (i
= 0; i
< tabs
; i
++)
2585 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2586 mode
->base
.id
, mode
->name
,
2587 mode
->vrefresh
, mode
->clock
,
2588 mode
->hdisplay
, mode
->hsync_start
,
2589 mode
->hsync_end
, mode
->htotal
,
2590 mode
->vdisplay
, mode
->vsync_start
,
2591 mode
->vsync_end
, mode
->vtotal
,
2592 mode
->type
, mode
->flags
);
2595 static void intel_encoder_info(struct seq_file
*m
,
2596 struct intel_crtc
*intel_crtc
,
2597 struct intel_encoder
*intel_encoder
)
2599 struct drm_info_node
*node
= m
->private;
2600 struct drm_device
*dev
= node
->minor
->dev
;
2601 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2602 struct intel_connector
*intel_connector
;
2603 struct drm_encoder
*encoder
;
2605 encoder
= &intel_encoder
->base
;
2606 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2607 encoder
->base
.id
, encoder
->name
);
2608 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2609 struct drm_connector
*connector
= &intel_connector
->base
;
2610 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2613 drm_get_connector_status_name(connector
->status
));
2614 if (connector
->status
== connector_status_connected
) {
2615 struct drm_display_mode
*mode
= &crtc
->mode
;
2616 seq_printf(m
, ", mode:\n");
2617 intel_seq_print_mode(m
, 2, mode
);
2624 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2626 struct drm_info_node
*node
= m
->private;
2627 struct drm_device
*dev
= node
->minor
->dev
;
2628 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2629 struct intel_encoder
*intel_encoder
;
2631 if (crtc
->primary
->fb
)
2632 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2633 crtc
->primary
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2634 crtc
->primary
->fb
->width
, crtc
->primary
->fb
->height
);
2636 seq_puts(m
, "\tprimary plane disabled\n");
2637 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2638 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2641 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2643 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2645 seq_printf(m
, "\tfixed mode:\n");
2646 intel_seq_print_mode(m
, 2, mode
);
2649 static void intel_dp_info(struct seq_file
*m
,
2650 struct intel_connector
*intel_connector
)
2652 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2653 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2655 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2656 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2658 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2659 intel_panel_info(m
, &intel_connector
->panel
);
2662 static void intel_hdmi_info(struct seq_file
*m
,
2663 struct intel_connector
*intel_connector
)
2665 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2666 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2668 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2672 static void intel_lvds_info(struct seq_file
*m
,
2673 struct intel_connector
*intel_connector
)
2675 intel_panel_info(m
, &intel_connector
->panel
);
2678 static void intel_connector_info(struct seq_file
*m
,
2679 struct drm_connector
*connector
)
2681 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2682 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2683 struct drm_display_mode
*mode
;
2685 seq_printf(m
, "connector %d: type %s, status: %s\n",
2686 connector
->base
.id
, connector
->name
,
2687 drm_get_connector_status_name(connector
->status
));
2688 if (connector
->status
== connector_status_connected
) {
2689 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2690 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2691 connector
->display_info
.width_mm
,
2692 connector
->display_info
.height_mm
);
2693 seq_printf(m
, "\tsubpixel order: %s\n",
2694 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2695 seq_printf(m
, "\tCEA rev: %d\n",
2696 connector
->display_info
.cea_rev
);
2698 if (intel_encoder
) {
2699 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2700 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2701 intel_dp_info(m
, intel_connector
);
2702 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2703 intel_hdmi_info(m
, intel_connector
);
2704 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2705 intel_lvds_info(m
, intel_connector
);
2708 seq_printf(m
, "\tmodes:\n");
2709 list_for_each_entry(mode
, &connector
->modes
, head
)
2710 intel_seq_print_mode(m
, 2, mode
);
2713 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2718 if (IS_845G(dev
) || IS_I865G(dev
))
2719 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2721 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2726 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2731 pos
= I915_READ(CURPOS(pipe
));
2733 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2734 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2737 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2738 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2741 return cursor_active(dev
, pipe
);
2744 static int i915_display_info(struct seq_file
*m
, void *unused
)
2746 struct drm_info_node
*node
= m
->private;
2747 struct drm_device
*dev
= node
->minor
->dev
;
2748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2749 struct intel_crtc
*crtc
;
2750 struct drm_connector
*connector
;
2752 intel_runtime_pm_get(dev_priv
);
2753 drm_modeset_lock_all(dev
);
2754 seq_printf(m
, "CRTC info\n");
2755 seq_printf(m
, "---------\n");
2756 for_each_intel_crtc(dev
, crtc
) {
2760 seq_printf(m
, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2761 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2762 yesno(crtc
->active
), crtc
->config
->pipe_src_w
,
2763 crtc
->config
->pipe_src_h
);
2765 intel_crtc_info(m
, crtc
);
2767 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2768 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2769 yesno(crtc
->cursor_base
),
2770 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
2771 crtc
->base
.cursor
->state
->crtc_h
,
2772 crtc
->cursor_addr
, yesno(active
));
2775 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
2776 yesno(!crtc
->cpu_fifo_underrun_disabled
),
2777 yesno(!crtc
->pch_fifo_underrun_disabled
));
2780 seq_printf(m
, "\n");
2781 seq_printf(m
, "Connector info\n");
2782 seq_printf(m
, "--------------\n");
2783 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2784 intel_connector_info(m
, connector
);
2786 drm_modeset_unlock_all(dev
);
2787 intel_runtime_pm_put(dev_priv
);
2792 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
2794 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2795 struct drm_device
*dev
= node
->minor
->dev
;
2796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2797 struct intel_engine_cs
*ring
;
2798 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
2801 if (!i915_semaphore_is_enabled(dev
)) {
2802 seq_puts(m
, "Semaphores are disabled\n");
2806 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2809 intel_runtime_pm_get(dev_priv
);
2811 if (IS_BROADWELL(dev
)) {
2815 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
2817 seqno
= (uint64_t *)kmap_atomic(page
);
2818 for_each_ring(ring
, dev_priv
, i
) {
2821 seq_printf(m
, "%s\n", ring
->name
);
2823 seq_puts(m
, " Last signal:");
2824 for (j
= 0; j
< num_rings
; j
++) {
2825 offset
= i
* I915_NUM_RINGS
+ j
;
2826 seq_printf(m
, "0x%08llx (0x%02llx) ",
2827 seqno
[offset
], offset
* 8);
2831 seq_puts(m
, " Last wait: ");
2832 for (j
= 0; j
< num_rings
; j
++) {
2833 offset
= i
+ (j
* I915_NUM_RINGS
);
2834 seq_printf(m
, "0x%08llx (0x%02llx) ",
2835 seqno
[offset
], offset
* 8);
2840 kunmap_atomic(seqno
);
2842 seq_puts(m
, " Last signal:");
2843 for_each_ring(ring
, dev_priv
, i
)
2844 for (j
= 0; j
< num_rings
; j
++)
2845 seq_printf(m
, "0x%08x\n",
2846 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
2850 seq_puts(m
, "\nSync seqno:\n");
2851 for_each_ring(ring
, dev_priv
, i
) {
2852 for (j
= 0; j
< num_rings
; j
++) {
2853 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
2859 intel_runtime_pm_put(dev_priv
);
2860 mutex_unlock(&dev
->struct_mutex
);
2864 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
2866 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2867 struct drm_device
*dev
= node
->minor
->dev
;
2868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2871 drm_modeset_lock_all(dev
);
2872 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2873 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
2875 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
2876 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2877 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
2878 seq_printf(m
, " tracked hardware state:\n");
2879 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
2880 seq_printf(m
, " dpll_md: 0x%08x\n",
2881 pll
->config
.hw_state
.dpll_md
);
2882 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
2883 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
2884 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
2886 drm_modeset_unlock_all(dev
);
2891 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
2895 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2896 struct drm_device
*dev
= node
->minor
->dev
;
2897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2899 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2903 intel_runtime_pm_get(dev_priv
);
2905 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
2906 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
2907 u32 addr
, mask
, value
, read
;
2910 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
2911 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
2912 value
= dev_priv
->workarounds
.reg
[i
].value
;
2913 read
= I915_READ(addr
);
2914 ok
= (value
& mask
) == (read
& mask
);
2915 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2916 addr
, value
, mask
, read
, ok
? "OK" : "FAIL");
2919 intel_runtime_pm_put(dev_priv
);
2920 mutex_unlock(&dev
->struct_mutex
);
2925 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
2927 struct drm_info_node
*node
= m
->private;
2928 struct drm_device
*dev
= node
->minor
->dev
;
2929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2930 struct skl_ddb_allocation
*ddb
;
2931 struct skl_ddb_entry
*entry
;
2935 if (INTEL_INFO(dev
)->gen
< 9)
2938 drm_modeset_lock_all(dev
);
2940 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
2942 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2944 for_each_pipe(dev_priv
, pipe
) {
2945 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
2947 for_each_plane(dev_priv
, pipe
, plane
) {
2948 entry
= &ddb
->plane
[pipe
][plane
];
2949 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
2950 entry
->start
, entry
->end
,
2951 skl_ddb_entry_size(entry
));
2954 entry
= &ddb
->cursor
[pipe
];
2955 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
2956 entry
->end
, skl_ddb_entry_size(entry
));
2959 drm_modeset_unlock_all(dev
);
2964 static void drrs_status_per_crtc(struct seq_file
*m
,
2965 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
2967 struct intel_encoder
*intel_encoder
;
2968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2969 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
2972 for_each_encoder_on_crtc(dev
, &intel_crtc
->base
, intel_encoder
) {
2973 /* Encoder connected on this CRTC */
2974 switch (intel_encoder
->type
) {
2975 case INTEL_OUTPUT_EDP
:
2976 seq_puts(m
, "eDP:\n");
2978 case INTEL_OUTPUT_DSI
:
2979 seq_puts(m
, "DSI:\n");
2981 case INTEL_OUTPUT_HDMI
:
2982 seq_puts(m
, "HDMI:\n");
2984 case INTEL_OUTPUT_DISPLAYPORT
:
2985 seq_puts(m
, "DP:\n");
2988 seq_printf(m
, "Other encoder (id=%d).\n",
2989 intel_encoder
->type
);
2994 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
2995 seq_puts(m
, "\tVBT: DRRS_type: Static");
2996 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
2997 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
2998 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
2999 seq_puts(m
, "\tVBT: DRRS_type: None");
3001 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3003 seq_puts(m
, "\n\n");
3005 if (intel_crtc
->config
->has_drrs
) {
3006 struct intel_panel
*panel
;
3008 mutex_lock(&drrs
->mutex
);
3009 /* DRRS Supported */
3010 seq_puts(m
, "\tDRRS Supported: Yes\n");
3012 /* disable_drrs() will make drrs->dp NULL */
3014 seq_puts(m
, "Idleness DRRS: Disabled");
3015 mutex_unlock(&drrs
->mutex
);
3019 panel
= &drrs
->dp
->attached_connector
->panel
;
3020 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3021 drrs
->busy_frontbuffer_bits
);
3023 seq_puts(m
, "\n\t\t");
3024 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3025 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3026 vrefresh
= panel
->fixed_mode
->vrefresh
;
3027 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3028 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3029 vrefresh
= panel
->downclock_mode
->vrefresh
;
3031 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3032 drrs
->refresh_rate_type
);
3033 mutex_unlock(&drrs
->mutex
);
3036 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3038 seq_puts(m
, "\n\t\t");
3039 mutex_unlock(&drrs
->mutex
);
3041 /* DRRS not supported. Print the VBT parameter*/
3042 seq_puts(m
, "\tDRRS Supported : No");
3047 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3049 struct drm_info_node
*node
= m
->private;
3050 struct drm_device
*dev
= node
->minor
->dev
;
3051 struct intel_crtc
*intel_crtc
;
3052 int active_crtc_cnt
= 0;
3054 for_each_intel_crtc(dev
, intel_crtc
) {
3055 drm_modeset_lock(&intel_crtc
->base
.mutex
, NULL
);
3057 if (intel_crtc
->active
) {
3059 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3061 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3064 drm_modeset_unlock(&intel_crtc
->base
.mutex
);
3067 if (!active_crtc_cnt
)
3068 seq_puts(m
, "No active crtc found\n");
3073 struct pipe_crc_info
{
3075 struct drm_device
*dev
;
3079 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3081 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3082 struct drm_device
*dev
= node
->minor
->dev
;
3083 struct drm_encoder
*encoder
;
3084 struct intel_encoder
*intel_encoder
;
3085 struct intel_digital_port
*intel_dig_port
;
3086 drm_modeset_lock_all(dev
);
3087 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3088 intel_encoder
= to_intel_encoder(encoder
);
3089 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
3091 intel_dig_port
= enc_to_dig_port(encoder
);
3092 if (!intel_dig_port
->dp
.can_mst
)
3095 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3097 drm_modeset_unlock_all(dev
);
3101 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3103 struct pipe_crc_info
*info
= inode
->i_private
;
3104 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3105 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3107 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3110 spin_lock_irq(&pipe_crc
->lock
);
3112 if (pipe_crc
->opened
) {
3113 spin_unlock_irq(&pipe_crc
->lock
);
3114 return -EBUSY
; /* already open */
3117 pipe_crc
->opened
= true;
3118 filep
->private_data
= inode
->i_private
;
3120 spin_unlock_irq(&pipe_crc
->lock
);
3125 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3127 struct pipe_crc_info
*info
= inode
->i_private
;
3128 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3129 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3131 spin_lock_irq(&pipe_crc
->lock
);
3132 pipe_crc
->opened
= false;
3133 spin_unlock_irq(&pipe_crc
->lock
);
3138 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3139 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3140 /* account for \'0' */
3141 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3143 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3145 assert_spin_locked(&pipe_crc
->lock
);
3146 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3147 INTEL_PIPE_CRC_ENTRIES_NR
);
3151 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3154 struct pipe_crc_info
*info
= filep
->private_data
;
3155 struct drm_device
*dev
= info
->dev
;
3156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3157 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3158 char buf
[PIPE_CRC_BUFFER_LEN
];
3163 * Don't allow user space to provide buffers not big enough to hold
3166 if (count
< PIPE_CRC_LINE_LEN
)
3169 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3172 /* nothing to read */
3173 spin_lock_irq(&pipe_crc
->lock
);
3174 while (pipe_crc_data_count(pipe_crc
) == 0) {
3177 if (filep
->f_flags
& O_NONBLOCK
) {
3178 spin_unlock_irq(&pipe_crc
->lock
);
3182 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3183 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3185 spin_unlock_irq(&pipe_crc
->lock
);
3190 /* We now have one or more entries to read */
3191 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3194 while (n_entries
> 0) {
3195 struct intel_pipe_crc_entry
*entry
=
3196 &pipe_crc
->entries
[pipe_crc
->tail
];
3199 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3200 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3203 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3204 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3206 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3207 "%8u %8x %8x %8x %8x %8x\n",
3208 entry
->frame
, entry
->crc
[0],
3209 entry
->crc
[1], entry
->crc
[2],
3210 entry
->crc
[3], entry
->crc
[4]);
3212 spin_unlock_irq(&pipe_crc
->lock
);
3214 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3215 if (ret
== PIPE_CRC_LINE_LEN
)
3218 user_buf
+= PIPE_CRC_LINE_LEN
;
3221 spin_lock_irq(&pipe_crc
->lock
);
3224 spin_unlock_irq(&pipe_crc
->lock
);
3229 static const struct file_operations i915_pipe_crc_fops
= {
3230 .owner
= THIS_MODULE
,
3231 .open
= i915_pipe_crc_open
,
3232 .read
= i915_pipe_crc_read
,
3233 .release
= i915_pipe_crc_release
,
3236 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3238 .name
= "i915_pipe_A_crc",
3242 .name
= "i915_pipe_B_crc",
3246 .name
= "i915_pipe_C_crc",
3251 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3254 struct drm_device
*dev
= minor
->dev
;
3256 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3259 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3260 &i915_pipe_crc_fops
);
3264 return drm_add_fake_info_node(minor
, ent
, info
);
3267 static const char * const pipe_crc_sources
[] = {
3280 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3282 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3283 return pipe_crc_sources
[source
];
3286 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3288 struct drm_device
*dev
= m
->private;
3289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3292 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3293 seq_printf(m
, "%c %s\n", pipe_name(i
),
3294 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3299 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3301 struct drm_device
*dev
= inode
->i_private
;
3303 return single_open(file
, display_crc_ctl_show
, dev
);
3306 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3309 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3310 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3313 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3314 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3316 case INTEL_PIPE_CRC_SOURCE_NONE
:
3326 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3327 enum intel_pipe_crc_source
*source
)
3329 struct intel_encoder
*encoder
;
3330 struct intel_crtc
*crtc
;
3331 struct intel_digital_port
*dig_port
;
3334 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3336 drm_modeset_lock_all(dev
);
3337 for_each_intel_encoder(dev
, encoder
) {
3338 if (!encoder
->base
.crtc
)
3341 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3343 if (crtc
->pipe
!= pipe
)
3346 switch (encoder
->type
) {
3347 case INTEL_OUTPUT_TVOUT
:
3348 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3350 case INTEL_OUTPUT_DISPLAYPORT
:
3351 case INTEL_OUTPUT_EDP
:
3352 dig_port
= enc_to_dig_port(&encoder
->base
);
3353 switch (dig_port
->port
) {
3355 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3358 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3361 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3364 WARN(1, "nonexisting DP port %c\n",
3365 port_name(dig_port
->port
));
3373 drm_modeset_unlock_all(dev
);
3378 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3380 enum intel_pipe_crc_source
*source
,
3383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3384 bool need_stable_symbols
= false;
3386 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3387 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3393 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3394 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3396 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3397 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3398 need_stable_symbols
= true;
3400 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3401 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3402 need_stable_symbols
= true;
3404 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3405 if (!IS_CHERRYVIEW(dev
))
3407 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3408 need_stable_symbols
= true;
3410 case INTEL_PIPE_CRC_SOURCE_NONE
:
3418 * When the pipe CRC tap point is after the transcoders we need
3419 * to tweak symbol-level features to produce a deterministic series of
3420 * symbols for a given frame. We need to reset those features only once
3421 * a frame (instead of every nth symbol):
3422 * - DC-balance: used to ensure a better clock recovery from the data
3424 * - DisplayPort scrambling: used for EMI reduction
3426 if (need_stable_symbols
) {
3427 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3429 tmp
|= DC_BALANCE_RESET_VLV
;
3432 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3435 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3438 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3443 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3449 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3451 enum intel_pipe_crc_source
*source
,
3454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3455 bool need_stable_symbols
= false;
3457 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3458 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3464 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3465 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3467 case INTEL_PIPE_CRC_SOURCE_TV
:
3468 if (!SUPPORTS_TV(dev
))
3470 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3472 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3475 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3476 need_stable_symbols
= true;
3478 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3481 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3482 need_stable_symbols
= true;
3484 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3487 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3488 need_stable_symbols
= true;
3490 case INTEL_PIPE_CRC_SOURCE_NONE
:
3498 * When the pipe CRC tap point is after the transcoders we need
3499 * to tweak symbol-level features to produce a deterministic series of
3500 * symbols for a given frame. We need to reset those features only once
3501 * a frame (instead of every nth symbol):
3502 * - DC-balance: used to ensure a better clock recovery from the data
3504 * - DisplayPort scrambling: used for EMI reduction
3506 if (need_stable_symbols
) {
3507 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3509 WARN_ON(!IS_G4X(dev
));
3511 I915_WRITE(PORT_DFT_I9XX
,
3512 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3515 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3517 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3519 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3525 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3529 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3533 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3536 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3539 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3544 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3545 tmp
&= ~DC_BALANCE_RESET_VLV
;
3546 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3550 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3554 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3557 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3559 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3560 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3562 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3563 I915_WRITE(PORT_DFT_I9XX
,
3564 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3568 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3571 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3572 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3575 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3576 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3578 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3579 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3581 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3582 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3584 case INTEL_PIPE_CRC_SOURCE_NONE
:
3594 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3597 struct intel_crtc
*crtc
=
3598 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3600 drm_modeset_lock_all(dev
);
3602 * If we use the eDP transcoder we need to make sure that we don't
3603 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3604 * relevant on hsw with pipe A when using the always-on power well
3607 if (crtc
->config
->cpu_transcoder
== TRANSCODER_EDP
&&
3608 !crtc
->config
->pch_pfit
.enabled
) {
3609 crtc
->config
->pch_pfit
.force_thru
= true;
3611 intel_display_power_get(dev_priv
,
3612 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3614 intel_crtc_reset(crtc
);
3616 drm_modeset_unlock_all(dev
);
3619 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3622 struct intel_crtc
*crtc
=
3623 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3625 drm_modeset_lock_all(dev
);
3627 * If we use the eDP transcoder we need to make sure that we don't
3628 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3629 * relevant on hsw with pipe A when using the always-on power well
3632 if (crtc
->config
->pch_pfit
.force_thru
) {
3633 crtc
->config
->pch_pfit
.force_thru
= false;
3635 intel_crtc_reset(crtc
);
3637 intel_display_power_put(dev_priv
,
3638 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3640 drm_modeset_unlock_all(dev
);
3643 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3645 enum intel_pipe_crc_source
*source
,
3648 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3649 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3652 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3653 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3655 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3656 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3658 case INTEL_PIPE_CRC_SOURCE_PF
:
3659 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3660 hsw_trans_edp_pipe_A_crc_wa(dev
);
3662 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3664 case INTEL_PIPE_CRC_SOURCE_NONE
:
3674 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3675 enum intel_pipe_crc_source source
)
3677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3678 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3679 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3681 u32 val
= 0; /* shut up gcc */
3684 if (pipe_crc
->source
== source
)
3687 /* forbid changing the source without going back to 'none' */
3688 if (pipe_crc
->source
&& source
)
3691 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PIPE(pipe
))) {
3692 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3697 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
3698 else if (INTEL_INFO(dev
)->gen
< 5)
3699 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3700 else if (IS_VALLEYVIEW(dev
))
3701 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3702 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
3703 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
3705 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3710 /* none -> real source transition */
3712 struct intel_pipe_crc_entry
*entries
;
3714 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3715 pipe_name(pipe
), pipe_crc_source_name(source
));
3717 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
3718 sizeof(pipe_crc
->entries
[0]),
3724 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3725 * enabled and disabled dynamically based on package C states,
3726 * user space can't make reliable use of the CRCs, so let's just
3727 * completely disable it.
3729 hsw_disable_ips(crtc
);
3731 spin_lock_irq(&pipe_crc
->lock
);
3732 kfree(pipe_crc
->entries
);
3733 pipe_crc
->entries
= entries
;
3736 spin_unlock_irq(&pipe_crc
->lock
);
3739 pipe_crc
->source
= source
;
3741 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
3742 POSTING_READ(PIPE_CRC_CTL(pipe
));
3744 /* real source -> none transition */
3745 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
3746 struct intel_pipe_crc_entry
*entries
;
3747 struct intel_crtc
*crtc
=
3748 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
3750 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3753 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
3755 intel_wait_for_vblank(dev
, pipe
);
3756 drm_modeset_unlock(&crtc
->base
.mutex
);
3758 spin_lock_irq(&pipe_crc
->lock
);
3759 entries
= pipe_crc
->entries
;
3760 pipe_crc
->entries
= NULL
;
3763 spin_unlock_irq(&pipe_crc
->lock
);
3768 g4x_undo_pipe_scramble_reset(dev
, pipe
);
3769 else if (IS_VALLEYVIEW(dev
))
3770 vlv_undo_pipe_scramble_reset(dev
, pipe
);
3771 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3772 hsw_undo_trans_edp_pipe_A_crc_wa(dev
);
3774 hsw_enable_ips(crtc
);
3781 * Parse pipe CRC command strings:
3782 * command: wsp* object wsp+ name wsp+ source wsp*
3785 * source: (none | plane1 | plane2 | pf)
3786 * wsp: (#0x20 | #0x9 | #0xA)+
3789 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3790 * "pipe A none" -> Stop CRC
3792 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
3799 /* skip leading white space */
3800 buf
= skip_spaces(buf
);
3802 break; /* end of buffer */
3804 /* find end of word */
3805 for (end
= buf
; *end
&& !isspace(*end
); end
++)
3808 if (n_words
== max_words
) {
3809 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3811 return -EINVAL
; /* ran out of words[] before bytes */
3816 words
[n_words
++] = buf
;
3823 enum intel_pipe_crc_object
{
3824 PIPE_CRC_OBJECT_PIPE
,
3827 static const char * const pipe_crc_objects
[] = {
3832 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
3836 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
3837 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
3845 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
3847 const char name
= buf
[0];
3849 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
3858 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
3862 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
3863 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3871 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3875 char *words
[N_WORDS
];
3877 enum intel_pipe_crc_object object
;
3878 enum intel_pipe_crc_source source
;
3880 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3881 if (n_words
!= N_WORDS
) {
3882 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3887 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3888 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3892 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3893 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3897 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3898 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3902 return pipe_crc_set_source(dev
, pipe
, source
);
3905 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3906 size_t len
, loff_t
*offp
)
3908 struct seq_file
*m
= file
->private_data
;
3909 struct drm_device
*dev
= m
->private;
3916 if (len
> PAGE_SIZE
- 1) {
3917 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3922 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3926 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3932 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3943 static const struct file_operations i915_display_crc_ctl_fops
= {
3944 .owner
= THIS_MODULE
,
3945 .open
= display_crc_ctl_open
,
3947 .llseek
= seq_lseek
,
3948 .release
= single_release
,
3949 .write
= display_crc_ctl_write
3952 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
3953 const char __user
*ubuf
,
3954 size_t len
, loff_t
*offp
)
3959 struct drm_device
*dev
;
3960 struct drm_connector
*connector
;
3961 struct list_head
*connector_list
;
3962 struct intel_dp
*intel_dp
;
3965 m
= file
->private_data
;
3976 connector_list
= &dev
->mode_config
.connector_list
;
3981 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
3985 if (copy_from_user(input_buffer
, ubuf
, len
)) {
3990 input_buffer
[len
] = '\0';
3991 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
3993 list_for_each_entry(connector
, connector_list
, head
) {
3995 if (connector
->connector_type
!=
3996 DRM_MODE_CONNECTOR_DisplayPort
)
3999 if (connector
->connector_type
==
4000 DRM_MODE_CONNECTOR_DisplayPort
&&
4001 connector
->status
== connector_status_connected
&&
4002 connector
->encoder
!= NULL
) {
4003 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4004 status
= kstrtoint(input_buffer
, 10, &val
);
4007 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4008 /* To prevent erroneous activation of the compliance
4009 * testing code, only accept an actual value of 1 here
4012 intel_dp
->compliance_test_active
= 1;
4014 intel_dp
->compliance_test_active
= 0;
4018 kfree(input_buffer
);
4026 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4028 struct drm_device
*dev
= m
->private;
4029 struct drm_connector
*connector
;
4030 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4031 struct intel_dp
*intel_dp
;
4036 list_for_each_entry(connector
, connector_list
, head
) {
4038 if (connector
->connector_type
!=
4039 DRM_MODE_CONNECTOR_DisplayPort
)
4042 if (connector
->status
== connector_status_connected
&&
4043 connector
->encoder
!= NULL
) {
4044 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4045 if (intel_dp
->compliance_test_active
)
4056 static int i915_displayport_test_active_open(struct inode
*inode
,
4059 struct drm_device
*dev
= inode
->i_private
;
4061 return single_open(file
, i915_displayport_test_active_show
, dev
);
4064 static const struct file_operations i915_displayport_test_active_fops
= {
4065 .owner
= THIS_MODULE
,
4066 .open
= i915_displayport_test_active_open
,
4068 .llseek
= seq_lseek
,
4069 .release
= single_release
,
4070 .write
= i915_displayport_test_active_write
4073 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4075 struct drm_device
*dev
= m
->private;
4076 struct drm_connector
*connector
;
4077 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4078 struct intel_dp
*intel_dp
;
4083 list_for_each_entry(connector
, connector_list
, head
) {
4085 if (connector
->connector_type
!=
4086 DRM_MODE_CONNECTOR_DisplayPort
)
4089 if (connector
->status
== connector_status_connected
&&
4090 connector
->encoder
!= NULL
) {
4091 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4092 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4099 static int i915_displayport_test_data_open(struct inode
*inode
,
4102 struct drm_device
*dev
= inode
->i_private
;
4104 return single_open(file
, i915_displayport_test_data_show
, dev
);
4107 static const struct file_operations i915_displayport_test_data_fops
= {
4108 .owner
= THIS_MODULE
,
4109 .open
= i915_displayport_test_data_open
,
4111 .llseek
= seq_lseek
,
4112 .release
= single_release
4115 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4117 struct drm_device
*dev
= m
->private;
4118 struct drm_connector
*connector
;
4119 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4120 struct intel_dp
*intel_dp
;
4125 list_for_each_entry(connector
, connector_list
, head
) {
4127 if (connector
->connector_type
!=
4128 DRM_MODE_CONNECTOR_DisplayPort
)
4131 if (connector
->status
== connector_status_connected
&&
4132 connector
->encoder
!= NULL
) {
4133 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4134 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4142 static int i915_displayport_test_type_open(struct inode
*inode
,
4145 struct drm_device
*dev
= inode
->i_private
;
4147 return single_open(file
, i915_displayport_test_type_show
, dev
);
4150 static const struct file_operations i915_displayport_test_type_fops
= {
4151 .owner
= THIS_MODULE
,
4152 .open
= i915_displayport_test_type_open
,
4154 .llseek
= seq_lseek
,
4155 .release
= single_release
4158 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4160 struct drm_device
*dev
= m
->private;
4161 int num_levels
= ilk_wm_max_level(dev
) + 1;
4164 drm_modeset_lock_all(dev
);
4166 for (level
= 0; level
< num_levels
; level
++) {
4167 unsigned int latency
= wm
[level
];
4170 * - WM1+ latency values in 0.5us units
4171 * - latencies are in us on gen9
4173 if (INTEL_INFO(dev
)->gen
>= 9)
4178 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4179 level
, wm
[level
], latency
/ 10, latency
% 10);
4182 drm_modeset_unlock_all(dev
);
4185 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4187 struct drm_device
*dev
= m
->private;
4188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4189 const uint16_t *latencies
;
4191 if (INTEL_INFO(dev
)->gen
>= 9)
4192 latencies
= dev_priv
->wm
.skl_latency
;
4194 latencies
= to_i915(dev
)->wm
.pri_latency
;
4196 wm_latency_show(m
, latencies
);
4201 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4203 struct drm_device
*dev
= m
->private;
4204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4205 const uint16_t *latencies
;
4207 if (INTEL_INFO(dev
)->gen
>= 9)
4208 latencies
= dev_priv
->wm
.skl_latency
;
4210 latencies
= to_i915(dev
)->wm
.spr_latency
;
4212 wm_latency_show(m
, latencies
);
4217 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4219 struct drm_device
*dev
= m
->private;
4220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4221 const uint16_t *latencies
;
4223 if (INTEL_INFO(dev
)->gen
>= 9)
4224 latencies
= dev_priv
->wm
.skl_latency
;
4226 latencies
= to_i915(dev
)->wm
.cur_latency
;
4228 wm_latency_show(m
, latencies
);
4233 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4235 struct drm_device
*dev
= inode
->i_private
;
4237 if (HAS_GMCH_DISPLAY(dev
))
4240 return single_open(file
, pri_wm_latency_show
, dev
);
4243 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4245 struct drm_device
*dev
= inode
->i_private
;
4247 if (HAS_GMCH_DISPLAY(dev
))
4250 return single_open(file
, spr_wm_latency_show
, dev
);
4253 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4255 struct drm_device
*dev
= inode
->i_private
;
4257 if (HAS_GMCH_DISPLAY(dev
))
4260 return single_open(file
, cur_wm_latency_show
, dev
);
4263 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4264 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4266 struct seq_file
*m
= file
->private_data
;
4267 struct drm_device
*dev
= m
->private;
4268 uint16_t new[8] = { 0 };
4269 int num_levels
= ilk_wm_max_level(dev
) + 1;
4274 if (len
>= sizeof(tmp
))
4277 if (copy_from_user(tmp
, ubuf
, len
))
4282 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4283 &new[0], &new[1], &new[2], &new[3],
4284 &new[4], &new[5], &new[6], &new[7]);
4285 if (ret
!= num_levels
)
4288 drm_modeset_lock_all(dev
);
4290 for (level
= 0; level
< num_levels
; level
++)
4291 wm
[level
] = new[level
];
4293 drm_modeset_unlock_all(dev
);
4299 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4300 size_t len
, loff_t
*offp
)
4302 struct seq_file
*m
= file
->private_data
;
4303 struct drm_device
*dev
= m
->private;
4304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4305 uint16_t *latencies
;
4307 if (INTEL_INFO(dev
)->gen
>= 9)
4308 latencies
= dev_priv
->wm
.skl_latency
;
4310 latencies
= to_i915(dev
)->wm
.pri_latency
;
4312 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4315 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4316 size_t len
, loff_t
*offp
)
4318 struct seq_file
*m
= file
->private_data
;
4319 struct drm_device
*dev
= m
->private;
4320 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4321 uint16_t *latencies
;
4323 if (INTEL_INFO(dev
)->gen
>= 9)
4324 latencies
= dev_priv
->wm
.skl_latency
;
4326 latencies
= to_i915(dev
)->wm
.spr_latency
;
4328 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4331 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4332 size_t len
, loff_t
*offp
)
4334 struct seq_file
*m
= file
->private_data
;
4335 struct drm_device
*dev
= m
->private;
4336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4337 uint16_t *latencies
;
4339 if (INTEL_INFO(dev
)->gen
>= 9)
4340 latencies
= dev_priv
->wm
.skl_latency
;
4342 latencies
= to_i915(dev
)->wm
.cur_latency
;
4344 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4347 static const struct file_operations i915_pri_wm_latency_fops
= {
4348 .owner
= THIS_MODULE
,
4349 .open
= pri_wm_latency_open
,
4351 .llseek
= seq_lseek
,
4352 .release
= single_release
,
4353 .write
= pri_wm_latency_write
4356 static const struct file_operations i915_spr_wm_latency_fops
= {
4357 .owner
= THIS_MODULE
,
4358 .open
= spr_wm_latency_open
,
4360 .llseek
= seq_lseek
,
4361 .release
= single_release
,
4362 .write
= spr_wm_latency_write
4365 static const struct file_operations i915_cur_wm_latency_fops
= {
4366 .owner
= THIS_MODULE
,
4367 .open
= cur_wm_latency_open
,
4369 .llseek
= seq_lseek
,
4370 .release
= single_release
,
4371 .write
= cur_wm_latency_write
4375 i915_wedged_get(void *data
, u64
*val
)
4377 struct drm_device
*dev
= data
;
4378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4380 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4386 i915_wedged_set(void *data
, u64 val
)
4388 struct drm_device
*dev
= data
;
4389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4392 * There is no safeguard against this debugfs entry colliding
4393 * with the hangcheck calling same i915_handle_error() in
4394 * parallel, causing an explosion. For now we assume that the
4395 * test harness is responsible enough not to inject gpu hangs
4396 * while it is writing to 'i915_wedged'
4399 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4402 intel_runtime_pm_get(dev_priv
);
4404 i915_handle_error(dev
, val
,
4405 "Manually setting wedged to %llu", val
);
4407 intel_runtime_pm_put(dev_priv
);
4412 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4413 i915_wedged_get
, i915_wedged_set
,
4417 i915_ring_stop_get(void *data
, u64
*val
)
4419 struct drm_device
*dev
= data
;
4420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4422 *val
= dev_priv
->gpu_error
.stop_rings
;
4428 i915_ring_stop_set(void *data
, u64 val
)
4430 struct drm_device
*dev
= data
;
4431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4434 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4436 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4440 dev_priv
->gpu_error
.stop_rings
= val
;
4441 mutex_unlock(&dev
->struct_mutex
);
4446 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4447 i915_ring_stop_get
, i915_ring_stop_set
,
4451 i915_ring_missed_irq_get(void *data
, u64
*val
)
4453 struct drm_device
*dev
= data
;
4454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4456 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4461 i915_ring_missed_irq_set(void *data
, u64 val
)
4463 struct drm_device
*dev
= data
;
4464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4467 /* Lock against concurrent debugfs callers */
4468 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4471 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4472 mutex_unlock(&dev
->struct_mutex
);
4477 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4478 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4482 i915_ring_test_irq_get(void *data
, u64
*val
)
4484 struct drm_device
*dev
= data
;
4485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4487 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4493 i915_ring_test_irq_set(void *data
, u64 val
)
4495 struct drm_device
*dev
= data
;
4496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4499 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4501 /* Lock against concurrent debugfs callers */
4502 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4506 dev_priv
->gpu_error
.test_irq_rings
= val
;
4507 mutex_unlock(&dev
->struct_mutex
);
4512 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4513 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4516 #define DROP_UNBOUND 0x1
4517 #define DROP_BOUND 0x2
4518 #define DROP_RETIRE 0x4
4519 #define DROP_ACTIVE 0x8
4520 #define DROP_ALL (DROP_UNBOUND | \
4525 i915_drop_caches_get(void *data
, u64
*val
)
4533 i915_drop_caches_set(void *data
, u64 val
)
4535 struct drm_device
*dev
= data
;
4536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4539 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4541 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4542 * on ioctls on -EAGAIN. */
4543 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4547 if (val
& DROP_ACTIVE
) {
4548 ret
= i915_gpu_idle(dev
);
4553 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4554 i915_gem_retire_requests(dev
);
4556 if (val
& DROP_BOUND
)
4557 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4559 if (val
& DROP_UNBOUND
)
4560 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4563 mutex_unlock(&dev
->struct_mutex
);
4568 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4569 i915_drop_caches_get
, i915_drop_caches_set
,
4573 i915_max_freq_get(void *data
, u64
*val
)
4575 struct drm_device
*dev
= data
;
4576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4579 if (INTEL_INFO(dev
)->gen
< 6)
4582 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4584 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4588 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4589 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4595 i915_max_freq_set(void *data
, u64 val
)
4597 struct drm_device
*dev
= data
;
4598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4602 if (INTEL_INFO(dev
)->gen
< 6)
4605 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4607 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4609 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4614 * Turbo will still be enabled, but won't go above the set value.
4616 val
= intel_freq_opcode(dev_priv
, val
);
4618 hw_max
= dev_priv
->rps
.max_freq
;
4619 hw_min
= dev_priv
->rps
.min_freq
;
4621 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4622 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4626 dev_priv
->rps
.max_freq_softlimit
= val
;
4628 intel_set_rps(dev
, val
);
4630 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4635 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4636 i915_max_freq_get
, i915_max_freq_set
,
4640 i915_min_freq_get(void *data
, u64
*val
)
4642 struct drm_device
*dev
= data
;
4643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4646 if (INTEL_INFO(dev
)->gen
< 6)
4649 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4651 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4655 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4656 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4662 i915_min_freq_set(void *data
, u64 val
)
4664 struct drm_device
*dev
= data
;
4665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4669 if (INTEL_INFO(dev
)->gen
< 6)
4672 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4674 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4676 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4681 * Turbo will still be enabled, but won't go below the set value.
4683 val
= intel_freq_opcode(dev_priv
, val
);
4685 hw_max
= dev_priv
->rps
.max_freq
;
4686 hw_min
= dev_priv
->rps
.min_freq
;
4688 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4689 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4693 dev_priv
->rps
.min_freq_softlimit
= val
;
4695 intel_set_rps(dev
, val
);
4697 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4702 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4703 i915_min_freq_get
, i915_min_freq_set
,
4707 i915_cache_sharing_get(void *data
, u64
*val
)
4709 struct drm_device
*dev
= data
;
4710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4714 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4717 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4720 intel_runtime_pm_get(dev_priv
);
4722 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4724 intel_runtime_pm_put(dev_priv
);
4725 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
4727 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4733 i915_cache_sharing_set(void *data
, u64 val
)
4735 struct drm_device
*dev
= data
;
4736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4739 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4745 intel_runtime_pm_get(dev_priv
);
4746 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4748 /* Update the cache sharing policy here as well */
4749 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4750 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4751 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4752 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4754 intel_runtime_pm_put(dev_priv
);
4758 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4759 i915_cache_sharing_get
, i915_cache_sharing_set
,
4762 struct sseu_dev_status
{
4763 unsigned int slice_total
;
4764 unsigned int subslice_total
;
4765 unsigned int subslice_per_slice
;
4766 unsigned int eu_total
;
4767 unsigned int eu_per_subslice
;
4770 static void cherryview_sseu_device_status(struct drm_device
*dev
,
4771 struct sseu_dev_status
*stat
)
4773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4774 const int ss_max
= 2;
4776 u32 sig1
[ss_max
], sig2
[ss_max
];
4778 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
4779 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
4780 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
4781 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
4783 for (ss
= 0; ss
< ss_max
; ss
++) {
4784 unsigned int eu_cnt
;
4786 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
4787 /* skip disabled subslice */
4790 stat
->slice_total
= 1;
4791 stat
->subslice_per_slice
++;
4792 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
4793 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
4794 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
4795 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
4796 stat
->eu_total
+= eu_cnt
;
4797 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
4799 stat
->subslice_total
= stat
->subslice_per_slice
;
4802 static void gen9_sseu_device_status(struct drm_device
*dev
,
4803 struct sseu_dev_status
*stat
)
4805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4806 int s_max
= 3, ss_max
= 4;
4808 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
4810 /* BXT has a single slice and at most 3 subslices. */
4811 if (IS_BROXTON(dev
)) {
4816 for (s
= 0; s
< s_max
; s
++) {
4817 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
4818 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
4819 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
4822 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
4823 GEN9_PGCTL_SSA_EU19_ACK
|
4824 GEN9_PGCTL_SSA_EU210_ACK
|
4825 GEN9_PGCTL_SSA_EU311_ACK
;
4826 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
4827 GEN9_PGCTL_SSB_EU19_ACK
|
4828 GEN9_PGCTL_SSB_EU210_ACK
|
4829 GEN9_PGCTL_SSB_EU311_ACK
;
4831 for (s
= 0; s
< s_max
; s
++) {
4832 unsigned int ss_cnt
= 0;
4834 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
4835 /* skip disabled slice */
4838 stat
->slice_total
++;
4840 if (IS_SKYLAKE(dev
))
4841 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
4843 for (ss
= 0; ss
< ss_max
; ss
++) {
4844 unsigned int eu_cnt
;
4846 if (IS_BROXTON(dev
) &&
4847 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
4848 /* skip disabled subslice */
4851 if (IS_BROXTON(dev
))
4854 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
4856 stat
->eu_total
+= eu_cnt
;
4857 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
4861 stat
->subslice_total
+= ss_cnt
;
4862 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
4867 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
4869 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
4870 struct drm_device
*dev
= node
->minor
->dev
;
4871 struct sseu_dev_status stat
;
4873 if ((INTEL_INFO(dev
)->gen
< 8) || IS_BROADWELL(dev
))
4876 seq_puts(m
, "SSEU Device Info\n");
4877 seq_printf(m
, " Available Slice Total: %u\n",
4878 INTEL_INFO(dev
)->slice_total
);
4879 seq_printf(m
, " Available Subslice Total: %u\n",
4880 INTEL_INFO(dev
)->subslice_total
);
4881 seq_printf(m
, " Available Subslice Per Slice: %u\n",
4882 INTEL_INFO(dev
)->subslice_per_slice
);
4883 seq_printf(m
, " Available EU Total: %u\n",
4884 INTEL_INFO(dev
)->eu_total
);
4885 seq_printf(m
, " Available EU Per Subslice: %u\n",
4886 INTEL_INFO(dev
)->eu_per_subslice
);
4887 seq_printf(m
, " Has Slice Power Gating: %s\n",
4888 yesno(INTEL_INFO(dev
)->has_slice_pg
));
4889 seq_printf(m
, " Has Subslice Power Gating: %s\n",
4890 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
4891 seq_printf(m
, " Has EU Power Gating: %s\n",
4892 yesno(INTEL_INFO(dev
)->has_eu_pg
));
4894 seq_puts(m
, "SSEU Device Status\n");
4895 memset(&stat
, 0, sizeof(stat
));
4896 if (IS_CHERRYVIEW(dev
)) {
4897 cherryview_sseu_device_status(dev
, &stat
);
4898 } else if (INTEL_INFO(dev
)->gen
>= 9) {
4899 gen9_sseu_device_status(dev
, &stat
);
4901 seq_printf(m
, " Enabled Slice Total: %u\n",
4903 seq_printf(m
, " Enabled Subslice Total: %u\n",
4904 stat
.subslice_total
);
4905 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
4906 stat
.subslice_per_slice
);
4907 seq_printf(m
, " Enabled EU Total: %u\n",
4909 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
4910 stat
.eu_per_subslice
);
4915 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
4917 struct drm_device
*dev
= inode
->i_private
;
4918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4920 if (INTEL_INFO(dev
)->gen
< 6)
4923 intel_runtime_pm_get(dev_priv
);
4924 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4929 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
4931 struct drm_device
*dev
= inode
->i_private
;
4932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4934 if (INTEL_INFO(dev
)->gen
< 6)
4937 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4938 intel_runtime_pm_put(dev_priv
);
4943 static const struct file_operations i915_forcewake_fops
= {
4944 .owner
= THIS_MODULE
,
4945 .open
= i915_forcewake_open
,
4946 .release
= i915_forcewake_release
,
4949 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
4951 struct drm_device
*dev
= minor
->dev
;
4954 ent
= debugfs_create_file("i915_forcewake_user",
4957 &i915_forcewake_fops
);
4961 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
4964 static int i915_debugfs_create(struct dentry
*root
,
4965 struct drm_minor
*minor
,
4967 const struct file_operations
*fops
)
4969 struct drm_device
*dev
= minor
->dev
;
4972 ent
= debugfs_create_file(name
,
4979 return drm_add_fake_info_node(minor
, ent
, fops
);
4982 static const struct drm_info_list i915_debugfs_list
[] = {
4983 {"i915_capabilities", i915_capabilities
, 0},
4984 {"i915_gem_objects", i915_gem_object_info
, 0},
4985 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
4986 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
4987 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
4988 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
4989 {"i915_gem_stolen", i915_gem_stolen_list_info
},
4990 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
4991 {"i915_gem_request", i915_gem_request_info
, 0},
4992 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
4993 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
4994 {"i915_gem_interrupt", i915_interrupt_info
, 0},
4995 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
4996 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
4997 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
4998 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
4999 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5000 {"i915_frequency_info", i915_frequency_info
, 0},
5001 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5002 {"i915_drpc_info", i915_drpc_info
, 0},
5003 {"i915_emon_status", i915_emon_status
, 0},
5004 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5005 {"i915_fbc_status", i915_fbc_status
, 0},
5006 {"i915_ips_status", i915_ips_status
, 0},
5007 {"i915_sr_status", i915_sr_status
, 0},
5008 {"i915_opregion", i915_opregion
, 0},
5009 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5010 {"i915_context_status", i915_context_status
, 0},
5011 {"i915_dump_lrc", i915_dump_lrc
, 0},
5012 {"i915_execlists", i915_execlists
, 0},
5013 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5014 {"i915_swizzle_info", i915_swizzle_info
, 0},
5015 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5016 {"i915_llc", i915_llc
, 0},
5017 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5018 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5019 {"i915_energy_uJ", i915_energy_uJ
, 0},
5020 {"i915_pc8_status", i915_pc8_status
, 0},
5021 {"i915_power_domain_info", i915_power_domain_info
, 0},
5022 {"i915_display_info", i915_display_info
, 0},
5023 {"i915_semaphore_status", i915_semaphore_status
, 0},
5024 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5025 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5026 {"i915_wa_registers", i915_wa_registers
, 0},
5027 {"i915_ddb_info", i915_ddb_info
, 0},
5028 {"i915_sseu_status", i915_sseu_status
, 0},
5029 {"i915_drrs_status", i915_drrs_status
, 0},
5030 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5032 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5034 static const struct i915_debugfs_files
{
5036 const struct file_operations
*fops
;
5037 } i915_debugfs_files
[] = {
5038 {"i915_wedged", &i915_wedged_fops
},
5039 {"i915_max_freq", &i915_max_freq_fops
},
5040 {"i915_min_freq", &i915_min_freq_fops
},
5041 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5042 {"i915_ring_stop", &i915_ring_stop_fops
},
5043 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5044 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5045 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5046 {"i915_error_state", &i915_error_state_fops
},
5047 {"i915_next_seqno", &i915_next_seqno_fops
},
5048 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5049 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5050 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5051 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5052 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5053 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5054 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5055 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5058 void intel_display_crc_init(struct drm_device
*dev
)
5060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5063 for_each_pipe(dev_priv
, pipe
) {
5064 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5066 pipe_crc
->opened
= false;
5067 spin_lock_init(&pipe_crc
->lock
);
5068 init_waitqueue_head(&pipe_crc
->wq
);
5072 int i915_debugfs_init(struct drm_minor
*minor
)
5076 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5080 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5081 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5086 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5087 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5088 i915_debugfs_files
[i
].name
,
5089 i915_debugfs_files
[i
].fops
);
5094 return drm_debugfs_create_files(i915_debugfs_list
,
5095 I915_DEBUGFS_ENTRIES
,
5096 minor
->debugfs_root
, minor
);
5099 void i915_debugfs_cleanup(struct drm_minor
*minor
)
5103 drm_debugfs_remove_files(i915_debugfs_list
,
5104 I915_DEBUGFS_ENTRIES
, minor
);
5106 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5109 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5110 struct drm_info_list
*info_list
=
5111 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5113 drm_debugfs_remove_files(info_list
, 1, minor
);
5116 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5117 struct drm_info_list
*info_list
=
5118 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5120 drm_debugfs_remove_files(info_list
, 1, minor
);
5125 /* DPCD dump start address. */
5126 unsigned int offset
;
5127 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5129 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5131 /* Only valid for eDP. */
5135 static const struct dpcd_block i915_dpcd_debug
[] = {
5136 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5137 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5138 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5139 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5140 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5141 { .offset
= DP_SET_POWER
},
5142 { .offset
= DP_EDP_DPCD_REV
},
5143 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5144 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5145 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5148 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5150 struct drm_connector
*connector
= m
->private;
5151 struct intel_dp
*intel_dp
=
5152 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5157 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5158 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5159 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5162 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5165 /* low tech for now */
5166 if (WARN_ON(size
> sizeof(buf
)))
5169 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5171 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5172 size
, b
->offset
, err
);
5176 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5182 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5184 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5187 static const struct file_operations i915_dpcd_fops
= {
5188 .owner
= THIS_MODULE
,
5189 .open
= i915_dpcd_open
,
5191 .llseek
= seq_lseek
,
5192 .release
= single_release
,
5196 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5197 * @connector: pointer to a registered drm_connector
5199 * Cleanup will be done by drm_connector_unregister() through a call to
5200 * drm_debugfs_connector_remove().
5202 * Returns 0 on success, negative error codes on error.
5204 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5206 struct dentry
*root
= connector
->debugfs_entry
;
5208 /* The connector must have been registered beforehands. */
5212 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5213 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5214 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,