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serial: imx: Move imx_port_ucrs_save/restore under CONFIG_CONSOLE_POLL
[linux-2.6/btrfs-unstable.git] / drivers / tty / serial / imx.c
bloba657f966b8528997daee32c7273837efc1ab0334
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/io.h>
52
53 #include <asm/irq.h>
54 #include <linux/platform_data/serial-imx.h>
55
56 /* Register definitions */
57 #define URXD0 0x0 /* Receiver Register */
58 #define URTX0 0x40 /* Transmitter Register */
59 #define UCR1 0x80 /* Control Register 1 */
60 #define UCR2 0x84 /* Control Register 2 */
61 #define UCR3 0x88 /* Control Register 3 */
62 #define UCR4 0x8c /* Control Register 4 */
63 #define UFCR 0x90 /* FIFO Control Register */
64 #define USR1 0x94 /* Status Register 1 */
65 #define USR2 0x98 /* Status Register 2 */
66 #define UESC 0x9c /* Escape Character Register */
67 #define UTIM 0xa0 /* Escape Timer Register */
68 #define UBIR 0xa4 /* BRM Incremental Register */
69 #define UBMR 0xa8 /* BRM Modulator Register */
70 #define UBRC 0xac /* Baud Rate Count Register */
71 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
72 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
73 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
74
75 /* UART Control Register Bit Fields.*/
76 #define URXD_CHARRDY (1<<15)
77 #define URXD_ERR (1<<14)
78 #define URXD_OVRRUN (1<<13)
79 #define URXD_FRMERR (1<<12)
80 #define URXD_BRK (1<<11)
81 #define URXD_PRERR (1<<10)
82 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
83 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
84 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
85 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
86 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
87 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
88 #define UCR1_IREN (1<<7) /* Infrared interface enable */
89 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
90 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
91 #define UCR1_SNDBRK (1<<4) /* Send break */
92 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
93 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
94 #define UCR1_DOZE (1<<1) /* Doze */
95 #define UCR1_UARTEN (1<<0) /* UART enabled */
96 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
97 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
98 #define UCR2_CTSC (1<<13) /* CTS pin control */
99 #define UCR2_CTS (1<<12) /* Clear to send */
100 #define UCR2_ESCEN (1<<11) /* Escape enable */
101 #define UCR2_PREN (1<<8) /* Parity enable */
102 #define UCR2_PROE (1<<7) /* Parity odd/even */
103 #define UCR2_STPB (1<<6) /* Stop */
104 #define UCR2_WS (1<<5) /* Word size */
105 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
106 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
107 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
108 #define UCR2_RXEN (1<<1) /* Receiver enabled */
109 #define UCR2_SRST (1<<0) /* SW reset */
110 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
111 #define UCR3_PARERREN (1<<12) /* Parity enable */
112 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
113 #define UCR3_DSR (1<<10) /* Data set ready */
114 #define UCR3_DCD (1<<9) /* Data carrier detect */
115 #define UCR3_RI (1<<8) /* Ring indicator */
116 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
117 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
118 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
119 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
120 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
121 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
122 #define UCR3_BPEN (1<<0) /* Preset registers enable */
123 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
124 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
125 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
126 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
127 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
128 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
129 #define UCR4_IRSC (1<<5) /* IR special case */
130 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
131 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
132 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
133 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
134 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
135 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
136 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
137 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
138 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
139 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
140 #define USR1_RTSS (1<<14) /* RTS pin status */
141 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
142 #define USR1_RTSD (1<<12) /* RTS delta */
143 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
144 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
145 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
146 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
147 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
148 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
149 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
150 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
151 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
152 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
153 #define USR2_IDLE (1<<12) /* Idle condition */
154 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
155 #define USR2_WAKE (1<<7) /* Wake */
156 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
157 #define USR2_TXDC (1<<3) /* Transmitter complete */
158 #define USR2_BRCD (1<<2) /* Break condition */
159 #define USR2_ORE (1<<1) /* Overrun error */
160 #define USR2_RDR (1<<0) /* Recv data ready */
161 #define UTS_FRCPERR (1<<13) /* Force parity error */
162 #define UTS_LOOP (1<<12) /* Loop tx and rx */
163 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
164 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
165 #define UTS_TXFULL (1<<4) /* TxFIFO full */
166 #define UTS_RXFULL (1<<3) /* RxFIFO full */
167 #define UTS_SOFTRST (1<<0) /* Software reset */
168
169 /* We've been assigned a range on the "Low-density serial ports" major */
170 #define SERIAL_IMX_MAJOR 207
171 #define MINOR_START 16
172 #define DEV_NAME "ttymxc"
173
174 /*
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
179 */
180 #define MCTRL_TIMEOUT (250*HZ/1000)
181
182 #define DRIVER_NAME "IMX-uart"
183
184 #define UART_NR 8
185
186 /* i.mx21 type uart runs on all i.mx except i.mx1 */
187 enum imx_uart_type {
188 IMX1_UART,
189 IMX21_UART,
190 };
191
192 /* device type dependent stuff */
193 struct imx_uart_data {
194 unsigned uts_reg;
195 enum imx_uart_type devtype;
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 int txirq, rxirq, rtsirq;
203 unsigned int have_rtscts:1;
204 unsigned int use_irda:1;
205 unsigned int irda_inv_rx:1;
206 unsigned int irda_inv_tx:1;
207 unsigned short trcv_delay; /* transceiver delay */
208 struct clk *clk_ipg;
209 struct clk *clk_per;
210 const struct imx_uart_data *devdata;
211 };
212
213 struct imx_port_ucrs {
214 unsigned int ucr1;
215 unsigned int ucr2;
216 unsigned int ucr3;
217 };
218
219 #ifdef CONFIG_IRDA
220 #define USE_IRDA(sport) ((sport)->use_irda)
221 #else
222 #define USE_IRDA(sport) (0)
223 #endif
224
225 static struct imx_uart_data imx_uart_devdata[] = {
226 [IMX1_UART] = {
227 .uts_reg = IMX1_UTS,
228 .devtype = IMX1_UART,
229 },
230 [IMX21_UART] = {
231 .uts_reg = IMX21_UTS,
232 .devtype = IMX21_UART,
233 },
234 };
235
236 static struct platform_device_id imx_uart_devtype[] = {
237 {
238 .name = "imx1-uart",
239 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
240 }, {
241 .name = "imx21-uart",
242 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
243 }, {
244 /* sentinel */
245 }
246 };
247 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
248
249 static struct of_device_id imx_uart_dt_ids[] = {
250 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
251 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
252 { /* sentinel */ }
253 };
254 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
255
256 static inline unsigned uts_reg(struct imx_port *sport)
257 {
258 return sport->devdata->uts_reg;
259 }
260
261 static inline int is_imx1_uart(struct imx_port *sport)
262 {
263 return sport->devdata->devtype == IMX1_UART;
264 }
265
266 static inline int is_imx21_uart(struct imx_port *sport)
267 {
268 return sport->devdata->devtype == IMX21_UART;
269 }
270
271 /*
272 * Handle any change of modem status signal since we were last called.
273 */
274 static void imx_mctrl_check(struct imx_port *sport)
275 {
276 unsigned int status, changed;
277
278 status = sport->port.ops->get_mctrl(&sport->port);
279 changed = status ^ sport->old_status;
280
281 if (changed == 0)
282 return;
283
284 sport->old_status = status;
285
286 if (changed & TIOCM_RI)
287 sport->port.icount.rng++;
288 if (changed & TIOCM_DSR)
289 sport->port.icount.dsr++;
290 if (changed & TIOCM_CAR)
291 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
292 if (changed & TIOCM_CTS)
293 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
294
295 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
296 }
297
298 /*
299 * This is our per-port timeout handler, for checking the
300 * modem status signals.
301 */
302 static void imx_timeout(unsigned long data)
303 {
304 struct imx_port *sport = (struct imx_port *)data;
305 unsigned long flags;
306
307 if (sport->port.state) {
308 spin_lock_irqsave(&sport->port.lock, flags);
309 imx_mctrl_check(sport);
310 spin_unlock_irqrestore(&sport->port.lock, flags);
311
312 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
313 }
314 }
315
316 /*
317 * interrupts disabled on entry
318 */
319 static void imx_stop_tx(struct uart_port *port)
320 {
321 struct imx_port *sport = (struct imx_port *)port;
322 unsigned long temp;
323
324 if (USE_IRDA(sport)) {
325 /* half duplex - wait for end of transmission */
326 int n = 256;
327 while ((--n > 0) &&
328 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
329 udelay(5);
330 barrier();
331 }
332 /*
333 * irda transceiver - wait a bit more to avoid
334 * cutoff, hardware dependent
335 */
336 udelay(sport->trcv_delay);
337
338 /*
339 * half duplex - reactivate receive mode,
340 * flush receive pipe echo crap
341 */
342 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
343 temp = readl(sport->port.membase + UCR1);
344 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
345 writel(temp, sport->port.membase + UCR1);
346
347 temp = readl(sport->port.membase + UCR4);
348 temp &= ~(UCR4_TCEN);
349 writel(temp, sport->port.membase + UCR4);
350
351 while (readl(sport->port.membase + URXD0) &
352 URXD_CHARRDY)
353 barrier();
354
355 temp = readl(sport->port.membase + UCR1);
356 temp |= UCR1_RRDYEN;
357 writel(temp, sport->port.membase + UCR1);
358
359 temp = readl(sport->port.membase + UCR4);
360 temp |= UCR4_DREN;
361 writel(temp, sport->port.membase + UCR4);
362 }
363 return;
364 }
365
366 temp = readl(sport->port.membase + UCR1);
367 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
368 }
369
370 /*
371 * interrupts disabled on entry
372 */
373 static void imx_stop_rx(struct uart_port *port)
374 {
375 struct imx_port *sport = (struct imx_port *)port;
376 unsigned long temp;
377
378 temp = readl(sport->port.membase + UCR2);
379 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
380 }
381
382 /*
383 * Set the modem control timer to fire immediately.
384 */
385 static void imx_enable_ms(struct uart_port *port)
386 {
387 struct imx_port *sport = (struct imx_port *)port;
388
389 mod_timer(&sport->timer, jiffies);
390 }
391
392 static inline void imx_transmit_buffer(struct imx_port *sport)
393 {
394 struct circ_buf *xmit = &sport->port.state->xmit;
395
396 while (!uart_circ_empty(xmit) &&
397 !(readl(sport->port.membase + uts_reg(sport))
398 & UTS_TXFULL)) {
399 /* send xmit->buf[xmit->tail]
400 * out the port here */
401 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
402 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
403 sport->port.icount.tx++;
404 }
405
406 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
407 uart_write_wakeup(&sport->port);
408
409 if (uart_circ_empty(xmit))
410 imx_stop_tx(&sport->port);
411 }
412
413 /*
414 * interrupts disabled on entry
415 */
416 static void imx_start_tx(struct uart_port *port)
417 {
418 struct imx_port *sport = (struct imx_port *)port;
419 unsigned long temp;
420
421 if (USE_IRDA(sport)) {
422 /* half duplex in IrDA mode; have to disable receive mode */
423 temp = readl(sport->port.membase + UCR4);
424 temp &= ~(UCR4_DREN);
425 writel(temp, sport->port.membase + UCR4);
426
427 temp = readl(sport->port.membase + UCR1);
428 temp &= ~(UCR1_RRDYEN);
429 writel(temp, sport->port.membase + UCR1);
430 }
431
432 temp = readl(sport->port.membase + UCR1);
433 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
434
435 if (USE_IRDA(sport)) {
436 temp = readl(sport->port.membase + UCR1);
437 temp |= UCR1_TRDYEN;
438 writel(temp, sport->port.membase + UCR1);
439
440 temp = readl(sport->port.membase + UCR4);
441 temp |= UCR4_TCEN;
442 writel(temp, sport->port.membase + UCR4);
443 }
444
445 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
446 imx_transmit_buffer(sport);
447 }
448
449 static irqreturn_t imx_rtsint(int irq, void *dev_id)
450 {
451 struct imx_port *sport = dev_id;
452 unsigned int val;
453 unsigned long flags;
454
455 spin_lock_irqsave(&sport->port.lock, flags);
456
457 writel(USR1_RTSD, sport->port.membase + USR1);
458 val = readl(sport->port.membase + USR1) & USR1_RTSS;
459 uart_handle_cts_change(&sport->port, !!val);
460 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
461
462 spin_unlock_irqrestore(&sport->port.lock, flags);
463 return IRQ_HANDLED;
464 }
465
466 static irqreturn_t imx_txint(int irq, void *dev_id)
467 {
468 struct imx_port *sport = dev_id;
469 struct circ_buf *xmit = &sport->port.state->xmit;
470 unsigned long flags;
471
472 spin_lock_irqsave(&sport->port.lock, flags);
473 if (sport->port.x_char) {
474 /* Send next char */
475 writel(sport->port.x_char, sport->port.membase + URTX0);
476 goto out;
477 }
478
479 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
480 imx_stop_tx(&sport->port);
481 goto out;
482 }
483
484 imx_transmit_buffer(sport);
485
486 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
487 uart_write_wakeup(&sport->port);
488
489 out:
490 spin_unlock_irqrestore(&sport->port.lock, flags);
491 return IRQ_HANDLED;
492 }
493
494 static irqreturn_t imx_rxint(int irq, void *dev_id)
495 {
496 struct imx_port *sport = dev_id;
497 unsigned int rx, flg, ignored = 0;
498 struct tty_port *port = &sport->port.state->port;
499 unsigned long flags, temp;
500
501 spin_lock_irqsave(&sport->port.lock, flags);
502
503 while (readl(sport->port.membase + USR2) & USR2_RDR) {
504 flg = TTY_NORMAL;
505 sport->port.icount.rx++;
506
507 rx = readl(sport->port.membase + URXD0);
508
509 temp = readl(sport->port.membase + USR2);
510 if (temp & USR2_BRCD) {
511 writel(USR2_BRCD, sport->port.membase + USR2);
512 if (uart_handle_break(&sport->port))
513 continue;
514 }
515
516 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
517 continue;
518
519 if (unlikely(rx & URXD_ERR)) {
520 if (rx & URXD_BRK)
521 sport->port.icount.brk++;
522 else if (rx & URXD_PRERR)
523 sport->port.icount.parity++;
524 else if (rx & URXD_FRMERR)
525 sport->port.icount.frame++;
526 if (rx & URXD_OVRRUN)
527 sport->port.icount.overrun++;
528
529 if (rx & sport->port.ignore_status_mask) {
530 if (++ignored > 100)
531 goto out;
532 continue;
533 }
534
535 rx &= sport->port.read_status_mask;
536
537 if (rx & URXD_BRK)
538 flg = TTY_BREAK;
539 else if (rx & URXD_PRERR)
540 flg = TTY_PARITY;
541 else if (rx & URXD_FRMERR)
542 flg = TTY_FRAME;
543 if (rx & URXD_OVRRUN)
544 flg = TTY_OVERRUN;
545
546 #ifdef SUPPORT_SYSRQ
547 sport->port.sysrq = 0;
548 #endif
549 }
550
551 tty_insert_flip_char(port, rx, flg);
552 }
553
554 out:
555 spin_unlock_irqrestore(&sport->port.lock, flags);
556 tty_flip_buffer_push(port);
557 return IRQ_HANDLED;
558 }
559
560 static irqreturn_t imx_int(int irq, void *dev_id)
561 {
562 struct imx_port *sport = dev_id;
563 unsigned int sts;
564
565 sts = readl(sport->port.membase + USR1);
566
567 if (sts & USR1_RRDY)
568 imx_rxint(irq, dev_id);
569
570 if (sts & USR1_TRDY &&
571 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
572 imx_txint(irq, dev_id);
573
574 if (sts & USR1_RTSD)
575 imx_rtsint(irq, dev_id);
576
577 if (sts & USR1_AWAKE)
578 writel(USR1_AWAKE, sport->port.membase + USR1);
579
580 return IRQ_HANDLED;
581 }
582
583 /*
584 * Return TIOCSER_TEMT when transmitter is not busy.
585 */
586 static unsigned int imx_tx_empty(struct uart_port *port)
587 {
588 struct imx_port *sport = (struct imx_port *)port;
589
590 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
591 }
592
593 /*
594 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
595 */
596 static unsigned int imx_get_mctrl(struct uart_port *port)
597 {
598 struct imx_port *sport = (struct imx_port *)port;
599 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
600
601 if (readl(sport->port.membase + USR1) & USR1_RTSS)
602 tmp |= TIOCM_CTS;
603
604 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
605 tmp |= TIOCM_RTS;
606
607 return tmp;
608 }
609
610 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
611 {
612 struct imx_port *sport = (struct imx_port *)port;
613 unsigned long temp;
614
615 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
616
617 if (mctrl & TIOCM_RTS)
618 temp |= UCR2_CTS;
619
620 writel(temp, sport->port.membase + UCR2);
621 }
622
623 /*
624 * Interrupts always disabled.
625 */
626 static void imx_break_ctl(struct uart_port *port, int break_state)
627 {
628 struct imx_port *sport = (struct imx_port *)port;
629 unsigned long flags, temp;
630
631 spin_lock_irqsave(&sport->port.lock, flags);
632
633 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
634
635 if (break_state != 0)
636 temp |= UCR1_SNDBRK;
637
638 writel(temp, sport->port.membase + UCR1);
639
640 spin_unlock_irqrestore(&sport->port.lock, flags);
641 }
642
643 #define TXTL 2 /* reset default */
644 #define RXTL 1 /* reset default */
645
646 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
647 {
648 unsigned int val;
649
650 /* set receiver / transmitter trigger level */
651 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
652 val |= TXTL << UFCR_TXTL_SHF | RXTL;
653 writel(val, sport->port.membase + UFCR);
654 return 0;
655 }
656
657 /* half the RX buffer size */
658 #define CTSTL 16
659
660 static int imx_startup(struct uart_port *port)
661 {
662 struct imx_port *sport = (struct imx_port *)port;
663 int retval;
664 unsigned long flags, temp;
665
666 imx_setup_ufcr(sport, 0);
667
668 /* disable the DREN bit (Data Ready interrupt enable) before
669 * requesting IRQs
670 */
671 temp = readl(sport->port.membase + UCR4);
672
673 if (USE_IRDA(sport))
674 temp |= UCR4_IRSC;
675
676 /* set the trigger level for CTS */
677 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
678 temp |= CTSTL << UCR4_CTSTL_SHF;
679
680 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
681
682 if (USE_IRDA(sport)) {
683 /* reset fifo's and state machines */
684 int i = 100;
685 temp = readl(sport->port.membase + UCR2);
686 temp &= ~UCR2_SRST;
687 writel(temp, sport->port.membase + UCR2);
688 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
689 (--i > 0)) {
690 udelay(1);
691 }
692 }
693
694 /*
695 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
696 * chips only have one interrupt.
697 */
698 if (sport->txirq > 0) {
699 retval = request_irq(sport->rxirq, imx_rxint, 0,
700 DRIVER_NAME, sport);
701 if (retval)
702 goto error_out1;
703
704 retval = request_irq(sport->txirq, imx_txint, 0,
705 DRIVER_NAME, sport);
706 if (retval)
707 goto error_out2;
708
709 /* do not use RTS IRQ on IrDA */
710 if (!USE_IRDA(sport)) {
711 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
712 DRIVER_NAME, sport);
713 if (retval)
714 goto error_out3;
715 }
716 } else {
717 retval = request_irq(sport->port.irq, imx_int, 0,
718 DRIVER_NAME, sport);
719 if (retval) {
720 free_irq(sport->port.irq, sport);
721 goto error_out1;
722 }
723 }
724
725 spin_lock_irqsave(&sport->port.lock, flags);
726 /*
727 * Finally, clear and enable interrupts
728 */
729 writel(USR1_RTSD, sport->port.membase + USR1);
730
731 temp = readl(sport->port.membase + UCR1);
732 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
733
734 if (USE_IRDA(sport)) {
735 temp |= UCR1_IREN;
736 temp &= ~(UCR1_RTSDEN);
737 }
738
739 writel(temp, sport->port.membase + UCR1);
740
741 temp = readl(sport->port.membase + UCR2);
742 temp |= (UCR2_RXEN | UCR2_TXEN);
743 writel(temp, sport->port.membase + UCR2);
744
745 if (USE_IRDA(sport)) {
746 /* clear RX-FIFO */
747 int i = 64;
748 while ((--i > 0) &&
749 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
750 barrier();
751 }
752 }
753
754 if (is_imx21_uart(sport)) {
755 temp = readl(sport->port.membase + UCR3);
756 temp |= IMX21_UCR3_RXDMUXSEL;
757 writel(temp, sport->port.membase + UCR3);
758 }
759
760 if (USE_IRDA(sport)) {
761 temp = readl(sport->port.membase + UCR4);
762 if (sport->irda_inv_rx)
763 temp |= UCR4_INVR;
764 else
765 temp &= ~(UCR4_INVR);
766 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
767
768 temp = readl(sport->port.membase + UCR3);
769 if (sport->irda_inv_tx)
770 temp |= UCR3_INVT;
771 else
772 temp &= ~(UCR3_INVT);
773 writel(temp, sport->port.membase + UCR3);
774 }
775
776 /*
777 * Enable modem status interrupts
778 */
779 imx_enable_ms(&sport->port);
780 spin_unlock_irqrestore(&sport->port.lock, flags);
781
782 if (USE_IRDA(sport)) {
783 struct imxuart_platform_data *pdata;
784 pdata = sport->port.dev->platform_data;
785 sport->irda_inv_rx = pdata->irda_inv_rx;
786 sport->irda_inv_tx = pdata->irda_inv_tx;
787 sport->trcv_delay = pdata->transceiver_delay;
788 if (pdata->irda_enable)
789 pdata->irda_enable(1);
790 }
791
792 return 0;
793
794 error_out3:
795 if (sport->txirq)
796 free_irq(sport->txirq, sport);
797 error_out2:
798 if (sport->rxirq)
799 free_irq(sport->rxirq, sport);
800 error_out1:
801 return retval;
802 }
803
804 static void imx_shutdown(struct uart_port *port)
805 {
806 struct imx_port *sport = (struct imx_port *)port;
807 unsigned long temp;
808 unsigned long flags;
809
810 spin_lock_irqsave(&sport->port.lock, flags);
811 temp = readl(sport->port.membase + UCR2);
812 temp &= ~(UCR2_TXEN);
813 writel(temp, sport->port.membase + UCR2);
814 spin_unlock_irqrestore(&sport->port.lock, flags);
815
816 if (USE_IRDA(sport)) {
817 struct imxuart_platform_data *pdata;
818 pdata = sport->port.dev->platform_data;
819 if (pdata->irda_enable)
820 pdata->irda_enable(0);
821 }
822
823 /*
824 * Stop our timer.
825 */
826 del_timer_sync(&sport->timer);
827
828 /*
829 * Free the interrupts
830 */
831 if (sport->txirq > 0) {
832 if (!USE_IRDA(sport))
833 free_irq(sport->rtsirq, sport);
834 free_irq(sport->txirq, sport);
835 free_irq(sport->rxirq, sport);
836 } else
837 free_irq(sport->port.irq, sport);
838
839 /*
840 * Disable all interrupts, port and break condition.
841 */
842
843 spin_lock_irqsave(&sport->port.lock, flags);
844 temp = readl(sport->port.membase + UCR1);
845 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
846 if (USE_IRDA(sport))
847 temp &= ~(UCR1_IREN);
848
849 writel(temp, sport->port.membase + UCR1);
850 spin_unlock_irqrestore(&sport->port.lock, flags);
851 }
852
853 static void
854 imx_set_termios(struct uart_port *port, struct ktermios *termios,
855 struct ktermios *old)
856 {
857 struct imx_port *sport = (struct imx_port *)port;
858 unsigned long flags;
859 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
860 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
861 unsigned int div, ufcr;
862 unsigned long num, denom;
863 uint64_t tdiv64;
864
865 /*
866 * If we don't support modem control lines, don't allow
867 * these to be set.
868 */
869 if (0) {
870 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
871 termios->c_cflag |= CLOCAL;
872 }
873
874 /*
875 * We only support CS7 and CS8.
876 */
877 while ((termios->c_cflag & CSIZE) != CS7 &&
878 (termios->c_cflag & CSIZE) != CS8) {
879 termios->c_cflag &= ~CSIZE;
880 termios->c_cflag |= old_csize;
881 old_csize = CS8;
882 }
883
884 if ((termios->c_cflag & CSIZE) == CS8)
885 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
886 else
887 ucr2 = UCR2_SRST | UCR2_IRTS;
888
889 if (termios->c_cflag & CRTSCTS) {
890 if (sport->have_rtscts) {
891 ucr2 &= ~UCR2_IRTS;
892 ucr2 |= UCR2_CTSC;
893 } else {
894 termios->c_cflag &= ~CRTSCTS;
895 }
896 }
897
898 if (termios->c_cflag & CSTOPB)
899 ucr2 |= UCR2_STPB;
900 if (termios->c_cflag & PARENB) {
901 ucr2 |= UCR2_PREN;
902 if (termios->c_cflag & PARODD)
903 ucr2 |= UCR2_PROE;
904 }
905
906 del_timer_sync(&sport->timer);
907
908 /*
909 * Ask the core to calculate the divisor for us.
910 */
911 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
912 quot = uart_get_divisor(port, baud);
913
914 spin_lock_irqsave(&sport->port.lock, flags);
915
916 sport->port.read_status_mask = 0;
917 if (termios->c_iflag & INPCK)
918 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
919 if (termios->c_iflag & (BRKINT | PARMRK))
920 sport->port.read_status_mask |= URXD_BRK;
921
922 /*
923 * Characters to ignore
924 */
925 sport->port.ignore_status_mask = 0;
926 if (termios->c_iflag & IGNPAR)
927 sport->port.ignore_status_mask |= URXD_PRERR;
928 if (termios->c_iflag & IGNBRK) {
929 sport->port.ignore_status_mask |= URXD_BRK;
930 /*
931 * If we're ignoring parity and break indicators,
932 * ignore overruns too (for real raw support).
933 */
934 if (termios->c_iflag & IGNPAR)
935 sport->port.ignore_status_mask |= URXD_OVRRUN;
936 }
937
938 /*
939 * Update the per-port timeout.
940 */
941 uart_update_timeout(port, termios->c_cflag, baud);
942
943 /*
944 * disable interrupts and drain transmitter
945 */
946 old_ucr1 = readl(sport->port.membase + UCR1);
947 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
948 sport->port.membase + UCR1);
949
950 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
951 barrier();
952
953 /* then, disable everything */
954 old_txrxen = readl(sport->port.membase + UCR2);
955 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
956 sport->port.membase + UCR2);
957 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
958
959 if (USE_IRDA(sport)) {
960 /*
961 * use maximum available submodule frequency to
962 * avoid missing short pulses due to low sampling rate
963 */
964 div = 1;
965 } else {
966 div = sport->port.uartclk / (baud * 16);
967 if (div > 7)
968 div = 7;
969 if (!div)
970 div = 1;
971 }
972
973 rational_best_approximation(16 * div * baud, sport->port.uartclk,
974 1 << 16, 1 << 16, &num, &denom);
975
976 tdiv64 = sport->port.uartclk;
977 tdiv64 *= num;
978 do_div(tdiv64, denom * 16 * div);
979 tty_termios_encode_baud_rate(termios,
980 (speed_t)tdiv64, (speed_t)tdiv64);
981
982 num -= 1;
983 denom -= 1;
984
985 ufcr = readl(sport->port.membase + UFCR);
986 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
987 writel(ufcr, sport->port.membase + UFCR);
988
989 writel(num, sport->port.membase + UBIR);
990 writel(denom, sport->port.membase + UBMR);
991
992 if (is_imx21_uart(sport))
993 writel(sport->port.uartclk / div / 1000,
994 sport->port.membase + IMX21_ONEMS);
995
996 writel(old_ucr1, sport->port.membase + UCR1);
997
998 /* set the parity, stop bits and data size */
999 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1000
1001 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1002 imx_enable_ms(&sport->port);
1003
1004 spin_unlock_irqrestore(&sport->port.lock, flags);
1005 }
1006
1007 static const char *imx_type(struct uart_port *port)
1008 {
1009 struct imx_port *sport = (struct imx_port *)port;
1010
1011 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1012 }
1013
1014 /*
1015 * Release the memory region(s) being used by 'port'.
1016 */
1017 static void imx_release_port(struct uart_port *port)
1018 {
1019 struct platform_device *pdev = to_platform_device(port->dev);
1020 struct resource *mmres;
1021
1022 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1023 release_mem_region(mmres->start, resource_size(mmres));
1024 }
1025
1026 /*
1027 * Request the memory region(s) being used by 'port'.
1028 */
1029 static int imx_request_port(struct uart_port *port)
1030 {
1031 struct platform_device *pdev = to_platform_device(port->dev);
1032 struct resource *mmres;
1033 void *ret;
1034
1035 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1036 if (!mmres)
1037 return -ENODEV;
1038
1039 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1040
1041 return ret ? 0 : -EBUSY;
1042 }
1043
1044 /*
1045 * Configure/autoconfigure the port.
1046 */
1047 static void imx_config_port(struct uart_port *port, int flags)
1048 {
1049 struct imx_port *sport = (struct imx_port *)port;
1050
1051 if (flags & UART_CONFIG_TYPE &&
1052 imx_request_port(&sport->port) == 0)
1053 sport->port.type = PORT_IMX;
1054 }
1055
1056 /*
1057 * Verify the new serial_struct (for TIOCSSERIAL).
1058 * The only change we allow are to the flags and type, and
1059 * even then only between PORT_IMX and PORT_UNKNOWN
1060 */
1061 static int
1062 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1063 {
1064 struct imx_port *sport = (struct imx_port *)port;
1065 int ret = 0;
1066
1067 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1068 ret = -EINVAL;
1069 if (sport->port.irq != ser->irq)
1070 ret = -EINVAL;
1071 if (ser->io_type != UPIO_MEM)
1072 ret = -EINVAL;
1073 if (sport->port.uartclk / 16 != ser->baud_base)
1074 ret = -EINVAL;
1075 if ((void *)sport->port.mapbase != ser->iomem_base)
1076 ret = -EINVAL;
1077 if (sport->port.iobase != ser->port)
1078 ret = -EINVAL;
1079 if (ser->hub6 != 0)
1080 ret = -EINVAL;
1081 return ret;
1082 }
1083
1084 #if defined(CONFIG_CONSOLE_POLL)
1085 /*
1086 * Save and restore functions for UCR1, UCR2 and UCR3 registers
1087 */
1088 static void imx_port_ucrs_save(struct uart_port *port,
1089 struct imx_port_ucrs *ucr)
1090 {
1091 /* save control registers */
1092 ucr->ucr1 = readl(port->membase + UCR1);
1093 ucr->ucr2 = readl(port->membase + UCR2);
1094 ucr->ucr3 = readl(port->membase + UCR3);
1095 }
1096
1097 static void imx_port_ucrs_restore(struct uart_port *port,
1098 struct imx_port_ucrs *ucr)
1099 {
1100 /* restore control registers */
1101 writel(ucr->ucr1, port->membase + UCR1);
1102 writel(ucr->ucr2, port->membase + UCR2);
1103 writel(ucr->ucr3, port->membase + UCR3);
1104 }
1105
1106 static int imx_poll_get_char(struct uart_port *port)
1107 {
1108 struct imx_port_ucrs old_ucr;
1109 unsigned int status;
1110 unsigned char c;
1111
1112 /* save control registers */
1113 imx_port_ucrs_save(port, &old_ucr);
1114
1115 /* disable interrupts */
1116 writel(UCR1_UARTEN, port->membase + UCR1);
1117 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1118 port->membase + UCR2);
1119 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1120 port->membase + UCR3);
1121
1122 /* poll */
1123 do {
1124 status = readl(port->membase + USR2);
1125 } while (~status & USR2_RDR);
1126
1127 /* read */
1128 c = readl(port->membase + URXD0);
1129
1130 /* restore control registers */
1131 imx_port_ucrs_restore(port, &old_ucr);
1132
1133 return c;
1134 }
1135
1136 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1137 {
1138 struct imx_port_ucrs old_ucr;
1139 unsigned int status;
1140
1141 /* save control registers */
1142 imx_port_ucrs_save(port, &old_ucr);
1143
1144 /* disable interrupts */
1145 writel(UCR1_UARTEN, port->membase + UCR1);
1146 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1147 port->membase + UCR2);
1148 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1149 port->membase + UCR3);
1150
1151 /* drain */
1152 do {
1153 status = readl(port->membase + USR1);
1154 } while (~status & USR1_TRDY);
1155
1156 /* write */
1157 writel(c, port->membase + URTX0);
1158
1159 /* flush */
1160 do {
1161 status = readl(port->membase + USR2);
1162 } while (~status & USR2_TXDC);
1163
1164 /* restore control registers */
1165 imx_port_ucrs_restore(port, &old_ucr);
1166 }
1167 #endif
1168
1169 static struct uart_ops imx_pops = {
1170 .tx_empty = imx_tx_empty,
1171 .set_mctrl = imx_set_mctrl,
1172 .get_mctrl = imx_get_mctrl,
1173 .stop_tx = imx_stop_tx,
1174 .start_tx = imx_start_tx,
1175 .stop_rx = imx_stop_rx,
1176 .enable_ms = imx_enable_ms,
1177 .break_ctl = imx_break_ctl,
1178 .startup = imx_startup,
1179 .shutdown = imx_shutdown,
1180 .set_termios = imx_set_termios,
1181 .type = imx_type,
1182 .release_port = imx_release_port,
1183 .request_port = imx_request_port,
1184 .config_port = imx_config_port,
1185 .verify_port = imx_verify_port,
1186 #if defined(CONFIG_CONSOLE_POLL)
1187 .poll_get_char = imx_poll_get_char,
1188 .poll_put_char = imx_poll_put_char,
1189 #endif
1190 };
1191
1192 static struct imx_port *imx_ports[UART_NR];
1193
1194 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1195 static void imx_console_putchar(struct uart_port *port, int ch)
1196 {
1197 struct imx_port *sport = (struct imx_port *)port;
1198
1199 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1200 barrier();
1201
1202 writel(ch, sport->port.membase + URTX0);
1203 }
1204
1205 /*
1206 * Interrupts are disabled on entering
1207 */
1208 static void
1209 imx_console_write(struct console *co, const char *s, unsigned int count)
1210 {
1211 struct imx_port *sport = imx_ports[co->index];
1212 struct imx_port_ucrs old_ucr;
1213 unsigned int ucr1;
1214 unsigned long flags;
1215
1216 spin_lock_irqsave(&sport->port.lock, flags);
1217
1218 /*
1219 * First, save UCR1/2/3 and then disable interrupts
1220 */
1221 imx_port_ucrs_save(&sport->port, &old_ucr);
1222 ucr1 = old_ucr.ucr1;
1223
1224 if (is_imx1_uart(sport))
1225 ucr1 |= IMX1_UCR1_UARTCLKEN;
1226 ucr1 |= UCR1_UARTEN;
1227 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1228
1229 writel(ucr1, sport->port.membase + UCR1);
1230
1231 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1232
1233 uart_console_write(&sport->port, s, count, imx_console_putchar);
1234
1235 /*
1236 * Finally, wait for transmitter to become empty
1237 * and restore UCR1/2/3
1238 */
1239 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1240
1241 imx_port_ucrs_restore(&sport->port, &old_ucr);
1242
1243 spin_unlock_irqrestore(&sport->port.lock, flags);
1244 }
1245
1246 /*
1247 * If the port was already initialised (eg, by a boot loader),
1248 * try to determine the current setup.
1249 */
1250 static void __init
1251 imx_console_get_options(struct imx_port *sport, int *baud,
1252 int *parity, int *bits)
1253 {
1254
1255 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1256 /* ok, the port was enabled */
1257 unsigned int ucr2, ubir, ubmr, uartclk;
1258 unsigned int baud_raw;
1259 unsigned int ucfr_rfdiv;
1260
1261 ucr2 = readl(sport->port.membase + UCR2);
1262
1263 *parity = 'n';
1264 if (ucr2 & UCR2_PREN) {
1265 if (ucr2 & UCR2_PROE)
1266 *parity = 'o';
1267 else
1268 *parity = 'e';
1269 }
1270
1271 if (ucr2 & UCR2_WS)
1272 *bits = 8;
1273 else
1274 *bits = 7;
1275
1276 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1277 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1278
1279 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1280 if (ucfr_rfdiv == 6)
1281 ucfr_rfdiv = 7;
1282 else
1283 ucfr_rfdiv = 6 - ucfr_rfdiv;
1284
1285 uartclk = clk_get_rate(sport->clk_per);
1286 uartclk /= ucfr_rfdiv;
1287
1288 { /*
1289 * The next code provides exact computation of
1290 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1291 * without need of float support or long long division,
1292 * which would be required to prevent 32bit arithmetic overflow
1293 */
1294 unsigned int mul = ubir + 1;
1295 unsigned int div = 16 * (ubmr + 1);
1296 unsigned int rem = uartclk % div;
1297
1298 baud_raw = (uartclk / div) * mul;
1299 baud_raw += (rem * mul + div / 2) / div;
1300 *baud = (baud_raw + 50) / 100 * 100;
1301 }
1302
1303 if (*baud != baud_raw)
1304 pr_info("Console IMX rounded baud rate from %d to %d\n",
1305 baud_raw, *baud);
1306 }
1307 }
1308
1309 static int __init
1310 imx_console_setup(struct console *co, char *options)
1311 {
1312 struct imx_port *sport;
1313 int baud = 9600;
1314 int bits = 8;
1315 int parity = 'n';
1316 int flow = 'n';
1317
1318 /*
1319 * Check whether an invalid uart number has been specified, and
1320 * if so, search for the first available port that does have
1321 * console support.
1322 */
1323 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1324 co->index = 0;
1325 sport = imx_ports[co->index];
1326 if (sport == NULL)
1327 return -ENODEV;
1328
1329 if (options)
1330 uart_parse_options(options, &baud, &parity, &bits, &flow);
1331 else
1332 imx_console_get_options(sport, &baud, &parity, &bits);
1333
1334 imx_setup_ufcr(sport, 0);
1335
1336 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1337 }
1338
1339 static struct uart_driver imx_reg;
1340 static struct console imx_console = {
1341 .name = DEV_NAME,
1342 .write = imx_console_write,
1343 .device = uart_console_device,
1344 .setup = imx_console_setup,
1345 .flags = CON_PRINTBUFFER,
1346 .index = -1,
1347 .data = &imx_reg,
1348 };
1349
1350 #define IMX_CONSOLE &imx_console
1351 #else
1352 #define IMX_CONSOLE NULL
1353 #endif
1354
1355 static struct uart_driver imx_reg = {
1356 .owner = THIS_MODULE,
1357 .driver_name = DRIVER_NAME,
1358 .dev_name = DEV_NAME,
1359 .major = SERIAL_IMX_MAJOR,
1360 .minor = MINOR_START,
1361 .nr = ARRAY_SIZE(imx_ports),
1362 .cons = IMX_CONSOLE,
1363 };
1364
1365 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1366 {
1367 struct imx_port *sport = platform_get_drvdata(dev);
1368 unsigned int val;
1369
1370 /* enable wakeup from i.MX UART */
1371 val = readl(sport->port.membase + UCR3);
1372 val |= UCR3_AWAKEN;
1373 writel(val, sport->port.membase + UCR3);
1374
1375 uart_suspend_port(&imx_reg, &sport->port);
1376
1377 return 0;
1378 }
1379
1380 static int serial_imx_resume(struct platform_device *dev)
1381 {
1382 struct imx_port *sport = platform_get_drvdata(dev);
1383 unsigned int val;
1384
1385 /* disable wakeup from i.MX UART */
1386 val = readl(sport->port.membase + UCR3);
1387 val &= ~UCR3_AWAKEN;
1388 writel(val, sport->port.membase + UCR3);
1389
1390 uart_resume_port(&imx_reg, &sport->port);
1391
1392 return 0;
1393 }
1394
1395 #ifdef CONFIG_OF
1396 /*
1397 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1398 * could successfully get all information from dt or a negative errno.
1399 */
1400 static int serial_imx_probe_dt(struct imx_port *sport,
1401 struct platform_device *pdev)
1402 {
1403 struct device_node *np = pdev->dev.of_node;
1404 const struct of_device_id *of_id =
1405 of_match_device(imx_uart_dt_ids, &pdev->dev);
1406 int ret;
1407
1408 if (!np)
1409 /* no device tree device */
1410 return 1;
1411
1412 ret = of_alias_get_id(np, "serial");
1413 if (ret < 0) {
1414 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1415 return ret;
1416 }
1417 sport->port.line = ret;
1418
1419 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1420 sport->have_rtscts = 1;
1421
1422 if (of_get_property(np, "fsl,irda-mode", NULL))
1423 sport->use_irda = 1;
1424
1425 sport->devdata = of_id->data;
1426
1427 return 0;
1428 }
1429 #else
1430 static inline int serial_imx_probe_dt(struct imx_port *sport,
1431 struct platform_device *pdev)
1432 {
1433 return 1;
1434 }
1435 #endif
1436
1437 static void serial_imx_probe_pdata(struct imx_port *sport,
1438 struct platform_device *pdev)
1439 {
1440 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1441
1442 sport->port.line = pdev->id;
1443 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1444
1445 if (!pdata)
1446 return;
1447
1448 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1449 sport->have_rtscts = 1;
1450
1451 if (pdata->flags & IMXUART_IRDA)
1452 sport->use_irda = 1;
1453 }
1454
1455 static int serial_imx_probe(struct platform_device *pdev)
1456 {
1457 struct imx_port *sport;
1458 struct imxuart_platform_data *pdata;
1459 void __iomem *base;
1460 int ret = 0;
1461 struct resource *res;
1462 struct pinctrl *pinctrl;
1463
1464 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1465 if (!sport)
1466 return -ENOMEM;
1467
1468 ret = serial_imx_probe_dt(sport, pdev);
1469 if (ret > 0)
1470 serial_imx_probe_pdata(sport, pdev);
1471 else if (ret < 0)
1472 return ret;
1473
1474 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1475 if (!res)
1476 return -ENODEV;
1477
1478 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
1479 if (!base)
1480 return -ENOMEM;
1481
1482 sport->port.dev = &pdev->dev;
1483 sport->port.mapbase = res->start;
1484 sport->port.membase = base;
1485 sport->port.type = PORT_IMX,
1486 sport->port.iotype = UPIO_MEM;
1487 sport->port.irq = platform_get_irq(pdev, 0);
1488 sport->rxirq = platform_get_irq(pdev, 0);
1489 sport->txirq = platform_get_irq(pdev, 1);
1490 sport->rtsirq = platform_get_irq(pdev, 2);
1491 sport->port.fifosize = 32;
1492 sport->port.ops = &imx_pops;
1493 sport->port.flags = UPF_BOOT_AUTOCONF;
1494 init_timer(&sport->timer);
1495 sport->timer.function = imx_timeout;
1496 sport->timer.data = (unsigned long)sport;
1497
1498 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1499 if (IS_ERR(pinctrl)) {
1500 ret = PTR_ERR(pinctrl);
1501 dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret);
1502 return ret;
1503 }
1504
1505 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1506 if (IS_ERR(sport->clk_ipg)) {
1507 ret = PTR_ERR(sport->clk_ipg);
1508 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1509 return ret;
1510 }
1511
1512 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1513 if (IS_ERR(sport->clk_per)) {
1514 ret = PTR_ERR(sport->clk_per);
1515 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1516 return ret;
1517 }
1518
1519 clk_prepare_enable(sport->clk_per);
1520 clk_prepare_enable(sport->clk_ipg);
1521
1522 sport->port.uartclk = clk_get_rate(sport->clk_per);
1523
1524 imx_ports[sport->port.line] = sport;
1525
1526 pdata = pdev->dev.platform_data;
1527 if (pdata && pdata->init) {
1528 ret = pdata->init(pdev);
1529 if (ret)
1530 goto clkput;
1531 }
1532
1533 ret = uart_add_one_port(&imx_reg, &sport->port);
1534 if (ret)
1535 goto deinit;
1536 platform_set_drvdata(pdev, sport);
1537
1538 return 0;
1539 deinit:
1540 if (pdata && pdata->exit)
1541 pdata->exit(pdev);
1542 clkput:
1543 clk_disable_unprepare(sport->clk_per);
1544 clk_disable_unprepare(sport->clk_ipg);
1545 return ret;
1546 }
1547
1548 static int serial_imx_remove(struct platform_device *pdev)
1549 {
1550 struct imxuart_platform_data *pdata;
1551 struct imx_port *sport = platform_get_drvdata(pdev);
1552
1553 pdata = pdev->dev.platform_data;
1554
1555 platform_set_drvdata(pdev, NULL);
1556
1557 uart_remove_one_port(&imx_reg, &sport->port);
1558
1559 clk_disable_unprepare(sport->clk_per);
1560 clk_disable_unprepare(sport->clk_ipg);
1561
1562 if (pdata && pdata->exit)
1563 pdata->exit(pdev);
1564
1565 return 0;
1566 }
1567
1568 static struct platform_driver serial_imx_driver = {
1569 .probe = serial_imx_probe,
1570 .remove = serial_imx_remove,
1571
1572 .suspend = serial_imx_suspend,
1573 .resume = serial_imx_resume,
1574 .id_table = imx_uart_devtype,
1575 .driver = {
1576 .name = "imx-uart",
1577 .owner = THIS_MODULE,
1578 .of_match_table = imx_uart_dt_ids,
1579 },
1580 };
1581
1582 static int __init imx_serial_init(void)
1583 {
1584 int ret;
1585
1586 pr_info("Serial: IMX driver\n");
1587
1588 ret = uart_register_driver(&imx_reg);
1589 if (ret)
1590 return ret;
1591
1592 ret = platform_driver_register(&serial_imx_driver);
1593 if (ret != 0)
1594 uart_unregister_driver(&imx_reg);
1595
1596 return ret;
1597 }
1598
1599 static void __exit imx_serial_exit(void)
1600 {
1601 platform_driver_unregister(&serial_imx_driver);
1602 uart_unregister_driver(&imx_reg);
1603 }
1604
1605 module_init(imx_serial_init);
1606 module_exit(imx_serial_exit);
1607
1608 MODULE_AUTHOR("Sascha Hauer");
1609 MODULE_DESCRIPTION("IMX generic serial port driver");
1610 MODULE_LICENSE("GPL");
1611 MODULE_ALIAS("platform:imx-uart");
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