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cnic: Add cnic_uio_dev struct
[linux-2.6/btrfs-unstable.git] / drivers / net / cnic.c
blobe8f2836b6301940b7ded8613786b43fc8e0cf0d9
1 /* cnic.c: Broadcom CNIC core network driver.
2 *
3 * Copyright (c) 2006-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
10 * Modified and maintained by: Michael Chan <mchan@broadcom.com>
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/module.h>
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/netdevice.h>
24 #include <linux/uio_driver.h>
25 #include <linux/in.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/delay.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
31 #define BCM_VLAN 1
32 #endif
33 #include <net/ip.h>
34 #include <net/tcp.h>
35 #include <net/route.h>
36 #include <net/ipv6.h>
37 #include <net/ip6_route.h>
38 #include <net/ip6_checksum.h>
39 #include <scsi/iscsi_if.h>
40
41 #include "cnic_if.h"
42 #include "bnx2.h"
43 #include "bnx2x/bnx2x_reg.h"
44 #include "bnx2x/bnx2x_fw_defs.h"
45 #include "bnx2x/bnx2x_hsi.h"
46 #include "../scsi/bnx2i/57xx_iscsi_constants.h"
47 #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
48 #include "cnic.h"
49 #include "cnic_defs.h"
50
51 #define DRV_MODULE_NAME "cnic"
52
53 static char version[] __devinitdata =
54 "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
55
56 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
57 "Chen (zongxi@broadcom.com");
58 MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
59 MODULE_LICENSE("GPL");
60 MODULE_VERSION(CNIC_MODULE_VERSION);
61
62 static LIST_HEAD(cnic_dev_list);
63 static DEFINE_RWLOCK(cnic_dev_lock);
64 static DEFINE_MUTEX(cnic_lock);
65
66 static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
67
68 static int cnic_service_bnx2(void *, void *);
69 static int cnic_service_bnx2x(void *, void *);
70 static int cnic_ctl(void *, struct cnic_ctl_info *);
71
72 static struct cnic_ops cnic_bnx2_ops = {
73 .cnic_owner = THIS_MODULE,
74 .cnic_handler = cnic_service_bnx2,
75 .cnic_ctl = cnic_ctl,
76 };
77
78 static struct cnic_ops cnic_bnx2x_ops = {
79 .cnic_owner = THIS_MODULE,
80 .cnic_handler = cnic_service_bnx2x,
81 .cnic_ctl = cnic_ctl,
82 };
83
84 static struct workqueue_struct *cnic_wq;
85
86 static void cnic_shutdown_rings(struct cnic_dev *);
87 static void cnic_init_rings(struct cnic_dev *);
88 static int cnic_cm_set_pg(struct cnic_sock *);
89
90 static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
91 {
92 struct cnic_uio_dev *udev = uinfo->priv;
93 struct cnic_dev *dev;
94
95 if (!capable(CAP_NET_ADMIN))
96 return -EPERM;
97
98 if (udev->uio_dev != -1)
99 return -EBUSY;
100
101 rtnl_lock();
102 dev = udev->dev;
103
104 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
105 rtnl_unlock();
106 return -ENODEV;
107 }
108
109 udev->uio_dev = iminor(inode);
110
111 cnic_init_rings(dev);
112 rtnl_unlock();
113
114 return 0;
115 }
116
117 static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
118 {
119 struct cnic_uio_dev *udev = uinfo->priv;
120 struct cnic_dev *dev = udev->dev;
121
122 cnic_shutdown_rings(dev);
123
124 udev->uio_dev = -1;
125 return 0;
126 }
127
128 static inline void cnic_hold(struct cnic_dev *dev)
129 {
130 atomic_inc(&dev->ref_count);
131 }
132
133 static inline void cnic_put(struct cnic_dev *dev)
134 {
135 atomic_dec(&dev->ref_count);
136 }
137
138 static inline void csk_hold(struct cnic_sock *csk)
139 {
140 atomic_inc(&csk->ref_count);
141 }
142
143 static inline void csk_put(struct cnic_sock *csk)
144 {
145 atomic_dec(&csk->ref_count);
146 }
147
148 static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
149 {
150 struct cnic_dev *cdev;
151
152 read_lock(&cnic_dev_lock);
153 list_for_each_entry(cdev, &cnic_dev_list, list) {
154 if (netdev == cdev->netdev) {
155 cnic_hold(cdev);
156 read_unlock(&cnic_dev_lock);
157 return cdev;
158 }
159 }
160 read_unlock(&cnic_dev_lock);
161 return NULL;
162 }
163
164 static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
165 {
166 atomic_inc(&ulp_ops->ref_count);
167 }
168
169 static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
170 {
171 atomic_dec(&ulp_ops->ref_count);
172 }
173
174 static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
175 {
176 struct cnic_local *cp = dev->cnic_priv;
177 struct cnic_eth_dev *ethdev = cp->ethdev;
178 struct drv_ctl_info info;
179 struct drv_ctl_io *io = &info.data.io;
180
181 info.cmd = DRV_CTL_CTX_WR_CMD;
182 io->cid_addr = cid_addr;
183 io->offset = off;
184 io->data = val;
185 ethdev->drv_ctl(dev->netdev, &info);
186 }
187
188 static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
189 {
190 struct cnic_local *cp = dev->cnic_priv;
191 struct cnic_eth_dev *ethdev = cp->ethdev;
192 struct drv_ctl_info info;
193 struct drv_ctl_io *io = &info.data.io;
194
195 info.cmd = DRV_CTL_CTXTBL_WR_CMD;
196 io->offset = off;
197 io->dma_addr = addr;
198 ethdev->drv_ctl(dev->netdev, &info);
199 }
200
201 static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
202 {
203 struct cnic_local *cp = dev->cnic_priv;
204 struct cnic_eth_dev *ethdev = cp->ethdev;
205 struct drv_ctl_info info;
206 struct drv_ctl_l2_ring *ring = &info.data.ring;
207
208 if (start)
209 info.cmd = DRV_CTL_START_L2_CMD;
210 else
211 info.cmd = DRV_CTL_STOP_L2_CMD;
212
213 ring->cid = cid;
214 ring->client_id = cl_id;
215 ethdev->drv_ctl(dev->netdev, &info);
216 }
217
218 static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
219 {
220 struct cnic_local *cp = dev->cnic_priv;
221 struct cnic_eth_dev *ethdev = cp->ethdev;
222 struct drv_ctl_info info;
223 struct drv_ctl_io *io = &info.data.io;
224
225 info.cmd = DRV_CTL_IO_WR_CMD;
226 io->offset = off;
227 io->data = val;
228 ethdev->drv_ctl(dev->netdev, &info);
229 }
230
231 static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
232 {
233 struct cnic_local *cp = dev->cnic_priv;
234 struct cnic_eth_dev *ethdev = cp->ethdev;
235 struct drv_ctl_info info;
236 struct drv_ctl_io *io = &info.data.io;
237
238 info.cmd = DRV_CTL_IO_RD_CMD;
239 io->offset = off;
240 ethdev->drv_ctl(dev->netdev, &info);
241 return io->data;
242 }
243
244 static int cnic_in_use(struct cnic_sock *csk)
245 {
246 return test_bit(SK_F_INUSE, &csk->flags);
247 }
248
249 static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
250 {
251 struct cnic_local *cp = dev->cnic_priv;
252 struct cnic_eth_dev *ethdev = cp->ethdev;
253 struct drv_ctl_info info;
254
255 info.cmd = cmd;
256 info.data.credit.credit_count = count;
257 ethdev->drv_ctl(dev->netdev, &info);
258 }
259
260 static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
261 {
262 u32 i;
263
264 for (i = 0; i < cp->max_cid_space; i++) {
265 if (cp->ctx_tbl[i].cid == cid) {
266 *l5_cid = i;
267 return 0;
268 }
269 }
270 return -EINVAL;
271 }
272
273 static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
274 struct cnic_sock *csk)
275 {
276 struct iscsi_path path_req;
277 char *buf = NULL;
278 u16 len = 0;
279 u32 msg_type = ISCSI_KEVENT_IF_DOWN;
280 struct cnic_ulp_ops *ulp_ops;
281 struct cnic_uio_dev *udev = cp->udev;
282
283 if (!udev || udev->uio_dev == -1)
284 return -ENODEV;
285
286 if (csk) {
287 len = sizeof(path_req);
288 buf = (char *) &path_req;
289 memset(&path_req, 0, len);
290
291 msg_type = ISCSI_KEVENT_PATH_REQ;
292 path_req.handle = (u64) csk->l5_cid;
293 if (test_bit(SK_F_IPV6, &csk->flags)) {
294 memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
295 sizeof(struct in6_addr));
296 path_req.ip_addr_len = 16;
297 } else {
298 memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
299 sizeof(struct in_addr));
300 path_req.ip_addr_len = 4;
301 }
302 path_req.vlan_id = csk->vlan_id;
303 path_req.pmtu = csk->mtu;
304 }
305
306 rcu_read_lock();
307 ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
308 if (ulp_ops)
309 ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
310 rcu_read_unlock();
311 return 0;
312 }
313
314 static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
315 char *buf, u16 len)
316 {
317 int rc = -EINVAL;
318
319 switch (msg_type) {
320 case ISCSI_UEVENT_PATH_UPDATE: {
321 struct cnic_local *cp;
322 u32 l5_cid;
323 struct cnic_sock *csk;
324 struct iscsi_path *path_resp;
325
326 if (len < sizeof(*path_resp))
327 break;
328
329 path_resp = (struct iscsi_path *) buf;
330 cp = dev->cnic_priv;
331 l5_cid = (u32) path_resp->handle;
332 if (l5_cid >= MAX_CM_SK_TBL_SZ)
333 break;
334
335 rcu_read_lock();
336 if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
337 rc = -ENODEV;
338 rcu_read_unlock();
339 break;
340 }
341 csk = &cp->csk_tbl[l5_cid];
342 csk_hold(csk);
343 if (cnic_in_use(csk)) {
344 memcpy(csk->ha, path_resp->mac_addr, 6);
345 if (test_bit(SK_F_IPV6, &csk->flags))
346 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
347 sizeof(struct in6_addr));
348 else
349 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
350 sizeof(struct in_addr));
351 if (is_valid_ether_addr(csk->ha))
352 cnic_cm_set_pg(csk);
353 }
354 csk_put(csk);
355 rcu_read_unlock();
356 rc = 0;
357 }
358 }
359
360 return rc;
361 }
362
363 static int cnic_offld_prep(struct cnic_sock *csk)
364 {
365 if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
366 return 0;
367
368 if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
369 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
370 return 0;
371 }
372
373 return 1;
374 }
375
376 static int cnic_close_prep(struct cnic_sock *csk)
377 {
378 clear_bit(SK_F_CONNECT_START, &csk->flags);
379 smp_mb__after_clear_bit();
380
381 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
382 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
383 msleep(1);
384
385 return 1;
386 }
387 return 0;
388 }
389
390 static int cnic_abort_prep(struct cnic_sock *csk)
391 {
392 clear_bit(SK_F_CONNECT_START, &csk->flags);
393 smp_mb__after_clear_bit();
394
395 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
396 msleep(1);
397
398 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
399 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
400 return 1;
401 }
402
403 return 0;
404 }
405
406 static void cnic_uio_stop(void)
407 {
408 struct cnic_dev *dev;
409
410 read_lock(&cnic_dev_lock);
411 list_for_each_entry(dev, &cnic_dev_list, list) {
412 struct cnic_local *cp = dev->cnic_priv;
413
414 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
415 }
416 read_unlock(&cnic_dev_lock);
417 }
418
419 int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
420 {
421 struct cnic_dev *dev;
422
423 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
424 pr_err("%s: Bad type %d\n", __func__, ulp_type);
425 return -EINVAL;
426 }
427 mutex_lock(&cnic_lock);
428 if (cnic_ulp_tbl[ulp_type]) {
429 pr_err("%s: Type %d has already been registered\n",
430 __func__, ulp_type);
431 mutex_unlock(&cnic_lock);
432 return -EBUSY;
433 }
434
435 read_lock(&cnic_dev_lock);
436 list_for_each_entry(dev, &cnic_dev_list, list) {
437 struct cnic_local *cp = dev->cnic_priv;
438
439 clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
440 }
441 read_unlock(&cnic_dev_lock);
442
443 atomic_set(&ulp_ops->ref_count, 0);
444 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
445 mutex_unlock(&cnic_lock);
446
447 /* Prevent race conditions with netdev_event */
448 rtnl_lock();
449 read_lock(&cnic_dev_lock);
450 list_for_each_entry(dev, &cnic_dev_list, list) {
451 struct cnic_local *cp = dev->cnic_priv;
452
453 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
454 ulp_ops->cnic_init(dev);
455 }
456 read_unlock(&cnic_dev_lock);
457 rtnl_unlock();
458
459 return 0;
460 }
461
462 int cnic_unregister_driver(int ulp_type)
463 {
464 struct cnic_dev *dev;
465 struct cnic_ulp_ops *ulp_ops;
466 int i = 0;
467
468 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
469 pr_err("%s: Bad type %d\n", __func__, ulp_type);
470 return -EINVAL;
471 }
472 mutex_lock(&cnic_lock);
473 ulp_ops = cnic_ulp_tbl[ulp_type];
474 if (!ulp_ops) {
475 pr_err("%s: Type %d has not been registered\n",
476 __func__, ulp_type);
477 goto out_unlock;
478 }
479 read_lock(&cnic_dev_lock);
480 list_for_each_entry(dev, &cnic_dev_list, list) {
481 struct cnic_local *cp = dev->cnic_priv;
482
483 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
484 pr_err("%s: Type %d still has devices registered\n",
485 __func__, ulp_type);
486 read_unlock(&cnic_dev_lock);
487 goto out_unlock;
488 }
489 }
490 read_unlock(&cnic_dev_lock);
491
492 if (ulp_type == CNIC_ULP_ISCSI)
493 cnic_uio_stop();
494
495 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
496
497 mutex_unlock(&cnic_lock);
498 synchronize_rcu();
499 while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
500 msleep(100);
501 i++;
502 }
503
504 if (atomic_read(&ulp_ops->ref_count) != 0)
505 netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
506 return 0;
507
508 out_unlock:
509 mutex_unlock(&cnic_lock);
510 return -EINVAL;
511 }
512
513 static int cnic_start_hw(struct cnic_dev *);
514 static void cnic_stop_hw(struct cnic_dev *);
515
516 static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
517 void *ulp_ctx)
518 {
519 struct cnic_local *cp = dev->cnic_priv;
520 struct cnic_ulp_ops *ulp_ops;
521
522 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
523 pr_err("%s: Bad type %d\n", __func__, ulp_type);
524 return -EINVAL;
525 }
526 mutex_lock(&cnic_lock);
527 if (cnic_ulp_tbl[ulp_type] == NULL) {
528 pr_err("%s: Driver with type %d has not been registered\n",
529 __func__, ulp_type);
530 mutex_unlock(&cnic_lock);
531 return -EAGAIN;
532 }
533 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
534 pr_err("%s: Type %d has already been registered to this device\n",
535 __func__, ulp_type);
536 mutex_unlock(&cnic_lock);
537 return -EBUSY;
538 }
539
540 clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
541 cp->ulp_handle[ulp_type] = ulp_ctx;
542 ulp_ops = cnic_ulp_tbl[ulp_type];
543 rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
544 cnic_hold(dev);
545
546 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
547 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
548 ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
549
550 mutex_unlock(&cnic_lock);
551
552 return 0;
553
554 }
555 EXPORT_SYMBOL(cnic_register_driver);
556
557 static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
558 {
559 struct cnic_local *cp = dev->cnic_priv;
560 int i = 0;
561
562 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
563 pr_err("%s: Bad type %d\n", __func__, ulp_type);
564 return -EINVAL;
565 }
566 mutex_lock(&cnic_lock);
567 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
568 rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
569 cnic_put(dev);
570 } else {
571 pr_err("%s: device not registered to this ulp type %d\n",
572 __func__, ulp_type);
573 mutex_unlock(&cnic_lock);
574 return -EINVAL;
575 }
576 mutex_unlock(&cnic_lock);
577
578 synchronize_rcu();
579
580 while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
581 i < 20) {
582 msleep(100);
583 i++;
584 }
585 if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
586 netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
587
588 return 0;
589 }
590 EXPORT_SYMBOL(cnic_unregister_driver);
591
592 static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
593 {
594 id_tbl->start = start_id;
595 id_tbl->max = size;
596 id_tbl->next = 0;
597 spin_lock_init(&id_tbl->lock);
598 id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
599 if (!id_tbl->table)
600 return -ENOMEM;
601
602 return 0;
603 }
604
605 static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
606 {
607 kfree(id_tbl->table);
608 id_tbl->table = NULL;
609 }
610
611 static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
612 {
613 int ret = -1;
614
615 id -= id_tbl->start;
616 if (id >= id_tbl->max)
617 return ret;
618
619 spin_lock(&id_tbl->lock);
620 if (!test_bit(id, id_tbl->table)) {
621 set_bit(id, id_tbl->table);
622 ret = 0;
623 }
624 spin_unlock(&id_tbl->lock);
625 return ret;
626 }
627
628 /* Returns -1 if not successful */
629 static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
630 {
631 u32 id;
632
633 spin_lock(&id_tbl->lock);
634 id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
635 if (id >= id_tbl->max) {
636 id = -1;
637 if (id_tbl->next != 0) {
638 id = find_first_zero_bit(id_tbl->table, id_tbl->next);
639 if (id >= id_tbl->next)
640 id = -1;
641 }
642 }
643
644 if (id < id_tbl->max) {
645 set_bit(id, id_tbl->table);
646 id_tbl->next = (id + 1) & (id_tbl->max - 1);
647 id += id_tbl->start;
648 }
649
650 spin_unlock(&id_tbl->lock);
651
652 return id;
653 }
654
655 static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
656 {
657 if (id == -1)
658 return;
659
660 id -= id_tbl->start;
661 if (id >= id_tbl->max)
662 return;
663
664 clear_bit(id, id_tbl->table);
665 }
666
667 static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
668 {
669 int i;
670
671 if (!dma->pg_arr)
672 return;
673
674 for (i = 0; i < dma->num_pages; i++) {
675 if (dma->pg_arr[i]) {
676 dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
677 dma->pg_arr[i], dma->pg_map_arr[i]);
678 dma->pg_arr[i] = NULL;
679 }
680 }
681 if (dma->pgtbl) {
682 dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
683 dma->pgtbl, dma->pgtbl_map);
684 dma->pgtbl = NULL;
685 }
686 kfree(dma->pg_arr);
687 dma->pg_arr = NULL;
688 dma->num_pages = 0;
689 }
690
691 static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
692 {
693 int i;
694 u32 *page_table = dma->pgtbl;
695
696 for (i = 0; i < dma->num_pages; i++) {
697 /* Each entry needs to be in big endian format. */
698 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
699 page_table++;
700 *page_table = (u32) dma->pg_map_arr[i];
701 page_table++;
702 }
703 }
704
705 static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
706 {
707 int i;
708 u32 *page_table = dma->pgtbl;
709
710 for (i = 0; i < dma->num_pages; i++) {
711 /* Each entry needs to be in little endian format. */
712 *page_table = dma->pg_map_arr[i] & 0xffffffff;
713 page_table++;
714 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
715 page_table++;
716 }
717 }
718
719 static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
720 int pages, int use_pg_tbl)
721 {
722 int i, size;
723 struct cnic_local *cp = dev->cnic_priv;
724
725 size = pages * (sizeof(void *) + sizeof(dma_addr_t));
726 dma->pg_arr = kzalloc(size, GFP_ATOMIC);
727 if (dma->pg_arr == NULL)
728 return -ENOMEM;
729
730 dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
731 dma->num_pages = pages;
732
733 for (i = 0; i < pages; i++) {
734 dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
735 BCM_PAGE_SIZE,
736 &dma->pg_map_arr[i],
737 GFP_ATOMIC);
738 if (dma->pg_arr[i] == NULL)
739 goto error;
740 }
741 if (!use_pg_tbl)
742 return 0;
743
744 dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
745 ~(BCM_PAGE_SIZE - 1);
746 dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
747 &dma->pgtbl_map, GFP_ATOMIC);
748 if (dma->pgtbl == NULL)
749 goto error;
750
751 cp->setup_pgtbl(dev, dma);
752
753 return 0;
754
755 error:
756 cnic_free_dma(dev, dma);
757 return -ENOMEM;
758 }
759
760 static void cnic_free_context(struct cnic_dev *dev)
761 {
762 struct cnic_local *cp = dev->cnic_priv;
763 int i;
764
765 for (i = 0; i < cp->ctx_blks; i++) {
766 if (cp->ctx_arr[i].ctx) {
767 dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
768 cp->ctx_arr[i].ctx,
769 cp->ctx_arr[i].mapping);
770 cp->ctx_arr[i].ctx = NULL;
771 }
772 }
773 }
774
775 static void __cnic_free_uio(struct cnic_uio_dev *udev)
776 {
777 uio_unregister_device(&udev->cnic_uinfo);
778
779 if (udev->l2_buf) {
780 dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
781 udev->l2_buf, udev->l2_buf_map);
782 udev->l2_buf = NULL;
783 }
784
785 if (udev->l2_ring) {
786 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
787 udev->l2_ring, udev->l2_ring_map);
788 udev->l2_ring = NULL;
789 }
790 }
791
792 static void cnic_free_uio(struct cnic_uio_dev *udev)
793 {
794 if (!udev)
795 return;
796
797 __cnic_free_uio(udev);
798 }
799
800 static void cnic_free_resc(struct cnic_dev *dev)
801 {
802 struct cnic_local *cp = dev->cnic_priv;
803 struct cnic_uio_dev *udev = cp->udev;
804 int i = 0;
805
806 if (udev) {
807 while (udev->uio_dev != -1 && i < 15) {
808 msleep(100);
809 i++;
810 }
811 cnic_free_uio(udev);
812 cp->udev = NULL;
813 }
814
815 cnic_free_context(dev);
816 kfree(cp->ctx_arr);
817 cp->ctx_arr = NULL;
818 cp->ctx_blks = 0;
819
820 cnic_free_dma(dev, &cp->gbl_buf_info);
821 cnic_free_dma(dev, &cp->conn_buf_info);
822 cnic_free_dma(dev, &cp->kwq_info);
823 cnic_free_dma(dev, &cp->kwq_16_data_info);
824 cnic_free_dma(dev, &cp->kcq1.dma);
825 kfree(cp->iscsi_tbl);
826 cp->iscsi_tbl = NULL;
827 kfree(cp->ctx_tbl);
828 cp->ctx_tbl = NULL;
829
830 cnic_free_id_tbl(&cp->cid_tbl);
831 }
832
833 static int cnic_alloc_context(struct cnic_dev *dev)
834 {
835 struct cnic_local *cp = dev->cnic_priv;
836
837 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
838 int i, k, arr_size;
839
840 cp->ctx_blk_size = BCM_PAGE_SIZE;
841 cp->cids_per_blk = BCM_PAGE_SIZE / 128;
842 arr_size = BNX2_MAX_CID / cp->cids_per_blk *
843 sizeof(struct cnic_ctx);
844 cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
845 if (cp->ctx_arr == NULL)
846 return -ENOMEM;
847
848 k = 0;
849 for (i = 0; i < 2; i++) {
850 u32 j, reg, off, lo, hi;
851
852 if (i == 0)
853 off = BNX2_PG_CTX_MAP;
854 else
855 off = BNX2_ISCSI_CTX_MAP;
856
857 reg = cnic_reg_rd_ind(dev, off);
858 lo = reg >> 16;
859 hi = reg & 0xffff;
860 for (j = lo; j < hi; j += cp->cids_per_blk, k++)
861 cp->ctx_arr[k].cid = j;
862 }
863
864 cp->ctx_blks = k;
865 if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
866 cp->ctx_blks = 0;
867 return -ENOMEM;
868 }
869
870 for (i = 0; i < cp->ctx_blks; i++) {
871 cp->ctx_arr[i].ctx =
872 dma_alloc_coherent(&dev->pcidev->dev,
873 BCM_PAGE_SIZE,
874 &cp->ctx_arr[i].mapping,
875 GFP_KERNEL);
876 if (cp->ctx_arr[i].ctx == NULL)
877 return -ENOMEM;
878 }
879 }
880 return 0;
881 }
882
883 static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
884 {
885 int err, i, is_bnx2 = 0;
886 struct kcqe **kcq;
887
888 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
889 is_bnx2 = 1;
890
891 err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
892 if (err)
893 return err;
894
895 kcq = (struct kcqe **) info->dma.pg_arr;
896 info->kcq = kcq;
897
898 if (is_bnx2)
899 return 0;
900
901 for (i = 0; i < KCQ_PAGE_CNT; i++) {
902 struct bnx2x_bd_chain_next *next =
903 (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
904 int j = i + 1;
905
906 if (j >= KCQ_PAGE_CNT)
907 j = 0;
908 next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
909 next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
910 }
911 return 0;
912 }
913
914 static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
915 {
916 struct cnic_local *cp = dev->cnic_priv;
917 struct cnic_uio_dev *udev;
918
919 udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
920 if (!udev)
921 return -ENOMEM;
922
923 udev->uio_dev = -1;
924
925 udev->dev = dev;
926 udev->pdev = dev->pcidev;
927 udev->l2_ring_size = pages * BCM_PAGE_SIZE;
928 udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
929 &udev->l2_ring_map,
930 GFP_KERNEL | __GFP_COMP);
931 if (!udev->l2_ring)
932 return -ENOMEM;
933
934 udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
935 udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
936 udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
937 &udev->l2_buf_map,
938 GFP_KERNEL | __GFP_COMP);
939 if (!udev->l2_buf)
940 return -ENOMEM;
941
942 cp->udev = udev;
943
944 return 0;
945 }
946
947 static int cnic_init_uio(struct cnic_dev *dev)
948 {
949 struct cnic_local *cp = dev->cnic_priv;
950 struct cnic_uio_dev *udev = cp->udev;
951 struct uio_info *uinfo;
952 int ret = 0;
953
954 if (!udev)
955 return -ENOMEM;
956
957 udev->uio_dev = -1;
958
959 uinfo = &udev->cnic_uinfo;
960
961 uinfo->mem[0].addr = dev->netdev->base_addr;
962 uinfo->mem[0].internal_addr = dev->regview;
963 uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
964 uinfo->mem[0].memtype = UIO_MEM_PHYS;
965
966 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
967 uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
968 PAGE_MASK;
969 if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
970 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
971 else
972 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
973
974 uinfo->name = "bnx2_cnic";
975 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
976 uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
977 PAGE_MASK;
978 uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
979
980 uinfo->name = "bnx2x_cnic";
981 }
982
983 uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
984
985 uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
986 uinfo->mem[2].size = udev->l2_ring_size;
987 uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
988
989 uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
990 uinfo->mem[3].size = udev->l2_buf_size;
991 uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
992
993 uinfo->version = CNIC_MODULE_VERSION;
994 uinfo->irq = UIO_IRQ_CUSTOM;
995
996 uinfo->open = cnic_uio_open;
997 uinfo->release = cnic_uio_close;
998
999 uinfo->priv = udev;
1000
1001 ret = uio_register_device(&udev->pdev->dev, uinfo);
1002
1003 return ret;
1004 }
1005
1006 static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
1007 {
1008 struct cnic_local *cp = dev->cnic_priv;
1009 int ret;
1010
1011 ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
1012 if (ret)
1013 goto error;
1014 cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
1015
1016 ret = cnic_alloc_kcq(dev, &cp->kcq1);
1017 if (ret)
1018 goto error;
1019
1020 ret = cnic_alloc_context(dev);
1021 if (ret)
1022 goto error;
1023
1024 ret = cnic_alloc_uio_rings(dev, 2);
1025 if (ret)
1026 goto error;
1027
1028 ret = cnic_init_uio(dev);
1029 if (ret)
1030 goto error;
1031
1032 return 0;
1033
1034 error:
1035 cnic_free_resc(dev);
1036 return ret;
1037 }
1038
1039 static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
1040 {
1041 struct cnic_local *cp = dev->cnic_priv;
1042 int ctx_blk_size = cp->ethdev->ctx_blk_size;
1043 int total_mem, blks, i;
1044
1045 total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
1046 blks = total_mem / ctx_blk_size;
1047 if (total_mem % ctx_blk_size)
1048 blks++;
1049
1050 if (blks > cp->ethdev->ctx_tbl_len)
1051 return -ENOMEM;
1052
1053 cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
1054 if (cp->ctx_arr == NULL)
1055 return -ENOMEM;
1056
1057 cp->ctx_blks = blks;
1058 cp->ctx_blk_size = ctx_blk_size;
1059 if (BNX2X_CHIP_IS_E1H(cp->chip_id))
1060 cp->ctx_align = 0;
1061 else
1062 cp->ctx_align = ctx_blk_size;
1063
1064 cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1065
1066 for (i = 0; i < blks; i++) {
1067 cp->ctx_arr[i].ctx =
1068 dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1069 &cp->ctx_arr[i].mapping,
1070 GFP_KERNEL);
1071 if (cp->ctx_arr[i].ctx == NULL)
1072 return -ENOMEM;
1073
1074 if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1075 if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1076 cnic_free_context(dev);
1077 cp->ctx_blk_size += cp->ctx_align;
1078 i = -1;
1079 continue;
1080 }
1081 }
1082 }
1083 return 0;
1084 }
1085
1086 static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1087 {
1088 struct cnic_local *cp = dev->cnic_priv;
1089 struct cnic_eth_dev *ethdev = cp->ethdev;
1090 u32 start_cid = ethdev->starting_cid;
1091 int i, j, n, ret, pages;
1092 struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1093
1094 cp->iro_arr = ethdev->iro_arr;
1095
1096 cp->max_cid_space = MAX_ISCSI_TBL_SZ;
1097 cp->iscsi_start_cid = start_cid;
1098 if (start_cid < BNX2X_ISCSI_START_CID) {
1099 u32 delta = BNX2X_ISCSI_START_CID - start_cid;
1100
1101 cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
1102 cp->max_cid_space += delta;
1103 }
1104
1105 cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
1106 GFP_KERNEL);
1107 if (!cp->iscsi_tbl)
1108 goto error;
1109
1110 cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
1111 cp->max_cid_space, GFP_KERNEL);
1112 if (!cp->ctx_tbl)
1113 goto error;
1114
1115 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1116 cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1117 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1118 }
1119
1120 pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
1121 PAGE_SIZE;
1122
1123 ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1124 if (ret)
1125 return -ENOMEM;
1126
1127 n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1128 for (i = 0, j = 0; i < cp->max_cid_space; i++) {
1129 long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1130
1131 cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1132 cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1133 off;
1134
1135 if ((i % n) == (n - 1))
1136 j++;
1137 }
1138
1139 ret = cnic_alloc_kcq(dev, &cp->kcq1);
1140 if (ret)
1141 goto error;
1142
1143 pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
1144 BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
1145 ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
1146 if (ret)
1147 goto error;
1148
1149 pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
1150 ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1151 if (ret)
1152 goto error;
1153
1154 ret = cnic_alloc_bnx2x_context(dev);
1155 if (ret)
1156 goto error;
1157
1158 cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1159
1160 cp->l2_rx_ring_size = 15;
1161
1162 ret = cnic_alloc_uio_rings(dev, 4);
1163 if (ret)
1164 goto error;
1165
1166 ret = cnic_init_uio(dev);
1167 if (ret)
1168 goto error;
1169
1170 return 0;
1171
1172 error:
1173 cnic_free_resc(dev);
1174 return -ENOMEM;
1175 }
1176
1177 static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1178 {
1179 return cp->max_kwq_idx -
1180 ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1181 }
1182
1183 static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1184 u32 num_wqes)
1185 {
1186 struct cnic_local *cp = dev->cnic_priv;
1187 struct kwqe *prod_qe;
1188 u16 prod, sw_prod, i;
1189
1190 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1191 return -EAGAIN; /* bnx2 is down */
1192
1193 spin_lock_bh(&cp->cnic_ulp_lock);
1194 if (num_wqes > cnic_kwq_avail(cp) &&
1195 !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
1196 spin_unlock_bh(&cp->cnic_ulp_lock);
1197 return -EAGAIN;
1198 }
1199
1200 clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
1201
1202 prod = cp->kwq_prod_idx;
1203 sw_prod = prod & MAX_KWQ_IDX;
1204 for (i = 0; i < num_wqes; i++) {
1205 prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1206 memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1207 prod++;
1208 sw_prod = prod & MAX_KWQ_IDX;
1209 }
1210 cp->kwq_prod_idx = prod;
1211
1212 CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1213
1214 spin_unlock_bh(&cp->cnic_ulp_lock);
1215 return 0;
1216 }
1217
1218 static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1219 union l5cm_specific_data *l5_data)
1220 {
1221 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1222 dma_addr_t map;
1223
1224 map = ctx->kwqe_data_mapping;
1225 l5_data->phy_address.lo = (u64) map & 0xffffffff;
1226 l5_data->phy_address.hi = (u64) map >> 32;
1227 return ctx->kwqe_data;
1228 }
1229
1230 static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1231 u32 type, union l5cm_specific_data *l5_data)
1232 {
1233 struct cnic_local *cp = dev->cnic_priv;
1234 struct l5cm_spe kwqe;
1235 struct kwqe_16 *kwq[1];
1236 int ret;
1237
1238 kwqe.hdr.conn_and_cmd_data =
1239 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
1240 BNX2X_HW_CID(cp, cid)));
1241 kwqe.hdr.type = cpu_to_le16(type);
1242 kwqe.hdr.reserved1 = 0;
1243 kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1244 kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1245
1246 kwq[0] = (struct kwqe_16 *) &kwqe;
1247
1248 spin_lock_bh(&cp->cnic_ulp_lock);
1249 ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1250 spin_unlock_bh(&cp->cnic_ulp_lock);
1251
1252 if (ret == 1)
1253 return 0;
1254
1255 return -EBUSY;
1256 }
1257
1258 static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1259 struct kcqe *cqes[], u32 num_cqes)
1260 {
1261 struct cnic_local *cp = dev->cnic_priv;
1262 struct cnic_ulp_ops *ulp_ops;
1263
1264 rcu_read_lock();
1265 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1266 if (likely(ulp_ops)) {
1267 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1268 cqes, num_cqes);
1269 }
1270 rcu_read_unlock();
1271 }
1272
1273 static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1274 {
1275 struct cnic_local *cp = dev->cnic_priv;
1276 struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1277 int hq_bds, pages;
1278 u32 pfid = cp->pfid;
1279
1280 cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1281 cp->num_ccells = req1->num_ccells_per_conn;
1282 cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1283 cp->num_iscsi_tasks;
1284 cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1285 BNX2X_ISCSI_R2TQE_SIZE;
1286 cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1287 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1288 hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1289 cp->num_cqs = req1->num_cqs;
1290
1291 if (!dev->max_iscsi_conn)
1292 return 0;
1293
1294 /* init Tstorm RAM */
1295 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1296 req1->rq_num_wqes);
1297 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1298 PAGE_SIZE);
1299 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1300 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1301 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1302 TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1303 req1->num_tasks_per_conn);
1304
1305 /* init Ustorm RAM */
1306 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1307 USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
1308 req1->rq_buffer_size);
1309 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1310 PAGE_SIZE);
1311 CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1312 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1313 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1314 USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1315 req1->num_tasks_per_conn);
1316 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1317 req1->rq_num_wqes);
1318 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1319 req1->cq_num_wqes);
1320 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1321 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1322
1323 /* init Xstorm RAM */
1324 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1325 PAGE_SIZE);
1326 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1327 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1328 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1329 XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1330 req1->num_tasks_per_conn);
1331 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1332 hq_bds);
1333 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
1334 req1->num_tasks_per_conn);
1335 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1336 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1337
1338 /* init Cstorm RAM */
1339 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1340 PAGE_SIZE);
1341 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1342 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1343 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1344 CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1345 req1->num_tasks_per_conn);
1346 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1347 req1->cq_num_wqes);
1348 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1349 hq_bds);
1350
1351 return 0;
1352 }
1353
1354 static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1355 {
1356 struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1357 struct cnic_local *cp = dev->cnic_priv;
1358 u32 pfid = cp->pfid;
1359 struct iscsi_kcqe kcqe;
1360 struct kcqe *cqes[1];
1361
1362 memset(&kcqe, 0, sizeof(kcqe));
1363 if (!dev->max_iscsi_conn) {
1364 kcqe.completion_status =
1365 ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1366 goto done;
1367 }
1368
1369 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1370 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1371 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1372 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1373 req2->error_bit_map[1]);
1374
1375 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1376 USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1377 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1378 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1379 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1380 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1381 req2->error_bit_map[1]);
1382
1383 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1384 CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1385
1386 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1387
1388 done:
1389 kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1390 cqes[0] = (struct kcqe *) &kcqe;
1391 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1392
1393 return 0;
1394 }
1395
1396 static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1397 {
1398 struct cnic_local *cp = dev->cnic_priv;
1399 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1400
1401 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1402 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1403
1404 cnic_free_dma(dev, &iscsi->hq_info);
1405 cnic_free_dma(dev, &iscsi->r2tq_info);
1406 cnic_free_dma(dev, &iscsi->task_array_info);
1407 }
1408 cnic_free_id(&cp->cid_tbl, ctx->cid);
1409 ctx->cid = 0;
1410 }
1411
1412 static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1413 {
1414 u32 cid;
1415 int ret, pages;
1416 struct cnic_local *cp = dev->cnic_priv;
1417 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1418 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1419
1420 cid = cnic_alloc_new_id(&cp->cid_tbl);
1421 if (cid == -1) {
1422 ret = -ENOMEM;
1423 goto error;
1424 }
1425
1426 ctx->cid = cid;
1427 pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
1428
1429 ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1430 if (ret)
1431 goto error;
1432
1433 pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
1434 ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1435 if (ret)
1436 goto error;
1437
1438 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1439 ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1440 if (ret)
1441 goto error;
1442
1443 return 0;
1444
1445 error:
1446 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1447 return ret;
1448 }
1449
1450 static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1451 struct regpair *ctx_addr)
1452 {
1453 struct cnic_local *cp = dev->cnic_priv;
1454 struct cnic_eth_dev *ethdev = cp->ethdev;
1455 int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1456 int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1457 unsigned long align_off = 0;
1458 dma_addr_t ctx_map;
1459 void *ctx;
1460
1461 if (cp->ctx_align) {
1462 unsigned long mask = cp->ctx_align - 1;
1463
1464 if (cp->ctx_arr[blk].mapping & mask)
1465 align_off = cp->ctx_align -
1466 (cp->ctx_arr[blk].mapping & mask);
1467 }
1468 ctx_map = cp->ctx_arr[blk].mapping + align_off +
1469 (off * BNX2X_CONTEXT_MEM_SIZE);
1470 ctx = cp->ctx_arr[blk].ctx + align_off +
1471 (off * BNX2X_CONTEXT_MEM_SIZE);
1472 if (init)
1473 memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1474
1475 ctx_addr->lo = ctx_map & 0xffffffff;
1476 ctx_addr->hi = (u64) ctx_map >> 32;
1477 return ctx;
1478 }
1479
1480 static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1481 u32 num)
1482 {
1483 struct cnic_local *cp = dev->cnic_priv;
1484 struct iscsi_kwqe_conn_offload1 *req1 =
1485 (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1486 struct iscsi_kwqe_conn_offload2 *req2 =
1487 (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1488 struct iscsi_kwqe_conn_offload3 *req3;
1489 struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1490 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1491 u32 cid = ctx->cid;
1492 u32 hw_cid = BNX2X_HW_CID(cp, cid);
1493 struct iscsi_context *ictx;
1494 struct regpair context_addr;
1495 int i, j, n = 2, n_max;
1496
1497 ctx->ctx_flags = 0;
1498 if (!req2->num_additional_wqes)
1499 return -EINVAL;
1500
1501 n_max = req2->num_additional_wqes + 2;
1502
1503 ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1504 if (ictx == NULL)
1505 return -ENOMEM;
1506
1507 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1508
1509 ictx->xstorm_ag_context.hq_prod = 1;
1510
1511 ictx->xstorm_st_context.iscsi.first_burst_length =
1512 ISCSI_DEF_FIRST_BURST_LEN;
1513 ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1514 ISCSI_DEF_MAX_RECV_SEG_LEN;
1515 ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1516 req1->sq_page_table_addr_lo;
1517 ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1518 req1->sq_page_table_addr_hi;
1519 ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1520 ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1521 ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1522 iscsi->hq_info.pgtbl_map & 0xffffffff;
1523 ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1524 (u64) iscsi->hq_info.pgtbl_map >> 32;
1525 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1526 iscsi->hq_info.pgtbl[0];
1527 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1528 iscsi->hq_info.pgtbl[1];
1529 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1530 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1531 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1532 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1533 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1534 iscsi->r2tq_info.pgtbl[0];
1535 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1536 iscsi->r2tq_info.pgtbl[1];
1537 ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1538 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1539 ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1540 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1541 ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1542 BNX2X_ISCSI_PBL_NOT_CACHED;
1543 ictx->xstorm_st_context.iscsi.flags.flags |=
1544 XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1545 ictx->xstorm_st_context.iscsi.flags.flags |=
1546 XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1547
1548 ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1549 /* TSTORM requires the base address of RQ DB & not PTE */
1550 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1551 req2->rq_page_table_addr_lo & PAGE_MASK;
1552 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1553 req2->rq_page_table_addr_hi;
1554 ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1555 ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1556 ictx->tstorm_st_context.tcp.flags2 |=
1557 TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
1558 ictx->tstorm_st_context.tcp.ooo_support_mode =
1559 TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
1560
1561 ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
1562
1563 ictx->ustorm_st_context.ring.rq.pbl_base.lo =
1564 req2->rq_page_table_addr_lo;
1565 ictx->ustorm_st_context.ring.rq.pbl_base.hi =
1566 req2->rq_page_table_addr_hi;
1567 ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1568 ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1569 ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1570 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1571 ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1572 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1573 ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1574 iscsi->r2tq_info.pgtbl[0];
1575 ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1576 iscsi->r2tq_info.pgtbl[1];
1577 ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1578 req1->cq_page_table_addr_lo;
1579 ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1580 req1->cq_page_table_addr_hi;
1581 ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1582 ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1583 ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1584 ictx->ustorm_st_context.task_pbe_cache_index =
1585 BNX2X_ISCSI_PBL_NOT_CACHED;
1586 ictx->ustorm_st_context.task_pdu_cache_index =
1587 BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1588
1589 for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1590 if (j == 3) {
1591 if (n >= n_max)
1592 break;
1593 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1594 j = 0;
1595 }
1596 ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1597 ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1598 req3->qp_first_pte[j].hi;
1599 ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1600 req3->qp_first_pte[j].lo;
1601 }
1602
1603 ictx->ustorm_st_context.task_pbl_base.lo =
1604 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1605 ictx->ustorm_st_context.task_pbl_base.hi =
1606 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1607 ictx->ustorm_st_context.tce_phy_addr.lo =
1608 iscsi->task_array_info.pgtbl[0];
1609 ictx->ustorm_st_context.tce_phy_addr.hi =
1610 iscsi->task_array_info.pgtbl[1];
1611 ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1612 ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1613 ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1614 ictx->ustorm_st_context.negotiated_rx_and_flags |=
1615 ISCSI_DEF_MAX_BURST_LEN;
1616 ictx->ustorm_st_context.negotiated_rx |=
1617 ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1618 USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1619
1620 ictx->cstorm_st_context.hq_pbl_base.lo =
1621 iscsi->hq_info.pgtbl_map & 0xffffffff;
1622 ictx->cstorm_st_context.hq_pbl_base.hi =
1623 (u64) iscsi->hq_info.pgtbl_map >> 32;
1624 ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1625 ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1626 ictx->cstorm_st_context.task_pbl_base.lo =
1627 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1628 ictx->cstorm_st_context.task_pbl_base.hi =
1629 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1630 /* CSTORM and USTORM initialization is different, CSTORM requires
1631 * CQ DB base & not PTE addr */
1632 ictx->cstorm_st_context.cq_db_base.lo =
1633 req1->cq_page_table_addr_lo & PAGE_MASK;
1634 ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1635 ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1636 ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1637 for (i = 0; i < cp->num_cqs; i++) {
1638 ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1639 ISCSI_INITIAL_SN;
1640 ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1641 ISCSI_INITIAL_SN;
1642 }
1643
1644 ictx->xstorm_ag_context.cdu_reserved =
1645 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1646 ISCSI_CONNECTION_TYPE);
1647 ictx->ustorm_ag_context.cdu_usage =
1648 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1649 ISCSI_CONNECTION_TYPE);
1650 return 0;
1651
1652 }
1653
1654 static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1655 u32 num, int *work)
1656 {
1657 struct iscsi_kwqe_conn_offload1 *req1;
1658 struct iscsi_kwqe_conn_offload2 *req2;
1659 struct cnic_local *cp = dev->cnic_priv;
1660 struct cnic_context *ctx;
1661 struct iscsi_kcqe kcqe;
1662 struct kcqe *cqes[1];
1663 u32 l5_cid;
1664 int ret = 0;
1665
1666 if (num < 2) {
1667 *work = num;
1668 return -EINVAL;
1669 }
1670
1671 req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1672 req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1673 if ((num - 2) < req2->num_additional_wqes) {
1674 *work = num;
1675 return -EINVAL;
1676 }
1677 *work = 2 + req2->num_additional_wqes;;
1678
1679 l5_cid = req1->iscsi_conn_id;
1680 if (l5_cid >= MAX_ISCSI_TBL_SZ)
1681 return -EINVAL;
1682
1683 memset(&kcqe, 0, sizeof(kcqe));
1684 kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1685 kcqe.iscsi_conn_id = l5_cid;
1686 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1687
1688 ctx = &cp->ctx_tbl[l5_cid];
1689 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
1690 kcqe.completion_status =
1691 ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
1692 goto done;
1693 }
1694
1695 if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1696 atomic_dec(&cp->iscsi_conn);
1697 goto done;
1698 }
1699 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1700 if (ret) {
1701 atomic_dec(&cp->iscsi_conn);
1702 ret = 0;
1703 goto done;
1704 }
1705 ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1706 if (ret < 0) {
1707 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1708 atomic_dec(&cp->iscsi_conn);
1709 goto done;
1710 }
1711
1712 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1713 kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
1714
1715 done:
1716 cqes[0] = (struct kcqe *) &kcqe;
1717 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1718 return ret;
1719 }
1720
1721
1722 static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1723 {
1724 struct cnic_local *cp = dev->cnic_priv;
1725 struct iscsi_kwqe_conn_update *req =
1726 (struct iscsi_kwqe_conn_update *) kwqe;
1727 void *data;
1728 union l5cm_specific_data l5_data;
1729 u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1730 int ret;
1731
1732 if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1733 return -EINVAL;
1734
1735 data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1736 if (!data)
1737 return -ENOMEM;
1738
1739 memcpy(data, kwqe, sizeof(struct kwqe));
1740
1741 ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1742 req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1743 return ret;
1744 }
1745
1746 static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
1747 {
1748 struct cnic_local *cp = dev->cnic_priv;
1749 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1750 union l5cm_specific_data l5_data;
1751 int ret;
1752 u32 hw_cid, type;
1753
1754 init_waitqueue_head(&ctx->waitq);
1755 ctx->wait_cond = 0;
1756 memset(&l5_data, 0, sizeof(l5_data));
1757 hw_cid = BNX2X_HW_CID(cp, ctx->cid);
1758 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
1759 & SPE_HDR_CONN_TYPE;
1760 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
1761 SPE_HDR_FUNCTION_ID);
1762
1763 ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
1764 hw_cid, type, &l5_data);
1765
1766 if (ret == 0)
1767 wait_event(ctx->waitq, ctx->wait_cond);
1768
1769 return ret;
1770 }
1771
1772 static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1773 {
1774 struct cnic_local *cp = dev->cnic_priv;
1775 struct iscsi_kwqe_conn_destroy *req =
1776 (struct iscsi_kwqe_conn_destroy *) kwqe;
1777 u32 l5_cid = req->reserved0;
1778 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1779 int ret = 0;
1780 struct iscsi_kcqe kcqe;
1781 struct kcqe *cqes[1];
1782
1783 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
1784 goto skip_cfc_delete;
1785
1786 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
1787 unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
1788
1789 if (delta > (2 * HZ))
1790 delta = 0;
1791
1792 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
1793 queue_delayed_work(cnic_wq, &cp->delete_task, delta);
1794 goto destroy_reply;
1795 }
1796
1797 ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
1798
1799 skip_cfc_delete:
1800 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1801
1802 atomic_dec(&cp->iscsi_conn);
1803 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
1804
1805 destroy_reply:
1806 memset(&kcqe, 0, sizeof(kcqe));
1807 kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
1808 kcqe.iscsi_conn_id = l5_cid;
1809 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1810 kcqe.iscsi_conn_context_id = req->context_id;
1811
1812 cqes[0] = (struct kcqe *) &kcqe;
1813 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1814
1815 return ret;
1816 }
1817
1818 static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
1819 struct l4_kwq_connect_req1 *kwqe1,
1820 struct l4_kwq_connect_req3 *kwqe3,
1821 struct l5cm_active_conn_buffer *conn_buf)
1822 {
1823 struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
1824 struct l5cm_xstorm_conn_buffer *xstorm_buf =
1825 &conn_buf->xstorm_conn_buffer;
1826 struct l5cm_tstorm_conn_buffer *tstorm_buf =
1827 &conn_buf->tstorm_conn_buffer;
1828 struct regpair context_addr;
1829 u32 cid = BNX2X_SW_CID(kwqe1->cid);
1830 struct in6_addr src_ip, dst_ip;
1831 int i;
1832 u32 *addrp;
1833
1834 addrp = (u32 *) &conn_addr->local_ip_addr;
1835 for (i = 0; i < 4; i++, addrp++)
1836 src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1837
1838 addrp = (u32 *) &conn_addr->remote_ip_addr;
1839 for (i = 0; i < 4; i++, addrp++)
1840 dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1841
1842 cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
1843
1844 xstorm_buf->context_addr.hi = context_addr.hi;
1845 xstorm_buf->context_addr.lo = context_addr.lo;
1846 xstorm_buf->mss = 0xffff;
1847 xstorm_buf->rcv_buf = kwqe3->rcv_buf;
1848 if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
1849 xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
1850 xstorm_buf->pseudo_header_checksum =
1851 swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
1852
1853 if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
1854 tstorm_buf->params |=
1855 L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
1856 if (kwqe3->ka_timeout) {
1857 tstorm_buf->ka_enable = 1;
1858 tstorm_buf->ka_timeout = kwqe3->ka_timeout;
1859 tstorm_buf->ka_interval = kwqe3->ka_interval;
1860 tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
1861 }
1862 tstorm_buf->rcv_buf = kwqe3->rcv_buf;
1863 tstorm_buf->snd_buf = kwqe3->snd_buf;
1864 tstorm_buf->max_rt_time = 0xffffffff;
1865 }
1866
1867 static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
1868 {
1869 struct cnic_local *cp = dev->cnic_priv;
1870 u32 pfid = cp->pfid;
1871 u8 *mac = dev->mac_addr;
1872
1873 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1874 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
1875 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1876 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
1877 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1878 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
1879 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1880 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
1881 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1882 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
1883 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1884 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
1885
1886 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1887 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
1888 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1889 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
1890 mac[4]);
1891 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1892 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
1893 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1894 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
1895 mac[2]);
1896 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1897 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
1898 mac[1]);
1899 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1900 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
1901 mac[0]);
1902 }
1903
1904 static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
1905 {
1906 struct cnic_local *cp = dev->cnic_priv;
1907 u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
1908 u16 tstorm_flags = 0;
1909
1910 if (tcp_ts) {
1911 xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1912 tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1913 }
1914
1915 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1916 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
1917
1918 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1919 TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
1920 }
1921
1922 static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
1923 u32 num, int *work)
1924 {
1925 struct cnic_local *cp = dev->cnic_priv;
1926 struct l4_kwq_connect_req1 *kwqe1 =
1927 (struct l4_kwq_connect_req1 *) wqes[0];
1928 struct l4_kwq_connect_req3 *kwqe3;
1929 struct l5cm_active_conn_buffer *conn_buf;
1930 struct l5cm_conn_addr_params *conn_addr;
1931 union l5cm_specific_data l5_data;
1932 u32 l5_cid = kwqe1->pg_cid;
1933 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
1934 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1935 int ret;
1936
1937 if (num < 2) {
1938 *work = num;
1939 return -EINVAL;
1940 }
1941
1942 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
1943 *work = 3;
1944 else
1945 *work = 2;
1946
1947 if (num < *work) {
1948 *work = num;
1949 return -EINVAL;
1950 }
1951
1952 if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
1953 netdev_err(dev->netdev, "conn_buf size too big\n");
1954 return -ENOMEM;
1955 }
1956 conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1957 if (!conn_buf)
1958 return -ENOMEM;
1959
1960 memset(conn_buf, 0, sizeof(*conn_buf));
1961
1962 conn_addr = &conn_buf->conn_addr_buf;
1963 conn_addr->remote_addr_0 = csk->ha[0];
1964 conn_addr->remote_addr_1 = csk->ha[1];
1965 conn_addr->remote_addr_2 = csk->ha[2];
1966 conn_addr->remote_addr_3 = csk->ha[3];
1967 conn_addr->remote_addr_4 = csk->ha[4];
1968 conn_addr->remote_addr_5 = csk->ha[5];
1969
1970 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
1971 struct l4_kwq_connect_req2 *kwqe2 =
1972 (struct l4_kwq_connect_req2 *) wqes[1];
1973
1974 conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
1975 conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
1976 conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
1977
1978 conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
1979 conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
1980 conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
1981 conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
1982 }
1983 kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
1984
1985 conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
1986 conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
1987 conn_addr->local_tcp_port = kwqe1->src_port;
1988 conn_addr->remote_tcp_port = kwqe1->dst_port;
1989
1990 conn_addr->pmtu = kwqe3->pmtu;
1991 cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
1992
1993 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1994 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
1995
1996 cnic_bnx2x_set_tcp_timestamp(dev,
1997 kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
1998
1999 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
2000 kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2001 if (!ret)
2002 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2003
2004 return ret;
2005 }
2006
2007 static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
2008 {
2009 struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
2010 union l5cm_specific_data l5_data;
2011 int ret;
2012
2013 memset(&l5_data, 0, sizeof(l5_data));
2014 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
2015 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2016 return ret;
2017 }
2018
2019 static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
2020 {
2021 struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
2022 union l5cm_specific_data l5_data;
2023 int ret;
2024
2025 memset(&l5_data, 0, sizeof(l5_data));
2026 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
2027 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2028 return ret;
2029 }
2030 static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2031 {
2032 struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
2033 struct l4_kcq kcqe;
2034 struct kcqe *cqes[1];
2035
2036 memset(&kcqe, 0, sizeof(kcqe));
2037 kcqe.pg_host_opaque = req->host_opaque;
2038 kcqe.pg_cid = req->host_opaque;
2039 kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
2040 cqes[0] = (struct kcqe *) &kcqe;
2041 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2042 return 0;
2043 }
2044
2045 static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2046 {
2047 struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
2048 struct l4_kcq kcqe;
2049 struct kcqe *cqes[1];
2050
2051 memset(&kcqe, 0, sizeof(kcqe));
2052 kcqe.pg_host_opaque = req->pg_host_opaque;
2053 kcqe.pg_cid = req->pg_cid;
2054 kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
2055 cqes[0] = (struct kcqe *) &kcqe;
2056 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2057 return 0;
2058 }
2059
2060 static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2061 u32 num_wqes)
2062 {
2063 int i, work, ret;
2064 u32 opcode;
2065 struct kwqe *kwqe;
2066
2067 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2068 return -EAGAIN; /* bnx2 is down */
2069
2070 for (i = 0; i < num_wqes; ) {
2071 kwqe = wqes[i];
2072 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2073 work = 1;
2074
2075 switch (opcode) {
2076 case ISCSI_KWQE_OPCODE_INIT1:
2077 ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
2078 break;
2079 case ISCSI_KWQE_OPCODE_INIT2:
2080 ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
2081 break;
2082 case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
2083 ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
2084 num_wqes - i, &work);
2085 break;
2086 case ISCSI_KWQE_OPCODE_UPDATE_CONN:
2087 ret = cnic_bnx2x_iscsi_update(dev, kwqe);
2088 break;
2089 case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2090 ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2091 break;
2092 case L4_KWQE_OPCODE_VALUE_CONNECT1:
2093 ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2094 &work);
2095 break;
2096 case L4_KWQE_OPCODE_VALUE_CLOSE:
2097 ret = cnic_bnx2x_close(dev, kwqe);
2098 break;
2099 case L4_KWQE_OPCODE_VALUE_RESET:
2100 ret = cnic_bnx2x_reset(dev, kwqe);
2101 break;
2102 case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2103 ret = cnic_bnx2x_offload_pg(dev, kwqe);
2104 break;
2105 case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2106 ret = cnic_bnx2x_update_pg(dev, kwqe);
2107 break;
2108 case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2109 ret = 0;
2110 break;
2111 default:
2112 ret = 0;
2113 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2114 opcode);
2115 break;
2116 }
2117 if (ret < 0)
2118 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2119 opcode);
2120 i += work;
2121 }
2122 return 0;
2123 }
2124
2125 static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2126 {
2127 struct cnic_local *cp = dev->cnic_priv;
2128 int i, j, comp = 0;
2129
2130 i = 0;
2131 j = 1;
2132 while (num_cqes) {
2133 struct cnic_ulp_ops *ulp_ops;
2134 int ulp_type;
2135 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2136 u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
2137
2138 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2139 comp++;
2140
2141 while (j < num_cqes) {
2142 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2143
2144 if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
2145 break;
2146
2147 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
2148 comp++;
2149 j++;
2150 }
2151
2152 if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2153 ulp_type = CNIC_ULP_RDMA;
2154 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2155 ulp_type = CNIC_ULP_ISCSI;
2156 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2157 ulp_type = CNIC_ULP_L4;
2158 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2159 goto end;
2160 else {
2161 netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2162 kcqe_op_flag);
2163 goto end;
2164 }
2165
2166 rcu_read_lock();
2167 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2168 if (likely(ulp_ops)) {
2169 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2170 cp->completed_kcq + i, j);
2171 }
2172 rcu_read_unlock();
2173 end:
2174 num_cqes -= j;
2175 i += j;
2176 j = 1;
2177 }
2178 if (unlikely(comp))
2179 cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
2180 }
2181
2182 static u16 cnic_bnx2_next_idx(u16 idx)
2183 {
2184 return idx + 1;
2185 }
2186
2187 static u16 cnic_bnx2_hw_idx(u16 idx)
2188 {
2189 return idx;
2190 }
2191
2192 static u16 cnic_bnx2x_next_idx(u16 idx)
2193 {
2194 idx++;
2195 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2196 idx++;
2197
2198 return idx;
2199 }
2200
2201 static u16 cnic_bnx2x_hw_idx(u16 idx)
2202 {
2203 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2204 idx++;
2205 return idx;
2206 }
2207
2208 static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
2209 {
2210 struct cnic_local *cp = dev->cnic_priv;
2211 u16 i, ri, hw_prod, last;
2212 struct kcqe *kcqe;
2213 int kcqe_cnt = 0, last_cnt = 0;
2214
2215 i = ri = last = info->sw_prod_idx;
2216 ri &= MAX_KCQ_IDX;
2217 hw_prod = *info->hw_prod_idx_ptr;
2218 hw_prod = cp->hw_idx(hw_prod);
2219
2220 while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
2221 kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
2222 cp->completed_kcq[kcqe_cnt++] = kcqe;
2223 i = cp->next_idx(i);
2224 ri = i & MAX_KCQ_IDX;
2225 if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2226 last_cnt = kcqe_cnt;
2227 last = i;
2228 }
2229 }
2230
2231 info->sw_prod_idx = last;
2232 return last_cnt;
2233 }
2234
2235 static int cnic_l2_completion(struct cnic_local *cp)
2236 {
2237 u16 hw_cons, sw_cons;
2238 struct cnic_uio_dev *udev = cp->udev;
2239 union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
2240 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
2241 u32 cmd;
2242 int comp = 0;
2243
2244 if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
2245 return 0;
2246
2247 hw_cons = *cp->rx_cons_ptr;
2248 if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
2249 hw_cons++;
2250
2251 sw_cons = cp->rx_cons;
2252 while (sw_cons != hw_cons) {
2253 u8 cqe_fp_flags;
2254
2255 cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
2256 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2257 if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
2258 cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
2259 cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
2260 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
2261 cmd == RAMROD_CMD_ID_ETH_HALT)
2262 comp++;
2263 }
2264 sw_cons = BNX2X_NEXT_RCQE(sw_cons);
2265 }
2266 return comp;
2267 }
2268
2269 static void cnic_chk_pkt_rings(struct cnic_local *cp)
2270 {
2271 u16 rx_cons, tx_cons;
2272 int comp = 0;
2273
2274 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
2275 return;
2276
2277 rx_cons = *cp->rx_cons_ptr;
2278 tx_cons = *cp->tx_cons_ptr;
2279 if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
2280 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
2281 comp = cnic_l2_completion(cp);
2282
2283 cp->tx_cons = tx_cons;
2284 cp->rx_cons = rx_cons;
2285
2286 if (cp->udev)
2287 uio_event_notify(&cp->udev->cnic_uinfo);
2288 }
2289 if (comp)
2290 clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
2291 }
2292
2293 static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
2294 {
2295 struct cnic_local *cp = dev->cnic_priv;
2296 u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2297 int kcqe_cnt;
2298
2299 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2300
2301 while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
2302
2303 service_kcqes(dev, kcqe_cnt);
2304
2305 /* Tell compiler that status_blk fields can change. */
2306 barrier();
2307 if (status_idx != *cp->kcq1.status_idx_ptr) {
2308 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2309 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2310 } else
2311 break;
2312 }
2313
2314 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
2315
2316 cnic_chk_pkt_rings(cp);
2317
2318 return status_idx;
2319 }
2320
2321 static int cnic_service_bnx2(void *data, void *status_blk)
2322 {
2323 struct cnic_dev *dev = data;
2324 struct cnic_local *cp = dev->cnic_priv;
2325 u32 status_idx = *cp->kcq1.status_idx_ptr;
2326
2327 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2328 return status_idx;
2329
2330 return cnic_service_bnx2_queues(dev);
2331 }
2332
2333 static void cnic_service_bnx2_msix(unsigned long data)
2334 {
2335 struct cnic_dev *dev = (struct cnic_dev *) data;
2336 struct cnic_local *cp = dev->cnic_priv;
2337
2338 cp->last_status_idx = cnic_service_bnx2_queues(dev);
2339
2340 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
2341 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
2342 }
2343
2344 static void cnic_doirq(struct cnic_dev *dev)
2345 {
2346 struct cnic_local *cp = dev->cnic_priv;
2347 u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
2348
2349 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2350 prefetch(cp->status_blk.gen);
2351 prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
2352
2353 tasklet_schedule(&cp->cnic_irq_task);
2354 }
2355 }
2356
2357 static irqreturn_t cnic_irq(int irq, void *dev_instance)
2358 {
2359 struct cnic_dev *dev = dev_instance;
2360 struct cnic_local *cp = dev->cnic_priv;
2361
2362 if (cp->ack_int)
2363 cp->ack_int(dev);
2364
2365 cnic_doirq(dev);
2366
2367 return IRQ_HANDLED;
2368 }
2369
2370 static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
2371 u16 index, u8 op, u8 update)
2372 {
2373 struct cnic_local *cp = dev->cnic_priv;
2374 u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
2375 COMMAND_REG_INT_ACK);
2376 struct igu_ack_register igu_ack;
2377
2378 igu_ack.status_block_index = index;
2379 igu_ack.sb_id_and_flags =
2380 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2381 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2382 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2383 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2384
2385 CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
2386 }
2387
2388 static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
2389 {
2390 struct cnic_local *cp = dev->cnic_priv;
2391
2392 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
2393 IGU_INT_DISABLE, 0);
2394 }
2395
2396 static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
2397 {
2398 u32 last_status = *info->status_idx_ptr;
2399 int kcqe_cnt;
2400
2401 while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
2402
2403 service_kcqes(dev, kcqe_cnt);
2404
2405 /* Tell compiler that sblk fields can change. */
2406 barrier();
2407 if (last_status == *info->status_idx_ptr)
2408 break;
2409
2410 last_status = *info->status_idx_ptr;
2411 }
2412 return last_status;
2413 }
2414
2415 static void cnic_service_bnx2x_bh(unsigned long data)
2416 {
2417 struct cnic_dev *dev = (struct cnic_dev *) data;
2418 struct cnic_local *cp = dev->cnic_priv;
2419 u32 status_idx;
2420
2421 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2422 return;
2423
2424 status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
2425
2426 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
2427 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
2428 status_idx, IGU_INT_ENABLE, 1);
2429 }
2430
2431 static int cnic_service_bnx2x(void *data, void *status_blk)
2432 {
2433 struct cnic_dev *dev = data;
2434 struct cnic_local *cp = dev->cnic_priv;
2435
2436 if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
2437 cnic_doirq(dev);
2438
2439 cnic_chk_pkt_rings(cp);
2440
2441 return 0;
2442 }
2443
2444 static void cnic_ulp_stop(struct cnic_dev *dev)
2445 {
2446 struct cnic_local *cp = dev->cnic_priv;
2447 int if_type;
2448
2449 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
2450
2451 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2452 struct cnic_ulp_ops *ulp_ops;
2453
2454 mutex_lock(&cnic_lock);
2455 ulp_ops = cp->ulp_ops[if_type];
2456 if (!ulp_ops) {
2457 mutex_unlock(&cnic_lock);
2458 continue;
2459 }
2460 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2461 mutex_unlock(&cnic_lock);
2462
2463 if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2464 ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
2465
2466 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2467 }
2468 }
2469
2470 static void cnic_ulp_start(struct cnic_dev *dev)
2471 {
2472 struct cnic_local *cp = dev->cnic_priv;
2473 int if_type;
2474
2475 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2476 struct cnic_ulp_ops *ulp_ops;
2477
2478 mutex_lock(&cnic_lock);
2479 ulp_ops = cp->ulp_ops[if_type];
2480 if (!ulp_ops || !ulp_ops->cnic_start) {
2481 mutex_unlock(&cnic_lock);
2482 continue;
2483 }
2484 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2485 mutex_unlock(&cnic_lock);
2486
2487 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2488 ulp_ops->cnic_start(cp->ulp_handle[if_type]);
2489
2490 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2491 }
2492 }
2493
2494 static int cnic_ctl(void *data, struct cnic_ctl_info *info)
2495 {
2496 struct cnic_dev *dev = data;
2497
2498 switch (info->cmd) {
2499 case CNIC_CTL_STOP_CMD:
2500 cnic_hold(dev);
2501
2502 cnic_ulp_stop(dev);
2503 cnic_stop_hw(dev);
2504
2505 cnic_put(dev);
2506 break;
2507 case CNIC_CTL_START_CMD:
2508 cnic_hold(dev);
2509
2510 if (!cnic_start_hw(dev))
2511 cnic_ulp_start(dev);
2512
2513 cnic_put(dev);
2514 break;
2515 case CNIC_CTL_COMPLETION_CMD: {
2516 u32 cid = BNX2X_SW_CID(info->data.comp.cid);
2517 u32 l5_cid;
2518 struct cnic_local *cp = dev->cnic_priv;
2519
2520 if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
2521 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2522
2523 ctx->wait_cond = 1;
2524 wake_up(&ctx->waitq);
2525 }
2526 break;
2527 }
2528 default:
2529 return -EINVAL;
2530 }
2531 return 0;
2532 }
2533
2534 static void cnic_ulp_init(struct cnic_dev *dev)
2535 {
2536 int i;
2537 struct cnic_local *cp = dev->cnic_priv;
2538
2539 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
2540 struct cnic_ulp_ops *ulp_ops;
2541
2542 mutex_lock(&cnic_lock);
2543 ulp_ops = cnic_ulp_tbl[i];
2544 if (!ulp_ops || !ulp_ops->cnic_init) {
2545 mutex_unlock(&cnic_lock);
2546 continue;
2547 }
2548 ulp_get(ulp_ops);
2549 mutex_unlock(&cnic_lock);
2550
2551 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
2552 ulp_ops->cnic_init(dev);
2553
2554 ulp_put(ulp_ops);
2555 }
2556 }
2557
2558 static void cnic_ulp_exit(struct cnic_dev *dev)
2559 {
2560 int i;
2561 struct cnic_local *cp = dev->cnic_priv;
2562
2563 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
2564 struct cnic_ulp_ops *ulp_ops;
2565
2566 mutex_lock(&cnic_lock);
2567 ulp_ops = cnic_ulp_tbl[i];
2568 if (!ulp_ops || !ulp_ops->cnic_exit) {
2569 mutex_unlock(&cnic_lock);
2570 continue;
2571 }
2572 ulp_get(ulp_ops);
2573 mutex_unlock(&cnic_lock);
2574
2575 if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
2576 ulp_ops->cnic_exit(dev);
2577
2578 ulp_put(ulp_ops);
2579 }
2580 }
2581
2582 static int cnic_cm_offload_pg(struct cnic_sock *csk)
2583 {
2584 struct cnic_dev *dev = csk->dev;
2585 struct l4_kwq_offload_pg *l4kwqe;
2586 struct kwqe *wqes[1];
2587
2588 l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
2589 memset(l4kwqe, 0, sizeof(*l4kwqe));
2590 wqes[0] = (struct kwqe *) l4kwqe;
2591
2592 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
2593 l4kwqe->flags =
2594 L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
2595 l4kwqe->l2hdr_nbytes = ETH_HLEN;
2596
2597 l4kwqe->da0 = csk->ha[0];
2598 l4kwqe->da1 = csk->ha[1];
2599 l4kwqe->da2 = csk->ha[2];
2600 l4kwqe->da3 = csk->ha[3];
2601 l4kwqe->da4 = csk->ha[4];
2602 l4kwqe->da5 = csk->ha[5];
2603
2604 l4kwqe->sa0 = dev->mac_addr[0];
2605 l4kwqe->sa1 = dev->mac_addr[1];
2606 l4kwqe->sa2 = dev->mac_addr[2];
2607 l4kwqe->sa3 = dev->mac_addr[3];
2608 l4kwqe->sa4 = dev->mac_addr[4];
2609 l4kwqe->sa5 = dev->mac_addr[5];
2610
2611 l4kwqe->etype = ETH_P_IP;
2612 l4kwqe->ipid_start = DEF_IPID_START;
2613 l4kwqe->host_opaque = csk->l5_cid;
2614
2615 if (csk->vlan_id) {
2616 l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
2617 l4kwqe->vlan_tag = csk->vlan_id;
2618 l4kwqe->l2hdr_nbytes += 4;
2619 }
2620
2621 return dev->submit_kwqes(dev, wqes, 1);
2622 }
2623
2624 static int cnic_cm_update_pg(struct cnic_sock *csk)
2625 {
2626 struct cnic_dev *dev = csk->dev;
2627 struct l4_kwq_update_pg *l4kwqe;
2628 struct kwqe *wqes[1];
2629
2630 l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
2631 memset(l4kwqe, 0, sizeof(*l4kwqe));
2632 wqes[0] = (struct kwqe *) l4kwqe;
2633
2634 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
2635 l4kwqe->flags =
2636 L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
2637 l4kwqe->pg_cid = csk->pg_cid;
2638
2639 l4kwqe->da0 = csk->ha[0];
2640 l4kwqe->da1 = csk->ha[1];
2641 l4kwqe->da2 = csk->ha[2];
2642 l4kwqe->da3 = csk->ha[3];
2643 l4kwqe->da4 = csk->ha[4];
2644 l4kwqe->da5 = csk->ha[5];
2645
2646 l4kwqe->pg_host_opaque = csk->l5_cid;
2647 l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
2648
2649 return dev->submit_kwqes(dev, wqes, 1);
2650 }
2651
2652 static int cnic_cm_upload_pg(struct cnic_sock *csk)
2653 {
2654 struct cnic_dev *dev = csk->dev;
2655 struct l4_kwq_upload *l4kwqe;
2656 struct kwqe *wqes[1];
2657
2658 l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
2659 memset(l4kwqe, 0, sizeof(*l4kwqe));
2660 wqes[0] = (struct kwqe *) l4kwqe;
2661
2662 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
2663 l4kwqe->flags =
2664 L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
2665 l4kwqe->cid = csk->pg_cid;
2666
2667 return dev->submit_kwqes(dev, wqes, 1);
2668 }
2669
2670 static int cnic_cm_conn_req(struct cnic_sock *csk)
2671 {
2672 struct cnic_dev *dev = csk->dev;
2673 struct l4_kwq_connect_req1 *l4kwqe1;
2674 struct l4_kwq_connect_req2 *l4kwqe2;
2675 struct l4_kwq_connect_req3 *l4kwqe3;
2676 struct kwqe *wqes[3];
2677 u8 tcp_flags = 0;
2678 int num_wqes = 2;
2679
2680 l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
2681 l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
2682 l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
2683 memset(l4kwqe1, 0, sizeof(*l4kwqe1));
2684 memset(l4kwqe2, 0, sizeof(*l4kwqe2));
2685 memset(l4kwqe3, 0, sizeof(*l4kwqe3));
2686
2687 l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
2688 l4kwqe3->flags =
2689 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
2690 l4kwqe3->ka_timeout = csk->ka_timeout;
2691 l4kwqe3->ka_interval = csk->ka_interval;
2692 l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
2693 l4kwqe3->tos = csk->tos;
2694 l4kwqe3->ttl = csk->ttl;
2695 l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
2696 l4kwqe3->pmtu = csk->mtu;
2697 l4kwqe3->rcv_buf = csk->rcv_buf;
2698 l4kwqe3->snd_buf = csk->snd_buf;
2699 l4kwqe3->seed = csk->seed;
2700
2701 wqes[0] = (struct kwqe *) l4kwqe1;
2702 if (test_bit(SK_F_IPV6, &csk->flags)) {
2703 wqes[1] = (struct kwqe *) l4kwqe2;
2704 wqes[2] = (struct kwqe *) l4kwqe3;
2705 num_wqes = 3;
2706
2707 l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
2708 l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
2709 l4kwqe2->flags =
2710 L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
2711 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
2712 l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
2713 l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
2714 l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
2715 l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
2716 l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
2717 l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
2718 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
2719 sizeof(struct tcphdr);
2720 } else {
2721 wqes[1] = (struct kwqe *) l4kwqe3;
2722 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
2723 sizeof(struct tcphdr);
2724 }
2725
2726 l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
2727 l4kwqe1->flags =
2728 (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
2729 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
2730 l4kwqe1->cid = csk->cid;
2731 l4kwqe1->pg_cid = csk->pg_cid;
2732 l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
2733 l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
2734 l4kwqe1->src_port = be16_to_cpu(csk->src_port);
2735 l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
2736 if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
2737 tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
2738 if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
2739 tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
2740 if (csk->tcp_flags & SK_TCP_NAGLE)
2741 tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
2742 if (csk->tcp_flags & SK_TCP_TIMESTAMP)
2743 tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
2744 if (csk->tcp_flags & SK_TCP_SACK)
2745 tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
2746 if (csk->tcp_flags & SK_TCP_SEG_SCALING)
2747 tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
2748
2749 l4kwqe1->tcp_flags = tcp_flags;
2750
2751 return dev->submit_kwqes(dev, wqes, num_wqes);
2752 }
2753
2754 static int cnic_cm_close_req(struct cnic_sock *csk)
2755 {
2756 struct cnic_dev *dev = csk->dev;
2757 struct l4_kwq_close_req *l4kwqe;
2758 struct kwqe *wqes[1];
2759
2760 l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
2761 memset(l4kwqe, 0, sizeof(*l4kwqe));
2762 wqes[0] = (struct kwqe *) l4kwqe;
2763
2764 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
2765 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
2766 l4kwqe->cid = csk->cid;
2767
2768 return dev->submit_kwqes(dev, wqes, 1);
2769 }
2770
2771 static int cnic_cm_abort_req(struct cnic_sock *csk)
2772 {
2773 struct cnic_dev *dev = csk->dev;
2774 struct l4_kwq_reset_req *l4kwqe;
2775 struct kwqe *wqes[1];
2776
2777 l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
2778 memset(l4kwqe, 0, sizeof(*l4kwqe));
2779 wqes[0] = (struct kwqe *) l4kwqe;
2780
2781 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
2782 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
2783 l4kwqe->cid = csk->cid;
2784
2785 return dev->submit_kwqes(dev, wqes, 1);
2786 }
2787
2788 static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
2789 u32 l5_cid, struct cnic_sock **csk, void *context)
2790 {
2791 struct cnic_local *cp = dev->cnic_priv;
2792 struct cnic_sock *csk1;
2793
2794 if (l5_cid >= MAX_CM_SK_TBL_SZ)
2795 return -EINVAL;
2796
2797 if (cp->ctx_tbl) {
2798 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2799
2800 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2801 return -EAGAIN;
2802 }
2803
2804 csk1 = &cp->csk_tbl[l5_cid];
2805 if (atomic_read(&csk1->ref_count))
2806 return -EAGAIN;
2807
2808 if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
2809 return -EBUSY;
2810
2811 csk1->dev = dev;
2812 csk1->cid = cid;
2813 csk1->l5_cid = l5_cid;
2814 csk1->ulp_type = ulp_type;
2815 csk1->context = context;
2816
2817 csk1->ka_timeout = DEF_KA_TIMEOUT;
2818 csk1->ka_interval = DEF_KA_INTERVAL;
2819 csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
2820 csk1->tos = DEF_TOS;
2821 csk1->ttl = DEF_TTL;
2822 csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
2823 csk1->rcv_buf = DEF_RCV_BUF;
2824 csk1->snd_buf = DEF_SND_BUF;
2825 csk1->seed = DEF_SEED;
2826
2827 *csk = csk1;
2828 return 0;
2829 }
2830
2831 static void cnic_cm_cleanup(struct cnic_sock *csk)
2832 {
2833 if (csk->src_port) {
2834 struct cnic_dev *dev = csk->dev;
2835 struct cnic_local *cp = dev->cnic_priv;
2836
2837 cnic_free_id(&cp->csk_port_tbl, csk->src_port);
2838 csk->src_port = 0;
2839 }
2840 }
2841
2842 static void cnic_close_conn(struct cnic_sock *csk)
2843 {
2844 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
2845 cnic_cm_upload_pg(csk);
2846 clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
2847 }
2848 cnic_cm_cleanup(csk);
2849 }
2850
2851 static int cnic_cm_destroy(struct cnic_sock *csk)
2852 {
2853 if (!cnic_in_use(csk))
2854 return -EINVAL;
2855
2856 csk_hold(csk);
2857 clear_bit(SK_F_INUSE, &csk->flags);
2858 smp_mb__after_clear_bit();
2859 while (atomic_read(&csk->ref_count) != 1)
2860 msleep(1);
2861 cnic_cm_cleanup(csk);
2862
2863 csk->flags = 0;
2864 csk_put(csk);
2865 return 0;
2866 }
2867
2868 static inline u16 cnic_get_vlan(struct net_device *dev,
2869 struct net_device **vlan_dev)
2870 {
2871 if (dev->priv_flags & IFF_802_1Q_VLAN) {
2872 *vlan_dev = vlan_dev_real_dev(dev);
2873 return vlan_dev_vlan_id(dev);
2874 }
2875 *vlan_dev = dev;
2876 return 0;
2877 }
2878
2879 static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
2880 struct dst_entry **dst)
2881 {
2882 #if defined(CONFIG_INET)
2883 struct flowi fl;
2884 int err;
2885 struct rtable *rt;
2886
2887 memset(&fl, 0, sizeof(fl));
2888 fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
2889
2890 err = ip_route_output_key(&init_net, &rt, &fl);
2891 if (!err)
2892 *dst = &rt->dst;
2893 return err;
2894 #else
2895 return -ENETUNREACH;
2896 #endif
2897 }
2898
2899 static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
2900 struct dst_entry **dst)
2901 {
2902 #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
2903 struct flowi fl;
2904
2905 memset(&fl, 0, sizeof(fl));
2906 ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
2907 if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
2908 fl.oif = dst_addr->sin6_scope_id;
2909
2910 *dst = ip6_route_output(&init_net, NULL, &fl);
2911 if (*dst)
2912 return 0;
2913 #endif
2914
2915 return -ENETUNREACH;
2916 }
2917
2918 static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
2919 int ulp_type)
2920 {
2921 struct cnic_dev *dev = NULL;
2922 struct dst_entry *dst;
2923 struct net_device *netdev = NULL;
2924 int err = -ENETUNREACH;
2925
2926 if (dst_addr->sin_family == AF_INET)
2927 err = cnic_get_v4_route(dst_addr, &dst);
2928 else if (dst_addr->sin_family == AF_INET6) {
2929 struct sockaddr_in6 *dst_addr6 =
2930 (struct sockaddr_in6 *) dst_addr;
2931
2932 err = cnic_get_v6_route(dst_addr6, &dst);
2933 } else
2934 return NULL;
2935
2936 if (err)
2937 return NULL;
2938
2939 if (!dst->dev)
2940 goto done;
2941
2942 cnic_get_vlan(dst->dev, &netdev);
2943
2944 dev = cnic_from_netdev(netdev);
2945
2946 done:
2947 dst_release(dst);
2948 if (dev)
2949 cnic_put(dev);
2950 return dev;
2951 }
2952
2953 static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2954 {
2955 struct cnic_dev *dev = csk->dev;
2956 struct cnic_local *cp = dev->cnic_priv;
2957
2958 return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
2959 }
2960
2961 static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2962 {
2963 struct cnic_dev *dev = csk->dev;
2964 struct cnic_local *cp = dev->cnic_priv;
2965 int is_v6, rc = 0;
2966 struct dst_entry *dst = NULL;
2967 struct net_device *realdev;
2968 u32 local_port;
2969
2970 if (saddr->local.v6.sin6_family == AF_INET6 &&
2971 saddr->remote.v6.sin6_family == AF_INET6)
2972 is_v6 = 1;
2973 else if (saddr->local.v4.sin_family == AF_INET &&
2974 saddr->remote.v4.sin_family == AF_INET)
2975 is_v6 = 0;
2976 else
2977 return -EINVAL;
2978
2979 clear_bit(SK_F_IPV6, &csk->flags);
2980
2981 if (is_v6) {
2982 set_bit(SK_F_IPV6, &csk->flags);
2983 cnic_get_v6_route(&saddr->remote.v6, &dst);
2984
2985 memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
2986 sizeof(struct in6_addr));
2987 csk->dst_port = saddr->remote.v6.sin6_port;
2988 local_port = saddr->local.v6.sin6_port;
2989
2990 } else {
2991 cnic_get_v4_route(&saddr->remote.v4, &dst);
2992
2993 csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
2994 csk->dst_port = saddr->remote.v4.sin_port;
2995 local_port = saddr->local.v4.sin_port;
2996 }
2997
2998 csk->vlan_id = 0;
2999 csk->mtu = dev->netdev->mtu;
3000 if (dst && dst->dev) {
3001 u16 vlan = cnic_get_vlan(dst->dev, &realdev);
3002 if (realdev == dev->netdev) {
3003 csk->vlan_id = vlan;
3004 csk->mtu = dst_mtu(dst);
3005 }
3006 }
3007
3008 if (local_port >= CNIC_LOCAL_PORT_MIN &&
3009 local_port < CNIC_LOCAL_PORT_MAX) {
3010 if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
3011 local_port = 0;
3012 } else
3013 local_port = 0;
3014
3015 if (!local_port) {
3016 local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
3017 if (local_port == -1) {
3018 rc = -ENOMEM;
3019 goto err_out;
3020 }
3021 }
3022 csk->src_port = local_port;
3023
3024 err_out:
3025 dst_release(dst);
3026 return rc;
3027 }
3028
3029 static void cnic_init_csk_state(struct cnic_sock *csk)
3030 {
3031 csk->state = 0;
3032 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3033 clear_bit(SK_F_CLOSING, &csk->flags);
3034 }
3035
3036 static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3037 {
3038 int err = 0;
3039
3040 if (!cnic_in_use(csk))
3041 return -EINVAL;
3042
3043 if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
3044 return -EINVAL;
3045
3046 cnic_init_csk_state(csk);
3047
3048 err = cnic_get_route(csk, saddr);
3049 if (err)
3050 goto err_out;
3051
3052 err = cnic_resolve_addr(csk, saddr);
3053 if (!err)
3054 return 0;
3055
3056 err_out:
3057 clear_bit(SK_F_CONNECT_START, &csk->flags);
3058 return err;
3059 }
3060
3061 static int cnic_cm_abort(struct cnic_sock *csk)
3062 {
3063 struct cnic_local *cp = csk->dev->cnic_priv;
3064 u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
3065
3066 if (!cnic_in_use(csk))
3067 return -EINVAL;
3068
3069 if (cnic_abort_prep(csk))
3070 return cnic_cm_abort_req(csk);
3071
3072 /* Getting here means that we haven't started connect, or
3073 * connect was not successful.
3074 */
3075
3076 cp->close_conn(csk, opcode);
3077 if (csk->state != opcode)
3078 return -EALREADY;
3079
3080 return 0;
3081 }
3082
3083 static int cnic_cm_close(struct cnic_sock *csk)
3084 {
3085 if (!cnic_in_use(csk))
3086 return -EINVAL;
3087
3088 if (cnic_close_prep(csk)) {
3089 csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
3090 return cnic_cm_close_req(csk);
3091 } else {
3092 return -EALREADY;
3093 }
3094 return 0;
3095 }
3096
3097 static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
3098 u8 opcode)
3099 {
3100 struct cnic_ulp_ops *ulp_ops;
3101 int ulp_type = csk->ulp_type;
3102
3103 rcu_read_lock();
3104 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3105 if (ulp_ops) {
3106 if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3107 ulp_ops->cm_connect_complete(csk);
3108 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3109 ulp_ops->cm_close_complete(csk);
3110 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3111 ulp_ops->cm_remote_abort(csk);
3112 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3113 ulp_ops->cm_abort_complete(csk);
3114 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3115 ulp_ops->cm_remote_close(csk);
3116 }
3117 rcu_read_unlock();
3118 }
3119
3120 static int cnic_cm_set_pg(struct cnic_sock *csk)
3121 {
3122 if (cnic_offld_prep(csk)) {
3123 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3124 cnic_cm_update_pg(csk);
3125 else
3126 cnic_cm_offload_pg(csk);
3127 }
3128 return 0;
3129 }
3130
3131 static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3132 {
3133 struct cnic_local *cp = dev->cnic_priv;
3134 u32 l5_cid = kcqe->pg_host_opaque;
3135 u8 opcode = kcqe->op_code;
3136 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3137
3138 csk_hold(csk);
3139 if (!cnic_in_use(csk))
3140 goto done;
3141
3142 if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3143 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3144 goto done;
3145 }
3146 /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3147 if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3148 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3149 cnic_cm_upcall(cp, csk,
3150 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3151 goto done;
3152 }
3153
3154 csk->pg_cid = kcqe->pg_cid;
3155 set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3156 cnic_cm_conn_req(csk);
3157
3158 done:
3159 csk_put(csk);
3160 }
3161
3162 static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3163 {
3164 struct cnic_local *cp = dev->cnic_priv;
3165 struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3166 u8 opcode = l4kcqe->op_code;
3167 u32 l5_cid;
3168 struct cnic_sock *csk;
3169
3170 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3171 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3172 cnic_cm_process_offld_pg(dev, l4kcqe);
3173 return;
3174 }
3175
3176 l5_cid = l4kcqe->conn_id;
3177 if (opcode & 0x80)
3178 l5_cid = l4kcqe->cid;
3179 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3180 return;
3181
3182 csk = &cp->csk_tbl[l5_cid];
3183 csk_hold(csk);
3184
3185 if (!cnic_in_use(csk)) {
3186 csk_put(csk);
3187 return;
3188 }
3189
3190 switch (opcode) {
3191 case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
3192 if (l4kcqe->status != 0) {
3193 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3194 cnic_cm_upcall(cp, csk,
3195 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3196 }
3197 break;
3198 case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
3199 if (l4kcqe->status == 0)
3200 set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
3201
3202 smp_mb__before_clear_bit();
3203 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3204 cnic_cm_upcall(cp, csk, opcode);
3205 break;
3206
3207 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3208 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3209 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3210 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3211 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3212 cp->close_conn(csk, opcode);
3213 break;
3214
3215 case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
3216 cnic_cm_upcall(cp, csk, opcode);
3217 break;
3218 }
3219 csk_put(csk);
3220 }
3221
3222 static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
3223 {
3224 struct cnic_dev *dev = data;
3225 int i;
3226
3227 for (i = 0; i < num; i++)
3228 cnic_cm_process_kcqe(dev, kcqe[i]);
3229 }
3230
3231 static struct cnic_ulp_ops cm_ulp_ops = {
3232 .indicate_kcqes = cnic_cm_indicate_kcqe,
3233 };
3234
3235 static void cnic_cm_free_mem(struct cnic_dev *dev)
3236 {
3237 struct cnic_local *cp = dev->cnic_priv;
3238
3239 kfree(cp->csk_tbl);
3240 cp->csk_tbl = NULL;
3241 cnic_free_id_tbl(&cp->csk_port_tbl);
3242 }
3243
3244 static int cnic_cm_alloc_mem(struct cnic_dev *dev)
3245 {
3246 struct cnic_local *cp = dev->cnic_priv;
3247
3248 cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
3249 GFP_KERNEL);
3250 if (!cp->csk_tbl)
3251 return -ENOMEM;
3252
3253 if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
3254 CNIC_LOCAL_PORT_MIN)) {
3255 cnic_cm_free_mem(dev);
3256 return -ENOMEM;
3257 }
3258 return 0;
3259 }
3260
3261 static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
3262 {
3263 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
3264 /* Unsolicited RESET_COMP or RESET_RECEIVED */
3265 opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
3266 csk->state = opcode;
3267 }
3268
3269 /* 1. If event opcode matches the expected event in csk->state
3270 * 2. If the expected event is CLOSE_COMP, we accept any event
3271 * 3. If the expected event is 0, meaning the connection was never
3272 * never established, we accept the opcode from cm_abort.
3273 */
3274 if (opcode == csk->state || csk->state == 0 ||
3275 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
3276 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
3277 if (csk->state == 0)
3278 csk->state = opcode;
3279 return 1;
3280 }
3281 }
3282 return 0;
3283 }
3284
3285 static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
3286 {
3287 struct cnic_dev *dev = csk->dev;
3288 struct cnic_local *cp = dev->cnic_priv;
3289
3290 if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
3291 cnic_cm_upcall(cp, csk, opcode);
3292 return;
3293 }
3294
3295 clear_bit(SK_F_CONNECT_START, &csk->flags);
3296 cnic_close_conn(csk);
3297 csk->state = opcode;
3298 cnic_cm_upcall(cp, csk, opcode);
3299 }
3300
3301 static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
3302 {
3303 }
3304
3305 static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
3306 {
3307 u32 seed;
3308
3309 get_random_bytes(&seed, 4);
3310 cnic_ctx_wr(dev, 45, 0, seed);
3311 return 0;
3312 }
3313
3314 static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
3315 {
3316 struct cnic_dev *dev = csk->dev;
3317 struct cnic_local *cp = dev->cnic_priv;
3318 struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
3319 union l5cm_specific_data l5_data;
3320 u32 cmd = 0;
3321 int close_complete = 0;
3322
3323 switch (opcode) {
3324 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3325 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3326 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3327 if (cnic_ready_to_close(csk, opcode)) {
3328 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3329 cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
3330 else
3331 close_complete = 1;
3332 }
3333 break;
3334 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3335 cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
3336 break;
3337 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3338 close_complete = 1;
3339 break;
3340 }
3341 if (cmd) {
3342 memset(&l5_data, 0, sizeof(l5_data));
3343
3344 cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
3345 &l5_data);
3346 } else if (close_complete) {
3347 ctx->timestamp = jiffies;
3348 cnic_close_conn(csk);
3349 cnic_cm_upcall(cp, csk, csk->state);
3350 }
3351 }
3352
3353 static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
3354 {
3355 struct cnic_local *cp = dev->cnic_priv;
3356 int i;
3357
3358 if (!cp->ctx_tbl)
3359 return;
3360
3361 if (!netif_running(dev->netdev))
3362 return;
3363
3364 for (i = 0; i < cp->max_cid_space; i++) {
3365 struct cnic_context *ctx = &cp->ctx_tbl[i];
3366
3367 while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3368 msleep(10);
3369
3370 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3371 netdev_warn(dev->netdev, "CID %x not deleted\n",
3372 ctx->cid);
3373 }
3374
3375 cancel_delayed_work(&cp->delete_task);
3376 flush_workqueue(cnic_wq);
3377
3378 if (atomic_read(&cp->iscsi_conn) != 0)
3379 netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
3380 atomic_read(&cp->iscsi_conn));
3381 }
3382
3383 static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
3384 {
3385 struct cnic_local *cp = dev->cnic_priv;
3386 u32 pfid = cp->pfid;
3387 u32 port = CNIC_PORT(cp);
3388
3389 cnic_init_bnx2x_mac(dev);
3390 cnic_bnx2x_set_tcp_timestamp(dev, 1);
3391
3392 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
3393 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
3394
3395 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3396 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
3397 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3398 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
3399 DEF_MAX_DA_COUNT);
3400
3401 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3402 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
3403 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3404 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
3405 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3406 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
3407 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3408 XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
3409
3410 CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
3411 DEF_MAX_CWND);
3412 return 0;
3413 }
3414
3415 static void cnic_delete_task(struct work_struct *work)
3416 {
3417 struct cnic_local *cp;
3418 struct cnic_dev *dev;
3419 u32 i;
3420 int need_resched = 0;
3421
3422 cp = container_of(work, struct cnic_local, delete_task.work);
3423 dev = cp->dev;
3424
3425 for (i = 0; i < cp->max_cid_space; i++) {
3426 struct cnic_context *ctx = &cp->ctx_tbl[i];
3427
3428 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
3429 !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3430 continue;
3431
3432 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
3433 need_resched = 1;
3434 continue;
3435 }
3436
3437 if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3438 continue;
3439
3440 cnic_bnx2x_destroy_ramrod(dev, i);
3441
3442 cnic_free_bnx2x_conn_resc(dev, i);
3443 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
3444 atomic_dec(&cp->iscsi_conn);
3445
3446 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
3447 }
3448
3449 if (need_resched)
3450 queue_delayed_work(cnic_wq, &cp->delete_task,
3451 msecs_to_jiffies(10));
3452
3453 }
3454
3455 static int cnic_cm_open(struct cnic_dev *dev)
3456 {
3457 struct cnic_local *cp = dev->cnic_priv;
3458 int err;
3459
3460 err = cnic_cm_alloc_mem(dev);
3461 if (err)
3462 return err;
3463
3464 err = cp->start_cm(dev);
3465
3466 if (err)
3467 goto err_out;
3468
3469 INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
3470
3471 dev->cm_create = cnic_cm_create;
3472 dev->cm_destroy = cnic_cm_destroy;
3473 dev->cm_connect = cnic_cm_connect;
3474 dev->cm_abort = cnic_cm_abort;
3475 dev->cm_close = cnic_cm_close;
3476 dev->cm_select_dev = cnic_cm_select_dev;
3477
3478 cp->ulp_handle[CNIC_ULP_L4] = dev;
3479 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
3480 return 0;
3481
3482 err_out:
3483 cnic_cm_free_mem(dev);
3484 return err;
3485 }
3486
3487 static int cnic_cm_shutdown(struct cnic_dev *dev)
3488 {
3489 struct cnic_local *cp = dev->cnic_priv;
3490 int i;
3491
3492 cp->stop_cm(dev);
3493
3494 if (!cp->csk_tbl)
3495 return 0;
3496
3497 for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
3498 struct cnic_sock *csk = &cp->csk_tbl[i];
3499
3500 clear_bit(SK_F_INUSE, &csk->flags);
3501 cnic_cm_cleanup(csk);
3502 }
3503 cnic_cm_free_mem(dev);
3504
3505 return 0;
3506 }
3507
3508 static void cnic_init_context(struct cnic_dev *dev, u32 cid)
3509 {
3510 u32 cid_addr;
3511 int i;
3512
3513 cid_addr = GET_CID_ADDR(cid);
3514
3515 for (i = 0; i < CTX_SIZE; i += 4)
3516 cnic_ctx_wr(dev, cid_addr, i, 0);
3517 }
3518
3519 static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
3520 {
3521 struct cnic_local *cp = dev->cnic_priv;
3522 int ret = 0, i;
3523 u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
3524
3525 if (CHIP_NUM(cp) != CHIP_NUM_5709)
3526 return 0;
3527
3528 for (i = 0; i < cp->ctx_blks; i++) {
3529 int j;
3530 u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
3531 u32 val;
3532
3533 memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
3534
3535 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
3536 (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
3537 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
3538 (u64) cp->ctx_arr[i].mapping >> 32);
3539 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
3540 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3541 for (j = 0; j < 10; j++) {
3542
3543 val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
3544 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
3545 break;
3546 udelay(5);
3547 }
3548 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
3549 ret = -EBUSY;
3550 break;
3551 }
3552 }
3553 return ret;
3554 }
3555
3556 static void cnic_free_irq(struct cnic_dev *dev)
3557 {
3558 struct cnic_local *cp = dev->cnic_priv;
3559 struct cnic_eth_dev *ethdev = cp->ethdev;
3560
3561 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3562 cp->disable_int_sync(dev);
3563 tasklet_kill(&cp->cnic_irq_task);
3564 free_irq(ethdev->irq_arr[0].vector, dev);
3565 }
3566 }
3567
3568 static int cnic_request_irq(struct cnic_dev *dev)
3569 {
3570 struct cnic_local *cp = dev->cnic_priv;
3571 struct cnic_eth_dev *ethdev = cp->ethdev;
3572 int err;
3573
3574 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
3575 if (err)
3576 tasklet_disable(&cp->cnic_irq_task);
3577
3578 return err;
3579 }
3580
3581 static int cnic_init_bnx2_irq(struct cnic_dev *dev)
3582 {
3583 struct cnic_local *cp = dev->cnic_priv;
3584 struct cnic_eth_dev *ethdev = cp->ethdev;
3585
3586 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3587 int err, i = 0;
3588 int sblk_num = cp->status_blk_num;
3589 u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
3590 BNX2_HC_SB_CONFIG_1;
3591
3592 CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
3593
3594 CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
3595 CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
3596 CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
3597
3598 cp->last_status_idx = cp->status_blk.bnx2->status_idx;
3599 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
3600 (unsigned long) dev);
3601 err = cnic_request_irq(dev);
3602 if (err)
3603 return err;
3604
3605 while (cp->status_blk.bnx2->status_completion_producer_index &&
3606 i < 10) {
3607 CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
3608 1 << (11 + sblk_num));
3609 udelay(10);
3610 i++;
3611 barrier();
3612 }
3613 if (cp->status_blk.bnx2->status_completion_producer_index) {
3614 cnic_free_irq(dev);
3615 goto failed;
3616 }
3617
3618 } else {
3619 struct status_block *sblk = cp->status_blk.gen;
3620 u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
3621 int i = 0;
3622
3623 while (sblk->status_completion_producer_index && i < 10) {
3624 CNIC_WR(dev, BNX2_HC_COMMAND,
3625 hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3626 udelay(10);
3627 i++;
3628 barrier();
3629 }
3630 if (sblk->status_completion_producer_index)
3631 goto failed;
3632
3633 }
3634 return 0;
3635
3636 failed:
3637 netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
3638 return -EBUSY;
3639 }
3640
3641 static void cnic_enable_bnx2_int(struct cnic_dev *dev)
3642 {
3643 struct cnic_local *cp = dev->cnic_priv;
3644 struct cnic_eth_dev *ethdev = cp->ethdev;
3645
3646 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3647 return;
3648
3649 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3650 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
3651 }
3652
3653 static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
3654 {
3655 struct cnic_local *cp = dev->cnic_priv;
3656 struct cnic_eth_dev *ethdev = cp->ethdev;
3657
3658 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3659 return;
3660
3661 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3662 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3663 CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
3664 synchronize_irq(ethdev->irq_arr[0].vector);
3665 }
3666
3667 static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
3668 {
3669 struct cnic_local *cp = dev->cnic_priv;
3670 struct cnic_eth_dev *ethdev = cp->ethdev;
3671 struct cnic_uio_dev *udev = cp->udev;
3672 u32 cid_addr, tx_cid, sb_id;
3673 u32 val, offset0, offset1, offset2, offset3;
3674 int i;
3675 struct tx_bd *txbd;
3676 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
3677 struct status_block *s_blk = cp->status_blk.gen;
3678
3679 sb_id = cp->status_blk_num;
3680 tx_cid = 20;
3681 cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
3682 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3683 struct status_block_msix *sblk = cp->status_blk.bnx2;
3684
3685 tx_cid = TX_TSS_CID + sb_id - 1;
3686 CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
3687 (TX_TSS_CID << 7));
3688 cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
3689 }
3690 cp->tx_cons = *cp->tx_cons_ptr;
3691
3692 cid_addr = GET_CID_ADDR(tx_cid);
3693 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
3694 u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
3695
3696 for (i = 0; i < PHY_CTX_SIZE; i += 4)
3697 cnic_ctx_wr(dev, cid_addr2, i, 0);
3698
3699 offset0 = BNX2_L2CTX_TYPE_XI;
3700 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
3701 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
3702 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
3703 } else {
3704 cnic_init_context(dev, tx_cid);
3705 cnic_init_context(dev, tx_cid + 1);
3706
3707 offset0 = BNX2_L2CTX_TYPE;
3708 offset1 = BNX2_L2CTX_CMD_TYPE;
3709 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
3710 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
3711 }
3712 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
3713 cnic_ctx_wr(dev, cid_addr, offset0, val);
3714
3715 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3716 cnic_ctx_wr(dev, cid_addr, offset1, val);
3717
3718 txbd = (struct tx_bd *) udev->l2_ring;
3719
3720 buf_map = udev->l2_buf_map;
3721 for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
3722 txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
3723 txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
3724 }
3725 val = (u64) ring_map >> 32;
3726 cnic_ctx_wr(dev, cid_addr, offset2, val);
3727 txbd->tx_bd_haddr_hi = val;
3728
3729 val = (u64) ring_map & 0xffffffff;
3730 cnic_ctx_wr(dev, cid_addr, offset3, val);
3731 txbd->tx_bd_haddr_lo = val;
3732 }
3733
3734 static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
3735 {
3736 struct cnic_local *cp = dev->cnic_priv;
3737 struct cnic_eth_dev *ethdev = cp->ethdev;
3738 struct cnic_uio_dev *udev = cp->udev;
3739 u32 cid_addr, sb_id, val, coal_reg, coal_val;
3740 int i;
3741 struct rx_bd *rxbd;
3742 struct status_block *s_blk = cp->status_blk.gen;
3743 dma_addr_t ring_map = udev->l2_ring_map;
3744
3745 sb_id = cp->status_blk_num;
3746 cnic_init_context(dev, 2);
3747 cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
3748 coal_reg = BNX2_HC_COMMAND;
3749 coal_val = CNIC_RD(dev, coal_reg);
3750 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3751 struct status_block_msix *sblk = cp->status_blk.bnx2;
3752
3753 cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
3754 coal_reg = BNX2_HC_COALESCE_NOW;
3755 coal_val = 1 << (11 + sb_id);
3756 }
3757 i = 0;
3758 while (!(*cp->rx_cons_ptr != 0) && i < 10) {
3759 CNIC_WR(dev, coal_reg, coal_val);
3760 udelay(10);
3761 i++;
3762 barrier();
3763 }
3764 cp->rx_cons = *cp->rx_cons_ptr;
3765
3766 cid_addr = GET_CID_ADDR(2);
3767 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3768 BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3769 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
3770
3771 if (sb_id == 0)
3772 val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
3773 else
3774 val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
3775 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
3776
3777 rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
3778 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3779 dma_addr_t buf_map;
3780 int n = (i % cp->l2_rx_ring_size) + 1;
3781
3782 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
3783 rxbd->rx_bd_len = cp->l2_single_buf_size;
3784 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3785 rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
3786 rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
3787 }
3788 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
3789 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
3790 rxbd->rx_bd_haddr_hi = val;
3791
3792 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
3793 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
3794 rxbd->rx_bd_haddr_lo = val;
3795
3796 val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
3797 cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
3798 }
3799
3800 static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
3801 {
3802 struct kwqe *wqes[1], l2kwqe;
3803
3804 memset(&l2kwqe, 0, sizeof(l2kwqe));
3805 wqes[0] = &l2kwqe;
3806 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
3807 (L2_KWQE_OPCODE_VALUE_FLUSH <<
3808 KWQE_OPCODE_SHIFT) | 2;
3809 dev->submit_kwqes(dev, wqes, 1);
3810 }
3811
3812 static void cnic_set_bnx2_mac(struct cnic_dev *dev)
3813 {
3814 struct cnic_local *cp = dev->cnic_priv;
3815 u32 val;
3816
3817 val = cp->func << 2;
3818
3819 cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
3820
3821 val = cnic_reg_rd_ind(dev, cp->shmem_base +
3822 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
3823 dev->mac_addr[0] = (u8) (val >> 8);
3824 dev->mac_addr[1] = (u8) val;
3825
3826 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
3827
3828 val = cnic_reg_rd_ind(dev, cp->shmem_base +
3829 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
3830 dev->mac_addr[2] = (u8) (val >> 24);
3831 dev->mac_addr[3] = (u8) (val >> 16);
3832 dev->mac_addr[4] = (u8) (val >> 8);
3833 dev->mac_addr[5] = (u8) val;
3834
3835 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
3836
3837 val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
3838 if (CHIP_NUM(cp) != CHIP_NUM_5709)
3839 val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
3840
3841 CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
3842 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
3843 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
3844 }
3845
3846 static int cnic_start_bnx2_hw(struct cnic_dev *dev)
3847 {
3848 struct cnic_local *cp = dev->cnic_priv;
3849 struct cnic_eth_dev *ethdev = cp->ethdev;
3850 struct status_block *sblk = cp->status_blk.gen;
3851 u32 val, kcq_cid_addr, kwq_cid_addr;
3852 int err;
3853
3854 cnic_set_bnx2_mac(dev);
3855
3856 val = CNIC_RD(dev, BNX2_MQ_CONFIG);
3857 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3858 if (BCM_PAGE_BITS > 12)
3859 val |= (12 - 8) << 4;
3860 else
3861 val |= (BCM_PAGE_BITS - 8) << 4;
3862
3863 CNIC_WR(dev, BNX2_MQ_CONFIG, val);
3864
3865 CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
3866 CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
3867 CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
3868
3869 err = cnic_setup_5709_context(dev, 1);
3870 if (err)
3871 return err;
3872
3873 cnic_init_context(dev, KWQ_CID);
3874 cnic_init_context(dev, KCQ_CID);
3875
3876 kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
3877 cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
3878
3879 cp->max_kwq_idx = MAX_KWQ_IDX;
3880 cp->kwq_prod_idx = 0;
3881 cp->kwq_con_idx = 0;
3882 set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
3883
3884 if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
3885 cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
3886 else
3887 cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
3888
3889 /* Initialize the kernel work queue context. */
3890 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
3891 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
3892 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
3893
3894 val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
3895 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
3896
3897 val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
3898 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
3899
3900 val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
3901 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
3902
3903 val = (u32) cp->kwq_info.pgtbl_map;
3904 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
3905
3906 kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
3907 cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
3908
3909 cp->kcq1.sw_prod_idx = 0;
3910 cp->kcq1.hw_prod_idx_ptr =
3911 (u16 *) &sblk->status_completion_producer_index;
3912
3913 cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
3914
3915 /* Initialize the kernel complete queue context. */
3916 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
3917 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
3918 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
3919
3920 val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
3921 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
3922
3923 val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
3924 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
3925
3926 val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
3927 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
3928
3929 val = (u32) cp->kcq1.dma.pgtbl_map;
3930 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
3931
3932 cp->int_num = 0;
3933 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3934 struct status_block_msix *msblk = cp->status_blk.bnx2;
3935 u32 sb_id = cp->status_blk_num;
3936 u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
3937
3938 cp->kcq1.hw_prod_idx_ptr =
3939 (u16 *) &msblk->status_completion_producer_index;
3940 cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
3941 cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
3942 cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
3943 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
3944 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
3945 }
3946
3947 /* Enable Commnad Scheduler notification when we write to the
3948 * host producer index of the kernel contexts. */
3949 CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
3950
3951 /* Enable Command Scheduler notification when we write to either
3952 * the Send Queue or Receive Queue producer indexes of the kernel
3953 * bypass contexts. */
3954 CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
3955 CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
3956
3957 /* Notify COM when the driver post an application buffer. */
3958 CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
3959
3960 /* Set the CP and COM doorbells. These two processors polls the
3961 * doorbell for a non zero value before running. This must be done
3962 * after setting up the kernel queue contexts. */
3963 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
3964 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
3965
3966 cnic_init_bnx2_tx_ring(dev);
3967 cnic_init_bnx2_rx_ring(dev);
3968
3969 err = cnic_init_bnx2_irq(dev);
3970 if (err) {
3971 netdev_err(dev->netdev, "cnic_init_irq failed\n");
3972 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
3973 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
3974 return err;
3975 }
3976
3977 return 0;
3978 }
3979
3980 static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
3981 {
3982 struct cnic_local *cp = dev->cnic_priv;
3983 struct cnic_eth_dev *ethdev = cp->ethdev;
3984 u32 start_offset = ethdev->ctx_tbl_offset;
3985 int i;
3986
3987 for (i = 0; i < cp->ctx_blks; i++) {
3988 struct cnic_ctx *ctx = &cp->ctx_arr[i];
3989 dma_addr_t map = ctx->mapping;
3990
3991 if (cp->ctx_align) {
3992 unsigned long mask = cp->ctx_align - 1;
3993
3994 map = (map + mask) & ~mask;
3995 }
3996
3997 cnic_ctx_tbl_wr(dev, start_offset + i, map);
3998 }
3999 }
4000
4001 static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
4002 {
4003 struct cnic_local *cp = dev->cnic_priv;
4004 struct cnic_eth_dev *ethdev = cp->ethdev;
4005 int err = 0;
4006
4007 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
4008 (unsigned long) dev);
4009 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
4010 err = cnic_request_irq(dev);
4011
4012 return err;
4013 }
4014
4015 static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
4016 u16 sb_id, u8 sb_index,
4017 u8 disable)
4018 {
4019
4020 u32 addr = BAR_CSTRORM_INTMEM +
4021 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4022 offsetof(struct hc_status_block_data_e1x, index_data) +
4023 sizeof(struct hc_index_data)*sb_index +
4024 offsetof(struct hc_index_data, flags);
4025 u16 flags = CNIC_RD16(dev, addr);
4026 /* clear and set */
4027 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4028 flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
4029 HC_INDEX_DATA_HC_ENABLED);
4030 CNIC_WR16(dev, addr, flags);
4031 }
4032
4033 static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
4034 {
4035 struct cnic_local *cp = dev->cnic_priv;
4036 u8 sb_id = cp->status_blk_num;
4037
4038 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4039 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4040 offsetof(struct hc_status_block_data_e1x, index_data) +
4041 sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
4042 offsetof(struct hc_index_data, timeout), 64 / 12);
4043 cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
4044 }
4045
4046 static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
4047 {
4048 }
4049
4050 static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
4051 struct client_init_ramrod_data *data)
4052 {
4053 struct cnic_local *cp = dev->cnic_priv;
4054 struct cnic_uio_dev *udev = cp->udev;
4055 union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
4056 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4057 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4058 int port = CNIC_PORT(cp);
4059 int i;
4060 int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
4061 u32 val;
4062
4063 memset(txbd, 0, BCM_PAGE_SIZE);
4064
4065 buf_map = udev->l2_buf_map;
4066 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
4067 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
4068 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
4069
4070 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4071 start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4072 reg_bd->addr_hi = start_bd->addr_hi;
4073 reg_bd->addr_lo = start_bd->addr_lo + 0x10;
4074 start_bd->nbytes = cpu_to_le16(0x10);
4075 start_bd->nbd = cpu_to_le16(3);
4076 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
4077 start_bd->general_data = (UNICAST_ADDRESS <<
4078 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
4079 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
4080
4081 }
4082
4083 val = (u64) ring_map >> 32;
4084 txbd->next_bd.addr_hi = cpu_to_le32(val);
4085
4086 data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
4087
4088 val = (u64) ring_map & 0xffffffff;
4089 txbd->next_bd.addr_lo = cpu_to_le32(val);
4090
4091 data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
4092
4093 /* Other ramrod params */
4094 data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
4095 data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
4096
4097 /* reset xstorm per client statistics */
4098 if (cli < MAX_STAT_COUNTER_ID) {
4099 val = BAR_XSTRORM_INTMEM +
4100 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4101 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
4102 CNIC_WR(dev, val + i * 4, 0);
4103 }
4104
4105 cp->tx_cons_ptr =
4106 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
4107 }
4108
4109 static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
4110 struct client_init_ramrod_data *data)
4111 {
4112 struct cnic_local *cp = dev->cnic_priv;
4113 struct cnic_uio_dev *udev = cp->udev;
4114 struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
4115 BCM_PAGE_SIZE);
4116 struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
4117 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
4118 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4119 int i;
4120 int port = CNIC_PORT(cp);
4121 int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
4122 int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4123 u32 val;
4124 dma_addr_t ring_map = udev->l2_ring_map;
4125
4126 /* General data */
4127 data->general.client_id = cli;
4128 data->general.statistics_en_flg = 1;
4129 data->general.statistics_counter_id = cli;
4130 data->general.activate_flg = 1;
4131 data->general.sp_client_id = cli;
4132
4133 for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
4134 dma_addr_t buf_map;
4135 int n = (i % cp->l2_rx_ring_size) + 1;
4136
4137 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4138 rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4139 rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4140 }
4141
4142 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4143 rxbd->addr_hi = cpu_to_le32(val);
4144 data->rx.bd_page_base.hi = cpu_to_le32(val);
4145
4146 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4147 rxbd->addr_lo = cpu_to_le32(val);
4148 data->rx.bd_page_base.lo = cpu_to_le32(val);
4149
4150 rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
4151 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
4152 rxcqe->addr_hi = cpu_to_le32(val);
4153 data->rx.cqe_page_base.hi = cpu_to_le32(val);
4154
4155 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
4156 rxcqe->addr_lo = cpu_to_le32(val);
4157 data->rx.cqe_page_base.lo = cpu_to_le32(val);
4158
4159 /* Other ramrod params */
4160 data->rx.client_qzone_id = cl_qzone_id;
4161 data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
4162 data->rx.status_block_id = BNX2X_DEF_SB_ID;
4163
4164 data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
4165 data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
4166
4167 data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
4168 data->rx.outer_vlan_removal_enable_flg = 1;
4169
4170 /* reset tstorm and ustorm per client statistics */
4171 if (cli < MAX_STAT_COUNTER_ID) {
4172 val = BAR_TSTRORM_INTMEM +
4173 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4174 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
4175 CNIC_WR(dev, val + i * 4, 0);
4176
4177 val = BAR_USTRORM_INTMEM +
4178 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4179 for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
4180 CNIC_WR(dev, val + i * 4, 0);
4181 }
4182
4183 cp->rx_cons_ptr =
4184 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
4185 }
4186
4187 static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
4188 {
4189 struct cnic_local *cp = dev->cnic_priv;
4190 u32 base, addr, val;
4191 int port = CNIC_PORT(cp);
4192
4193 dev->max_iscsi_conn = 0;
4194 base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
4195 if (base == 0)
4196 return;
4197
4198 addr = BNX2X_SHMEM_ADDR(base,
4199 dev_info.port_hw_config[port].iscsi_mac_upper);
4200
4201 val = CNIC_RD(dev, addr);
4202
4203 dev->mac_addr[0] = (u8) (val >> 8);
4204 dev->mac_addr[1] = (u8) val;
4205
4206 addr = BNX2X_SHMEM_ADDR(base,
4207 dev_info.port_hw_config[port].iscsi_mac_lower);
4208
4209 val = CNIC_RD(dev, addr);
4210
4211 dev->mac_addr[2] = (u8) (val >> 24);
4212 dev->mac_addr[3] = (u8) (val >> 16);
4213 dev->mac_addr[4] = (u8) (val >> 8);
4214 dev->mac_addr[5] = (u8) val;
4215
4216 addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
4217 val = CNIC_RD(dev, addr);
4218
4219 if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
4220 u16 val16;
4221
4222 addr = BNX2X_SHMEM_ADDR(base,
4223 drv_lic_key[port].max_iscsi_init_conn);
4224 val16 = CNIC_RD16(dev, addr);
4225
4226 if (val16)
4227 val16 ^= 0x1e1e;
4228 dev->max_iscsi_conn = val16;
4229 }
4230 if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
4231 int func = CNIC_FUNC(cp);
4232 u32 mf_cfg_addr;
4233
4234 mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
4235
4236 addr = mf_cfg_addr +
4237 offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
4238
4239 val = CNIC_RD(dev, addr);
4240 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
4241 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
4242 addr = mf_cfg_addr +
4243 offsetof(struct mf_cfg,
4244 func_mf_config[func].config);
4245 val = CNIC_RD(dev, addr);
4246 val &= FUNC_MF_CFG_PROTOCOL_MASK;
4247 if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
4248 dev->max_iscsi_conn = 0;
4249 }
4250 }
4251 }
4252
4253 static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
4254 {
4255 struct cnic_local *cp = dev->cnic_priv;
4256 struct cnic_eth_dev *ethdev = cp->ethdev;
4257 int func = CNIC_FUNC(cp), ret, i;
4258 u32 pfid;
4259 struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
4260
4261 cp->pfid = func;
4262 pfid = cp->pfid;
4263
4264 ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
4265 cp->iscsi_start_cid);
4266
4267 if (ret)
4268 return -ENOMEM;
4269
4270 cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
4271
4272 cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
4273 CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
4274 cp->kcq1.sw_prod_idx = 0;
4275
4276 cp->kcq1.hw_prod_idx_ptr =
4277 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4278 cp->kcq1.status_idx_ptr =
4279 &sb->sb.running_index[SM_RX_ID];
4280
4281 cnic_get_bnx2x_iscsi_info(dev);
4282
4283 /* Only 1 EQ */
4284 CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
4285 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4286 CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
4287 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4288 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
4289 cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
4290 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4291 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
4292 (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
4293 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4294 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
4295 cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
4296 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4297 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
4298 (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
4299 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4300 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
4301 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
4302 CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
4303 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4304 CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
4305 HC_INDEX_ISCSI_EQ_CONS);
4306
4307 for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
4308 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4309 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
4310 cp->conn_buf_info.pgtbl[2 * i]);
4311 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4312 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
4313 cp->conn_buf_info.pgtbl[(2 * i) + 1]);
4314 }
4315
4316 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4317 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
4318 cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
4319 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4320 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
4321 (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
4322
4323 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4324 TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
4325
4326 cnic_setup_bnx2x_context(dev);
4327
4328 ret = cnic_init_bnx2x_irq(dev);
4329 if (ret)
4330 return ret;
4331
4332 return 0;
4333 }
4334
4335 static void cnic_init_rings(struct cnic_dev *dev)
4336 {
4337 struct cnic_local *cp = dev->cnic_priv;
4338 struct cnic_uio_dev *udev = cp->udev;
4339
4340 if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4341 return;
4342
4343 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4344 cnic_init_bnx2_tx_ring(dev);
4345 cnic_init_bnx2_rx_ring(dev);
4346 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4347 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4348 u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
4349 u32 cl_qzone_id, type;
4350 struct client_init_ramrod_data *data;
4351 union l5cm_specific_data l5_data;
4352 struct ustorm_eth_rx_producers rx_prods = {0};
4353 u32 off, i;
4354
4355 rx_prods.bd_prod = 0;
4356 rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
4357 barrier();
4358
4359 cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4360
4361 off = BAR_USTRORM_INTMEM +
4362 USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli);
4363
4364 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
4365 CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
4366
4367 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4368
4369 data = udev->l2_buf;
4370
4371 memset(data, 0, sizeof(*data));
4372
4373 cnic_init_bnx2x_tx_ring(dev, data);
4374 cnic_init_bnx2x_rx_ring(dev, data);
4375
4376 l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
4377 l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
4378
4379 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
4380 & SPE_HDR_CONN_TYPE;
4381 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
4382 SPE_HDR_FUNCTION_ID);
4383
4384 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4385
4386 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4387 BNX2X_ISCSI_L2_CID, type, &l5_data);
4388
4389 i = 0;
4390 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4391 ++i < 10)
4392 msleep(1);
4393
4394 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4395 netdev_err(dev->netdev,
4396 "iSCSI CLIENT_SETUP did not complete\n");
4397 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
4398 cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
4399 }
4400 }
4401
4402 static void cnic_shutdown_rings(struct cnic_dev *dev)
4403 {
4404 struct cnic_local *cp = dev->cnic_priv;
4405
4406 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4407 return;
4408
4409 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4410 cnic_shutdown_bnx2_rx_ring(dev);
4411 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4412 struct cnic_local *cp = dev->cnic_priv;
4413 u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
4414 union l5cm_specific_data l5_data;
4415 int i;
4416 u32 type;
4417
4418 cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
4419
4420 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4421
4422 l5_data.phy_address.lo = cli;
4423 l5_data.phy_address.hi = 0;
4424 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
4425 BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
4426 i = 0;
4427 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4428 ++i < 10)
4429 msleep(1);
4430
4431 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4432 netdev_err(dev->netdev,
4433 "iSCSI CLIENT_HALT did not complete\n");
4434 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
4435
4436 memset(&l5_data, 0, sizeof(l5_data));
4437 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
4438 & SPE_HDR_CONN_TYPE;
4439 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
4440 SPE_HDR_FUNCTION_ID);
4441 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
4442 BNX2X_ISCSI_L2_CID, type, &l5_data);
4443 msleep(10);
4444 }
4445 clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4446 }
4447
4448 static int cnic_register_netdev(struct cnic_dev *dev)
4449 {
4450 struct cnic_local *cp = dev->cnic_priv;
4451 struct cnic_eth_dev *ethdev = cp->ethdev;
4452 int err;
4453
4454 if (!ethdev)
4455 return -ENODEV;
4456
4457 if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
4458 return 0;
4459
4460 err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
4461 if (err)
4462 netdev_err(dev->netdev, "register_cnic failed\n");
4463
4464 return err;
4465 }
4466
4467 static void cnic_unregister_netdev(struct cnic_dev *dev)
4468 {
4469 struct cnic_local *cp = dev->cnic_priv;
4470 struct cnic_eth_dev *ethdev = cp->ethdev;
4471
4472 if (!ethdev)
4473 return;
4474
4475 ethdev->drv_unregister_cnic(dev->netdev);
4476 }
4477
4478 static int cnic_start_hw(struct cnic_dev *dev)
4479 {
4480 struct cnic_local *cp = dev->cnic_priv;
4481 struct cnic_eth_dev *ethdev = cp->ethdev;
4482 int err;
4483
4484 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
4485 return -EALREADY;
4486
4487 dev->regview = ethdev->io_base;
4488 cp->chip_id = ethdev->chip_id;
4489 pci_dev_get(dev->pcidev);
4490 cp->func = PCI_FUNC(dev->pcidev->devfn);
4491 cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
4492 cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
4493
4494 err = cp->alloc_resc(dev);
4495 if (err) {
4496 netdev_err(dev->netdev, "allocate resource failure\n");
4497 goto err1;
4498 }
4499
4500 err = cp->start_hw(dev);
4501 if (err)
4502 goto err1;
4503
4504 err = cnic_cm_open(dev);
4505 if (err)
4506 goto err1;
4507
4508 set_bit(CNIC_F_CNIC_UP, &dev->flags);
4509
4510 cp->enable_int(dev);
4511
4512 return 0;
4513
4514 err1:
4515 cp->free_resc(dev);
4516 pci_dev_put(dev->pcidev);
4517 return err;
4518 }
4519
4520 static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
4521 {
4522 cnic_disable_bnx2_int_sync(dev);
4523
4524 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4525 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4526
4527 cnic_init_context(dev, KWQ_CID);
4528 cnic_init_context(dev, KCQ_CID);
4529
4530 cnic_setup_5709_context(dev, 0);
4531 cnic_free_irq(dev);
4532
4533 cnic_free_resc(dev);
4534 }
4535
4536
4537 static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
4538 {
4539 struct cnic_local *cp = dev->cnic_priv;
4540
4541 cnic_free_irq(dev);
4542 *cp->kcq1.hw_prod_idx_ptr = 0;
4543 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4544 CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
4545 CNIC_WR16(dev, cp->kcq1.io_addr, 0);
4546 cnic_free_resc(dev);
4547 }
4548
4549 static void cnic_stop_hw(struct cnic_dev *dev)
4550 {
4551 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
4552 struct cnic_local *cp = dev->cnic_priv;
4553 int i = 0;
4554
4555 /* Need to wait for the ring shutdown event to complete
4556 * before clearing the CNIC_UP flag.
4557 */
4558 while (cp->udev->uio_dev != -1 && i < 15) {
4559 msleep(100);
4560 i++;
4561 }
4562 clear_bit(CNIC_F_CNIC_UP, &dev->flags);
4563 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
4564 synchronize_rcu();
4565 cnic_cm_shutdown(dev);
4566 cp->stop_hw(dev);
4567 pci_dev_put(dev->pcidev);
4568 }
4569 }
4570
4571 static void cnic_free_dev(struct cnic_dev *dev)
4572 {
4573 int i = 0;
4574
4575 while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
4576 msleep(100);
4577 i++;
4578 }
4579 if (atomic_read(&dev->ref_count) != 0)
4580 netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
4581
4582 netdev_info(dev->netdev, "Removed CNIC device\n");
4583 dev_put(dev->netdev);
4584 kfree(dev);
4585 }
4586
4587 static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
4588 struct pci_dev *pdev)
4589 {
4590 struct cnic_dev *cdev;
4591 struct cnic_local *cp;
4592 int alloc_size;
4593
4594 alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
4595
4596 cdev = kzalloc(alloc_size , GFP_KERNEL);
4597 if (cdev == NULL) {
4598 netdev_err(dev, "allocate dev struct failure\n");
4599 return NULL;
4600 }
4601
4602 cdev->netdev = dev;
4603 cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
4604 cdev->register_device = cnic_register_device;
4605 cdev->unregister_device = cnic_unregister_device;
4606 cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
4607
4608 cp = cdev->cnic_priv;
4609 cp->dev = cdev;
4610 cp->l2_single_buf_size = 0x400;
4611 cp->l2_rx_ring_size = 3;
4612
4613 spin_lock_init(&cp->cnic_ulp_lock);
4614
4615 netdev_info(dev, "Added CNIC device\n");
4616
4617 return cdev;
4618 }
4619
4620 static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
4621 {
4622 struct pci_dev *pdev;
4623 struct cnic_dev *cdev;
4624 struct cnic_local *cp;
4625 struct cnic_eth_dev *ethdev = NULL;
4626 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
4627
4628 probe = symbol_get(bnx2_cnic_probe);
4629 if (probe) {
4630 ethdev = (*probe)(dev);
4631 symbol_put(bnx2_cnic_probe);
4632 }
4633 if (!ethdev)
4634 return NULL;
4635
4636 pdev = ethdev->pdev;
4637 if (!pdev)
4638 return NULL;
4639
4640 dev_hold(dev);
4641 pci_dev_get(pdev);
4642 if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
4643 pdev->device == PCI_DEVICE_ID_NX2_5709S) {
4644 u8 rev;
4645
4646 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
4647 if (rev < 0x10) {
4648 pci_dev_put(pdev);
4649 goto cnic_err;
4650 }
4651 }
4652 pci_dev_put(pdev);
4653
4654 cdev = cnic_alloc_dev(dev, pdev);
4655 if (cdev == NULL)
4656 goto cnic_err;
4657
4658 set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
4659 cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
4660
4661 cp = cdev->cnic_priv;
4662 cp->ethdev = ethdev;
4663 cdev->pcidev = pdev;
4664
4665 cp->cnic_ops = &cnic_bnx2_ops;
4666 cp->start_hw = cnic_start_bnx2_hw;
4667 cp->stop_hw = cnic_stop_bnx2_hw;
4668 cp->setup_pgtbl = cnic_setup_page_tbl;
4669 cp->alloc_resc = cnic_alloc_bnx2_resc;
4670 cp->free_resc = cnic_free_resc;
4671 cp->start_cm = cnic_cm_init_bnx2_hw;
4672 cp->stop_cm = cnic_cm_stop_bnx2_hw;
4673 cp->enable_int = cnic_enable_bnx2_int;
4674 cp->disable_int_sync = cnic_disable_bnx2_int_sync;
4675 cp->close_conn = cnic_close_bnx2_conn;
4676 cp->next_idx = cnic_bnx2_next_idx;
4677 cp->hw_idx = cnic_bnx2_hw_idx;
4678 return cdev;
4679
4680 cnic_err:
4681 dev_put(dev);
4682 return NULL;
4683 }
4684
4685 static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
4686 {
4687 struct pci_dev *pdev;
4688 struct cnic_dev *cdev;
4689 struct cnic_local *cp;
4690 struct cnic_eth_dev *ethdev = NULL;
4691 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
4692
4693 probe = symbol_get(bnx2x_cnic_probe);
4694 if (probe) {
4695 ethdev = (*probe)(dev);
4696 symbol_put(bnx2x_cnic_probe);
4697 }
4698 if (!ethdev)
4699 return NULL;
4700
4701 pdev = ethdev->pdev;
4702 if (!pdev)
4703 return NULL;
4704
4705 dev_hold(dev);
4706 cdev = cnic_alloc_dev(dev, pdev);
4707 if (cdev == NULL) {
4708 dev_put(dev);
4709 return NULL;
4710 }
4711
4712 set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
4713 cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
4714
4715 cp = cdev->cnic_priv;
4716 cp->ethdev = ethdev;
4717 cdev->pcidev = pdev;
4718
4719 cp->cnic_ops = &cnic_bnx2x_ops;
4720 cp->start_hw = cnic_start_bnx2x_hw;
4721 cp->stop_hw = cnic_stop_bnx2x_hw;
4722 cp->setup_pgtbl = cnic_setup_page_tbl_le;
4723 cp->alloc_resc = cnic_alloc_bnx2x_resc;
4724 cp->free_resc = cnic_free_resc;
4725 cp->start_cm = cnic_cm_init_bnx2x_hw;
4726 cp->stop_cm = cnic_cm_stop_bnx2x_hw;
4727 cp->enable_int = cnic_enable_bnx2x_int;
4728 cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
4729 cp->ack_int = cnic_ack_bnx2x_msix;
4730 cp->close_conn = cnic_close_bnx2x_conn;
4731 cp->next_idx = cnic_bnx2x_next_idx;
4732 cp->hw_idx = cnic_bnx2x_hw_idx;
4733 return cdev;
4734 }
4735
4736 static struct cnic_dev *is_cnic_dev(struct net_device *dev)
4737 {
4738 struct ethtool_drvinfo drvinfo;
4739 struct cnic_dev *cdev = NULL;
4740
4741 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
4742 memset(&drvinfo, 0, sizeof(drvinfo));
4743 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
4744
4745 if (!strcmp(drvinfo.driver, "bnx2"))
4746 cdev = init_bnx2_cnic(dev);
4747 if (!strcmp(drvinfo.driver, "bnx2x"))
4748 cdev = init_bnx2x_cnic(dev);
4749 if (cdev) {
4750 write_lock(&cnic_dev_lock);
4751 list_add(&cdev->list, &cnic_dev_list);
4752 write_unlock(&cnic_dev_lock);
4753 }
4754 }
4755 return cdev;
4756 }
4757
4758 /**
4759 * netdev event handler
4760 */
4761 static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
4762 void *ptr)
4763 {
4764 struct net_device *netdev = ptr;
4765 struct cnic_dev *dev;
4766 int if_type;
4767 int new_dev = 0;
4768
4769 dev = cnic_from_netdev(netdev);
4770
4771 if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
4772 /* Check for the hot-plug device */
4773 dev = is_cnic_dev(netdev);
4774 if (dev) {
4775 new_dev = 1;
4776 cnic_hold(dev);
4777 }
4778 }
4779 if (dev) {
4780 struct cnic_local *cp = dev->cnic_priv;
4781
4782 if (new_dev)
4783 cnic_ulp_init(dev);
4784 else if (event == NETDEV_UNREGISTER)
4785 cnic_ulp_exit(dev);
4786
4787 if (event == NETDEV_UP) {
4788 if (cnic_register_netdev(dev) != 0) {
4789 cnic_put(dev);
4790 goto done;
4791 }
4792 if (!cnic_start_hw(dev))
4793 cnic_ulp_start(dev);
4794 }
4795
4796 rcu_read_lock();
4797 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
4798 struct cnic_ulp_ops *ulp_ops;
4799 void *ctx;
4800
4801 ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
4802 if (!ulp_ops || !ulp_ops->indicate_netevent)
4803 continue;
4804
4805 ctx = cp->ulp_handle[if_type];
4806
4807 ulp_ops->indicate_netevent(ctx, event);
4808 }
4809 rcu_read_unlock();
4810
4811 if (event == NETDEV_GOING_DOWN) {
4812 cnic_ulp_stop(dev);
4813 cnic_stop_hw(dev);
4814 cnic_unregister_netdev(dev);
4815 } else if (event == NETDEV_UNREGISTER) {
4816 write_lock(&cnic_dev_lock);
4817 list_del_init(&dev->list);
4818 write_unlock(&cnic_dev_lock);
4819
4820 cnic_put(dev);
4821 cnic_free_dev(dev);
4822 goto done;
4823 }
4824 cnic_put(dev);
4825 }
4826 done:
4827 return NOTIFY_DONE;
4828 }
4829
4830 static struct notifier_block cnic_netdev_notifier = {
4831 .notifier_call = cnic_netdev_event
4832 };
4833
4834 static void cnic_release(void)
4835 {
4836 struct cnic_dev *dev;
4837
4838 while (!list_empty(&cnic_dev_list)) {
4839 dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
4840 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
4841 cnic_ulp_stop(dev);
4842 cnic_stop_hw(dev);
4843 }
4844
4845 cnic_ulp_exit(dev);
4846 cnic_unregister_netdev(dev);
4847 list_del_init(&dev->list);
4848 cnic_free_dev(dev);
4849 }
4850 }
4851
4852 static int __init cnic_init(void)
4853 {
4854 int rc = 0;
4855
4856 pr_info("%s", version);
4857
4858 rc = register_netdevice_notifier(&cnic_netdev_notifier);
4859 if (rc) {
4860 cnic_release();
4861 return rc;
4862 }
4863
4864 cnic_wq = create_singlethread_workqueue("cnic_wq");
4865 if (!cnic_wq) {
4866 cnic_release();
4867 unregister_netdevice_notifier(&cnic_netdev_notifier);
4868 return -ENOMEM;
4869 }
4870
4871 return 0;
4872 }
4873
4874 static void __exit cnic_exit(void)
4875 {
4876 unregister_netdevice_notifier(&cnic_netdev_notifier);
4877 cnic_release();
4878 destroy_workqueue(cnic_wq);
4879 }
4880
4881 module_init(cnic_init);
4882 module_exit(cnic_exit);
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