1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/etherdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/bitops.h>
19 #include <linux/mii.h>
21 #include <linux/if_ether.h>
22 #include <linux/if_vlan.h>
25 #include <linux/ipv6.h>
26 #include <linux/log2.h>
27 #include <linux/jiffies.h>
28 #include <linux/crc32.h>
29 #include <linux/list.h>
30 #include <linux/slab.h>
33 #include <linux/of_device.h>
37 #define DRV_MODULE_NAME "niu"
38 #define DRV_MODULE_VERSION "1.1"
39 #define DRV_MODULE_RELDATE "Apr 22, 2010"
41 static char version
[] =
42 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
44 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
45 MODULE_DESCRIPTION("NIU ethernet driver");
46 MODULE_LICENSE("GPL");
47 MODULE_VERSION(DRV_MODULE_VERSION
);
50 static u64
readq(void __iomem
*reg
)
52 return ((u64
) readl(reg
)) | (((u64
) readl(reg
+ 4UL)) << 32);
55 static void writeq(u64 val
, void __iomem
*reg
)
57 writel(val
& 0xffffffff, reg
);
58 writel(val
>> 32, reg
+ 0x4UL
);
62 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl
) = {
63 {PCI_DEVICE(PCI_VENDOR_ID_SUN
, 0xabcd)},
67 MODULE_DEVICE_TABLE(pci
, niu_pci_tbl
);
69 #define NIU_TX_TIMEOUT (5 * HZ)
71 #define nr64(reg) readq(np->regs + (reg))
72 #define nw64(reg, val) writeq((val), np->regs + (reg))
74 #define nr64_mac(reg) readq(np->mac_regs + (reg))
75 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
77 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
78 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
80 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
81 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
83 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
84 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
86 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
89 static int debug
= -1;
90 module_param(debug
, int, 0);
91 MODULE_PARM_DESC(debug
, "NIU debug level");
93 #define niu_lock_parent(np, flags) \
94 spin_lock_irqsave(&np->parent->lock, flags)
95 #define niu_unlock_parent(np, flags) \
96 spin_unlock_irqrestore(&np->parent->lock, flags)
98 static int serdes_init_10g_serdes(struct niu
*np
);
100 static int __niu_wait_bits_clear_mac(struct niu
*np
, unsigned long reg
,
101 u64 bits
, int limit
, int delay
)
103 while (--limit
>= 0) {
104 u64 val
= nr64_mac(reg
);
115 static int __niu_set_and_wait_clear_mac(struct niu
*np
, unsigned long reg
,
116 u64 bits
, int limit
, int delay
,
117 const char *reg_name
)
122 err
= __niu_wait_bits_clear_mac(np
, reg
, bits
, limit
, delay
);
124 netdev_err(np
->dev
, "bits (%llx) of register %s would not clear, val[%llx]\n",
125 (unsigned long long)bits
, reg_name
,
126 (unsigned long long)nr64_mac(reg
));
130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
131 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
132 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
135 static int __niu_wait_bits_clear_ipp(struct niu
*np
, unsigned long reg
,
136 u64 bits
, int limit
, int delay
)
138 while (--limit
>= 0) {
139 u64 val
= nr64_ipp(reg
);
150 static int __niu_set_and_wait_clear_ipp(struct niu
*np
, unsigned long reg
,
151 u64 bits
, int limit
, int delay
,
152 const char *reg_name
)
161 err
= __niu_wait_bits_clear_ipp(np
, reg
, bits
, limit
, delay
);
163 netdev_err(np
->dev
, "bits (%llx) of register %s would not clear, val[%llx]\n",
164 (unsigned long long)bits
, reg_name
,
165 (unsigned long long)nr64_ipp(reg
));
169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
170 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
171 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
174 static int __niu_wait_bits_clear(struct niu
*np
, unsigned long reg
,
175 u64 bits
, int limit
, int delay
)
177 while (--limit
>= 0) {
189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
194 static int __niu_set_and_wait_clear(struct niu
*np
, unsigned long reg
,
195 u64 bits
, int limit
, int delay
,
196 const char *reg_name
)
201 err
= __niu_wait_bits_clear(np
, reg
, bits
, limit
, delay
);
203 netdev_err(np
->dev
, "bits (%llx) of register %s would not clear, val[%llx]\n",
204 (unsigned long long)bits
, reg_name
,
205 (unsigned long long)nr64(reg
));
209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
214 static void niu_ldg_rearm(struct niu
*np
, struct niu_ldg
*lp
, int on
)
216 u64 val
= (u64
) lp
->timer
;
219 val
|= LDG_IMGMT_ARM
;
221 nw64(LDG_IMGMT(lp
->ldg_num
), val
);
224 static int niu_ldn_irq_enable(struct niu
*np
, int ldn
, int on
)
226 unsigned long mask_reg
, bits
;
229 if (ldn
< 0 || ldn
> LDN_MAX
)
233 mask_reg
= LD_IM0(ldn
);
236 mask_reg
= LD_IM1(ldn
- 64);
240 val
= nr64(mask_reg
);
250 static int niu_enable_ldn_in_ldg(struct niu
*np
, struct niu_ldg
*lp
, int on
)
252 struct niu_parent
*parent
= np
->parent
;
255 for (i
= 0; i
<= LDN_MAX
; i
++) {
258 if (parent
->ldg_map
[i
] != lp
->ldg_num
)
261 err
= niu_ldn_irq_enable(np
, i
, on
);
268 static int niu_enable_interrupts(struct niu
*np
, int on
)
272 for (i
= 0; i
< np
->num_ldg
; i
++) {
273 struct niu_ldg
*lp
= &np
->ldg
[i
];
276 err
= niu_enable_ldn_in_ldg(np
, lp
, on
);
280 for (i
= 0; i
< np
->num_ldg
; i
++)
281 niu_ldg_rearm(np
, &np
->ldg
[i
], on
);
286 static u32
phy_encode(u32 type
, int port
)
288 return type
<< (port
* 2);
291 static u32
phy_decode(u32 val
, int port
)
293 return (val
>> (port
* 2)) & PORT_TYPE_MASK
;
296 static int mdio_wait(struct niu
*np
)
301 while (--limit
> 0) {
302 val
= nr64(MIF_FRAME_OUTPUT
);
303 if ((val
>> MIF_FRAME_OUTPUT_TA_SHIFT
) & 0x1)
304 return val
& MIF_FRAME_OUTPUT_DATA
;
312 static int mdio_read(struct niu
*np
, int port
, int dev
, int reg
)
316 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
321 nw64(MIF_FRAME_OUTPUT
, MDIO_READ_OP(port
, dev
));
322 return mdio_wait(np
);
325 static int mdio_write(struct niu
*np
, int port
, int dev
, int reg
, int data
)
329 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
334 nw64(MIF_FRAME_OUTPUT
, MDIO_WRITE_OP(port
, dev
, data
));
342 static int mii_read(struct niu
*np
, int port
, int reg
)
344 nw64(MIF_FRAME_OUTPUT
, MII_READ_OP(port
, reg
));
345 return mdio_wait(np
);
348 static int mii_write(struct niu
*np
, int port
, int reg
, int data
)
352 nw64(MIF_FRAME_OUTPUT
, MII_WRITE_OP(port
, reg
, data
));
360 static int esr2_set_tx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
364 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
365 ESR2_TI_PLL_TX_CFG_L(channel
),
368 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
369 ESR2_TI_PLL_TX_CFG_H(channel
),
374 static int esr2_set_rx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
378 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
379 ESR2_TI_PLL_RX_CFG_L(channel
),
382 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
383 ESR2_TI_PLL_RX_CFG_H(channel
),
388 /* Mode is always 10G fiber. */
389 static int serdes_init_niu_10g_fiber(struct niu
*np
)
391 struct niu_link_config
*lp
= &np
->link_config
;
395 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
396 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
397 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
398 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
400 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
401 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
403 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
404 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
406 tx_cfg
|= PLL_TX_CFG_ENTEST
;
407 rx_cfg
|= PLL_RX_CFG_ENTEST
;
410 /* Initialize all 4 lanes of the SERDES. */
411 for (i
= 0; i
< 4; i
++) {
412 int err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
417 for (i
= 0; i
< 4; i
++) {
418 int err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
426 static int serdes_init_niu_1g_serdes(struct niu
*np
)
428 struct niu_link_config
*lp
= &np
->link_config
;
429 u16 pll_cfg
, pll_sts
;
431 u64
uninitialized_var(sig
), mask
, val
;
436 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
|
437 PLL_TX_CFG_RATE_HALF
);
438 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
439 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
440 PLL_RX_CFG_RATE_HALF
);
443 rx_cfg
|= PLL_RX_CFG_EQ_LP_ADAPTIVE
;
445 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
446 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
448 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
449 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
451 tx_cfg
|= PLL_TX_CFG_ENTEST
;
452 rx_cfg
|= PLL_RX_CFG_ENTEST
;
455 /* Initialize PLL for 1G */
456 pll_cfg
= (PLL_CFG_ENPLL
| PLL_CFG_MPY_8X
);
458 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
459 ESR2_TI_PLL_CFG_L
, pll_cfg
);
461 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
466 pll_sts
= PLL_CFG_ENPLL
;
468 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
469 ESR2_TI_PLL_STS_L
, pll_sts
);
471 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
478 /* Initialize all 4 lanes of the SERDES. */
479 for (i
= 0; i
< 4; i
++) {
480 err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
485 for (i
= 0; i
< 4; i
++) {
486 err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
493 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
498 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
506 while (max_retry
--) {
507 sig
= nr64(ESR_INT_SIGNALS
);
508 if ((sig
& mask
) == val
)
514 if ((sig
& mask
) != val
) {
515 netdev_err(np
->dev
, "Port %u signal bits [%08x] are not [%08x]\n",
516 np
->port
, (int)(sig
& mask
), (int)val
);
523 static int serdes_init_niu_10g_serdes(struct niu
*np
)
525 struct niu_link_config
*lp
= &np
->link_config
;
526 u32 tx_cfg
, rx_cfg
, pll_cfg
, pll_sts
;
528 u64
uninitialized_var(sig
), mask
, val
;
532 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
533 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
534 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
535 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
537 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
538 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
540 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
541 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
543 tx_cfg
|= PLL_TX_CFG_ENTEST
;
544 rx_cfg
|= PLL_RX_CFG_ENTEST
;
547 /* Initialize PLL for 10G */
548 pll_cfg
= (PLL_CFG_ENPLL
| PLL_CFG_MPY_10X
);
550 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
551 ESR2_TI_PLL_CFG_L
, pll_cfg
& 0xffff);
553 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
558 pll_sts
= PLL_CFG_ENPLL
;
560 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
561 ESR2_TI_PLL_STS_L
, pll_sts
& 0xffff);
563 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
570 /* Initialize all 4 lanes of the SERDES. */
571 for (i
= 0; i
< 4; i
++) {
572 err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
577 for (i
= 0; i
< 4; i
++) {
578 err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
583 /* check if serdes is ready */
587 mask
= ESR_INT_SIGNALS_P0_BITS
;
588 val
= (ESR_INT_SRDY0_P0
|
598 mask
= ESR_INT_SIGNALS_P1_BITS
;
599 val
= (ESR_INT_SRDY0_P1
|
612 while (max_retry
--) {
613 sig
= nr64(ESR_INT_SIGNALS
);
614 if ((sig
& mask
) == val
)
620 if ((sig
& mask
) != val
) {
621 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
622 np
->port
, (int)(sig
& mask
), (int)val
);
624 /* 10G failed, try initializing at 1G */
625 err
= serdes_init_niu_1g_serdes(np
);
627 np
->flags
&= ~NIU_FLAGS_10G
;
628 np
->mac_xcvr
= MAC_XCVR_PCS
;
630 netdev_err(np
->dev
, "Port %u 10G/1G SERDES Link Failed\n",
638 static int esr_read_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32
*val
)
642 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
, ESR_RXTX_CTRL_L(chan
));
644 *val
= (err
& 0xffff);
645 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
646 ESR_RXTX_CTRL_H(chan
));
648 *val
|= ((err
& 0xffff) << 16);
654 static int esr_read_glue0(struct niu
*np
, unsigned long chan
, u32
*val
)
658 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
659 ESR_GLUE_CTRL0_L(chan
));
661 *val
= (err
& 0xffff);
662 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
663 ESR_GLUE_CTRL0_H(chan
));
665 *val
|= ((err
& 0xffff) << 16);
672 static int esr_read_reset(struct niu
*np
, u32
*val
)
676 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
677 ESR_RXTX_RESET_CTRL_L
);
679 *val
= (err
& 0xffff);
680 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
681 ESR_RXTX_RESET_CTRL_H
);
683 *val
|= ((err
& 0xffff) << 16);
690 static int esr_write_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32 val
)
694 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
695 ESR_RXTX_CTRL_L(chan
), val
& 0xffff);
697 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
698 ESR_RXTX_CTRL_H(chan
), (val
>> 16));
702 static int esr_write_glue0(struct niu
*np
, unsigned long chan
, u32 val
)
706 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
707 ESR_GLUE_CTRL0_L(chan
), val
& 0xffff);
709 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
710 ESR_GLUE_CTRL0_H(chan
), (val
>> 16));
714 static int esr_reset(struct niu
*np
)
716 u32
uninitialized_var(reset
);
719 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
720 ESR_RXTX_RESET_CTRL_L
, 0x0000);
723 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
724 ESR_RXTX_RESET_CTRL_H
, 0xffff);
729 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
730 ESR_RXTX_RESET_CTRL_L
, 0xffff);
735 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
736 ESR_RXTX_RESET_CTRL_H
, 0x0000);
741 err
= esr_read_reset(np
, &reset
);
745 netdev_err(np
->dev
, "Port %u ESR_RESET did not clear [%08x]\n",
753 static int serdes_init_10g(struct niu
*np
)
755 struct niu_link_config
*lp
= &np
->link_config
;
756 unsigned long ctrl_reg
, test_cfg_reg
, i
;
757 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
762 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
763 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
766 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
767 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
773 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
774 ENET_SERDES_CTRL_SDET_1
|
775 ENET_SERDES_CTRL_SDET_2
|
776 ENET_SERDES_CTRL_SDET_3
|
777 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
780 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
784 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
787 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
788 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
789 ENET_SERDES_TEST_MD_0_SHIFT
) |
790 (ENET_TEST_MD_PAD_LOOPBACK
<<
791 ENET_SERDES_TEST_MD_1_SHIFT
) |
792 (ENET_TEST_MD_PAD_LOOPBACK
<<
793 ENET_SERDES_TEST_MD_2_SHIFT
) |
794 (ENET_TEST_MD_PAD_LOOPBACK
<<
795 ENET_SERDES_TEST_MD_3_SHIFT
));
798 nw64(ctrl_reg
, ctrl_val
);
799 nw64(test_cfg_reg
, test_cfg_val
);
801 /* Initialize all 4 lanes of the SERDES. */
802 for (i
= 0; i
< 4; i
++) {
803 u32 rxtx_ctrl
, glue0
;
805 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
808 err
= esr_read_glue0(np
, i
, &glue0
);
812 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
813 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
814 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
816 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
817 ESR_GLUE_CTRL0_THCNT
|
818 ESR_GLUE_CTRL0_BLTIME
);
819 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
820 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
821 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
822 (BLTIME_300_CYCLES
<<
823 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
825 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
828 err
= esr_write_glue0(np
, i
, glue0
);
837 sig
= nr64(ESR_INT_SIGNALS
);
840 mask
= ESR_INT_SIGNALS_P0_BITS
;
841 val
= (ESR_INT_SRDY0_P0
|
851 mask
= ESR_INT_SIGNALS_P1_BITS
;
852 val
= (ESR_INT_SRDY0_P1
|
865 if ((sig
& mask
) != val
) {
866 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
867 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
870 netdev_err(np
->dev
, "Port %u signal bits [%08x] are not [%08x]\n",
871 np
->port
, (int)(sig
& mask
), (int)val
);
874 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
)
875 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
879 static int serdes_init_1g(struct niu
*np
)
883 val
= nr64(ENET_SERDES_1_PLL_CFG
);
884 val
&= ~ENET_SERDES_PLL_FBDIV2
;
887 val
|= ENET_SERDES_PLL_HRATE0
;
890 val
|= ENET_SERDES_PLL_HRATE1
;
893 val
|= ENET_SERDES_PLL_HRATE2
;
896 val
|= ENET_SERDES_PLL_HRATE3
;
901 nw64(ENET_SERDES_1_PLL_CFG
, val
);
906 static int serdes_init_1g_serdes(struct niu
*np
)
908 struct niu_link_config
*lp
= &np
->link_config
;
909 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
910 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
912 u64 reset_val
, val_rd
;
914 val
= ENET_SERDES_PLL_HRATE0
| ENET_SERDES_PLL_HRATE1
|
915 ENET_SERDES_PLL_HRATE2
| ENET_SERDES_PLL_HRATE3
|
916 ENET_SERDES_PLL_FBDIV0
;
919 reset_val
= ENET_SERDES_RESET_0
;
920 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
921 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
922 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
925 reset_val
= ENET_SERDES_RESET_1
;
926 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
927 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
928 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
934 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
935 ENET_SERDES_CTRL_SDET_1
|
936 ENET_SERDES_CTRL_SDET_2
|
937 ENET_SERDES_CTRL_SDET_3
|
938 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
941 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
945 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
948 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
949 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
950 ENET_SERDES_TEST_MD_0_SHIFT
) |
951 (ENET_TEST_MD_PAD_LOOPBACK
<<
952 ENET_SERDES_TEST_MD_1_SHIFT
) |
953 (ENET_TEST_MD_PAD_LOOPBACK
<<
954 ENET_SERDES_TEST_MD_2_SHIFT
) |
955 (ENET_TEST_MD_PAD_LOOPBACK
<<
956 ENET_SERDES_TEST_MD_3_SHIFT
));
959 nw64(ENET_SERDES_RESET
, reset_val
);
961 val_rd
= nr64(ENET_SERDES_RESET
);
962 val_rd
&= ~reset_val
;
964 nw64(ctrl_reg
, ctrl_val
);
965 nw64(test_cfg_reg
, test_cfg_val
);
966 nw64(ENET_SERDES_RESET
, val_rd
);
969 /* Initialize all 4 lanes of the SERDES. */
970 for (i
= 0; i
< 4; i
++) {
971 u32 rxtx_ctrl
, glue0
;
973 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
976 err
= esr_read_glue0(np
, i
, &glue0
);
980 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
981 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
982 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
984 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
985 ESR_GLUE_CTRL0_THCNT
|
986 ESR_GLUE_CTRL0_BLTIME
);
987 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
988 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
989 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
990 (BLTIME_300_CYCLES
<<
991 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
993 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
996 err
= esr_write_glue0(np
, i
, glue0
);
1002 sig
= nr64(ESR_INT_SIGNALS
);
1005 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
1010 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
1018 if ((sig
& mask
) != val
) {
1019 netdev_err(np
->dev
, "Port %u signal bits [%08x] are not [%08x]\n",
1020 np
->port
, (int)(sig
& mask
), (int)val
);
1027 static int link_status_1g_serdes(struct niu
*np
, int *link_up_p
)
1029 struct niu_link_config
*lp
= &np
->link_config
;
1033 unsigned long flags
;
1037 current_speed
= SPEED_INVALID
;
1038 current_duplex
= DUPLEX_INVALID
;
1040 spin_lock_irqsave(&np
->lock
, flags
);
1042 val
= nr64_pcs(PCS_MII_STAT
);
1044 if (val
& PCS_MII_STAT_LINK_STATUS
) {
1046 current_speed
= SPEED_1000
;
1047 current_duplex
= DUPLEX_FULL
;
1050 lp
->active_speed
= current_speed
;
1051 lp
->active_duplex
= current_duplex
;
1052 spin_unlock_irqrestore(&np
->lock
, flags
);
1054 *link_up_p
= link_up
;
1058 static int link_status_10g_serdes(struct niu
*np
, int *link_up_p
)
1060 unsigned long flags
;
1061 struct niu_link_config
*lp
= &np
->link_config
;
1068 if (!(np
->flags
& NIU_FLAGS_10G
))
1069 return link_status_1g_serdes(np
, link_up_p
);
1071 current_speed
= SPEED_INVALID
;
1072 current_duplex
= DUPLEX_INVALID
;
1073 spin_lock_irqsave(&np
->lock
, flags
);
1075 val
= nr64_xpcs(XPCS_STATUS(0));
1076 val2
= nr64_mac(XMAC_INTER2
);
1077 if (val2
& 0x01000000)
1080 if ((val
& 0x1000ULL
) && link_ok
) {
1082 current_speed
= SPEED_10000
;
1083 current_duplex
= DUPLEX_FULL
;
1085 lp
->active_speed
= current_speed
;
1086 lp
->active_duplex
= current_duplex
;
1087 spin_unlock_irqrestore(&np
->lock
, flags
);
1088 *link_up_p
= link_up
;
1092 static int link_status_mii(struct niu
*np
, int *link_up_p
)
1094 struct niu_link_config
*lp
= &np
->link_config
;
1096 int bmsr
, advert
, ctrl1000
, stat1000
, lpa
, bmcr
, estatus
;
1097 int supported
, advertising
, active_speed
, active_duplex
;
1099 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1100 if (unlikely(err
< 0))
1104 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1105 if (unlikely(err
< 0))
1109 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1110 if (unlikely(err
< 0))
1114 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1115 if (unlikely(err
< 0))
1119 if (likely(bmsr
& BMSR_ESTATEN
)) {
1120 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1121 if (unlikely(err
< 0))
1125 err
= mii_read(np
, np
->phy_addr
, MII_CTRL1000
);
1126 if (unlikely(err
< 0))
1130 err
= mii_read(np
, np
->phy_addr
, MII_STAT1000
);
1131 if (unlikely(err
< 0))
1135 estatus
= ctrl1000
= stat1000
= 0;
1138 if (bmsr
& BMSR_ANEGCAPABLE
)
1139 supported
|= SUPPORTED_Autoneg
;
1140 if (bmsr
& BMSR_10HALF
)
1141 supported
|= SUPPORTED_10baseT_Half
;
1142 if (bmsr
& BMSR_10FULL
)
1143 supported
|= SUPPORTED_10baseT_Full
;
1144 if (bmsr
& BMSR_100HALF
)
1145 supported
|= SUPPORTED_100baseT_Half
;
1146 if (bmsr
& BMSR_100FULL
)
1147 supported
|= SUPPORTED_100baseT_Full
;
1148 if (estatus
& ESTATUS_1000_THALF
)
1149 supported
|= SUPPORTED_1000baseT_Half
;
1150 if (estatus
& ESTATUS_1000_TFULL
)
1151 supported
|= SUPPORTED_1000baseT_Full
;
1152 lp
->supported
= supported
;
1154 advertising
= mii_adv_to_ethtool_adv_t(advert
);
1155 advertising
|= mii_ctrl1000_to_ethtool_adv_t(ctrl1000
);
1157 if (bmcr
& BMCR_ANENABLE
) {
1160 lp
->active_autoneg
= 1;
1161 advertising
|= ADVERTISED_Autoneg
;
1164 neg1000
= (ctrl1000
<< 2) & stat1000
;
1166 if (neg1000
& (LPA_1000FULL
| LPA_1000HALF
))
1167 active_speed
= SPEED_1000
;
1168 else if (neg
& LPA_100
)
1169 active_speed
= SPEED_100
;
1170 else if (neg
& (LPA_10HALF
| LPA_10FULL
))
1171 active_speed
= SPEED_10
;
1173 active_speed
= SPEED_INVALID
;
1175 if ((neg1000
& LPA_1000FULL
) || (neg
& LPA_DUPLEX
))
1176 active_duplex
= DUPLEX_FULL
;
1177 else if (active_speed
!= SPEED_INVALID
)
1178 active_duplex
= DUPLEX_HALF
;
1180 active_duplex
= DUPLEX_INVALID
;
1182 lp
->active_autoneg
= 0;
1184 if ((bmcr
& BMCR_SPEED1000
) && !(bmcr
& BMCR_SPEED100
))
1185 active_speed
= SPEED_1000
;
1186 else if (bmcr
& BMCR_SPEED100
)
1187 active_speed
= SPEED_100
;
1189 active_speed
= SPEED_10
;
1191 if (bmcr
& BMCR_FULLDPLX
)
1192 active_duplex
= DUPLEX_FULL
;
1194 active_duplex
= DUPLEX_HALF
;
1197 lp
->active_advertising
= advertising
;
1198 lp
->active_speed
= active_speed
;
1199 lp
->active_duplex
= active_duplex
;
1200 *link_up_p
= !!(bmsr
& BMSR_LSTATUS
);
1205 static int link_status_1g_rgmii(struct niu
*np
, int *link_up_p
)
1207 struct niu_link_config
*lp
= &np
->link_config
;
1208 u16 current_speed
, bmsr
;
1209 unsigned long flags
;
1214 current_speed
= SPEED_INVALID
;
1215 current_duplex
= DUPLEX_INVALID
;
1217 spin_lock_irqsave(&np
->lock
, flags
);
1221 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1226 if (bmsr
& BMSR_LSTATUS
) {
1229 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1234 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1239 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1243 current_speed
= SPEED_1000
;
1244 current_duplex
= DUPLEX_FULL
;
1247 lp
->active_speed
= current_speed
;
1248 lp
->active_duplex
= current_duplex
;
1252 spin_unlock_irqrestore(&np
->lock
, flags
);
1254 *link_up_p
= link_up
;
1258 static int link_status_1g(struct niu
*np
, int *link_up_p
)
1260 struct niu_link_config
*lp
= &np
->link_config
;
1261 unsigned long flags
;
1264 spin_lock_irqsave(&np
->lock
, flags
);
1266 err
= link_status_mii(np
, link_up_p
);
1267 lp
->supported
|= SUPPORTED_TP
;
1268 lp
->active_advertising
|= ADVERTISED_TP
;
1270 spin_unlock_irqrestore(&np
->lock
, flags
);
1274 static int bcm8704_reset(struct niu
*np
)
1278 err
= mdio_read(np
, np
->phy_addr
,
1279 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
1280 if (err
< 0 || err
== 0xffff)
1283 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1289 while (--limit
>= 0) {
1290 err
= mdio_read(np
, np
->phy_addr
,
1291 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
1294 if (!(err
& BMCR_RESET
))
1298 netdev_err(np
->dev
, "Port %u PHY will not reset (bmcr=%04x)\n",
1299 np
->port
, (err
& 0xffff));
1305 /* When written, certain PHY registers need to be read back twice
1306 * in order for the bits to settle properly.
1308 static int bcm8704_user_dev3_readback(struct niu
*np
, int reg
)
1310 int err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1313 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1319 static int bcm8706_init_user_dev3(struct niu
*np
)
1324 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1325 BCM8704_USER_OPT_DIGITAL_CTRL
);
1328 err
&= ~USER_ODIG_CTRL_GPIOS
;
1329 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1330 err
|= USER_ODIG_CTRL_RESV2
;
1331 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1332 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1341 static int bcm8704_init_user_dev3(struct niu
*np
)
1345 err
= mdio_write(np
, np
->phy_addr
,
1346 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_CONTROL
,
1347 (USER_CONTROL_OPTXRST_LVL
|
1348 USER_CONTROL_OPBIASFLT_LVL
|
1349 USER_CONTROL_OBTMPFLT_LVL
|
1350 USER_CONTROL_OPPRFLT_LVL
|
1351 USER_CONTROL_OPTXFLT_LVL
|
1352 USER_CONTROL_OPRXLOS_LVL
|
1353 USER_CONTROL_OPRXFLT_LVL
|
1354 USER_CONTROL_OPTXON_LVL
|
1355 (0x3f << USER_CONTROL_RES1_SHIFT
)));
1359 err
= mdio_write(np
, np
->phy_addr
,
1360 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_PMD_TX_CONTROL
,
1361 (USER_PMD_TX_CTL_XFP_CLKEN
|
1362 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH
) |
1363 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH
) |
1364 USER_PMD_TX_CTL_TSCK_LPWREN
));
1368 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_CONTROL
);
1371 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_PMD_TX_CONTROL
);
1375 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1376 BCM8704_USER_OPT_DIGITAL_CTRL
);
1379 err
&= ~USER_ODIG_CTRL_GPIOS
;
1380 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1381 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1382 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1391 static int mrvl88x2011_act_led(struct niu
*np
, int val
)
1395 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1396 MRVL88X2011_LED_8_TO_11_CTL
);
1400 err
&= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT
,MRVL88X2011_LED_CTL_MASK
);
1401 err
|= MRVL88X2011_LED(MRVL88X2011_LED_ACT
,val
);
1403 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1404 MRVL88X2011_LED_8_TO_11_CTL
, err
);
1407 static int mrvl88x2011_led_blink_rate(struct niu
*np
, int rate
)
1411 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1412 MRVL88X2011_LED_BLINK_CTL
);
1414 err
&= ~MRVL88X2011_LED_BLKRATE_MASK
;
1417 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1418 MRVL88X2011_LED_BLINK_CTL
, err
);
1424 static int xcvr_init_10g_mrvl88x2011(struct niu
*np
)
1428 /* Set LED functions */
1429 err
= mrvl88x2011_led_blink_rate(np
, MRVL88X2011_LED_BLKRATE_134MS
);
1434 err
= mrvl88x2011_act_led(np
, MRVL88X2011_LED_CTL_OFF
);
1438 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1439 MRVL88X2011_GENERAL_CTL
);
1443 err
|= MRVL88X2011_ENA_XFPREFCLK
;
1445 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1446 MRVL88X2011_GENERAL_CTL
, err
);
1450 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1451 MRVL88X2011_PMA_PMD_CTL_1
);
1455 if (np
->link_config
.loopback_mode
== LOOPBACK_MAC
)
1456 err
|= MRVL88X2011_LOOPBACK
;
1458 err
&= ~MRVL88X2011_LOOPBACK
;
1460 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1461 MRVL88X2011_PMA_PMD_CTL_1
, err
);
1466 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1467 MRVL88X2011_10G_PMD_TX_DIS
, MRVL88X2011_ENA_PMDTX
);
1471 static int xcvr_diag_bcm870x(struct niu
*np
)
1473 u16 analog_stat0
, tx_alarm_status
;
1477 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1481 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np
->port
, err
);
1483 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, 0x20);
1486 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np
->port
, err
);
1488 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1492 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np
->port
, err
);
1495 /* XXX dig this out it might not be so useful XXX */
1496 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1497 BCM8704_USER_ANALOG_STATUS0
);
1500 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1501 BCM8704_USER_ANALOG_STATUS0
);
1506 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1507 BCM8704_USER_TX_ALARM_STATUS
);
1510 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1511 BCM8704_USER_TX_ALARM_STATUS
);
1514 tx_alarm_status
= err
;
1516 if (analog_stat0
!= 0x03fc) {
1517 if ((analog_stat0
== 0x43bc) && (tx_alarm_status
!= 0)) {
1518 pr_info("Port %u cable not connected or bad cable\n",
1520 } else if (analog_stat0
== 0x639c) {
1521 pr_info("Port %u optical module is bad or missing\n",
1529 static int xcvr_10g_set_lb_bcm870x(struct niu
*np
)
1531 struct niu_link_config
*lp
= &np
->link_config
;
1534 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1539 err
&= ~BMCR_LOOPBACK
;
1541 if (lp
->loopback_mode
== LOOPBACK_MAC
)
1542 err
|= BMCR_LOOPBACK
;
1544 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1552 static int xcvr_init_10g_bcm8706(struct niu
*np
)
1557 if ((np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) &&
1558 (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) == 0)
1561 val
= nr64_mac(XMAC_CONFIG
);
1562 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1563 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1564 nw64_mac(XMAC_CONFIG
, val
);
1566 val
= nr64(MIF_CONFIG
);
1567 val
|= MIF_CONFIG_INDIRECT_MODE
;
1568 nw64(MIF_CONFIG
, val
);
1570 err
= bcm8704_reset(np
);
1574 err
= xcvr_10g_set_lb_bcm870x(np
);
1578 err
= bcm8706_init_user_dev3(np
);
1582 err
= xcvr_diag_bcm870x(np
);
1589 static int xcvr_init_10g_bcm8704(struct niu
*np
)
1593 err
= bcm8704_reset(np
);
1597 err
= bcm8704_init_user_dev3(np
);
1601 err
= xcvr_10g_set_lb_bcm870x(np
);
1605 err
= xcvr_diag_bcm870x(np
);
1612 static int xcvr_init_10g(struct niu
*np
)
1617 val
= nr64_mac(XMAC_CONFIG
);
1618 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1619 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1620 nw64_mac(XMAC_CONFIG
, val
);
1622 /* XXX shared resource, lock parent XXX */
1623 val
= nr64(MIF_CONFIG
);
1624 val
|= MIF_CONFIG_INDIRECT_MODE
;
1625 nw64(MIF_CONFIG
, val
);
1627 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
1628 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
1630 /* handle different phy types */
1631 switch (phy_id
& NIU_PHY_ID_MASK
) {
1632 case NIU_PHY_ID_MRVL88X2011
:
1633 err
= xcvr_init_10g_mrvl88x2011(np
);
1636 default: /* bcom 8704 */
1637 err
= xcvr_init_10g_bcm8704(np
);
1644 static int mii_reset(struct niu
*np
)
1648 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, BMCR_RESET
);
1653 while (--limit
>= 0) {
1655 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1658 if (!(err
& BMCR_RESET
))
1662 netdev_err(np
->dev
, "Port %u MII would not reset, bmcr[%04x]\n",
1670 static int xcvr_init_1g_rgmii(struct niu
*np
)
1674 u16 bmcr
, bmsr
, estat
;
1676 val
= nr64(MIF_CONFIG
);
1677 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1678 nw64(MIF_CONFIG
, val
);
1680 err
= mii_reset(np
);
1684 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1690 if (bmsr
& BMSR_ESTATEN
) {
1691 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1698 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1702 if (bmsr
& BMSR_ESTATEN
) {
1705 if (estat
& ESTATUS_1000_TFULL
)
1706 ctrl1000
|= ADVERTISE_1000FULL
;
1707 err
= mii_write(np
, np
->phy_addr
, MII_CTRL1000
, ctrl1000
);
1712 bmcr
= (BMCR_SPEED1000
| BMCR_FULLDPLX
);
1714 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1718 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1721 bmcr
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1723 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1730 static int mii_init_common(struct niu
*np
)
1732 struct niu_link_config
*lp
= &np
->link_config
;
1733 u16 bmcr
, bmsr
, adv
, estat
;
1736 err
= mii_reset(np
);
1740 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1746 if (bmsr
& BMSR_ESTATEN
) {
1747 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1754 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1758 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
1759 bmcr
|= BMCR_LOOPBACK
;
1760 if (lp
->active_speed
== SPEED_1000
)
1761 bmcr
|= BMCR_SPEED1000
;
1762 if (lp
->active_duplex
== DUPLEX_FULL
)
1763 bmcr
|= BMCR_FULLDPLX
;
1766 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
1769 aux
= (BCM5464R_AUX_CTL_EXT_LB
|
1770 BCM5464R_AUX_CTL_WRITE_1
);
1771 err
= mii_write(np
, np
->phy_addr
, BCM5464R_AUX_CTL
, aux
);
1779 adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1780 if ((bmsr
& BMSR_10HALF
) &&
1781 (lp
->advertising
& ADVERTISED_10baseT_Half
))
1782 adv
|= ADVERTISE_10HALF
;
1783 if ((bmsr
& BMSR_10FULL
) &&
1784 (lp
->advertising
& ADVERTISED_10baseT_Full
))
1785 adv
|= ADVERTISE_10FULL
;
1786 if ((bmsr
& BMSR_100HALF
) &&
1787 (lp
->advertising
& ADVERTISED_100baseT_Half
))
1788 adv
|= ADVERTISE_100HALF
;
1789 if ((bmsr
& BMSR_100FULL
) &&
1790 (lp
->advertising
& ADVERTISED_100baseT_Full
))
1791 adv
|= ADVERTISE_100FULL
;
1792 err
= mii_write(np
, np
->phy_addr
, MII_ADVERTISE
, adv
);
1796 if (likely(bmsr
& BMSR_ESTATEN
)) {
1798 if ((estat
& ESTATUS_1000_THALF
) &&
1799 (lp
->advertising
& ADVERTISED_1000baseT_Half
))
1800 ctrl1000
|= ADVERTISE_1000HALF
;
1801 if ((estat
& ESTATUS_1000_TFULL
) &&
1802 (lp
->advertising
& ADVERTISED_1000baseT_Full
))
1803 ctrl1000
|= ADVERTISE_1000FULL
;
1804 err
= mii_write(np
, np
->phy_addr
,
1805 MII_CTRL1000
, ctrl1000
);
1810 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1815 if (lp
->duplex
== DUPLEX_FULL
) {
1816 bmcr
|= BMCR_FULLDPLX
;
1818 } else if (lp
->duplex
== DUPLEX_HALF
)
1823 if (lp
->speed
== SPEED_1000
) {
1824 /* if X-full requested while not supported, or
1825 X-half requested while not supported... */
1826 if ((fulldpx
&& !(estat
& ESTATUS_1000_TFULL
)) ||
1827 (!fulldpx
&& !(estat
& ESTATUS_1000_THALF
)))
1829 bmcr
|= BMCR_SPEED1000
;
1830 } else if (lp
->speed
== SPEED_100
) {
1831 if ((fulldpx
&& !(bmsr
& BMSR_100FULL
)) ||
1832 (!fulldpx
&& !(bmsr
& BMSR_100HALF
)))
1834 bmcr
|= BMCR_SPEED100
;
1835 } else if (lp
->speed
== SPEED_10
) {
1836 if ((fulldpx
&& !(bmsr
& BMSR_10FULL
)) ||
1837 (!fulldpx
&& !(bmsr
& BMSR_10HALF
)))
1843 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1848 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1853 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1858 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1859 np
->port
, bmcr
, bmsr
);
1865 static int xcvr_init_1g(struct niu
*np
)
1869 /* XXX shared resource, lock parent XXX */
1870 val
= nr64(MIF_CONFIG
);
1871 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1872 nw64(MIF_CONFIG
, val
);
1874 return mii_init_common(np
);
1877 static int niu_xcvr_init(struct niu
*np
)
1879 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1884 err
= ops
->xcvr_init(np
);
1889 static int niu_serdes_init(struct niu
*np
)
1891 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1895 if (ops
->serdes_init
)
1896 err
= ops
->serdes_init(np
);
1901 static void niu_init_xif(struct niu
*);
1902 static void niu_handle_led(struct niu
*, int status
);
1904 static int niu_link_status_common(struct niu
*np
, int link_up
)
1906 struct niu_link_config
*lp
= &np
->link_config
;
1907 struct net_device
*dev
= np
->dev
;
1908 unsigned long flags
;
1910 if (!netif_carrier_ok(dev
) && link_up
) {
1911 netif_info(np
, link
, dev
, "Link is up at %s, %s duplex\n",
1912 lp
->active_speed
== SPEED_10000
? "10Gb/sec" :
1913 lp
->active_speed
== SPEED_1000
? "1Gb/sec" :
1914 lp
->active_speed
== SPEED_100
? "100Mbit/sec" :
1916 lp
->active_duplex
== DUPLEX_FULL
? "full" : "half");
1918 spin_lock_irqsave(&np
->lock
, flags
);
1920 niu_handle_led(np
, 1);
1921 spin_unlock_irqrestore(&np
->lock
, flags
);
1923 netif_carrier_on(dev
);
1924 } else if (netif_carrier_ok(dev
) && !link_up
) {
1925 netif_warn(np
, link
, dev
, "Link is down\n");
1926 spin_lock_irqsave(&np
->lock
, flags
);
1927 niu_handle_led(np
, 0);
1928 spin_unlock_irqrestore(&np
->lock
, flags
);
1929 netif_carrier_off(dev
);
1935 static int link_status_10g_mrvl(struct niu
*np
, int *link_up_p
)
1937 int err
, link_up
, pma_status
, pcs_status
;
1941 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1942 MRVL88X2011_10G_PMD_STATUS_2
);
1946 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1947 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1948 MRVL88X2011_PMA_PMD_STATUS_1
);
1952 pma_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
1954 /* Check PMC Register : 3.0001.2 == 1: read twice */
1955 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1956 MRVL88X2011_PMA_PMD_STATUS_1
);
1960 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1961 MRVL88X2011_PMA_PMD_STATUS_1
);
1965 pcs_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
1967 /* Check XGXS Register : 4.0018.[0-3,12] */
1968 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV4_ADDR
,
1969 MRVL88X2011_10G_XGXS_LANE_STAT
);
1973 if (err
== (PHYXS_XGXS_LANE_STAT_ALINGED
| PHYXS_XGXS_LANE_STAT_LANE3
|
1974 PHYXS_XGXS_LANE_STAT_LANE2
| PHYXS_XGXS_LANE_STAT_LANE1
|
1975 PHYXS_XGXS_LANE_STAT_LANE0
| PHYXS_XGXS_LANE_STAT_MAGIC
|
1977 link_up
= (pma_status
&& pcs_status
) ? 1 : 0;
1979 np
->link_config
.active_speed
= SPEED_10000
;
1980 np
->link_config
.active_duplex
= DUPLEX_FULL
;
1983 mrvl88x2011_act_led(np
, (link_up
?
1984 MRVL88X2011_LED_CTL_PCS_ACT
:
1985 MRVL88X2011_LED_CTL_OFF
));
1987 *link_up_p
= link_up
;
1991 static int link_status_10g_bcm8706(struct niu
*np
, int *link_up_p
)
1996 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1997 BCM8704_PMD_RCV_SIGDET
);
1998 if (err
< 0 || err
== 0xffff)
2000 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
2005 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
2006 BCM8704_PCS_10G_R_STATUS
);
2010 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
2015 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
2016 BCM8704_PHYXS_XGXS_LANE_STAT
);
2019 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
2020 PHYXS_XGXS_LANE_STAT_MAGIC
|
2021 PHYXS_XGXS_LANE_STAT_PATTEST
|
2022 PHYXS_XGXS_LANE_STAT_LANE3
|
2023 PHYXS_XGXS_LANE_STAT_LANE2
|
2024 PHYXS_XGXS_LANE_STAT_LANE1
|
2025 PHYXS_XGXS_LANE_STAT_LANE0
)) {
2027 np
->link_config
.active_speed
= SPEED_INVALID
;
2028 np
->link_config
.active_duplex
= DUPLEX_INVALID
;
2033 np
->link_config
.active_speed
= SPEED_10000
;
2034 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2038 *link_up_p
= link_up
;
2042 static int link_status_10g_bcom(struct niu
*np
, int *link_up_p
)
2048 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
2049 BCM8704_PMD_RCV_SIGDET
);
2052 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
2057 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
2058 BCM8704_PCS_10G_R_STATUS
);
2061 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
2066 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
2067 BCM8704_PHYXS_XGXS_LANE_STAT
);
2071 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
2072 PHYXS_XGXS_LANE_STAT_MAGIC
|
2073 PHYXS_XGXS_LANE_STAT_LANE3
|
2074 PHYXS_XGXS_LANE_STAT_LANE2
|
2075 PHYXS_XGXS_LANE_STAT_LANE1
|
2076 PHYXS_XGXS_LANE_STAT_LANE0
)) {
2082 np
->link_config
.active_speed
= SPEED_10000
;
2083 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2087 *link_up_p
= link_up
;
2091 static int link_status_10g(struct niu
*np
, int *link_up_p
)
2093 unsigned long flags
;
2096 spin_lock_irqsave(&np
->lock
, flags
);
2098 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
2101 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
2102 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
2104 /* handle different phy types */
2105 switch (phy_id
& NIU_PHY_ID_MASK
) {
2106 case NIU_PHY_ID_MRVL88X2011
:
2107 err
= link_status_10g_mrvl(np
, link_up_p
);
2110 default: /* bcom 8704 */
2111 err
= link_status_10g_bcom(np
, link_up_p
);
2116 spin_unlock_irqrestore(&np
->lock
, flags
);
2121 static int niu_10g_phy_present(struct niu
*np
)
2125 sig
= nr64(ESR_INT_SIGNALS
);
2128 mask
= ESR_INT_SIGNALS_P0_BITS
;
2129 val
= (ESR_INT_SRDY0_P0
|
2132 ESR_INT_XDP_P0_CH3
|
2133 ESR_INT_XDP_P0_CH2
|
2134 ESR_INT_XDP_P0_CH1
|
2135 ESR_INT_XDP_P0_CH0
);
2139 mask
= ESR_INT_SIGNALS_P1_BITS
;
2140 val
= (ESR_INT_SRDY0_P1
|
2143 ESR_INT_XDP_P1_CH3
|
2144 ESR_INT_XDP_P1_CH2
|
2145 ESR_INT_XDP_P1_CH1
|
2146 ESR_INT_XDP_P1_CH0
);
2153 if ((sig
& mask
) != val
)
2158 static int link_status_10g_hotplug(struct niu
*np
, int *link_up_p
)
2160 unsigned long flags
;
2163 int phy_present_prev
;
2165 spin_lock_irqsave(&np
->lock
, flags
);
2167 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
2168 phy_present_prev
= (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) ?
2170 phy_present
= niu_10g_phy_present(np
);
2171 if (phy_present
!= phy_present_prev
) {
2174 /* A NEM was just plugged in */
2175 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2176 if (np
->phy_ops
->xcvr_init
)
2177 err
= np
->phy_ops
->xcvr_init(np
);
2179 err
= mdio_read(np
, np
->phy_addr
,
2180 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
2181 if (err
== 0xffff) {
2182 /* No mdio, back-to-back XAUI */
2186 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2189 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2191 netif_warn(np
, link
, np
->dev
,
2192 "Hotplug PHY Removed\n");
2196 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) {
2197 err
= link_status_10g_bcm8706(np
, link_up_p
);
2198 if (err
== 0xffff) {
2199 /* No mdio, back-to-back XAUI: it is C10NEM */
2201 np
->link_config
.active_speed
= SPEED_10000
;
2202 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2207 spin_unlock_irqrestore(&np
->lock
, flags
);
2212 static int niu_link_status(struct niu
*np
, int *link_up_p
)
2214 const struct niu_phy_ops
*ops
= np
->phy_ops
;
2218 if (ops
->link_status
)
2219 err
= ops
->link_status(np
, link_up_p
);
2224 static void niu_timer(unsigned long __opaque
)
2226 struct niu
*np
= (struct niu
*) __opaque
;
2230 err
= niu_link_status(np
, &link_up
);
2232 niu_link_status_common(np
, link_up
);
2234 if (netif_carrier_ok(np
->dev
))
2238 np
->timer
.expires
= jiffies
+ off
;
2240 add_timer(&np
->timer
);
2243 static const struct niu_phy_ops phy_ops_10g_serdes
= {
2244 .serdes_init
= serdes_init_10g_serdes
,
2245 .link_status
= link_status_10g_serdes
,
2248 static const struct niu_phy_ops phy_ops_10g_serdes_niu
= {
2249 .serdes_init
= serdes_init_niu_10g_serdes
,
2250 .link_status
= link_status_10g_serdes
,
2253 static const struct niu_phy_ops phy_ops_1g_serdes_niu
= {
2254 .serdes_init
= serdes_init_niu_1g_serdes
,
2255 .link_status
= link_status_1g_serdes
,
2258 static const struct niu_phy_ops phy_ops_1g_rgmii
= {
2259 .xcvr_init
= xcvr_init_1g_rgmii
,
2260 .link_status
= link_status_1g_rgmii
,
2263 static const struct niu_phy_ops phy_ops_10g_fiber_niu
= {
2264 .serdes_init
= serdes_init_niu_10g_fiber
,
2265 .xcvr_init
= xcvr_init_10g
,
2266 .link_status
= link_status_10g
,
2269 static const struct niu_phy_ops phy_ops_10g_fiber
= {
2270 .serdes_init
= serdes_init_10g
,
2271 .xcvr_init
= xcvr_init_10g
,
2272 .link_status
= link_status_10g
,
2275 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug
= {
2276 .serdes_init
= serdes_init_10g
,
2277 .xcvr_init
= xcvr_init_10g_bcm8706
,
2278 .link_status
= link_status_10g_hotplug
,
2281 static const struct niu_phy_ops phy_ops_niu_10g_hotplug
= {
2282 .serdes_init
= serdes_init_niu_10g_fiber
,
2283 .xcvr_init
= xcvr_init_10g_bcm8706
,
2284 .link_status
= link_status_10g_hotplug
,
2287 static const struct niu_phy_ops phy_ops_10g_copper
= {
2288 .serdes_init
= serdes_init_10g
,
2289 .link_status
= link_status_10g
, /* XXX */
2292 static const struct niu_phy_ops phy_ops_1g_fiber
= {
2293 .serdes_init
= serdes_init_1g
,
2294 .xcvr_init
= xcvr_init_1g
,
2295 .link_status
= link_status_1g
,
2298 static const struct niu_phy_ops phy_ops_1g_copper
= {
2299 .xcvr_init
= xcvr_init_1g
,
2300 .link_status
= link_status_1g
,
2303 struct niu_phy_template
{
2304 const struct niu_phy_ops
*ops
;
2308 static const struct niu_phy_template phy_template_niu_10g_fiber
= {
2309 .ops
= &phy_ops_10g_fiber_niu
,
2310 .phy_addr_base
= 16,
2313 static const struct niu_phy_template phy_template_niu_10g_serdes
= {
2314 .ops
= &phy_ops_10g_serdes_niu
,
2318 static const struct niu_phy_template phy_template_niu_1g_serdes
= {
2319 .ops
= &phy_ops_1g_serdes_niu
,
2323 static const struct niu_phy_template phy_template_10g_fiber
= {
2324 .ops
= &phy_ops_10g_fiber
,
2328 static const struct niu_phy_template phy_template_10g_fiber_hotplug
= {
2329 .ops
= &phy_ops_10g_fiber_hotplug
,
2333 static const struct niu_phy_template phy_template_niu_10g_hotplug
= {
2334 .ops
= &phy_ops_niu_10g_hotplug
,
2338 static const struct niu_phy_template phy_template_10g_copper
= {
2339 .ops
= &phy_ops_10g_copper
,
2340 .phy_addr_base
= 10,
2343 static const struct niu_phy_template phy_template_1g_fiber
= {
2344 .ops
= &phy_ops_1g_fiber
,
2348 static const struct niu_phy_template phy_template_1g_copper
= {
2349 .ops
= &phy_ops_1g_copper
,
2353 static const struct niu_phy_template phy_template_1g_rgmii
= {
2354 .ops
= &phy_ops_1g_rgmii
,
2358 static const struct niu_phy_template phy_template_10g_serdes
= {
2359 .ops
= &phy_ops_10g_serdes
,
2363 static int niu_atca_port_num
[4] = {
2367 static int serdes_init_10g_serdes(struct niu
*np
)
2369 struct niu_link_config
*lp
= &np
->link_config
;
2370 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
2371 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
2375 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
2376 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
2377 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
2380 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
2381 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
2382 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
2388 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
2389 ENET_SERDES_CTRL_SDET_1
|
2390 ENET_SERDES_CTRL_SDET_2
|
2391 ENET_SERDES_CTRL_SDET_3
|
2392 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
2393 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
2394 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
2395 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
2396 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
2397 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
2398 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
2399 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
2402 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
2403 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
2404 ENET_SERDES_TEST_MD_0_SHIFT
) |
2405 (ENET_TEST_MD_PAD_LOOPBACK
<<
2406 ENET_SERDES_TEST_MD_1_SHIFT
) |
2407 (ENET_TEST_MD_PAD_LOOPBACK
<<
2408 ENET_SERDES_TEST_MD_2_SHIFT
) |
2409 (ENET_TEST_MD_PAD_LOOPBACK
<<
2410 ENET_SERDES_TEST_MD_3_SHIFT
));
2414 nw64(pll_cfg
, ENET_SERDES_PLL_FBDIV2
);
2415 nw64(ctrl_reg
, ctrl_val
);
2416 nw64(test_cfg_reg
, test_cfg_val
);
2418 /* Initialize all 4 lanes of the SERDES. */
2419 for (i
= 0; i
< 4; i
++) {
2420 u32 rxtx_ctrl
, glue0
;
2423 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
2426 err
= esr_read_glue0(np
, i
, &glue0
);
2430 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
2431 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
2432 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
2434 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
2435 ESR_GLUE_CTRL0_THCNT
|
2436 ESR_GLUE_CTRL0_BLTIME
);
2437 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
2438 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
2439 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
2440 (BLTIME_300_CYCLES
<<
2441 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
2443 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
2446 err
= esr_write_glue0(np
, i
, glue0
);
2452 sig
= nr64(ESR_INT_SIGNALS
);
2455 mask
= ESR_INT_SIGNALS_P0_BITS
;
2456 val
= (ESR_INT_SRDY0_P0
|
2459 ESR_INT_XDP_P0_CH3
|
2460 ESR_INT_XDP_P0_CH2
|
2461 ESR_INT_XDP_P0_CH1
|
2462 ESR_INT_XDP_P0_CH0
);
2466 mask
= ESR_INT_SIGNALS_P1_BITS
;
2467 val
= (ESR_INT_SRDY0_P1
|
2470 ESR_INT_XDP_P1_CH3
|
2471 ESR_INT_XDP_P1_CH2
|
2472 ESR_INT_XDP_P1_CH1
|
2473 ESR_INT_XDP_P1_CH0
);
2480 if ((sig
& mask
) != val
) {
2482 err
= serdes_init_1g_serdes(np
);
2484 np
->flags
&= ~NIU_FLAGS_10G
;
2485 np
->mac_xcvr
= MAC_XCVR_PCS
;
2487 netdev_err(np
->dev
, "Port %u 10G/1G SERDES Link Failed\n",
2496 static int niu_determine_phy_disposition(struct niu
*np
)
2498 struct niu_parent
*parent
= np
->parent
;
2499 u8 plat_type
= parent
->plat_type
;
2500 const struct niu_phy_template
*tp
;
2501 u32 phy_addr_off
= 0;
2503 if (plat_type
== PLAT_TYPE_NIU
) {
2507 NIU_FLAGS_XCVR_SERDES
)) {
2508 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2510 tp
= &phy_template_niu_10g_serdes
;
2512 case NIU_FLAGS_XCVR_SERDES
:
2514 tp
= &phy_template_niu_1g_serdes
;
2516 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2519 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2520 tp
= &phy_template_niu_10g_hotplug
;
2526 tp
= &phy_template_niu_10g_fiber
;
2527 phy_addr_off
+= np
->port
;
2535 NIU_FLAGS_XCVR_SERDES
)) {
2538 tp
= &phy_template_1g_copper
;
2539 if (plat_type
== PLAT_TYPE_VF_P0
)
2541 else if (plat_type
== PLAT_TYPE_VF_P1
)
2544 phy_addr_off
+= (np
->port
^ 0x3);
2549 tp
= &phy_template_10g_copper
;
2552 case NIU_FLAGS_FIBER
:
2554 tp
= &phy_template_1g_fiber
;
2557 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2559 tp
= &phy_template_10g_fiber
;
2560 if (plat_type
== PLAT_TYPE_VF_P0
||
2561 plat_type
== PLAT_TYPE_VF_P1
)
2563 phy_addr_off
+= np
->port
;
2564 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2565 tp
= &phy_template_10g_fiber_hotplug
;
2573 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2574 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
2575 case NIU_FLAGS_XCVR_SERDES
:
2579 tp
= &phy_template_10g_serdes
;
2583 tp
= &phy_template_1g_rgmii
;
2589 phy_addr_off
= niu_atca_port_num
[np
->port
];
2597 np
->phy_ops
= tp
->ops
;
2598 np
->phy_addr
= tp
->phy_addr_base
+ phy_addr_off
;
2603 static int niu_init_link(struct niu
*np
)
2605 struct niu_parent
*parent
= np
->parent
;
2608 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
2609 err
= niu_xcvr_init(np
);
2614 err
= niu_serdes_init(np
);
2615 if (err
&& !(np
->flags
& NIU_FLAGS_HOTPLUG_PHY
))
2618 err
= niu_xcvr_init(np
);
2619 if (!err
|| (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
))
2620 niu_link_status(np
, &ignore
);
2624 static void niu_set_primary_mac(struct niu
*np
, unsigned char *addr
)
2626 u16 reg0
= addr
[4] << 8 | addr
[5];
2627 u16 reg1
= addr
[2] << 8 | addr
[3];
2628 u16 reg2
= addr
[0] << 8 | addr
[1];
2630 if (np
->flags
& NIU_FLAGS_XMAC
) {
2631 nw64_mac(XMAC_ADDR0
, reg0
);
2632 nw64_mac(XMAC_ADDR1
, reg1
);
2633 nw64_mac(XMAC_ADDR2
, reg2
);
2635 nw64_mac(BMAC_ADDR0
, reg0
);
2636 nw64_mac(BMAC_ADDR1
, reg1
);
2637 nw64_mac(BMAC_ADDR2
, reg2
);
2641 static int niu_num_alt_addr(struct niu
*np
)
2643 if (np
->flags
& NIU_FLAGS_XMAC
)
2644 return XMAC_NUM_ALT_ADDR
;
2646 return BMAC_NUM_ALT_ADDR
;
2649 static int niu_set_alt_mac(struct niu
*np
, int index
, unsigned char *addr
)
2651 u16 reg0
= addr
[4] << 8 | addr
[5];
2652 u16 reg1
= addr
[2] << 8 | addr
[3];
2653 u16 reg2
= addr
[0] << 8 | addr
[1];
2655 if (index
>= niu_num_alt_addr(np
))
2658 if (np
->flags
& NIU_FLAGS_XMAC
) {
2659 nw64_mac(XMAC_ALT_ADDR0(index
), reg0
);
2660 nw64_mac(XMAC_ALT_ADDR1(index
), reg1
);
2661 nw64_mac(XMAC_ALT_ADDR2(index
), reg2
);
2663 nw64_mac(BMAC_ALT_ADDR0(index
), reg0
);
2664 nw64_mac(BMAC_ALT_ADDR1(index
), reg1
);
2665 nw64_mac(BMAC_ALT_ADDR2(index
), reg2
);
2671 static int niu_enable_alt_mac(struct niu
*np
, int index
, int on
)
2676 if (index
>= niu_num_alt_addr(np
))
2679 if (np
->flags
& NIU_FLAGS_XMAC
) {
2680 reg
= XMAC_ADDR_CMPEN
;
2683 reg
= BMAC_ADDR_CMPEN
;
2684 mask
= 1 << (index
+ 1);
2687 val
= nr64_mac(reg
);
2697 static void __set_rdc_table_num_hw(struct niu
*np
, unsigned long reg
,
2698 int num
, int mac_pref
)
2700 u64 val
= nr64_mac(reg
);
2701 val
&= ~(HOST_INFO_MACRDCTBLN
| HOST_INFO_MPR
);
2704 val
|= HOST_INFO_MPR
;
2708 static int __set_rdc_table_num(struct niu
*np
,
2709 int xmac_index
, int bmac_index
,
2710 int rdc_table_num
, int mac_pref
)
2714 if (rdc_table_num
& ~HOST_INFO_MACRDCTBLN
)
2716 if (np
->flags
& NIU_FLAGS_XMAC
)
2717 reg
= XMAC_HOST_INFO(xmac_index
);
2719 reg
= BMAC_HOST_INFO(bmac_index
);
2720 __set_rdc_table_num_hw(np
, reg
, rdc_table_num
, mac_pref
);
2724 static int niu_set_primary_mac_rdc_table(struct niu
*np
, int table_num
,
2727 return __set_rdc_table_num(np
, 17, 0, table_num
, mac_pref
);
2730 static int niu_set_multicast_mac_rdc_table(struct niu
*np
, int table_num
,
2733 return __set_rdc_table_num(np
, 16, 8, table_num
, mac_pref
);
2736 static int niu_set_alt_mac_rdc_table(struct niu
*np
, int idx
,
2737 int table_num
, int mac_pref
)
2739 if (idx
>= niu_num_alt_addr(np
))
2741 return __set_rdc_table_num(np
, idx
, idx
+ 1, table_num
, mac_pref
);
2744 static u64
vlan_entry_set_parity(u64 reg_val
)
2749 port01_mask
= 0x00ff;
2750 port23_mask
= 0xff00;
2752 if (hweight64(reg_val
& port01_mask
) & 1)
2753 reg_val
|= ENET_VLAN_TBL_PARITY0
;
2755 reg_val
&= ~ENET_VLAN_TBL_PARITY0
;
2757 if (hweight64(reg_val
& port23_mask
) & 1)
2758 reg_val
|= ENET_VLAN_TBL_PARITY1
;
2760 reg_val
&= ~ENET_VLAN_TBL_PARITY1
;
2765 static void vlan_tbl_write(struct niu
*np
, unsigned long index
,
2766 int port
, int vpr
, int rdc_table
)
2768 u64 reg_val
= nr64(ENET_VLAN_TBL(index
));
2770 reg_val
&= ~((ENET_VLAN_TBL_VPR
|
2771 ENET_VLAN_TBL_VLANRDCTBLN
) <<
2772 ENET_VLAN_TBL_SHIFT(port
));
2774 reg_val
|= (ENET_VLAN_TBL_VPR
<<
2775 ENET_VLAN_TBL_SHIFT(port
));
2776 reg_val
|= (rdc_table
<< ENET_VLAN_TBL_SHIFT(port
));
2778 reg_val
= vlan_entry_set_parity(reg_val
);
2780 nw64(ENET_VLAN_TBL(index
), reg_val
);
2783 static void vlan_tbl_clear(struct niu
*np
)
2787 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++)
2788 nw64(ENET_VLAN_TBL(i
), 0);
2791 static int tcam_wait_bit(struct niu
*np
, u64 bit
)
2795 while (--limit
> 0) {
2796 if (nr64(TCAM_CTL
) & bit
)
2806 static int tcam_flush(struct niu
*np
, int index
)
2808 nw64(TCAM_KEY_0
, 0x00);
2809 nw64(TCAM_KEY_MASK_0
, 0xff);
2810 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2812 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2816 static int tcam_read(struct niu
*np
, int index
,
2817 u64
*key
, u64
*mask
)
2821 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_READ
| index
));
2822 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2824 key
[0] = nr64(TCAM_KEY_0
);
2825 key
[1] = nr64(TCAM_KEY_1
);
2826 key
[2] = nr64(TCAM_KEY_2
);
2827 key
[3] = nr64(TCAM_KEY_3
);
2828 mask
[0] = nr64(TCAM_KEY_MASK_0
);
2829 mask
[1] = nr64(TCAM_KEY_MASK_1
);
2830 mask
[2] = nr64(TCAM_KEY_MASK_2
);
2831 mask
[3] = nr64(TCAM_KEY_MASK_3
);
2837 static int tcam_write(struct niu
*np
, int index
,
2838 u64
*key
, u64
*mask
)
2840 nw64(TCAM_KEY_0
, key
[0]);
2841 nw64(TCAM_KEY_1
, key
[1]);
2842 nw64(TCAM_KEY_2
, key
[2]);
2843 nw64(TCAM_KEY_3
, key
[3]);
2844 nw64(TCAM_KEY_MASK_0
, mask
[0]);
2845 nw64(TCAM_KEY_MASK_1
, mask
[1]);
2846 nw64(TCAM_KEY_MASK_2
, mask
[2]);
2847 nw64(TCAM_KEY_MASK_3
, mask
[3]);
2848 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2850 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2854 static int tcam_assoc_read(struct niu
*np
, int index
, u64
*data
)
2858 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_READ
| index
));
2859 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2861 *data
= nr64(TCAM_KEY_1
);
2867 static int tcam_assoc_write(struct niu
*np
, int index
, u64 assoc_data
)
2869 nw64(TCAM_KEY_1
, assoc_data
);
2870 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_WRITE
| index
));
2872 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2875 static void tcam_enable(struct niu
*np
, int on
)
2877 u64 val
= nr64(FFLP_CFG_1
);
2880 val
&= ~FFLP_CFG_1_TCAM_DIS
;
2882 val
|= FFLP_CFG_1_TCAM_DIS
;
2883 nw64(FFLP_CFG_1
, val
);
2886 static void tcam_set_lat_and_ratio(struct niu
*np
, u64 latency
, u64 ratio
)
2888 u64 val
= nr64(FFLP_CFG_1
);
2890 val
&= ~(FFLP_CFG_1_FFLPINITDONE
|
2892 FFLP_CFG_1_CAMRATIO
);
2893 val
|= (latency
<< FFLP_CFG_1_CAMLAT_SHIFT
);
2894 val
|= (ratio
<< FFLP_CFG_1_CAMRATIO_SHIFT
);
2895 nw64(FFLP_CFG_1
, val
);
2897 val
= nr64(FFLP_CFG_1
);
2898 val
|= FFLP_CFG_1_FFLPINITDONE
;
2899 nw64(FFLP_CFG_1
, val
);
2902 static int tcam_user_eth_class_enable(struct niu
*np
, unsigned long class,
2908 if (class < CLASS_CODE_ETHERTYPE1
||
2909 class > CLASS_CODE_ETHERTYPE2
)
2912 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2924 static int tcam_user_eth_class_set(struct niu
*np
, unsigned long class,
2930 if (class < CLASS_CODE_ETHERTYPE1
||
2931 class > CLASS_CODE_ETHERTYPE2
||
2932 (ether_type
& ~(u64
)0xffff) != 0)
2935 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2937 val
&= ~L2_CLS_ETYPE
;
2938 val
|= (ether_type
<< L2_CLS_ETYPE_SHIFT
);
2945 static int tcam_user_ip_class_enable(struct niu
*np
, unsigned long class,
2951 if (class < CLASS_CODE_USER_PROG1
||
2952 class > CLASS_CODE_USER_PROG4
)
2955 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
2958 val
|= L3_CLS_VALID
;
2960 val
&= ~L3_CLS_VALID
;
2966 static int tcam_user_ip_class_set(struct niu
*np
, unsigned long class,
2967 int ipv6
, u64 protocol_id
,
2968 u64 tos_mask
, u64 tos_val
)
2973 if (class < CLASS_CODE_USER_PROG1
||
2974 class > CLASS_CODE_USER_PROG4
||
2975 (protocol_id
& ~(u64
)0xff) != 0 ||
2976 (tos_mask
& ~(u64
)0xff) != 0 ||
2977 (tos_val
& ~(u64
)0xff) != 0)
2980 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
2982 val
&= ~(L3_CLS_IPVER
| L3_CLS_PID
|
2983 L3_CLS_TOSMASK
| L3_CLS_TOS
);
2985 val
|= L3_CLS_IPVER
;
2986 val
|= (protocol_id
<< L3_CLS_PID_SHIFT
);
2987 val
|= (tos_mask
<< L3_CLS_TOSMASK_SHIFT
);
2988 val
|= (tos_val
<< L3_CLS_TOS_SHIFT
);
2994 static int tcam_early_init(struct niu
*np
)
3000 tcam_set_lat_and_ratio(np
,
3001 DEFAULT_TCAM_LATENCY
,
3002 DEFAULT_TCAM_ACCESS_RATIO
);
3003 for (i
= CLASS_CODE_ETHERTYPE1
; i
<= CLASS_CODE_ETHERTYPE2
; i
++) {
3004 err
= tcam_user_eth_class_enable(np
, i
, 0);
3008 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_USER_PROG4
; i
++) {
3009 err
= tcam_user_ip_class_enable(np
, i
, 0);
3017 static int tcam_flush_all(struct niu
*np
)
3021 for (i
= 0; i
< np
->parent
->tcam_num_entries
; i
++) {
3022 int err
= tcam_flush(np
, i
);
3029 static u64
hash_addr_regval(unsigned long index
, unsigned long num_entries
)
3031 return (u64
)index
| (num_entries
== 1 ? HASH_TBL_ADDR_AUTOINC
: 0);
3035 static int hash_read(struct niu
*np
, unsigned long partition
,
3036 unsigned long index
, unsigned long num_entries
,
3039 u64 val
= hash_addr_regval(index
, num_entries
);
3042 if (partition
>= FCRAM_NUM_PARTITIONS
||
3043 index
+ num_entries
> FCRAM_SIZE
)
3046 nw64(HASH_TBL_ADDR(partition
), val
);
3047 for (i
= 0; i
< num_entries
; i
++)
3048 data
[i
] = nr64(HASH_TBL_DATA(partition
));
3054 static int hash_write(struct niu
*np
, unsigned long partition
,
3055 unsigned long index
, unsigned long num_entries
,
3058 u64 val
= hash_addr_regval(index
, num_entries
);
3061 if (partition
>= FCRAM_NUM_PARTITIONS
||
3062 index
+ (num_entries
* 8) > FCRAM_SIZE
)
3065 nw64(HASH_TBL_ADDR(partition
), val
);
3066 for (i
= 0; i
< num_entries
; i
++)
3067 nw64(HASH_TBL_DATA(partition
), data
[i
]);
3072 static void fflp_reset(struct niu
*np
)
3076 nw64(FFLP_CFG_1
, FFLP_CFG_1_PIO_FIO_RST
);
3078 nw64(FFLP_CFG_1
, 0);
3080 val
= FFLP_CFG_1_FCRAMOUTDR_NORMAL
| FFLP_CFG_1_FFLPINITDONE
;
3081 nw64(FFLP_CFG_1
, val
);
3084 static void fflp_set_timings(struct niu
*np
)
3086 u64 val
= nr64(FFLP_CFG_1
);
3088 val
&= ~FFLP_CFG_1_FFLPINITDONE
;
3089 val
|= (DEFAULT_FCRAMRATIO
<< FFLP_CFG_1_FCRAMRATIO_SHIFT
);
3090 nw64(FFLP_CFG_1
, val
);
3092 val
= nr64(FFLP_CFG_1
);
3093 val
|= FFLP_CFG_1_FFLPINITDONE
;
3094 nw64(FFLP_CFG_1
, val
);
3096 val
= nr64(FCRAM_REF_TMR
);
3097 val
&= ~(FCRAM_REF_TMR_MAX
| FCRAM_REF_TMR_MIN
);
3098 val
|= (DEFAULT_FCRAM_REFRESH_MAX
<< FCRAM_REF_TMR_MAX_SHIFT
);
3099 val
|= (DEFAULT_FCRAM_REFRESH_MIN
<< FCRAM_REF_TMR_MIN_SHIFT
);
3100 nw64(FCRAM_REF_TMR
, val
);
3103 static int fflp_set_partition(struct niu
*np
, u64 partition
,
3104 u64 mask
, u64 base
, int enable
)
3109 if (partition
>= FCRAM_NUM_PARTITIONS
||
3110 (mask
& ~(u64
)0x1f) != 0 ||
3111 (base
& ~(u64
)0x1f) != 0)
3114 reg
= FLW_PRT_SEL(partition
);
3117 val
&= ~(FLW_PRT_SEL_EXT
| FLW_PRT_SEL_MASK
| FLW_PRT_SEL_BASE
);
3118 val
|= (mask
<< FLW_PRT_SEL_MASK_SHIFT
);
3119 val
|= (base
<< FLW_PRT_SEL_BASE_SHIFT
);
3121 val
|= FLW_PRT_SEL_EXT
;
3127 static int fflp_disable_all_partitions(struct niu
*np
)
3131 for (i
= 0; i
< FCRAM_NUM_PARTITIONS
; i
++) {
3132 int err
= fflp_set_partition(np
, 0, 0, 0, 0);
3139 static void fflp_llcsnap_enable(struct niu
*np
, int on
)
3141 u64 val
= nr64(FFLP_CFG_1
);
3144 val
|= FFLP_CFG_1_LLCSNAP
;
3146 val
&= ~FFLP_CFG_1_LLCSNAP
;
3147 nw64(FFLP_CFG_1
, val
);
3150 static void fflp_errors_enable(struct niu
*np
, int on
)
3152 u64 val
= nr64(FFLP_CFG_1
);
3155 val
&= ~FFLP_CFG_1_ERRORDIS
;
3157 val
|= FFLP_CFG_1_ERRORDIS
;
3158 nw64(FFLP_CFG_1
, val
);
3161 static int fflp_hash_clear(struct niu
*np
)
3163 struct fcram_hash_ipv4 ent
;
3166 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3167 memset(&ent
, 0, sizeof(ent
));
3168 ent
.header
= HASH_HEADER_EXT
;
3170 for (i
= 0; i
< FCRAM_SIZE
; i
+= sizeof(ent
)) {
3171 int err
= hash_write(np
, 0, i
, 1, (u64
*) &ent
);
3178 static int fflp_early_init(struct niu
*np
)
3180 struct niu_parent
*parent
;
3181 unsigned long flags
;
3184 niu_lock_parent(np
, flags
);
3186 parent
= np
->parent
;
3188 if (!(parent
->flags
& PARENT_FLGS_CLS_HWINIT
)) {
3189 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
3191 fflp_set_timings(np
);
3192 err
= fflp_disable_all_partitions(np
);
3194 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3195 "fflp_disable_all_partitions failed, err=%d\n",
3201 err
= tcam_early_init(np
);
3203 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3204 "tcam_early_init failed, err=%d\n", err
);
3207 fflp_llcsnap_enable(np
, 1);
3208 fflp_errors_enable(np
, 0);
3212 err
= tcam_flush_all(np
);
3214 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3215 "tcam_flush_all failed, err=%d\n", err
);
3218 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
3219 err
= fflp_hash_clear(np
);
3221 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3222 "fflp_hash_clear failed, err=%d\n",
3230 parent
->flags
|= PARENT_FLGS_CLS_HWINIT
;
3233 niu_unlock_parent(np
, flags
);
3237 static int niu_set_flow_key(struct niu
*np
, unsigned long class_code
, u64 key
)
3239 if (class_code
< CLASS_CODE_USER_PROG1
||
3240 class_code
> CLASS_CODE_SCTP_IPV6
)
3243 nw64(FLOW_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
3247 static int niu_set_tcam_key(struct niu
*np
, unsigned long class_code
, u64 key
)
3249 if (class_code
< CLASS_CODE_USER_PROG1
||
3250 class_code
> CLASS_CODE_SCTP_IPV6
)
3253 nw64(TCAM_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
3257 /* Entries for the ports are interleaved in the TCAM */
3258 static u16
tcam_get_index(struct niu
*np
, u16 idx
)
3260 /* One entry reserved for IP fragment rule */
3261 if (idx
>= (np
->clas
.tcam_sz
- 1))
3263 return np
->clas
.tcam_top
+ ((idx
+1) * np
->parent
->num_ports
);
3266 static u16
tcam_get_size(struct niu
*np
)
3268 /* One entry reserved for IP fragment rule */
3269 return np
->clas
.tcam_sz
- 1;
3272 static u16
tcam_get_valid_entry_cnt(struct niu
*np
)
3274 /* One entry reserved for IP fragment rule */
3275 return np
->clas
.tcam_valid_entries
- 1;
3278 static void niu_rx_skb_append(struct sk_buff
*skb
, struct page
*page
,
3279 u32 offset
, u32 size
, u32 truesize
)
3281 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
, page
, offset
, size
);
3284 skb
->data_len
+= size
;
3285 skb
->truesize
+= truesize
;
3288 static unsigned int niu_hash_rxaddr(struct rx_ring_info
*rp
, u64 a
)
3291 a
^= (a
>> ilog2(MAX_RBR_RING_SIZE
));
3293 return a
& (MAX_RBR_RING_SIZE
- 1);
3296 static struct page
*niu_find_rxpage(struct rx_ring_info
*rp
, u64 addr
,
3297 struct page
***link
)
3299 unsigned int h
= niu_hash_rxaddr(rp
, addr
);
3300 struct page
*p
, **pp
;
3303 pp
= &rp
->rxhash
[h
];
3304 for (; (p
= *pp
) != NULL
; pp
= (struct page
**) &p
->mapping
) {
3305 if (p
->index
== addr
) {
3316 static void niu_hash_page(struct rx_ring_info
*rp
, struct page
*page
, u64 base
)
3318 unsigned int h
= niu_hash_rxaddr(rp
, base
);
3321 page
->mapping
= (struct address_space
*) rp
->rxhash
[h
];
3322 rp
->rxhash
[h
] = page
;
3325 static int niu_rbr_add_page(struct niu
*np
, struct rx_ring_info
*rp
,
3326 gfp_t mask
, int start_index
)
3332 page
= alloc_page(mask
);
3336 addr
= np
->ops
->map_page(np
->device
, page
, 0,
3337 PAGE_SIZE
, DMA_FROM_DEVICE
);
3343 niu_hash_page(rp
, page
, addr
);
3344 if (rp
->rbr_blocks_per_page
> 1)
3345 atomic_add(rp
->rbr_blocks_per_page
- 1,
3346 &compound_head(page
)->_count
);
3348 for (i
= 0; i
< rp
->rbr_blocks_per_page
; i
++) {
3349 __le32
*rbr
= &rp
->rbr
[start_index
+ i
];
3351 *rbr
= cpu_to_le32(addr
>> RBR_DESCR_ADDR_SHIFT
);
3352 addr
+= rp
->rbr_block_size
;
3358 static void niu_rbr_refill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3360 int index
= rp
->rbr_index
;
3363 if ((rp
->rbr_pending
% rp
->rbr_blocks_per_page
) == 0) {
3364 int err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3366 if (unlikely(err
)) {
3371 rp
->rbr_index
+= rp
->rbr_blocks_per_page
;
3372 BUG_ON(rp
->rbr_index
> rp
->rbr_table_size
);
3373 if (rp
->rbr_index
== rp
->rbr_table_size
)
3376 if (rp
->rbr_pending
>= rp
->rbr_kick_thresh
) {
3377 nw64(RBR_KICK(rp
->rx_channel
), rp
->rbr_pending
);
3378 rp
->rbr_pending
= 0;
3383 static int niu_rx_pkt_ignore(struct niu
*np
, struct rx_ring_info
*rp
)
3385 unsigned int index
= rp
->rcr_index
;
3390 struct page
*page
, **link
;
3396 val
= le64_to_cpup(&rp
->rcr
[index
]);
3397 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3398 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3399 page
= niu_find_rxpage(rp
, addr
, &link
);
3401 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3402 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3403 if ((page
->index
+ PAGE_SIZE
) - rcr_size
== addr
) {
3404 *link
= (struct page
*) page
->mapping
;
3405 np
->ops
->unmap_page(np
->device
, page
->index
,
3406 PAGE_SIZE
, DMA_FROM_DEVICE
);
3408 page
->mapping
= NULL
;
3410 rp
->rbr_refill_pending
++;
3413 index
= NEXT_RCR(rp
, index
);
3414 if (!(val
& RCR_ENTRY_MULTI
))
3418 rp
->rcr_index
= index
;
3423 static int niu_process_rx_pkt(struct napi_struct
*napi
, struct niu
*np
,
3424 struct rx_ring_info
*rp
)
3426 unsigned int index
= rp
->rcr_index
;
3427 struct rx_pkt_hdr1
*rh
;
3428 struct sk_buff
*skb
;
3431 skb
= netdev_alloc_skb(np
->dev
, RX_SKB_ALLOC_SIZE
);
3433 return niu_rx_pkt_ignore(np
, rp
);
3437 struct page
*page
, **link
;
3438 u32 rcr_size
, append_size
;
3443 val
= le64_to_cpup(&rp
->rcr
[index
]);
3445 len
= (val
& RCR_ENTRY_L2_LEN
) >>
3446 RCR_ENTRY_L2_LEN_SHIFT
;
3449 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3450 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3451 page
= niu_find_rxpage(rp
, addr
, &link
);
3453 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3454 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3456 off
= addr
& ~PAGE_MASK
;
3457 append_size
= rcr_size
;
3461 ptype
= (val
>> RCR_ENTRY_PKT_TYPE_SHIFT
);
3462 if ((ptype
== RCR_PKT_TYPE_TCP
||
3463 ptype
== RCR_PKT_TYPE_UDP
) &&
3464 !(val
& (RCR_ENTRY_NOPORT
|
3466 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3468 skb_checksum_none_assert(skb
);
3469 } else if (!(val
& RCR_ENTRY_MULTI
))
3470 append_size
= len
- skb
->len
;
3472 niu_rx_skb_append(skb
, page
, off
, append_size
, rcr_size
);
3473 if ((page
->index
+ rp
->rbr_block_size
) - rcr_size
== addr
) {
3474 *link
= (struct page
*) page
->mapping
;
3475 np
->ops
->unmap_page(np
->device
, page
->index
,
3476 PAGE_SIZE
, DMA_FROM_DEVICE
);
3478 page
->mapping
= NULL
;
3479 rp
->rbr_refill_pending
++;
3483 index
= NEXT_RCR(rp
, index
);
3484 if (!(val
& RCR_ENTRY_MULTI
))
3488 rp
->rcr_index
= index
;
3491 len
= min_t(int, len
, sizeof(*rh
) + VLAN_ETH_HLEN
);
3492 __pskb_pull_tail(skb
, len
);
3494 rh
= (struct rx_pkt_hdr1
*) skb
->data
;
3495 if (np
->dev
->features
& NETIF_F_RXHASH
)
3496 skb
->rxhash
= ((u32
)rh
->hashval2_0
<< 24 |
3497 (u32
)rh
->hashval2_1
<< 16 |
3498 (u32
)rh
->hashval1_1
<< 8 |
3499 (u32
)rh
->hashval1_2
<< 0);
3500 skb_pull(skb
, sizeof(*rh
));
3503 rp
->rx_bytes
+= skb
->len
;
3505 skb
->protocol
= eth_type_trans(skb
, np
->dev
);
3506 skb_record_rx_queue(skb
, rp
->rx_channel
);
3507 napi_gro_receive(napi
, skb
);
3512 static int niu_rbr_fill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3514 int blocks_per_page
= rp
->rbr_blocks_per_page
;
3515 int err
, index
= rp
->rbr_index
;
3518 while (index
< (rp
->rbr_table_size
- blocks_per_page
)) {
3519 err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3523 index
+= blocks_per_page
;
3526 rp
->rbr_index
= index
;
3530 static void niu_rbr_free(struct niu
*np
, struct rx_ring_info
*rp
)
3534 for (i
= 0; i
< MAX_RBR_RING_SIZE
; i
++) {
3537 page
= rp
->rxhash
[i
];
3539 struct page
*next
= (struct page
*) page
->mapping
;
3540 u64 base
= page
->index
;
3542 np
->ops
->unmap_page(np
->device
, base
, PAGE_SIZE
,
3545 page
->mapping
= NULL
;
3553 for (i
= 0; i
< rp
->rbr_table_size
; i
++)
3554 rp
->rbr
[i
] = cpu_to_le32(0);
3558 static int release_tx_packet(struct niu
*np
, struct tx_ring_info
*rp
, int idx
)
3560 struct tx_buff_info
*tb
= &rp
->tx_buffs
[idx
];
3561 struct sk_buff
*skb
= tb
->skb
;
3562 struct tx_pkt_hdr
*tp
;
3566 tp
= (struct tx_pkt_hdr
*) skb
->data
;
3567 tx_flags
= le64_to_cpup(&tp
->flags
);
3570 rp
->tx_bytes
+= (((tx_flags
& TXHDR_LEN
) >> TXHDR_LEN_SHIFT
) -
3571 ((tx_flags
& TXHDR_PAD
) / 2));
3573 len
= skb_headlen(skb
);
3574 np
->ops
->unmap_single(np
->device
, tb
->mapping
,
3575 len
, DMA_TO_DEVICE
);
3577 if (le64_to_cpu(rp
->descr
[idx
]) & TX_DESC_MARK
)
3582 idx
= NEXT_TX(rp
, idx
);
3583 len
-= MAX_TX_DESC_LEN
;
3586 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
3587 tb
= &rp
->tx_buffs
[idx
];
3588 BUG_ON(tb
->skb
!= NULL
);
3589 np
->ops
->unmap_page(np
->device
, tb
->mapping
,
3590 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
3592 idx
= NEXT_TX(rp
, idx
);
3600 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3602 static void niu_tx_work(struct niu
*np
, struct tx_ring_info
*rp
)
3604 struct netdev_queue
*txq
;
3609 index
= (rp
- np
->tx_rings
);
3610 txq
= netdev_get_tx_queue(np
->dev
, index
);
3613 if (unlikely(!(cs
& (TX_CS_MK
| TX_CS_MMK
))))
3616 tmp
= pkt_cnt
= (cs
& TX_CS_PKT_CNT
) >> TX_CS_PKT_CNT_SHIFT
;
3617 pkt_cnt
= (pkt_cnt
- rp
->last_pkt_cnt
) &
3618 (TX_CS_PKT_CNT
>> TX_CS_PKT_CNT_SHIFT
);
3620 rp
->last_pkt_cnt
= tmp
;
3624 netif_printk(np
, tx_done
, KERN_DEBUG
, np
->dev
,
3625 "%s() pkt_cnt[%u] cons[%d]\n", __func__
, pkt_cnt
, cons
);
3628 cons
= release_tx_packet(np
, rp
, cons
);
3634 if (unlikely(netif_tx_queue_stopped(txq
) &&
3635 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))) {
3636 __netif_tx_lock(txq
, smp_processor_id());
3637 if (netif_tx_queue_stopped(txq
) &&
3638 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))
3639 netif_tx_wake_queue(txq
);
3640 __netif_tx_unlock(txq
);
3644 static inline void niu_sync_rx_discard_stats(struct niu
*np
,
3645 struct rx_ring_info
*rp
,
3648 /* This elaborate scheme is needed for reading the RX discard
3649 * counters, as they are only 16-bit and can overflow quickly,
3650 * and because the overflow indication bit is not usable as
3651 * the counter value does not wrap, but remains at max value
3654 * In theory and in practice counters can be lost in between
3655 * reading nr64() and clearing the counter nw64(). For this
3656 * reason, the number of counter clearings nw64() is
3657 * limited/reduced though the limit parameter.
3659 int rx_channel
= rp
->rx_channel
;
3662 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3663 * following discard events: IPP (Input Port Process),
3664 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3665 * Block Ring) prefetch buffer is empty.
3667 misc
= nr64(RXMISC(rx_channel
));
3668 if (unlikely((misc
& RXMISC_COUNT
) > limit
)) {
3669 nw64(RXMISC(rx_channel
), 0);
3670 rp
->rx_errors
+= misc
& RXMISC_COUNT
;
3672 if (unlikely(misc
& RXMISC_OFLOW
))
3673 dev_err(np
->device
, "rx-%d: Counter overflow RXMISC discard\n",
3676 netif_printk(np
, rx_err
, KERN_DEBUG
, np
->dev
,
3677 "rx-%d: MISC drop=%u over=%u\n",
3678 rx_channel
, misc
, misc
-limit
);
3681 /* WRED (Weighted Random Early Discard) by hardware */
3682 wred
= nr64(RED_DIS_CNT(rx_channel
));
3683 if (unlikely((wred
& RED_DIS_CNT_COUNT
) > limit
)) {
3684 nw64(RED_DIS_CNT(rx_channel
), 0);
3685 rp
->rx_dropped
+= wred
& RED_DIS_CNT_COUNT
;
3687 if (unlikely(wred
& RED_DIS_CNT_OFLOW
))
3688 dev_err(np
->device
, "rx-%d: Counter overflow WRED discard\n", rx_channel
);
3690 netif_printk(np
, rx_err
, KERN_DEBUG
, np
->dev
,
3691 "rx-%d: WRED drop=%u over=%u\n",
3692 rx_channel
, wred
, wred
-limit
);
3696 static int niu_rx_work(struct napi_struct
*napi
, struct niu
*np
,
3697 struct rx_ring_info
*rp
, int budget
)
3699 int qlen
, rcr_done
= 0, work_done
= 0;
3700 struct rxdma_mailbox
*mbox
= rp
->mbox
;
3704 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3705 qlen
= nr64(RCRSTAT_A(rp
->rx_channel
)) & RCRSTAT_A_QLEN
;
3707 stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
3708 qlen
= (le64_to_cpup(&mbox
->rcrstat_a
) & RCRSTAT_A_QLEN
);
3710 mbox
->rx_dma_ctl_stat
= 0;
3711 mbox
->rcrstat_a
= 0;
3713 netif_printk(np
, rx_status
, KERN_DEBUG
, np
->dev
,
3714 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3715 __func__
, rp
->rx_channel
, (unsigned long long)stat
, qlen
);
3717 rcr_done
= work_done
= 0;
3718 qlen
= min(qlen
, budget
);
3719 while (work_done
< qlen
) {
3720 rcr_done
+= niu_process_rx_pkt(napi
, np
, rp
);
3724 if (rp
->rbr_refill_pending
>= rp
->rbr_kick_thresh
) {
3727 for (i
= 0; i
< rp
->rbr_refill_pending
; i
++)
3728 niu_rbr_refill(np
, rp
, GFP_ATOMIC
);
3729 rp
->rbr_refill_pending
= 0;
3732 stat
= (RX_DMA_CTL_STAT_MEX
|
3733 ((u64
)work_done
<< RX_DMA_CTL_STAT_PKTREAD_SHIFT
) |
3734 ((u64
)rcr_done
<< RX_DMA_CTL_STAT_PTRREAD_SHIFT
));
3736 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat
);
3738 /* Only sync discards stats when qlen indicate potential for drops */
3740 niu_sync_rx_discard_stats(np
, rp
, 0x7FFF);
3745 static int niu_poll_core(struct niu
*np
, struct niu_ldg
*lp
, int budget
)
3748 u32 tx_vec
= (v0
>> 32);
3749 u32 rx_vec
= (v0
& 0xffffffff);
3750 int i
, work_done
= 0;
3752 netif_printk(np
, intr
, KERN_DEBUG
, np
->dev
,
3753 "%s() v0[%016llx]\n", __func__
, (unsigned long long)v0
);
3755 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3756 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3757 if (tx_vec
& (1 << rp
->tx_channel
))
3758 niu_tx_work(np
, rp
);
3759 nw64(LD_IM0(LDN_TXDMA(rp
->tx_channel
)), 0);
3762 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3763 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3765 if (rx_vec
& (1 << rp
->rx_channel
)) {
3768 this_work_done
= niu_rx_work(&lp
->napi
, np
, rp
,
3771 budget
-= this_work_done
;
3772 work_done
+= this_work_done
;
3774 nw64(LD_IM0(LDN_RXDMA(rp
->rx_channel
)), 0);
3780 static int niu_poll(struct napi_struct
*napi
, int budget
)
3782 struct niu_ldg
*lp
= container_of(napi
, struct niu_ldg
, napi
);
3783 struct niu
*np
= lp
->np
;
3786 work_done
= niu_poll_core(np
, lp
, budget
);
3788 if (work_done
< budget
) {
3789 napi_complete(napi
);
3790 niu_ldg_rearm(np
, lp
, 1);
3795 static void niu_log_rxchan_errors(struct niu
*np
, struct rx_ring_info
*rp
,
3798 netdev_err(np
->dev
, "RX channel %u errors ( ", rp
->rx_channel
);
3800 if (stat
& RX_DMA_CTL_STAT_RBR_TMOUT
)
3801 pr_cont("RBR_TMOUT ");
3802 if (stat
& RX_DMA_CTL_STAT_RSP_CNT_ERR
)
3803 pr_cont("RSP_CNT ");
3804 if (stat
& RX_DMA_CTL_STAT_BYTE_EN_BUS
)
3805 pr_cont("BYTE_EN_BUS ");
3806 if (stat
& RX_DMA_CTL_STAT_RSP_DAT_ERR
)
3807 pr_cont("RSP_DAT ");
3808 if (stat
& RX_DMA_CTL_STAT_RCR_ACK_ERR
)
3809 pr_cont("RCR_ACK ");
3810 if (stat
& RX_DMA_CTL_STAT_RCR_SHA_PAR
)
3811 pr_cont("RCR_SHA_PAR ");
3812 if (stat
& RX_DMA_CTL_STAT_RBR_PRE_PAR
)
3813 pr_cont("RBR_PRE_PAR ");
3814 if (stat
& RX_DMA_CTL_STAT_CONFIG_ERR
)
3816 if (stat
& RX_DMA_CTL_STAT_RCRINCON
)
3817 pr_cont("RCRINCON ");
3818 if (stat
& RX_DMA_CTL_STAT_RCRFULL
)
3819 pr_cont("RCRFULL ");
3820 if (stat
& RX_DMA_CTL_STAT_RBRFULL
)
3821 pr_cont("RBRFULL ");
3822 if (stat
& RX_DMA_CTL_STAT_RBRLOGPAGE
)
3823 pr_cont("RBRLOGPAGE ");
3824 if (stat
& RX_DMA_CTL_STAT_CFIGLOGPAGE
)
3825 pr_cont("CFIGLOGPAGE ");
3826 if (stat
& RX_DMA_CTL_STAT_DC_FIFO_ERR
)
3827 pr_cont("DC_FIDO ");
3832 static int niu_rx_error(struct niu
*np
, struct rx_ring_info
*rp
)
3834 u64 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3838 if (stat
& (RX_DMA_CTL_STAT_CHAN_FATAL
|
3839 RX_DMA_CTL_STAT_PORT_FATAL
))
3843 netdev_err(np
->dev
, "RX channel %u error, stat[%llx]\n",
3845 (unsigned long long) stat
);
3847 niu_log_rxchan_errors(np
, rp
, stat
);
3850 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
3851 stat
& RX_DMA_CTL_WRITE_CLEAR_ERRS
);
3856 static void niu_log_txchan_errors(struct niu
*np
, struct tx_ring_info
*rp
,
3859 netdev_err(np
->dev
, "TX channel %u errors ( ", rp
->tx_channel
);
3861 if (cs
& TX_CS_MBOX_ERR
)
3863 if (cs
& TX_CS_PKT_SIZE_ERR
)
3864 pr_cont("PKT_SIZE ");
3865 if (cs
& TX_CS_TX_RING_OFLOW
)
3866 pr_cont("TX_RING_OFLOW ");
3867 if (cs
& TX_CS_PREF_BUF_PAR_ERR
)
3868 pr_cont("PREF_BUF_PAR ");
3869 if (cs
& TX_CS_NACK_PREF
)
3870 pr_cont("NACK_PREF ");
3871 if (cs
& TX_CS_NACK_PKT_RD
)
3872 pr_cont("NACK_PKT_RD ");
3873 if (cs
& TX_CS_CONF_PART_ERR
)
3874 pr_cont("CONF_PART ");
3875 if (cs
& TX_CS_PKT_PRT_ERR
)
3876 pr_cont("PKT_PTR ");
3881 static int niu_tx_error(struct niu
*np
, struct tx_ring_info
*rp
)
3885 cs
= nr64(TX_CS(rp
->tx_channel
));
3886 logh
= nr64(TX_RNG_ERR_LOGH(rp
->tx_channel
));
3887 logl
= nr64(TX_RNG_ERR_LOGL(rp
->tx_channel
));
3889 netdev_err(np
->dev
, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3891 (unsigned long long)cs
,
3892 (unsigned long long)logh
,
3893 (unsigned long long)logl
);
3895 niu_log_txchan_errors(np
, rp
, cs
);
3900 static int niu_mif_interrupt(struct niu
*np
)
3902 u64 mif_status
= nr64(MIF_STATUS
);
3905 if (np
->flags
& NIU_FLAGS_XMAC
) {
3906 u64 xrxmac_stat
= nr64_mac(XRXMAC_STATUS
);
3908 if (xrxmac_stat
& XRXMAC_STATUS_PHY_MDINT
)
3912 netdev_err(np
->dev
, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3913 (unsigned long long)mif_status
, phy_mdint
);
3918 static void niu_xmac_interrupt(struct niu
*np
)
3920 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
3923 val
= nr64_mac(XTXMAC_STATUS
);
3924 if (val
& XTXMAC_STATUS_FRAME_CNT_EXP
)
3925 mp
->tx_frames
+= TXMAC_FRM_CNT_COUNT
;
3926 if (val
& XTXMAC_STATUS_BYTE_CNT_EXP
)
3927 mp
->tx_bytes
+= TXMAC_BYTE_CNT_COUNT
;
3928 if (val
& XTXMAC_STATUS_TXFIFO_XFR_ERR
)
3929 mp
->tx_fifo_errors
++;
3930 if (val
& XTXMAC_STATUS_TXMAC_OFLOW
)
3931 mp
->tx_overflow_errors
++;
3932 if (val
& XTXMAC_STATUS_MAX_PSIZE_ERR
)
3933 mp
->tx_max_pkt_size_errors
++;
3934 if (val
& XTXMAC_STATUS_TXMAC_UFLOW
)
3935 mp
->tx_underflow_errors
++;
3937 val
= nr64_mac(XRXMAC_STATUS
);
3938 if (val
& XRXMAC_STATUS_LCL_FLT_STATUS
)
3939 mp
->rx_local_faults
++;
3940 if (val
& XRXMAC_STATUS_RFLT_DET
)
3941 mp
->rx_remote_faults
++;
3942 if (val
& XRXMAC_STATUS_LFLT_CNT_EXP
)
3943 mp
->rx_link_faults
+= LINK_FAULT_CNT_COUNT
;
3944 if (val
& XRXMAC_STATUS_ALIGNERR_CNT_EXP
)
3945 mp
->rx_align_errors
+= RXMAC_ALIGN_ERR_CNT_COUNT
;
3946 if (val
& XRXMAC_STATUS_RXFRAG_CNT_EXP
)
3947 mp
->rx_frags
+= RXMAC_FRAG_CNT_COUNT
;
3948 if (val
& XRXMAC_STATUS_RXMULTF_CNT_EXP
)
3949 mp
->rx_mcasts
+= RXMAC_MC_FRM_CNT_COUNT
;
3950 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3951 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3952 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3953 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3954 if (val
& XRXMAC_STATUS_RXHIST1_CNT_EXP
)
3955 mp
->rx_hist_cnt1
+= RXMAC_HIST_CNT1_COUNT
;
3956 if (val
& XRXMAC_STATUS_RXHIST2_CNT_EXP
)
3957 mp
->rx_hist_cnt2
+= RXMAC_HIST_CNT2_COUNT
;
3958 if (val
& XRXMAC_STATUS_RXHIST3_CNT_EXP
)
3959 mp
->rx_hist_cnt3
+= RXMAC_HIST_CNT3_COUNT
;
3960 if (val
& XRXMAC_STATUS_RXHIST4_CNT_EXP
)
3961 mp
->rx_hist_cnt4
+= RXMAC_HIST_CNT4_COUNT
;
3962 if (val
& XRXMAC_STATUS_RXHIST5_CNT_EXP
)
3963 mp
->rx_hist_cnt5
+= RXMAC_HIST_CNT5_COUNT
;
3964 if (val
& XRXMAC_STATUS_RXHIST6_CNT_EXP
)
3965 mp
->rx_hist_cnt6
+= RXMAC_HIST_CNT6_COUNT
;
3966 if (val
& XRXMAC_STATUS_RXHIST7_CNT_EXP
)
3967 mp
->rx_hist_cnt7
+= RXMAC_HIST_CNT7_COUNT
;
3968 if (val
& XRXMAC_STATUS_RXOCTET_CNT_EXP
)
3969 mp
->rx_octets
+= RXMAC_BT_CNT_COUNT
;
3970 if (val
& XRXMAC_STATUS_CVIOLERR_CNT_EXP
)
3971 mp
->rx_code_violations
+= RXMAC_CD_VIO_CNT_COUNT
;
3972 if (val
& XRXMAC_STATUS_LENERR_CNT_EXP
)
3973 mp
->rx_len_errors
+= RXMAC_MPSZER_CNT_COUNT
;
3974 if (val
& XRXMAC_STATUS_CRCERR_CNT_EXP
)
3975 mp
->rx_crc_errors
+= RXMAC_CRC_ER_CNT_COUNT
;
3976 if (val
& XRXMAC_STATUS_RXUFLOW
)
3977 mp
->rx_underflows
++;
3978 if (val
& XRXMAC_STATUS_RXOFLOW
)
3981 val
= nr64_mac(XMAC_FC_STAT
);
3982 if (val
& XMAC_FC_STAT_TX_MAC_NPAUSE
)
3983 mp
->pause_off_state
++;
3984 if (val
& XMAC_FC_STAT_TX_MAC_PAUSE
)
3985 mp
->pause_on_state
++;
3986 if (val
& XMAC_FC_STAT_RX_MAC_RPAUSE
)
3987 mp
->pause_received
++;
3990 static void niu_bmac_interrupt(struct niu
*np
)
3992 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
3995 val
= nr64_mac(BTXMAC_STATUS
);
3996 if (val
& BTXMAC_STATUS_UNDERRUN
)
3997 mp
->tx_underflow_errors
++;
3998 if (val
& BTXMAC_STATUS_MAX_PKT_ERR
)
3999 mp
->tx_max_pkt_size_errors
++;
4000 if (val
& BTXMAC_STATUS_BYTE_CNT_EXP
)
4001 mp
->tx_bytes
+= BTXMAC_BYTE_CNT_COUNT
;
4002 if (val
& BTXMAC_STATUS_FRAME_CNT_EXP
)
4003 mp
->tx_frames
+= BTXMAC_FRM_CNT_COUNT
;
4005 val
= nr64_mac(BRXMAC_STATUS
);
4006 if (val
& BRXMAC_STATUS_OVERFLOW
)
4008 if (val
& BRXMAC_STATUS_FRAME_CNT_EXP
)
4009 mp
->rx_frames
+= BRXMAC_FRAME_CNT_COUNT
;
4010 if (val
& BRXMAC_STATUS_ALIGN_ERR_EXP
)
4011 mp
->rx_align_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
4012 if (val
& BRXMAC_STATUS_CRC_ERR_EXP
)
4013 mp
->rx_crc_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
4014 if (val
& BRXMAC_STATUS_LEN_ERR_EXP
)
4015 mp
->rx_len_errors
+= BRXMAC_CODE_VIOL_ERR_CNT_COUNT
;
4017 val
= nr64_mac(BMAC_CTRL_STATUS
);
4018 if (val
& BMAC_CTRL_STATUS_NOPAUSE
)
4019 mp
->pause_off_state
++;
4020 if (val
& BMAC_CTRL_STATUS_PAUSE
)
4021 mp
->pause_on_state
++;
4022 if (val
& BMAC_CTRL_STATUS_PAUSE_RECV
)
4023 mp
->pause_received
++;
4026 static int niu_mac_interrupt(struct niu
*np
)
4028 if (np
->flags
& NIU_FLAGS_XMAC
)
4029 niu_xmac_interrupt(np
);
4031 niu_bmac_interrupt(np
);
4036 static void niu_log_device_error(struct niu
*np
, u64 stat
)
4038 netdev_err(np
->dev
, "Core device errors ( ");
4040 if (stat
& SYS_ERR_MASK_META2
)
4042 if (stat
& SYS_ERR_MASK_META1
)
4044 if (stat
& SYS_ERR_MASK_PEU
)
4046 if (stat
& SYS_ERR_MASK_TXC
)
4048 if (stat
& SYS_ERR_MASK_RDMC
)
4050 if (stat
& SYS_ERR_MASK_TDMC
)
4052 if (stat
& SYS_ERR_MASK_ZCP
)
4054 if (stat
& SYS_ERR_MASK_FFLP
)
4056 if (stat
& SYS_ERR_MASK_IPP
)
4058 if (stat
& SYS_ERR_MASK_MAC
)
4060 if (stat
& SYS_ERR_MASK_SMX
)
4066 static int niu_device_error(struct niu
*np
)
4068 u64 stat
= nr64(SYS_ERR_STAT
);
4070 netdev_err(np
->dev
, "Core device error, stat[%llx]\n",
4071 (unsigned long long)stat
);
4073 niu_log_device_error(np
, stat
);
4078 static int niu_slowpath_interrupt(struct niu
*np
, struct niu_ldg
*lp
,
4079 u64 v0
, u64 v1
, u64 v2
)
4088 if (v1
& 0x00000000ffffffffULL
) {
4089 u32 rx_vec
= (v1
& 0xffffffff);
4091 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4092 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4094 if (rx_vec
& (1 << rp
->rx_channel
)) {
4095 int r
= niu_rx_error(np
, rp
);
4100 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
4101 RX_DMA_CTL_STAT_MEX
);
4106 if (v1
& 0x7fffffff00000000ULL
) {
4107 u32 tx_vec
= (v1
>> 32) & 0x7fffffff;
4109 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4110 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4112 if (tx_vec
& (1 << rp
->tx_channel
)) {
4113 int r
= niu_tx_error(np
, rp
);
4119 if ((v0
| v1
) & 0x8000000000000000ULL
) {
4120 int r
= niu_mif_interrupt(np
);
4126 int r
= niu_mac_interrupt(np
);
4131 int r
= niu_device_error(np
);
4138 niu_enable_interrupts(np
, 0);
4143 static void niu_rxchan_intr(struct niu
*np
, struct rx_ring_info
*rp
,
4146 struct rxdma_mailbox
*mbox
= rp
->mbox
;
4147 u64 stat_write
, stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
4149 stat_write
= (RX_DMA_CTL_STAT_RCRTHRES
|
4150 RX_DMA_CTL_STAT_RCRTO
);
4151 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat_write
);
4153 netif_printk(np
, intr
, KERN_DEBUG
, np
->dev
,
4154 "%s() stat[%llx]\n", __func__
, (unsigned long long)stat
);
4157 static void niu_txchan_intr(struct niu
*np
, struct tx_ring_info
*rp
,
4160 rp
->tx_cs
= nr64(TX_CS(rp
->tx_channel
));
4162 netif_printk(np
, intr
, KERN_DEBUG
, np
->dev
,
4163 "%s() cs[%llx]\n", __func__
, (unsigned long long)rp
->tx_cs
);
4166 static void __niu_fastpath_interrupt(struct niu
*np
, int ldg
, u64 v0
)
4168 struct niu_parent
*parent
= np
->parent
;
4172 tx_vec
= (v0
>> 32);
4173 rx_vec
= (v0
& 0xffffffff);
4175 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4176 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4177 int ldn
= LDN_RXDMA(rp
->rx_channel
);
4179 if (parent
->ldg_map
[ldn
] != ldg
)
4182 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
4183 if (rx_vec
& (1 << rp
->rx_channel
))
4184 niu_rxchan_intr(np
, rp
, ldn
);
4187 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4188 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4189 int ldn
= LDN_TXDMA(rp
->tx_channel
);
4191 if (parent
->ldg_map
[ldn
] != ldg
)
4194 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
4195 if (tx_vec
& (1 << rp
->tx_channel
))
4196 niu_txchan_intr(np
, rp
, ldn
);
4200 static void niu_schedule_napi(struct niu
*np
, struct niu_ldg
*lp
,
4201 u64 v0
, u64 v1
, u64 v2
)
4203 if (likely(napi_schedule_prep(&lp
->napi
))) {
4207 __niu_fastpath_interrupt(np
, lp
->ldg_num
, v0
);
4208 __napi_schedule(&lp
->napi
);
4212 static irqreturn_t
niu_interrupt(int irq
, void *dev_id
)
4214 struct niu_ldg
*lp
= dev_id
;
4215 struct niu
*np
= lp
->np
;
4216 int ldg
= lp
->ldg_num
;
4217 unsigned long flags
;
4220 if (netif_msg_intr(np
))
4221 printk(KERN_DEBUG KBUILD_MODNAME
": " "%s() ldg[%p](%d)",
4224 spin_lock_irqsave(&np
->lock
, flags
);
4226 v0
= nr64(LDSV0(ldg
));
4227 v1
= nr64(LDSV1(ldg
));
4228 v2
= nr64(LDSV2(ldg
));
4230 if (netif_msg_intr(np
))
4231 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4232 (unsigned long long) v0
,
4233 (unsigned long long) v1
,
4234 (unsigned long long) v2
);
4236 if (unlikely(!v0
&& !v1
&& !v2
)) {
4237 spin_unlock_irqrestore(&np
->lock
, flags
);
4241 if (unlikely((v0
& ((u64
)1 << LDN_MIF
)) || v1
|| v2
)) {
4242 int err
= niu_slowpath_interrupt(np
, lp
, v0
, v1
, v2
);
4246 if (likely(v0
& ~((u64
)1 << LDN_MIF
)))
4247 niu_schedule_napi(np
, lp
, v0
, v1
, v2
);
4249 niu_ldg_rearm(np
, lp
, 1);
4251 spin_unlock_irqrestore(&np
->lock
, flags
);
4256 static void niu_free_rx_ring_info(struct niu
*np
, struct rx_ring_info
*rp
)
4259 np
->ops
->free_coherent(np
->device
,
4260 sizeof(struct rxdma_mailbox
),
4261 rp
->mbox
, rp
->mbox_dma
);
4265 np
->ops
->free_coherent(np
->device
,
4266 MAX_RCR_RING_SIZE
* sizeof(__le64
),
4267 rp
->rcr
, rp
->rcr_dma
);
4269 rp
->rcr_table_size
= 0;
4273 niu_rbr_free(np
, rp
);
4275 np
->ops
->free_coherent(np
->device
,
4276 MAX_RBR_RING_SIZE
* sizeof(__le32
),
4277 rp
->rbr
, rp
->rbr_dma
);
4279 rp
->rbr_table_size
= 0;
4286 static void niu_free_tx_ring_info(struct niu
*np
, struct tx_ring_info
*rp
)
4289 np
->ops
->free_coherent(np
->device
,
4290 sizeof(struct txdma_mailbox
),
4291 rp
->mbox
, rp
->mbox_dma
);
4297 for (i
= 0; i
< MAX_TX_RING_SIZE
; i
++) {
4298 if (rp
->tx_buffs
[i
].skb
)
4299 (void) release_tx_packet(np
, rp
, i
);
4302 np
->ops
->free_coherent(np
->device
,
4303 MAX_TX_RING_SIZE
* sizeof(__le64
),
4304 rp
->descr
, rp
->descr_dma
);
4313 static void niu_free_channels(struct niu
*np
)
4318 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4319 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4321 niu_free_rx_ring_info(np
, rp
);
4323 kfree(np
->rx_rings
);
4324 np
->rx_rings
= NULL
;
4325 np
->num_rx_rings
= 0;
4329 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4330 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4332 niu_free_tx_ring_info(np
, rp
);
4334 kfree(np
->tx_rings
);
4335 np
->tx_rings
= NULL
;
4336 np
->num_tx_rings
= 0;
4340 static int niu_alloc_rx_ring_info(struct niu
*np
,
4341 struct rx_ring_info
*rp
)
4343 BUILD_BUG_ON(sizeof(struct rxdma_mailbox
) != 64);
4345 rp
->rxhash
= kcalloc(MAX_RBR_RING_SIZE
, sizeof(struct page
*),
4350 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
4351 sizeof(struct rxdma_mailbox
),
4352 &rp
->mbox_dma
, GFP_KERNEL
);
4355 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
4356 netdev_err(np
->dev
, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4361 rp
->rcr
= np
->ops
->alloc_coherent(np
->device
,
4362 MAX_RCR_RING_SIZE
* sizeof(__le64
),
4363 &rp
->rcr_dma
, GFP_KERNEL
);
4366 if ((unsigned long)rp
->rcr
& (64UL - 1)) {
4367 netdev_err(np
->dev
, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4371 rp
->rcr_table_size
= MAX_RCR_RING_SIZE
;
4374 rp
->rbr
= np
->ops
->alloc_coherent(np
->device
,
4375 MAX_RBR_RING_SIZE
* sizeof(__le32
),
4376 &rp
->rbr_dma
, GFP_KERNEL
);
4379 if ((unsigned long)rp
->rbr
& (64UL - 1)) {
4380 netdev_err(np
->dev
, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4384 rp
->rbr_table_size
= MAX_RBR_RING_SIZE
;
4386 rp
->rbr_pending
= 0;
4391 static void niu_set_max_burst(struct niu
*np
, struct tx_ring_info
*rp
)
4393 int mtu
= np
->dev
->mtu
;
4395 /* These values are recommended by the HW designers for fair
4396 * utilization of DRR amongst the rings.
4398 rp
->max_burst
= mtu
+ 32;
4399 if (rp
->max_burst
> 4096)
4400 rp
->max_burst
= 4096;
4403 static int niu_alloc_tx_ring_info(struct niu
*np
,
4404 struct tx_ring_info
*rp
)
4406 BUILD_BUG_ON(sizeof(struct txdma_mailbox
) != 64);
4408 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
4409 sizeof(struct txdma_mailbox
),
4410 &rp
->mbox_dma
, GFP_KERNEL
);
4413 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
4414 netdev_err(np
->dev
, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4419 rp
->descr
= np
->ops
->alloc_coherent(np
->device
,
4420 MAX_TX_RING_SIZE
* sizeof(__le64
),
4421 &rp
->descr_dma
, GFP_KERNEL
);
4424 if ((unsigned long)rp
->descr
& (64UL - 1)) {
4425 netdev_err(np
->dev
, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4430 rp
->pending
= MAX_TX_RING_SIZE
;
4435 /* XXX make these configurable... XXX */
4436 rp
->mark_freq
= rp
->pending
/ 4;
4438 niu_set_max_burst(np
, rp
);
4443 static void niu_size_rbr(struct niu
*np
, struct rx_ring_info
*rp
)
4447 bss
= min(PAGE_SHIFT
, 15);
4449 rp
->rbr_block_size
= 1 << bss
;
4450 rp
->rbr_blocks_per_page
= 1 << (PAGE_SHIFT
-bss
);
4452 rp
->rbr_sizes
[0] = 256;
4453 rp
->rbr_sizes
[1] = 1024;
4454 if (np
->dev
->mtu
> ETH_DATA_LEN
) {
4455 switch (PAGE_SIZE
) {
4457 rp
->rbr_sizes
[2] = 4096;
4461 rp
->rbr_sizes
[2] = 8192;
4465 rp
->rbr_sizes
[2] = 2048;
4467 rp
->rbr_sizes
[3] = rp
->rbr_block_size
;
4470 static int niu_alloc_channels(struct niu
*np
)
4472 struct niu_parent
*parent
= np
->parent
;
4473 int first_rx_channel
, first_tx_channel
;
4474 int num_rx_rings
, num_tx_rings
;
4475 struct rx_ring_info
*rx_rings
;
4476 struct tx_ring_info
*tx_rings
;
4480 first_rx_channel
= first_tx_channel
= 0;
4481 for (i
= 0; i
< port
; i
++) {
4482 first_rx_channel
+= parent
->rxchan_per_port
[i
];
4483 first_tx_channel
+= parent
->txchan_per_port
[i
];
4486 num_rx_rings
= parent
->rxchan_per_port
[port
];
4487 num_tx_rings
= parent
->txchan_per_port
[port
];
4489 rx_rings
= kcalloc(num_rx_rings
, sizeof(struct rx_ring_info
),
4495 np
->num_rx_rings
= num_rx_rings
;
4497 np
->rx_rings
= rx_rings
;
4499 netif_set_real_num_rx_queues(np
->dev
, num_rx_rings
);
4501 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4502 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4505 rp
->rx_channel
= first_rx_channel
+ i
;
4507 err
= niu_alloc_rx_ring_info(np
, rp
);
4511 niu_size_rbr(np
, rp
);
4513 /* XXX better defaults, configurable, etc... XXX */
4514 rp
->nonsyn_window
= 64;
4515 rp
->nonsyn_threshold
= rp
->rcr_table_size
- 64;
4516 rp
->syn_window
= 64;
4517 rp
->syn_threshold
= rp
->rcr_table_size
- 64;
4518 rp
->rcr_pkt_threshold
= 16;
4519 rp
->rcr_timeout
= 8;
4520 rp
->rbr_kick_thresh
= RBR_REFILL_MIN
;
4521 if (rp
->rbr_kick_thresh
< rp
->rbr_blocks_per_page
)
4522 rp
->rbr_kick_thresh
= rp
->rbr_blocks_per_page
;
4524 err
= niu_rbr_fill(np
, rp
, GFP_KERNEL
);
4529 tx_rings
= kcalloc(num_tx_rings
, sizeof(struct tx_ring_info
),
4535 np
->num_tx_rings
= num_tx_rings
;
4537 np
->tx_rings
= tx_rings
;
4539 netif_set_real_num_tx_queues(np
->dev
, num_tx_rings
);
4541 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4542 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4545 rp
->tx_channel
= first_tx_channel
+ i
;
4547 err
= niu_alloc_tx_ring_info(np
, rp
);
4555 niu_free_channels(np
);
4559 static int niu_tx_cs_sng_poll(struct niu
*np
, int channel
)
4563 while (--limit
> 0) {
4564 u64 val
= nr64(TX_CS(channel
));
4565 if (val
& TX_CS_SNG_STATE
)
4571 static int niu_tx_channel_stop(struct niu
*np
, int channel
)
4573 u64 val
= nr64(TX_CS(channel
));
4575 val
|= TX_CS_STOP_N_GO
;
4576 nw64(TX_CS(channel
), val
);
4578 return niu_tx_cs_sng_poll(np
, channel
);
4581 static int niu_tx_cs_reset_poll(struct niu
*np
, int channel
)
4585 while (--limit
> 0) {
4586 u64 val
= nr64(TX_CS(channel
));
4587 if (!(val
& TX_CS_RST
))
4593 static int niu_tx_channel_reset(struct niu
*np
, int channel
)
4595 u64 val
= nr64(TX_CS(channel
));
4599 nw64(TX_CS(channel
), val
);
4601 err
= niu_tx_cs_reset_poll(np
, channel
);
4603 nw64(TX_RING_KICK(channel
), 0);
4608 static int niu_tx_channel_lpage_init(struct niu
*np
, int channel
)
4612 nw64(TX_LOG_MASK1(channel
), 0);
4613 nw64(TX_LOG_VAL1(channel
), 0);
4614 nw64(TX_LOG_MASK2(channel
), 0);
4615 nw64(TX_LOG_VAL2(channel
), 0);
4616 nw64(TX_LOG_PAGE_RELO1(channel
), 0);
4617 nw64(TX_LOG_PAGE_RELO2(channel
), 0);
4618 nw64(TX_LOG_PAGE_HDL(channel
), 0);
4620 val
= (u64
)np
->port
<< TX_LOG_PAGE_VLD_FUNC_SHIFT
;
4621 val
|= (TX_LOG_PAGE_VLD_PAGE0
| TX_LOG_PAGE_VLD_PAGE1
);
4622 nw64(TX_LOG_PAGE_VLD(channel
), val
);
4624 /* XXX TXDMA 32bit mode? XXX */
4629 static void niu_txc_enable_port(struct niu
*np
, int on
)
4631 unsigned long flags
;
4634 niu_lock_parent(np
, flags
);
4635 val
= nr64(TXC_CONTROL
);
4636 mask
= (u64
)1 << np
->port
;
4638 val
|= TXC_CONTROL_ENABLE
| mask
;
4641 if ((val
& ~TXC_CONTROL_ENABLE
) == 0)
4642 val
&= ~TXC_CONTROL_ENABLE
;
4644 nw64(TXC_CONTROL
, val
);
4645 niu_unlock_parent(np
, flags
);
4648 static void niu_txc_set_imask(struct niu
*np
, u64 imask
)
4650 unsigned long flags
;
4653 niu_lock_parent(np
, flags
);
4654 val
= nr64(TXC_INT_MASK
);
4655 val
&= ~TXC_INT_MASK_VAL(np
->port
);
4656 val
|= (imask
<< TXC_INT_MASK_VAL_SHIFT(np
->port
));
4657 niu_unlock_parent(np
, flags
);
4660 static void niu_txc_port_dma_enable(struct niu
*np
, int on
)
4667 for (i
= 0; i
< np
->num_tx_rings
; i
++)
4668 val
|= (1 << np
->tx_rings
[i
].tx_channel
);
4670 nw64(TXC_PORT_DMA(np
->port
), val
);
4673 static int niu_init_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
4675 int err
, channel
= rp
->tx_channel
;
4678 err
= niu_tx_channel_stop(np
, channel
);
4682 err
= niu_tx_channel_reset(np
, channel
);
4686 err
= niu_tx_channel_lpage_init(np
, channel
);
4690 nw64(TXC_DMA_MAX(channel
), rp
->max_burst
);
4691 nw64(TX_ENT_MSK(channel
), 0);
4693 if (rp
->descr_dma
& ~(TX_RNG_CFIG_STADDR_BASE
|
4694 TX_RNG_CFIG_STADDR
)) {
4695 netdev_err(np
->dev
, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4696 channel
, (unsigned long long)rp
->descr_dma
);
4700 /* The length field in TX_RNG_CFIG is measured in 64-byte
4701 * blocks. rp->pending is the number of TX descriptors in
4702 * our ring, 8 bytes each, thus we divide by 8 bytes more
4703 * to get the proper value the chip wants.
4705 ring_len
= (rp
->pending
/ 8);
4707 val
= ((ring_len
<< TX_RNG_CFIG_LEN_SHIFT
) |
4709 nw64(TX_RNG_CFIG(channel
), val
);
4711 if (((rp
->mbox_dma
>> 32) & ~TXDMA_MBH_MBADDR
) ||
4712 ((u32
)rp
->mbox_dma
& ~TXDMA_MBL_MBADDR
)) {
4713 netdev_err(np
->dev
, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4714 channel
, (unsigned long long)rp
->mbox_dma
);
4717 nw64(TXDMA_MBH(channel
), rp
->mbox_dma
>> 32);
4718 nw64(TXDMA_MBL(channel
), rp
->mbox_dma
& TXDMA_MBL_MBADDR
);
4720 nw64(TX_CS(channel
), 0);
4722 rp
->last_pkt_cnt
= 0;
4727 static void niu_init_rdc_groups(struct niu
*np
)
4729 struct niu_rdc_tables
*tp
= &np
->parent
->rdc_group_cfg
[np
->port
];
4730 int i
, first_table_num
= tp
->first_table_num
;
4732 for (i
= 0; i
< tp
->num_tables
; i
++) {
4733 struct rdc_table
*tbl
= &tp
->tables
[i
];
4734 int this_table
= first_table_num
+ i
;
4737 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++)
4738 nw64(RDC_TBL(this_table
, slot
),
4739 tbl
->rxdma_channel
[slot
]);
4742 nw64(DEF_RDC(np
->port
), np
->parent
->rdc_default
[np
->port
]);
4745 static void niu_init_drr_weight(struct niu
*np
)
4747 int type
= phy_decode(np
->parent
->port_phy
, np
->port
);
4752 val
= PT_DRR_WEIGHT_DEFAULT_10G
;
4757 val
= PT_DRR_WEIGHT_DEFAULT_1G
;
4760 nw64(PT_DRR_WT(np
->port
), val
);
4763 static int niu_init_hostinfo(struct niu
*np
)
4765 struct niu_parent
*parent
= np
->parent
;
4766 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
4767 int i
, err
, num_alt
= niu_num_alt_addr(np
);
4768 int first_rdc_table
= tp
->first_table_num
;
4770 err
= niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
4774 err
= niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
4778 for (i
= 0; i
< num_alt
; i
++) {
4779 err
= niu_set_alt_mac_rdc_table(np
, i
, first_rdc_table
, 1);
4787 static int niu_rx_channel_reset(struct niu
*np
, int channel
)
4789 return niu_set_and_wait_clear(np
, RXDMA_CFIG1(channel
),
4790 RXDMA_CFIG1_RST
, 1000, 10,
4794 static int niu_rx_channel_lpage_init(struct niu
*np
, int channel
)
4798 nw64(RX_LOG_MASK1(channel
), 0);
4799 nw64(RX_LOG_VAL1(channel
), 0);
4800 nw64(RX_LOG_MASK2(channel
), 0);
4801 nw64(RX_LOG_VAL2(channel
), 0);
4802 nw64(RX_LOG_PAGE_RELO1(channel
), 0);
4803 nw64(RX_LOG_PAGE_RELO2(channel
), 0);
4804 nw64(RX_LOG_PAGE_HDL(channel
), 0);
4806 val
= (u64
)np
->port
<< RX_LOG_PAGE_VLD_FUNC_SHIFT
;
4807 val
|= (RX_LOG_PAGE_VLD_PAGE0
| RX_LOG_PAGE_VLD_PAGE1
);
4808 nw64(RX_LOG_PAGE_VLD(channel
), val
);
4813 static void niu_rx_channel_wred_init(struct niu
*np
, struct rx_ring_info
*rp
)
4817 val
= (((u64
)rp
->nonsyn_window
<< RDC_RED_PARA_WIN_SHIFT
) |
4818 ((u64
)rp
->nonsyn_threshold
<< RDC_RED_PARA_THRE_SHIFT
) |
4819 ((u64
)rp
->syn_window
<< RDC_RED_PARA_WIN_SYN_SHIFT
) |
4820 ((u64
)rp
->syn_threshold
<< RDC_RED_PARA_THRE_SYN_SHIFT
));
4821 nw64(RDC_RED_PARA(rp
->rx_channel
), val
);
4824 static int niu_compute_rbr_cfig_b(struct rx_ring_info
*rp
, u64
*ret
)
4829 switch (rp
->rbr_block_size
) {
4831 val
|= (RBR_BLKSIZE_4K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4834 val
|= (RBR_BLKSIZE_8K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4837 val
|= (RBR_BLKSIZE_16K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4840 val
|= (RBR_BLKSIZE_32K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4845 val
|= RBR_CFIG_B_VLD2
;
4846 switch (rp
->rbr_sizes
[2]) {
4848 val
|= (RBR_BUFSZ2_2K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4851 val
|= (RBR_BUFSZ2_4K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4854 val
|= (RBR_BUFSZ2_8K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4857 val
|= (RBR_BUFSZ2_16K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4863 val
|= RBR_CFIG_B_VLD1
;
4864 switch (rp
->rbr_sizes
[1]) {
4866 val
|= (RBR_BUFSZ1_1K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4869 val
|= (RBR_BUFSZ1_2K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4872 val
|= (RBR_BUFSZ1_4K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4875 val
|= (RBR_BUFSZ1_8K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4881 val
|= RBR_CFIG_B_VLD0
;
4882 switch (rp
->rbr_sizes
[0]) {
4884 val
|= (RBR_BUFSZ0_256
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4887 val
|= (RBR_BUFSZ0_512
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4890 val
|= (RBR_BUFSZ0_1K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4893 val
|= (RBR_BUFSZ0_2K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4904 static int niu_enable_rx_channel(struct niu
*np
, int channel
, int on
)
4906 u64 val
= nr64(RXDMA_CFIG1(channel
));
4910 val
|= RXDMA_CFIG1_EN
;
4912 val
&= ~RXDMA_CFIG1_EN
;
4913 nw64(RXDMA_CFIG1(channel
), val
);
4916 while (--limit
> 0) {
4917 if (nr64(RXDMA_CFIG1(channel
)) & RXDMA_CFIG1_QST
)
4926 static int niu_init_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
4928 int err
, channel
= rp
->rx_channel
;
4931 err
= niu_rx_channel_reset(np
, channel
);
4935 err
= niu_rx_channel_lpage_init(np
, channel
);
4939 niu_rx_channel_wred_init(np
, rp
);
4941 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_RBR_EMPTY
);
4942 nw64(RX_DMA_CTL_STAT(channel
),
4943 (RX_DMA_CTL_STAT_MEX
|
4944 RX_DMA_CTL_STAT_RCRTHRES
|
4945 RX_DMA_CTL_STAT_RCRTO
|
4946 RX_DMA_CTL_STAT_RBR_EMPTY
));
4947 nw64(RXDMA_CFIG1(channel
), rp
->mbox_dma
>> 32);
4948 nw64(RXDMA_CFIG2(channel
),
4949 ((rp
->mbox_dma
& RXDMA_CFIG2_MBADDR_L
) |
4950 RXDMA_CFIG2_FULL_HDR
));
4951 nw64(RBR_CFIG_A(channel
),
4952 ((u64
)rp
->rbr_table_size
<< RBR_CFIG_A_LEN_SHIFT
) |
4953 (rp
->rbr_dma
& (RBR_CFIG_A_STADDR_BASE
| RBR_CFIG_A_STADDR
)));
4954 err
= niu_compute_rbr_cfig_b(rp
, &val
);
4957 nw64(RBR_CFIG_B(channel
), val
);
4958 nw64(RCRCFIG_A(channel
),
4959 ((u64
)rp
->rcr_table_size
<< RCRCFIG_A_LEN_SHIFT
) |
4960 (rp
->rcr_dma
& (RCRCFIG_A_STADDR_BASE
| RCRCFIG_A_STADDR
)));
4961 nw64(RCRCFIG_B(channel
),
4962 ((u64
)rp
->rcr_pkt_threshold
<< RCRCFIG_B_PTHRES_SHIFT
) |
4964 ((u64
)rp
->rcr_timeout
<< RCRCFIG_B_TIMEOUT_SHIFT
));
4966 err
= niu_enable_rx_channel(np
, channel
, 1);
4970 nw64(RBR_KICK(channel
), rp
->rbr_index
);
4972 val
= nr64(RX_DMA_CTL_STAT(channel
));
4973 val
|= RX_DMA_CTL_STAT_RBR_EMPTY
;
4974 nw64(RX_DMA_CTL_STAT(channel
), val
);
4979 static int niu_init_rx_channels(struct niu
*np
)
4981 unsigned long flags
;
4982 u64 seed
= jiffies_64
;
4985 niu_lock_parent(np
, flags
);
4986 nw64(RX_DMA_CK_DIV
, np
->parent
->rxdma_clock_divider
);
4987 nw64(RED_RAN_INIT
, RED_RAN_INIT_OPMODE
| (seed
& RED_RAN_INIT_VAL
));
4988 niu_unlock_parent(np
, flags
);
4990 /* XXX RXDMA 32bit mode? XXX */
4992 niu_init_rdc_groups(np
);
4993 niu_init_drr_weight(np
);
4995 err
= niu_init_hostinfo(np
);
4999 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5000 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5002 err
= niu_init_one_rx_channel(np
, rp
);
5010 static int niu_set_ip_frag_rule(struct niu
*np
)
5012 struct niu_parent
*parent
= np
->parent
;
5013 struct niu_classifier
*cp
= &np
->clas
;
5014 struct niu_tcam_entry
*tp
;
5017 index
= cp
->tcam_top
;
5018 tp
= &parent
->tcam
[index
];
5020 /* Note that the noport bit is the same in both ipv4 and
5021 * ipv6 format TCAM entries.
5023 memset(tp
, 0, sizeof(*tp
));
5024 tp
->key
[1] = TCAM_V4KEY1_NOPORT
;
5025 tp
->key_mask
[1] = TCAM_V4KEY1_NOPORT
;
5026 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
5027 ((u64
)0 << TCAM_ASSOCDATA_OFFSET_SHIFT
));
5028 err
= tcam_write(np
, index
, tp
->key
, tp
->key_mask
);
5031 err
= tcam_assoc_write(np
, index
, tp
->assoc_data
);
5035 cp
->tcam_valid_entries
++;
5040 static int niu_init_classifier_hw(struct niu
*np
)
5042 struct niu_parent
*parent
= np
->parent
;
5043 struct niu_classifier
*cp
= &np
->clas
;
5046 nw64(H1POLY
, cp
->h1_init
);
5047 nw64(H2POLY
, cp
->h2_init
);
5049 err
= niu_init_hostinfo(np
);
5053 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++) {
5054 struct niu_vlan_rdc
*vp
= &cp
->vlan_mappings
[i
];
5056 vlan_tbl_write(np
, i
, np
->port
,
5057 vp
->vlan_pref
, vp
->rdc_num
);
5060 for (i
= 0; i
< cp
->num_alt_mac_mappings
; i
++) {
5061 struct niu_altmac_rdc
*ap
= &cp
->alt_mac_mappings
[i
];
5063 err
= niu_set_alt_mac_rdc_table(np
, ap
->alt_mac_num
,
5064 ap
->rdc_num
, ap
->mac_pref
);
5069 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
5070 int index
= i
- CLASS_CODE_USER_PROG1
;
5072 err
= niu_set_tcam_key(np
, i
, parent
->tcam_key
[index
]);
5075 err
= niu_set_flow_key(np
, i
, parent
->flow_key
[index
]);
5080 err
= niu_set_ip_frag_rule(np
);
5089 static int niu_zcp_write(struct niu
*np
, int index
, u64
*data
)
5091 nw64(ZCP_RAM_DATA0
, data
[0]);
5092 nw64(ZCP_RAM_DATA1
, data
[1]);
5093 nw64(ZCP_RAM_DATA2
, data
[2]);
5094 nw64(ZCP_RAM_DATA3
, data
[3]);
5095 nw64(ZCP_RAM_DATA4
, data
[4]);
5096 nw64(ZCP_RAM_BE
, ZCP_RAM_BE_VAL
);
5098 (ZCP_RAM_ACC_WRITE
|
5099 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
5100 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
5102 return niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5106 static int niu_zcp_read(struct niu
*np
, int index
, u64
*data
)
5110 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5113 netdev_err(np
->dev
, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5114 (unsigned long long)nr64(ZCP_RAM_ACC
));
5120 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
5121 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
5123 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5126 netdev_err(np
->dev
, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5127 (unsigned long long)nr64(ZCP_RAM_ACC
));
5131 data
[0] = nr64(ZCP_RAM_DATA0
);
5132 data
[1] = nr64(ZCP_RAM_DATA1
);
5133 data
[2] = nr64(ZCP_RAM_DATA2
);
5134 data
[3] = nr64(ZCP_RAM_DATA3
);
5135 data
[4] = nr64(ZCP_RAM_DATA4
);
5140 static void niu_zcp_cfifo_reset(struct niu
*np
)
5142 u64 val
= nr64(RESET_CFIFO
);
5144 val
|= RESET_CFIFO_RST(np
->port
);
5145 nw64(RESET_CFIFO
, val
);
5148 val
&= ~RESET_CFIFO_RST(np
->port
);
5149 nw64(RESET_CFIFO
, val
);
5152 static int niu_init_zcp(struct niu
*np
)
5154 u64 data
[5], rbuf
[5];
5157 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
5158 if (np
->port
== 0 || np
->port
== 1)
5159 max
= ATLAS_P0_P1_CFIFO_ENTRIES
;
5161 max
= ATLAS_P2_P3_CFIFO_ENTRIES
;
5163 max
= NIU_CFIFO_ENTRIES
;
5171 for (i
= 0; i
< max
; i
++) {
5172 err
= niu_zcp_write(np
, i
, data
);
5175 err
= niu_zcp_read(np
, i
, rbuf
);
5180 niu_zcp_cfifo_reset(np
);
5181 nw64(CFIFO_ECC(np
->port
), 0);
5182 nw64(ZCP_INT_STAT
, ZCP_INT_STAT_ALL
);
5183 (void) nr64(ZCP_INT_STAT
);
5184 nw64(ZCP_INT_MASK
, ZCP_INT_MASK_ALL
);
5189 static void niu_ipp_write(struct niu
*np
, int index
, u64
*data
)
5191 u64 val
= nr64_ipp(IPP_CFIG
);
5193 nw64_ipp(IPP_CFIG
, val
| IPP_CFIG_DFIFO_PIO_W
);
5194 nw64_ipp(IPP_DFIFO_WR_PTR
, index
);
5195 nw64_ipp(IPP_DFIFO_WR0
, data
[0]);
5196 nw64_ipp(IPP_DFIFO_WR1
, data
[1]);
5197 nw64_ipp(IPP_DFIFO_WR2
, data
[2]);
5198 nw64_ipp(IPP_DFIFO_WR3
, data
[3]);
5199 nw64_ipp(IPP_DFIFO_WR4
, data
[4]);
5200 nw64_ipp(IPP_CFIG
, val
& ~IPP_CFIG_DFIFO_PIO_W
);
5203 static void niu_ipp_read(struct niu
*np
, int index
, u64
*data
)
5205 nw64_ipp(IPP_DFIFO_RD_PTR
, index
);
5206 data
[0] = nr64_ipp(IPP_DFIFO_RD0
);
5207 data
[1] = nr64_ipp(IPP_DFIFO_RD1
);
5208 data
[2] = nr64_ipp(IPP_DFIFO_RD2
);
5209 data
[3] = nr64_ipp(IPP_DFIFO_RD3
);
5210 data
[4] = nr64_ipp(IPP_DFIFO_RD4
);
5213 static int niu_ipp_reset(struct niu
*np
)
5215 return niu_set_and_wait_clear_ipp(np
, IPP_CFIG
, IPP_CFIG_SOFT_RST
,
5216 1000, 100, "IPP_CFIG");
5219 static int niu_init_ipp(struct niu
*np
)
5221 u64 data
[5], rbuf
[5], val
;
5224 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
5225 if (np
->port
== 0 || np
->port
== 1)
5226 max
= ATLAS_P0_P1_DFIFO_ENTRIES
;
5228 max
= ATLAS_P2_P3_DFIFO_ENTRIES
;
5230 max
= NIU_DFIFO_ENTRIES
;
5238 for (i
= 0; i
< max
; i
++) {
5239 niu_ipp_write(np
, i
, data
);
5240 niu_ipp_read(np
, i
, rbuf
);
5243 (void) nr64_ipp(IPP_INT_STAT
);
5244 (void) nr64_ipp(IPP_INT_STAT
);
5246 err
= niu_ipp_reset(np
);
5250 (void) nr64_ipp(IPP_PKT_DIS
);
5251 (void) nr64_ipp(IPP_BAD_CS_CNT
);
5252 (void) nr64_ipp(IPP_ECC
);
5254 (void) nr64_ipp(IPP_INT_STAT
);
5256 nw64_ipp(IPP_MSK
, ~IPP_MSK_ALL
);
5258 val
= nr64_ipp(IPP_CFIG
);
5259 val
&= ~IPP_CFIG_IP_MAX_PKT
;
5260 val
|= (IPP_CFIG_IPP_ENABLE
|
5261 IPP_CFIG_DFIFO_ECC_EN
|
5262 IPP_CFIG_DROP_BAD_CRC
|
5264 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT
));
5265 nw64_ipp(IPP_CFIG
, val
);
5270 static void niu_handle_led(struct niu
*np
, int status
)
5273 val
= nr64_mac(XMAC_CONFIG
);
5275 if ((np
->flags
& NIU_FLAGS_10G
) != 0 &&
5276 (np
->flags
& NIU_FLAGS_FIBER
) != 0) {
5278 val
|= XMAC_CONFIG_LED_POLARITY
;
5279 val
&= ~XMAC_CONFIG_FORCE_LED_ON
;
5281 val
|= XMAC_CONFIG_FORCE_LED_ON
;
5282 val
&= ~XMAC_CONFIG_LED_POLARITY
;
5286 nw64_mac(XMAC_CONFIG
, val
);
5289 static void niu_init_xif_xmac(struct niu
*np
)
5291 struct niu_link_config
*lp
= &np
->link_config
;
5294 if (np
->flags
& NIU_FLAGS_XCVR_SERDES
) {
5295 val
= nr64(MIF_CONFIG
);
5296 val
|= MIF_CONFIG_ATCA_GE
;
5297 nw64(MIF_CONFIG
, val
);
5300 val
= nr64_mac(XMAC_CONFIG
);
5301 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
5303 val
|= XMAC_CONFIG_TX_OUTPUT_EN
;
5305 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
5306 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
5307 val
|= XMAC_CONFIG_LOOPBACK
;
5309 val
&= ~XMAC_CONFIG_LOOPBACK
;
5312 if (np
->flags
& NIU_FLAGS_10G
) {
5313 val
&= ~XMAC_CONFIG_LFS_DISABLE
;
5315 val
|= XMAC_CONFIG_LFS_DISABLE
;
5316 if (!(np
->flags
& NIU_FLAGS_FIBER
) &&
5317 !(np
->flags
& NIU_FLAGS_XCVR_SERDES
))
5318 val
|= XMAC_CONFIG_1G_PCS_BYPASS
;
5320 val
&= ~XMAC_CONFIG_1G_PCS_BYPASS
;
5323 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5325 if (lp
->active_speed
== SPEED_100
)
5326 val
|= XMAC_CONFIG_SEL_CLK_25MHZ
;
5328 val
&= ~XMAC_CONFIG_SEL_CLK_25MHZ
;
5330 nw64_mac(XMAC_CONFIG
, val
);
5332 val
= nr64_mac(XMAC_CONFIG
);
5333 val
&= ~XMAC_CONFIG_MODE_MASK
;
5334 if (np
->flags
& NIU_FLAGS_10G
) {
5335 val
|= XMAC_CONFIG_MODE_XGMII
;
5337 if (lp
->active_speed
== SPEED_1000
)
5338 val
|= XMAC_CONFIG_MODE_GMII
;
5340 val
|= XMAC_CONFIG_MODE_MII
;
5343 nw64_mac(XMAC_CONFIG
, val
);
5346 static void niu_init_xif_bmac(struct niu
*np
)
5348 struct niu_link_config
*lp
= &np
->link_config
;
5351 val
= BMAC_XIF_CONFIG_TX_OUTPUT_EN
;
5353 if (lp
->loopback_mode
== LOOPBACK_MAC
)
5354 val
|= BMAC_XIF_CONFIG_MII_LOOPBACK
;
5356 val
&= ~BMAC_XIF_CONFIG_MII_LOOPBACK
;
5358 if (lp
->active_speed
== SPEED_1000
)
5359 val
|= BMAC_XIF_CONFIG_GMII_MODE
;
5361 val
&= ~BMAC_XIF_CONFIG_GMII_MODE
;
5363 val
&= ~(BMAC_XIF_CONFIG_LINK_LED
|
5364 BMAC_XIF_CONFIG_LED_POLARITY
);
5366 if (!(np
->flags
& NIU_FLAGS_10G
) &&
5367 !(np
->flags
& NIU_FLAGS_FIBER
) &&
5368 lp
->active_speed
== SPEED_100
)
5369 val
|= BMAC_XIF_CONFIG_25MHZ_CLOCK
;
5371 val
&= ~BMAC_XIF_CONFIG_25MHZ_CLOCK
;
5373 nw64_mac(BMAC_XIF_CONFIG
, val
);
5376 static void niu_init_xif(struct niu
*np
)
5378 if (np
->flags
& NIU_FLAGS_XMAC
)
5379 niu_init_xif_xmac(np
);
5381 niu_init_xif_bmac(np
);
5384 static void niu_pcs_mii_reset(struct niu
*np
)
5387 u64 val
= nr64_pcs(PCS_MII_CTL
);
5388 val
|= PCS_MII_CTL_RST
;
5389 nw64_pcs(PCS_MII_CTL
, val
);
5390 while ((--limit
>= 0) && (val
& PCS_MII_CTL_RST
)) {
5392 val
= nr64_pcs(PCS_MII_CTL
);
5396 static void niu_xpcs_reset(struct niu
*np
)
5399 u64 val
= nr64_xpcs(XPCS_CONTROL1
);
5400 val
|= XPCS_CONTROL1_RESET
;
5401 nw64_xpcs(XPCS_CONTROL1
, val
);
5402 while ((--limit
>= 0) && (val
& XPCS_CONTROL1_RESET
)) {
5404 val
= nr64_xpcs(XPCS_CONTROL1
);
5408 static int niu_init_pcs(struct niu
*np
)
5410 struct niu_link_config
*lp
= &np
->link_config
;
5413 switch (np
->flags
& (NIU_FLAGS_10G
|
5415 NIU_FLAGS_XCVR_SERDES
)) {
5416 case NIU_FLAGS_FIBER
:
5418 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5419 nw64_pcs(PCS_DPATH_MODE
, 0);
5420 niu_pcs_mii_reset(np
);
5424 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
5425 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
5427 if (!(np
->flags
& NIU_FLAGS_XMAC
))
5430 /* 10G copper or fiber */
5431 val
= nr64_mac(XMAC_CONFIG
);
5432 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5433 nw64_mac(XMAC_CONFIG
, val
);
5437 val
= nr64_xpcs(XPCS_CONTROL1
);
5438 if (lp
->loopback_mode
== LOOPBACK_PHY
)
5439 val
|= XPCS_CONTROL1_LOOPBACK
;
5441 val
&= ~XPCS_CONTROL1_LOOPBACK
;
5442 nw64_xpcs(XPCS_CONTROL1
, val
);
5444 nw64_xpcs(XPCS_DESKEW_ERR_CNT
, 0);
5445 (void) nr64_xpcs(XPCS_SYMERR_CNT01
);
5446 (void) nr64_xpcs(XPCS_SYMERR_CNT23
);
5450 case NIU_FLAGS_XCVR_SERDES
:
5452 niu_pcs_mii_reset(np
);
5453 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5454 nw64_pcs(PCS_DPATH_MODE
, 0);
5459 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
5460 /* 1G RGMII FIBER */
5461 nw64_pcs(PCS_DPATH_MODE
, PCS_DPATH_MODE_MII
);
5462 niu_pcs_mii_reset(np
);
5472 static int niu_reset_tx_xmac(struct niu
*np
)
5474 return niu_set_and_wait_clear_mac(np
, XTXMAC_SW_RST
,
5475 (XTXMAC_SW_RST_REG_RS
|
5476 XTXMAC_SW_RST_SOFT_RST
),
5477 1000, 100, "XTXMAC_SW_RST");
5480 static int niu_reset_tx_bmac(struct niu
*np
)
5484 nw64_mac(BTXMAC_SW_RST
, BTXMAC_SW_RST_RESET
);
5486 while (--limit
>= 0) {
5487 if (!(nr64_mac(BTXMAC_SW_RST
) & BTXMAC_SW_RST_RESET
))
5492 dev_err(np
->device
, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5494 (unsigned long long) nr64_mac(BTXMAC_SW_RST
));
5501 static int niu_reset_tx_mac(struct niu
*np
)
5503 if (np
->flags
& NIU_FLAGS_XMAC
)
5504 return niu_reset_tx_xmac(np
);
5506 return niu_reset_tx_bmac(np
);
5509 static void niu_init_tx_xmac(struct niu
*np
, u64 min
, u64 max
)
5513 val
= nr64_mac(XMAC_MIN
);
5514 val
&= ~(XMAC_MIN_TX_MIN_PKT_SIZE
|
5515 XMAC_MIN_RX_MIN_PKT_SIZE
);
5516 val
|= (min
<< XMAC_MIN_RX_MIN_PKT_SIZE_SHFT
);
5517 val
|= (min
<< XMAC_MIN_TX_MIN_PKT_SIZE_SHFT
);
5518 nw64_mac(XMAC_MIN
, val
);
5520 nw64_mac(XMAC_MAX
, max
);
5522 nw64_mac(XTXMAC_STAT_MSK
, ~(u64
)0);
5524 val
= nr64_mac(XMAC_IPG
);
5525 if (np
->flags
& NIU_FLAGS_10G
) {
5526 val
&= ~XMAC_IPG_IPG_XGMII
;
5527 val
|= (IPG_12_15_XGMII
<< XMAC_IPG_IPG_XGMII_SHIFT
);
5529 val
&= ~XMAC_IPG_IPG_MII_GMII
;
5530 val
|= (IPG_12_MII_GMII
<< XMAC_IPG_IPG_MII_GMII_SHIFT
);
5532 nw64_mac(XMAC_IPG
, val
);
5534 val
= nr64_mac(XMAC_CONFIG
);
5535 val
&= ~(XMAC_CONFIG_ALWAYS_NO_CRC
|
5536 XMAC_CONFIG_STRETCH_MODE
|
5537 XMAC_CONFIG_VAR_MIN_IPG_EN
|
5538 XMAC_CONFIG_TX_ENABLE
);
5539 nw64_mac(XMAC_CONFIG
, val
);
5541 nw64_mac(TXMAC_FRM_CNT
, 0);
5542 nw64_mac(TXMAC_BYTE_CNT
, 0);
5545 static void niu_init_tx_bmac(struct niu
*np
, u64 min
, u64 max
)
5549 nw64_mac(BMAC_MIN_FRAME
, min
);
5550 nw64_mac(BMAC_MAX_FRAME
, max
);
5552 nw64_mac(BTXMAC_STATUS_MASK
, ~(u64
)0);
5553 nw64_mac(BMAC_CTRL_TYPE
, 0x8808);
5554 nw64_mac(BMAC_PREAMBLE_SIZE
, 7);
5556 val
= nr64_mac(BTXMAC_CONFIG
);
5557 val
&= ~(BTXMAC_CONFIG_FCS_DISABLE
|
5558 BTXMAC_CONFIG_ENABLE
);
5559 nw64_mac(BTXMAC_CONFIG
, val
);
5562 static void niu_init_tx_mac(struct niu
*np
)
5567 if (np
->dev
->mtu
> ETH_DATA_LEN
)
5572 /* The XMAC_MIN register only accepts values for TX min which
5573 * have the low 3 bits cleared.
5577 if (np
->flags
& NIU_FLAGS_XMAC
)
5578 niu_init_tx_xmac(np
, min
, max
);
5580 niu_init_tx_bmac(np
, min
, max
);
5583 static int niu_reset_rx_xmac(struct niu
*np
)
5587 nw64_mac(XRXMAC_SW_RST
,
5588 XRXMAC_SW_RST_REG_RS
| XRXMAC_SW_RST_SOFT_RST
);
5590 while (--limit
>= 0) {
5591 if (!(nr64_mac(XRXMAC_SW_RST
) & (XRXMAC_SW_RST_REG_RS
|
5592 XRXMAC_SW_RST_SOFT_RST
)))
5597 dev_err(np
->device
, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5599 (unsigned long long) nr64_mac(XRXMAC_SW_RST
));
5606 static int niu_reset_rx_bmac(struct niu
*np
)
5610 nw64_mac(BRXMAC_SW_RST
, BRXMAC_SW_RST_RESET
);
5612 while (--limit
>= 0) {
5613 if (!(nr64_mac(BRXMAC_SW_RST
) & BRXMAC_SW_RST_RESET
))
5618 dev_err(np
->device
, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5620 (unsigned long long) nr64_mac(BRXMAC_SW_RST
));
5627 static int niu_reset_rx_mac(struct niu
*np
)
5629 if (np
->flags
& NIU_FLAGS_XMAC
)
5630 return niu_reset_rx_xmac(np
);
5632 return niu_reset_rx_bmac(np
);
5635 static void niu_init_rx_xmac(struct niu
*np
)
5637 struct niu_parent
*parent
= np
->parent
;
5638 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5639 int first_rdc_table
= tp
->first_table_num
;
5643 nw64_mac(XMAC_ADD_FILT0
, 0);
5644 nw64_mac(XMAC_ADD_FILT1
, 0);
5645 nw64_mac(XMAC_ADD_FILT2
, 0);
5646 nw64_mac(XMAC_ADD_FILT12_MASK
, 0);
5647 nw64_mac(XMAC_ADD_FILT00_MASK
, 0);
5648 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5649 nw64_mac(XMAC_HASH_TBL(i
), 0);
5650 nw64_mac(XRXMAC_STAT_MSK
, ~(u64
)0);
5651 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5652 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5654 val
= nr64_mac(XMAC_CONFIG
);
5655 val
&= ~(XMAC_CONFIG_RX_MAC_ENABLE
|
5656 XMAC_CONFIG_PROMISCUOUS
|
5657 XMAC_CONFIG_PROMISC_GROUP
|
5658 XMAC_CONFIG_ERR_CHK_DIS
|
5659 XMAC_CONFIG_RX_CRC_CHK_DIS
|
5660 XMAC_CONFIG_RESERVED_MULTICAST
|
5661 XMAC_CONFIG_RX_CODEV_CHK_DIS
|
5662 XMAC_CONFIG_ADDR_FILTER_EN
|
5663 XMAC_CONFIG_RCV_PAUSE_ENABLE
|
5664 XMAC_CONFIG_STRIP_CRC
|
5665 XMAC_CONFIG_PASS_FLOW_CTRL
|
5666 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN
);
5667 val
|= (XMAC_CONFIG_HASH_FILTER_EN
);
5668 nw64_mac(XMAC_CONFIG
, val
);
5670 nw64_mac(RXMAC_BT_CNT
, 0);
5671 nw64_mac(RXMAC_BC_FRM_CNT
, 0);
5672 nw64_mac(RXMAC_MC_FRM_CNT
, 0);
5673 nw64_mac(RXMAC_FRAG_CNT
, 0);
5674 nw64_mac(RXMAC_HIST_CNT1
, 0);
5675 nw64_mac(RXMAC_HIST_CNT2
, 0);
5676 nw64_mac(RXMAC_HIST_CNT3
, 0);
5677 nw64_mac(RXMAC_HIST_CNT4
, 0);
5678 nw64_mac(RXMAC_HIST_CNT5
, 0);
5679 nw64_mac(RXMAC_HIST_CNT6
, 0);
5680 nw64_mac(RXMAC_HIST_CNT7
, 0);
5681 nw64_mac(RXMAC_MPSZER_CNT
, 0);
5682 nw64_mac(RXMAC_CRC_ER_CNT
, 0);
5683 nw64_mac(RXMAC_CD_VIO_CNT
, 0);
5684 nw64_mac(LINK_FAULT_CNT
, 0);
5687 static void niu_init_rx_bmac(struct niu
*np
)
5689 struct niu_parent
*parent
= np
->parent
;
5690 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5691 int first_rdc_table
= tp
->first_table_num
;
5695 nw64_mac(BMAC_ADD_FILT0
, 0);
5696 nw64_mac(BMAC_ADD_FILT1
, 0);
5697 nw64_mac(BMAC_ADD_FILT2
, 0);
5698 nw64_mac(BMAC_ADD_FILT12_MASK
, 0);
5699 nw64_mac(BMAC_ADD_FILT00_MASK
, 0);
5700 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5701 nw64_mac(BMAC_HASH_TBL(i
), 0);
5702 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5703 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5704 nw64_mac(BRXMAC_STATUS_MASK
, ~(u64
)0);
5706 val
= nr64_mac(BRXMAC_CONFIG
);
5707 val
&= ~(BRXMAC_CONFIG_ENABLE
|
5708 BRXMAC_CONFIG_STRIP_PAD
|
5709 BRXMAC_CONFIG_STRIP_FCS
|
5710 BRXMAC_CONFIG_PROMISC
|
5711 BRXMAC_CONFIG_PROMISC_GRP
|
5712 BRXMAC_CONFIG_ADDR_FILT_EN
|
5713 BRXMAC_CONFIG_DISCARD_DIS
);
5714 val
|= (BRXMAC_CONFIG_HASH_FILT_EN
);
5715 nw64_mac(BRXMAC_CONFIG
, val
);
5717 val
= nr64_mac(BMAC_ADDR_CMPEN
);
5718 val
|= BMAC_ADDR_CMPEN_EN0
;
5719 nw64_mac(BMAC_ADDR_CMPEN
, val
);
5722 static void niu_init_rx_mac(struct niu
*np
)
5724 niu_set_primary_mac(np
, np
->dev
->dev_addr
);
5726 if (np
->flags
& NIU_FLAGS_XMAC
)
5727 niu_init_rx_xmac(np
);
5729 niu_init_rx_bmac(np
);
5732 static void niu_enable_tx_xmac(struct niu
*np
, int on
)
5734 u64 val
= nr64_mac(XMAC_CONFIG
);
5737 val
|= XMAC_CONFIG_TX_ENABLE
;
5739 val
&= ~XMAC_CONFIG_TX_ENABLE
;
5740 nw64_mac(XMAC_CONFIG
, val
);
5743 static void niu_enable_tx_bmac(struct niu
*np
, int on
)
5745 u64 val
= nr64_mac(BTXMAC_CONFIG
);
5748 val
|= BTXMAC_CONFIG_ENABLE
;
5750 val
&= ~BTXMAC_CONFIG_ENABLE
;
5751 nw64_mac(BTXMAC_CONFIG
, val
);
5754 static void niu_enable_tx_mac(struct niu
*np
, int on
)
5756 if (np
->flags
& NIU_FLAGS_XMAC
)
5757 niu_enable_tx_xmac(np
, on
);
5759 niu_enable_tx_bmac(np
, on
);
5762 static void niu_enable_rx_xmac(struct niu
*np
, int on
)
5764 u64 val
= nr64_mac(XMAC_CONFIG
);
5766 val
&= ~(XMAC_CONFIG_HASH_FILTER_EN
|
5767 XMAC_CONFIG_PROMISCUOUS
);
5769 if (np
->flags
& NIU_FLAGS_MCAST
)
5770 val
|= XMAC_CONFIG_HASH_FILTER_EN
;
5771 if (np
->flags
& NIU_FLAGS_PROMISC
)
5772 val
|= XMAC_CONFIG_PROMISCUOUS
;
5775 val
|= XMAC_CONFIG_RX_MAC_ENABLE
;
5777 val
&= ~XMAC_CONFIG_RX_MAC_ENABLE
;
5778 nw64_mac(XMAC_CONFIG
, val
);
5781 static void niu_enable_rx_bmac(struct niu
*np
, int on
)
5783 u64 val
= nr64_mac(BRXMAC_CONFIG
);
5785 val
&= ~(BRXMAC_CONFIG_HASH_FILT_EN
|
5786 BRXMAC_CONFIG_PROMISC
);
5788 if (np
->flags
& NIU_FLAGS_MCAST
)
5789 val
|= BRXMAC_CONFIG_HASH_FILT_EN
;
5790 if (np
->flags
& NIU_FLAGS_PROMISC
)
5791 val
|= BRXMAC_CONFIG_PROMISC
;
5794 val
|= BRXMAC_CONFIG_ENABLE
;
5796 val
&= ~BRXMAC_CONFIG_ENABLE
;
5797 nw64_mac(BRXMAC_CONFIG
, val
);
5800 static void niu_enable_rx_mac(struct niu
*np
, int on
)
5802 if (np
->flags
& NIU_FLAGS_XMAC
)
5803 niu_enable_rx_xmac(np
, on
);
5805 niu_enable_rx_bmac(np
, on
);
5808 static int niu_init_mac(struct niu
*np
)
5813 err
= niu_init_pcs(np
);
5817 err
= niu_reset_tx_mac(np
);
5820 niu_init_tx_mac(np
);
5821 err
= niu_reset_rx_mac(np
);
5824 niu_init_rx_mac(np
);
5826 /* This looks hookey but the RX MAC reset we just did will
5827 * undo some of the state we setup in niu_init_tx_mac() so we
5828 * have to call it again. In particular, the RX MAC reset will
5829 * set the XMAC_MAX register back to it's default value.
5831 niu_init_tx_mac(np
);
5832 niu_enable_tx_mac(np
, 1);
5834 niu_enable_rx_mac(np
, 1);
5839 static void niu_stop_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5841 (void) niu_tx_channel_stop(np
, rp
->tx_channel
);
5844 static void niu_stop_tx_channels(struct niu
*np
)
5848 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5849 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5851 niu_stop_one_tx_channel(np
, rp
);
5855 static void niu_reset_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5857 (void) niu_tx_channel_reset(np
, rp
->tx_channel
);
5860 static void niu_reset_tx_channels(struct niu
*np
)
5864 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5865 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5867 niu_reset_one_tx_channel(np
, rp
);
5871 static void niu_stop_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5873 (void) niu_enable_rx_channel(np
, rp
->rx_channel
, 0);
5876 static void niu_stop_rx_channels(struct niu
*np
)
5880 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5881 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5883 niu_stop_one_rx_channel(np
, rp
);
5887 static void niu_reset_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5889 int channel
= rp
->rx_channel
;
5891 (void) niu_rx_channel_reset(np
, channel
);
5892 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_ALL
);
5893 nw64(RX_DMA_CTL_STAT(channel
), 0);
5894 (void) niu_enable_rx_channel(np
, channel
, 0);
5897 static void niu_reset_rx_channels(struct niu
*np
)
5901 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5902 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5904 niu_reset_one_rx_channel(np
, rp
);
5908 static void niu_disable_ipp(struct niu
*np
)
5913 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5914 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5916 while (--limit
>= 0 && (rd
!= wr
)) {
5917 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5918 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5921 (rd
!= 0 && wr
!= 1)) {
5922 netdev_err(np
->dev
, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5923 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR
),
5924 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR
));
5927 val
= nr64_ipp(IPP_CFIG
);
5928 val
&= ~(IPP_CFIG_IPP_ENABLE
|
5929 IPP_CFIG_DFIFO_ECC_EN
|
5930 IPP_CFIG_DROP_BAD_CRC
|
5932 nw64_ipp(IPP_CFIG
, val
);
5934 (void) niu_ipp_reset(np
);
5937 static int niu_init_hw(struct niu
*np
)
5941 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize TXC\n");
5942 niu_txc_enable_port(np
, 1);
5943 niu_txc_port_dma_enable(np
, 1);
5944 niu_txc_set_imask(np
, 0);
5946 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize TX channels\n");
5947 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5948 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5950 err
= niu_init_one_tx_channel(np
, rp
);
5955 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize RX channels\n");
5956 err
= niu_init_rx_channels(np
);
5958 goto out_uninit_tx_channels
;
5960 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize classifier\n");
5961 err
= niu_init_classifier_hw(np
);
5963 goto out_uninit_rx_channels
;
5965 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize ZCP\n");
5966 err
= niu_init_zcp(np
);
5968 goto out_uninit_rx_channels
;
5970 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize IPP\n");
5971 err
= niu_init_ipp(np
);
5973 goto out_uninit_rx_channels
;
5975 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize MAC\n");
5976 err
= niu_init_mac(np
);
5978 goto out_uninit_ipp
;
5983 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Uninit IPP\n");
5984 niu_disable_ipp(np
);
5986 out_uninit_rx_channels
:
5987 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Uninit RX channels\n");
5988 niu_stop_rx_channels(np
);
5989 niu_reset_rx_channels(np
);
5991 out_uninit_tx_channels
:
5992 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Uninit TX channels\n");
5993 niu_stop_tx_channels(np
);
5994 niu_reset_tx_channels(np
);
5999 static void niu_stop_hw(struct niu
*np
)
6001 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Disable interrupts\n");
6002 niu_enable_interrupts(np
, 0);
6004 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Disable RX MAC\n");
6005 niu_enable_rx_mac(np
, 0);
6007 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Disable IPP\n");
6008 niu_disable_ipp(np
);
6010 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Stop TX channels\n");
6011 niu_stop_tx_channels(np
);
6013 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Stop RX channels\n");
6014 niu_stop_rx_channels(np
);
6016 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Reset TX channels\n");
6017 niu_reset_tx_channels(np
);
6019 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Reset RX channels\n");
6020 niu_reset_rx_channels(np
);
6023 static void niu_set_irq_name(struct niu
*np
)
6025 int port
= np
->port
;
6028 sprintf(np
->irq_name
[0], "%s:MAC", np
->dev
->name
);
6031 sprintf(np
->irq_name
[1], "%s:MIF", np
->dev
->name
);
6032 sprintf(np
->irq_name
[2], "%s:SYSERR", np
->dev
->name
);
6036 for (i
= 0; i
< np
->num_ldg
- j
; i
++) {
6037 if (i
< np
->num_rx_rings
)
6038 sprintf(np
->irq_name
[i
+j
], "%s-rx-%d",
6040 else if (i
< np
->num_tx_rings
+ np
->num_rx_rings
)
6041 sprintf(np
->irq_name
[i
+j
], "%s-tx-%d", np
->dev
->name
,
6042 i
- np
->num_rx_rings
);
6046 static int niu_request_irq(struct niu
*np
)
6050 niu_set_irq_name(np
);
6053 for (i
= 0; i
< np
->num_ldg
; i
++) {
6054 struct niu_ldg
*lp
= &np
->ldg
[i
];
6056 err
= request_irq(lp
->irq
, niu_interrupt
, IRQF_SHARED
,
6057 np
->irq_name
[i
], lp
);
6066 for (j
= 0; j
< i
; j
++) {
6067 struct niu_ldg
*lp
= &np
->ldg
[j
];
6069 free_irq(lp
->irq
, lp
);
6074 static void niu_free_irq(struct niu
*np
)
6078 for (i
= 0; i
< np
->num_ldg
; i
++) {
6079 struct niu_ldg
*lp
= &np
->ldg
[i
];
6081 free_irq(lp
->irq
, lp
);
6085 static void niu_enable_napi(struct niu
*np
)
6089 for (i
= 0; i
< np
->num_ldg
; i
++)
6090 napi_enable(&np
->ldg
[i
].napi
);
6093 static void niu_disable_napi(struct niu
*np
)
6097 for (i
= 0; i
< np
->num_ldg
; i
++)
6098 napi_disable(&np
->ldg
[i
].napi
);
6101 static int niu_open(struct net_device
*dev
)
6103 struct niu
*np
= netdev_priv(dev
);
6106 netif_carrier_off(dev
);
6108 err
= niu_alloc_channels(np
);
6112 err
= niu_enable_interrupts(np
, 0);
6114 goto out_free_channels
;
6116 err
= niu_request_irq(np
);
6118 goto out_free_channels
;
6120 niu_enable_napi(np
);
6122 spin_lock_irq(&np
->lock
);
6124 err
= niu_init_hw(np
);
6126 init_timer(&np
->timer
);
6127 np
->timer
.expires
= jiffies
+ HZ
;
6128 np
->timer
.data
= (unsigned long) np
;
6129 np
->timer
.function
= niu_timer
;
6131 err
= niu_enable_interrupts(np
, 1);
6136 spin_unlock_irq(&np
->lock
);
6139 niu_disable_napi(np
);
6143 netif_tx_start_all_queues(dev
);
6145 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6146 netif_carrier_on(dev
);
6148 add_timer(&np
->timer
);
6156 niu_free_channels(np
);
6162 static void niu_full_shutdown(struct niu
*np
, struct net_device
*dev
)
6164 cancel_work_sync(&np
->reset_task
);
6166 niu_disable_napi(np
);
6167 netif_tx_stop_all_queues(dev
);
6169 del_timer_sync(&np
->timer
);
6171 spin_lock_irq(&np
->lock
);
6175 spin_unlock_irq(&np
->lock
);
6178 static int niu_close(struct net_device
*dev
)
6180 struct niu
*np
= netdev_priv(dev
);
6182 niu_full_shutdown(np
, dev
);
6186 niu_free_channels(np
);
6188 niu_handle_led(np
, 0);
6193 static void niu_sync_xmac_stats(struct niu
*np
)
6195 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
6197 mp
->tx_frames
+= nr64_mac(TXMAC_FRM_CNT
);
6198 mp
->tx_bytes
+= nr64_mac(TXMAC_BYTE_CNT
);
6200 mp
->rx_link_faults
+= nr64_mac(LINK_FAULT_CNT
);
6201 mp
->rx_align_errors
+= nr64_mac(RXMAC_ALIGN_ERR_CNT
);
6202 mp
->rx_frags
+= nr64_mac(RXMAC_FRAG_CNT
);
6203 mp
->rx_mcasts
+= nr64_mac(RXMAC_MC_FRM_CNT
);
6204 mp
->rx_bcasts
+= nr64_mac(RXMAC_BC_FRM_CNT
);
6205 mp
->rx_hist_cnt1
+= nr64_mac(RXMAC_HIST_CNT1
);
6206 mp
->rx_hist_cnt2
+= nr64_mac(RXMAC_HIST_CNT2
);
6207 mp
->rx_hist_cnt3
+= nr64_mac(RXMAC_HIST_CNT3
);
6208 mp
->rx_hist_cnt4
+= nr64_mac(RXMAC_HIST_CNT4
);
6209 mp
->rx_hist_cnt5
+= nr64_mac(RXMAC_HIST_CNT5
);
6210 mp
->rx_hist_cnt6
+= nr64_mac(RXMAC_HIST_CNT6
);
6211 mp
->rx_hist_cnt7
+= nr64_mac(RXMAC_HIST_CNT7
);
6212 mp
->rx_octets
+= nr64_mac(RXMAC_BT_CNT
);
6213 mp
->rx_code_violations
+= nr64_mac(RXMAC_CD_VIO_CNT
);
6214 mp
->rx_len_errors
+= nr64_mac(RXMAC_MPSZER_CNT
);
6215 mp
->rx_crc_errors
+= nr64_mac(RXMAC_CRC_ER_CNT
);
6218 static void niu_sync_bmac_stats(struct niu
*np
)
6220 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
6222 mp
->tx_bytes
+= nr64_mac(BTXMAC_BYTE_CNT
);
6223 mp
->tx_frames
+= nr64_mac(BTXMAC_FRM_CNT
);
6225 mp
->rx_frames
+= nr64_mac(BRXMAC_FRAME_CNT
);
6226 mp
->rx_align_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
6227 mp
->rx_crc_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
6228 mp
->rx_len_errors
+= nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT
);
6231 static void niu_sync_mac_stats(struct niu
*np
)
6233 if (np
->flags
& NIU_FLAGS_XMAC
)
6234 niu_sync_xmac_stats(np
);
6236 niu_sync_bmac_stats(np
);
6239 static void niu_get_rx_stats(struct niu
*np
,
6240 struct rtnl_link_stats64
*stats
)
6242 u64 pkts
, dropped
, errors
, bytes
;
6243 struct rx_ring_info
*rx_rings
;
6246 pkts
= dropped
= errors
= bytes
= 0;
6248 rx_rings
= ACCESS_ONCE(np
->rx_rings
);
6252 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6253 struct rx_ring_info
*rp
= &rx_rings
[i
];
6255 niu_sync_rx_discard_stats(np
, rp
, 0);
6257 pkts
+= rp
->rx_packets
;
6258 bytes
+= rp
->rx_bytes
;
6259 dropped
+= rp
->rx_dropped
;
6260 errors
+= rp
->rx_errors
;
6264 stats
->rx_packets
= pkts
;
6265 stats
->rx_bytes
= bytes
;
6266 stats
->rx_dropped
= dropped
;
6267 stats
->rx_errors
= errors
;
6270 static void niu_get_tx_stats(struct niu
*np
,
6271 struct rtnl_link_stats64
*stats
)
6273 u64 pkts
, errors
, bytes
;
6274 struct tx_ring_info
*tx_rings
;
6277 pkts
= errors
= bytes
= 0;
6279 tx_rings
= ACCESS_ONCE(np
->tx_rings
);
6283 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6284 struct tx_ring_info
*rp
= &tx_rings
[i
];
6286 pkts
+= rp
->tx_packets
;
6287 bytes
+= rp
->tx_bytes
;
6288 errors
+= rp
->tx_errors
;
6292 stats
->tx_packets
= pkts
;
6293 stats
->tx_bytes
= bytes
;
6294 stats
->tx_errors
= errors
;
6297 static struct rtnl_link_stats64
*niu_get_stats(struct net_device
*dev
,
6298 struct rtnl_link_stats64
*stats
)
6300 struct niu
*np
= netdev_priv(dev
);
6302 if (netif_running(dev
)) {
6303 niu_get_rx_stats(np
, stats
);
6304 niu_get_tx_stats(np
, stats
);
6310 static void niu_load_hash_xmac(struct niu
*np
, u16
*hash
)
6314 for (i
= 0; i
< 16; i
++)
6315 nw64_mac(XMAC_HASH_TBL(i
), hash
[i
]);
6318 static void niu_load_hash_bmac(struct niu
*np
, u16
*hash
)
6322 for (i
= 0; i
< 16; i
++)
6323 nw64_mac(BMAC_HASH_TBL(i
), hash
[i
]);
6326 static void niu_load_hash(struct niu
*np
, u16
*hash
)
6328 if (np
->flags
& NIU_FLAGS_XMAC
)
6329 niu_load_hash_xmac(np
, hash
);
6331 niu_load_hash_bmac(np
, hash
);
6334 static void niu_set_rx_mode(struct net_device
*dev
)
6336 struct niu
*np
= netdev_priv(dev
);
6337 int i
, alt_cnt
, err
;
6338 struct netdev_hw_addr
*ha
;
6339 unsigned long flags
;
6340 u16 hash
[16] = { 0, };
6342 spin_lock_irqsave(&np
->lock
, flags
);
6343 niu_enable_rx_mac(np
, 0);
6345 np
->flags
&= ~(NIU_FLAGS_MCAST
| NIU_FLAGS_PROMISC
);
6346 if (dev
->flags
& IFF_PROMISC
)
6347 np
->flags
|= NIU_FLAGS_PROMISC
;
6348 if ((dev
->flags
& IFF_ALLMULTI
) || (!netdev_mc_empty(dev
)))
6349 np
->flags
|= NIU_FLAGS_MCAST
;
6351 alt_cnt
= netdev_uc_count(dev
);
6352 if (alt_cnt
> niu_num_alt_addr(np
)) {
6354 np
->flags
|= NIU_FLAGS_PROMISC
;
6360 netdev_for_each_uc_addr(ha
, dev
) {
6361 err
= niu_set_alt_mac(np
, index
, ha
->addr
);
6363 netdev_warn(dev
, "Error %d adding alt mac %d\n",
6365 err
= niu_enable_alt_mac(np
, index
, 1);
6367 netdev_warn(dev
, "Error %d enabling alt mac %d\n",
6374 if (np
->flags
& NIU_FLAGS_XMAC
)
6378 for (i
= alt_start
; i
< niu_num_alt_addr(np
); i
++) {
6379 err
= niu_enable_alt_mac(np
, i
, 0);
6381 netdev_warn(dev
, "Error %d disabling alt mac %d\n",
6385 if (dev
->flags
& IFF_ALLMULTI
) {
6386 for (i
= 0; i
< 16; i
++)
6388 } else if (!netdev_mc_empty(dev
)) {
6389 netdev_for_each_mc_addr(ha
, dev
) {
6390 u32 crc
= ether_crc_le(ETH_ALEN
, ha
->addr
);
6393 hash
[crc
>> 4] |= (1 << (15 - (crc
& 0xf)));
6397 if (np
->flags
& NIU_FLAGS_MCAST
)
6398 niu_load_hash(np
, hash
);
6400 niu_enable_rx_mac(np
, 1);
6401 spin_unlock_irqrestore(&np
->lock
, flags
);
6404 static int niu_set_mac_addr(struct net_device
*dev
, void *p
)
6406 struct niu
*np
= netdev_priv(dev
);
6407 struct sockaddr
*addr
= p
;
6408 unsigned long flags
;
6410 if (!is_valid_ether_addr(addr
->sa_data
))
6411 return -EADDRNOTAVAIL
;
6413 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
6415 if (!netif_running(dev
))
6418 spin_lock_irqsave(&np
->lock
, flags
);
6419 niu_enable_rx_mac(np
, 0);
6420 niu_set_primary_mac(np
, dev
->dev_addr
);
6421 niu_enable_rx_mac(np
, 1);
6422 spin_unlock_irqrestore(&np
->lock
, flags
);
6427 static int niu_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
6432 static void niu_netif_stop(struct niu
*np
)
6434 np
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
6436 niu_disable_napi(np
);
6438 netif_tx_disable(np
->dev
);
6441 static void niu_netif_start(struct niu
*np
)
6443 /* NOTE: unconditional netif_wake_queue is only appropriate
6444 * so long as all callers are assured to have free tx slots
6445 * (such as after niu_init_hw).
6447 netif_tx_wake_all_queues(np
->dev
);
6449 niu_enable_napi(np
);
6451 niu_enable_interrupts(np
, 1);
6454 static void niu_reset_buffers(struct niu
*np
)
6459 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6460 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6462 for (j
= 0, k
= 0; j
< MAX_RBR_RING_SIZE
; j
++) {
6465 page
= rp
->rxhash
[j
];
6468 (struct page
*) page
->mapping
;
6469 u64 base
= page
->index
;
6470 base
= base
>> RBR_DESCR_ADDR_SHIFT
;
6471 rp
->rbr
[k
++] = cpu_to_le32(base
);
6475 for (; k
< MAX_RBR_RING_SIZE
; k
++) {
6476 err
= niu_rbr_add_page(np
, rp
, GFP_ATOMIC
, k
);
6481 rp
->rbr_index
= rp
->rbr_table_size
- 1;
6483 rp
->rbr_pending
= 0;
6484 rp
->rbr_refill_pending
= 0;
6488 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6489 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6491 for (j
= 0; j
< MAX_TX_RING_SIZE
; j
++) {
6492 if (rp
->tx_buffs
[j
].skb
)
6493 (void) release_tx_packet(np
, rp
, j
);
6496 rp
->pending
= MAX_TX_RING_SIZE
;
6504 static void niu_reset_task(struct work_struct
*work
)
6506 struct niu
*np
= container_of(work
, struct niu
, reset_task
);
6507 unsigned long flags
;
6510 spin_lock_irqsave(&np
->lock
, flags
);
6511 if (!netif_running(np
->dev
)) {
6512 spin_unlock_irqrestore(&np
->lock
, flags
);
6516 spin_unlock_irqrestore(&np
->lock
, flags
);
6518 del_timer_sync(&np
->timer
);
6522 spin_lock_irqsave(&np
->lock
, flags
);
6526 spin_unlock_irqrestore(&np
->lock
, flags
);
6528 niu_reset_buffers(np
);
6530 spin_lock_irqsave(&np
->lock
, flags
);
6532 err
= niu_init_hw(np
);
6534 np
->timer
.expires
= jiffies
+ HZ
;
6535 add_timer(&np
->timer
);
6536 niu_netif_start(np
);
6539 spin_unlock_irqrestore(&np
->lock
, flags
);
6542 static void niu_tx_timeout(struct net_device
*dev
)
6544 struct niu
*np
= netdev_priv(dev
);
6546 dev_err(np
->device
, "%s: Transmit timed out, resetting\n",
6549 schedule_work(&np
->reset_task
);
6552 static void niu_set_txd(struct tx_ring_info
*rp
, int index
,
6553 u64 mapping
, u64 len
, u64 mark
,
6556 __le64
*desc
= &rp
->descr
[index
];
6558 *desc
= cpu_to_le64(mark
|
6559 (n_frags
<< TX_DESC_NUM_PTR_SHIFT
) |
6560 (len
<< TX_DESC_TR_LEN_SHIFT
) |
6561 (mapping
& TX_DESC_SAD
));
6564 static u64
niu_compute_tx_flags(struct sk_buff
*skb
, struct ethhdr
*ehdr
,
6565 u64 pad_bytes
, u64 len
)
6567 u16 eth_proto
, eth_proto_inner
;
6568 u64 csum_bits
, l3off
, ihl
, ret
;
6572 eth_proto
= be16_to_cpu(ehdr
->h_proto
);
6573 eth_proto_inner
= eth_proto
;
6574 if (eth_proto
== ETH_P_8021Q
) {
6575 struct vlan_ethhdr
*vp
= (struct vlan_ethhdr
*) ehdr
;
6576 __be16 val
= vp
->h_vlan_encapsulated_proto
;
6578 eth_proto_inner
= be16_to_cpu(val
);
6582 switch (skb
->protocol
) {
6583 case cpu_to_be16(ETH_P_IP
):
6584 ip_proto
= ip_hdr(skb
)->protocol
;
6585 ihl
= ip_hdr(skb
)->ihl
;
6587 case cpu_to_be16(ETH_P_IPV6
):
6588 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
6597 csum_bits
= TXHDR_CSUM_NONE
;
6598 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6601 csum_bits
= (ip_proto
== IPPROTO_TCP
?
6603 (ip_proto
== IPPROTO_UDP
?
6604 TXHDR_CSUM_UDP
: TXHDR_CSUM_SCTP
));
6606 start
= skb_checksum_start_offset(skb
) -
6607 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6608 stuff
= start
+ skb
->csum_offset
;
6610 csum_bits
|= (start
/ 2) << TXHDR_L4START_SHIFT
;
6611 csum_bits
|= (stuff
/ 2) << TXHDR_L4STUFF_SHIFT
;
6614 l3off
= skb_network_offset(skb
) -
6615 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6617 ret
= (((pad_bytes
/ 2) << TXHDR_PAD_SHIFT
) |
6618 (len
<< TXHDR_LEN_SHIFT
) |
6619 ((l3off
/ 2) << TXHDR_L3START_SHIFT
) |
6620 (ihl
<< TXHDR_IHL_SHIFT
) |
6621 ((eth_proto_inner
< ETH_P_802_3_MIN
) ? TXHDR_LLC
: 0) |
6622 ((eth_proto
== ETH_P_8021Q
) ? TXHDR_VLAN
: 0) |
6623 (ipv6
? TXHDR_IP_VER
: 0) |
6629 static netdev_tx_t
niu_start_xmit(struct sk_buff
*skb
,
6630 struct net_device
*dev
)
6632 struct niu
*np
= netdev_priv(dev
);
6633 unsigned long align
, headroom
;
6634 struct netdev_queue
*txq
;
6635 struct tx_ring_info
*rp
;
6636 struct tx_pkt_hdr
*tp
;
6637 unsigned int len
, nfg
;
6638 struct ethhdr
*ehdr
;
6642 i
= skb_get_queue_mapping(skb
);
6643 rp
= &np
->tx_rings
[i
];
6644 txq
= netdev_get_tx_queue(dev
, i
);
6646 if (niu_tx_avail(rp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
6647 netif_tx_stop_queue(txq
);
6648 dev_err(np
->device
, "%s: BUG! Tx ring full when queue awake!\n", dev
->name
);
6650 return NETDEV_TX_BUSY
;
6653 if (skb
->len
< ETH_ZLEN
) {
6654 unsigned int pad_bytes
= ETH_ZLEN
- skb
->len
;
6656 if (skb_pad(skb
, pad_bytes
))
6658 skb_put(skb
, pad_bytes
);
6661 len
= sizeof(struct tx_pkt_hdr
) + 15;
6662 if (skb_headroom(skb
) < len
) {
6663 struct sk_buff
*skb_new
;
6665 skb_new
= skb_realloc_headroom(skb
, len
);
6675 align
= ((unsigned long) skb
->data
& (16 - 1));
6676 headroom
= align
+ sizeof(struct tx_pkt_hdr
);
6678 ehdr
= (struct ethhdr
*) skb
->data
;
6679 tp
= (struct tx_pkt_hdr
*) skb_push(skb
, headroom
);
6681 len
= skb
->len
- sizeof(struct tx_pkt_hdr
);
6682 tp
->flags
= cpu_to_le64(niu_compute_tx_flags(skb
, ehdr
, align
, len
));
6685 len
= skb_headlen(skb
);
6686 mapping
= np
->ops
->map_single(np
->device
, skb
->data
,
6687 len
, DMA_TO_DEVICE
);
6691 rp
->tx_buffs
[prod
].skb
= skb
;
6692 rp
->tx_buffs
[prod
].mapping
= mapping
;
6695 if (++rp
->mark_counter
== rp
->mark_freq
) {
6696 rp
->mark_counter
= 0;
6697 mrk
|= TX_DESC_MARK
;
6702 nfg
= skb_shinfo(skb
)->nr_frags
;
6704 tlen
-= MAX_TX_DESC_LEN
;
6709 unsigned int this_len
= len
;
6711 if (this_len
> MAX_TX_DESC_LEN
)
6712 this_len
= MAX_TX_DESC_LEN
;
6714 niu_set_txd(rp
, prod
, mapping
, this_len
, mrk
, nfg
);
6717 prod
= NEXT_TX(rp
, prod
);
6718 mapping
+= this_len
;
6722 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
6723 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6725 len
= skb_frag_size(frag
);
6726 mapping
= np
->ops
->map_page(np
->device
, skb_frag_page(frag
),
6727 frag
->page_offset
, len
,
6730 rp
->tx_buffs
[prod
].skb
= NULL
;
6731 rp
->tx_buffs
[prod
].mapping
= mapping
;
6733 niu_set_txd(rp
, prod
, mapping
, len
, 0, 0);
6735 prod
= NEXT_TX(rp
, prod
);
6738 if (prod
< rp
->prod
)
6739 rp
->wrap_bit
^= TX_RING_KICK_WRAP
;
6742 nw64(TX_RING_KICK(rp
->tx_channel
), rp
->wrap_bit
| (prod
<< 3));
6744 if (unlikely(niu_tx_avail(rp
) <= (MAX_SKB_FRAGS
+ 1))) {
6745 netif_tx_stop_queue(txq
);
6746 if (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
))
6747 netif_tx_wake_queue(txq
);
6751 return NETDEV_TX_OK
;
6759 static int niu_change_mtu(struct net_device
*dev
, int new_mtu
)
6761 struct niu
*np
= netdev_priv(dev
);
6762 int err
, orig_jumbo
, new_jumbo
;
6764 if (new_mtu
< 68 || new_mtu
> NIU_MAX_MTU
)
6767 orig_jumbo
= (dev
->mtu
> ETH_DATA_LEN
);
6768 new_jumbo
= (new_mtu
> ETH_DATA_LEN
);
6772 if (!netif_running(dev
) ||
6773 (orig_jumbo
== new_jumbo
))
6776 niu_full_shutdown(np
, dev
);
6778 niu_free_channels(np
);
6780 niu_enable_napi(np
);
6782 err
= niu_alloc_channels(np
);
6786 spin_lock_irq(&np
->lock
);
6788 err
= niu_init_hw(np
);
6790 init_timer(&np
->timer
);
6791 np
->timer
.expires
= jiffies
+ HZ
;
6792 np
->timer
.data
= (unsigned long) np
;
6793 np
->timer
.function
= niu_timer
;
6795 err
= niu_enable_interrupts(np
, 1);
6800 spin_unlock_irq(&np
->lock
);
6803 netif_tx_start_all_queues(dev
);
6804 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6805 netif_carrier_on(dev
);
6807 add_timer(&np
->timer
);
6813 static void niu_get_drvinfo(struct net_device
*dev
,
6814 struct ethtool_drvinfo
*info
)
6816 struct niu
*np
= netdev_priv(dev
);
6817 struct niu_vpd
*vpd
= &np
->vpd
;
6819 strlcpy(info
->driver
, DRV_MODULE_NAME
, sizeof(info
->driver
));
6820 strlcpy(info
->version
, DRV_MODULE_VERSION
, sizeof(info
->version
));
6821 snprintf(info
->fw_version
, sizeof(info
->fw_version
), "%d.%d",
6822 vpd
->fcode_major
, vpd
->fcode_minor
);
6823 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
)
6824 strlcpy(info
->bus_info
, pci_name(np
->pdev
),
6825 sizeof(info
->bus_info
));
6828 static int niu_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6830 struct niu
*np
= netdev_priv(dev
);
6831 struct niu_link_config
*lp
;
6833 lp
= &np
->link_config
;
6835 memset(cmd
, 0, sizeof(*cmd
));
6836 cmd
->phy_address
= np
->phy_addr
;
6837 cmd
->supported
= lp
->supported
;
6838 cmd
->advertising
= lp
->active_advertising
;
6839 cmd
->autoneg
= lp
->active_autoneg
;
6840 ethtool_cmd_speed_set(cmd
, lp
->active_speed
);
6841 cmd
->duplex
= lp
->active_duplex
;
6842 cmd
->port
= (np
->flags
& NIU_FLAGS_FIBER
) ? PORT_FIBRE
: PORT_TP
;
6843 cmd
->transceiver
= (np
->flags
& NIU_FLAGS_XCVR_SERDES
) ?
6844 XCVR_EXTERNAL
: XCVR_INTERNAL
;
6849 static int niu_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6851 struct niu
*np
= netdev_priv(dev
);
6852 struct niu_link_config
*lp
= &np
->link_config
;
6854 lp
->advertising
= cmd
->advertising
;
6855 lp
->speed
= ethtool_cmd_speed(cmd
);
6856 lp
->duplex
= cmd
->duplex
;
6857 lp
->autoneg
= cmd
->autoneg
;
6858 return niu_init_link(np
);
6861 static u32
niu_get_msglevel(struct net_device
*dev
)
6863 struct niu
*np
= netdev_priv(dev
);
6864 return np
->msg_enable
;
6867 static void niu_set_msglevel(struct net_device
*dev
, u32 value
)
6869 struct niu
*np
= netdev_priv(dev
);
6870 np
->msg_enable
= value
;
6873 static int niu_nway_reset(struct net_device
*dev
)
6875 struct niu
*np
= netdev_priv(dev
);
6877 if (np
->link_config
.autoneg
)
6878 return niu_init_link(np
);
6883 static int niu_get_eeprom_len(struct net_device
*dev
)
6885 struct niu
*np
= netdev_priv(dev
);
6887 return np
->eeprom_len
;
6890 static int niu_get_eeprom(struct net_device
*dev
,
6891 struct ethtool_eeprom
*eeprom
, u8
*data
)
6893 struct niu
*np
= netdev_priv(dev
);
6894 u32 offset
, len
, val
;
6896 offset
= eeprom
->offset
;
6899 if (offset
+ len
< offset
)
6901 if (offset
>= np
->eeprom_len
)
6903 if (offset
+ len
> np
->eeprom_len
)
6904 len
= eeprom
->len
= np
->eeprom_len
- offset
;
6907 u32 b_offset
, b_count
;
6909 b_offset
= offset
& 3;
6910 b_count
= 4 - b_offset
;
6914 val
= nr64(ESPC_NCR((offset
- b_offset
) / 4));
6915 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
6921 val
= nr64(ESPC_NCR(offset
/ 4));
6922 memcpy(data
, &val
, 4);
6928 val
= nr64(ESPC_NCR(offset
/ 4));
6929 memcpy(data
, &val
, len
);
6934 static void niu_ethflow_to_l3proto(int flow_type
, u8
*pid
)
6936 switch (flow_type
) {
6947 *pid
= IPPROTO_SCTP
;
6963 static int niu_class_to_ethflow(u64
class, int *flow_type
)
6966 case CLASS_CODE_TCP_IPV4
:
6967 *flow_type
= TCP_V4_FLOW
;
6969 case CLASS_CODE_UDP_IPV4
:
6970 *flow_type
= UDP_V4_FLOW
;
6972 case CLASS_CODE_AH_ESP_IPV4
:
6973 *flow_type
= AH_V4_FLOW
;
6975 case CLASS_CODE_SCTP_IPV4
:
6976 *flow_type
= SCTP_V4_FLOW
;
6978 case CLASS_CODE_TCP_IPV6
:
6979 *flow_type
= TCP_V6_FLOW
;
6981 case CLASS_CODE_UDP_IPV6
:
6982 *flow_type
= UDP_V6_FLOW
;
6984 case CLASS_CODE_AH_ESP_IPV6
:
6985 *flow_type
= AH_V6_FLOW
;
6987 case CLASS_CODE_SCTP_IPV6
:
6988 *flow_type
= SCTP_V6_FLOW
;
6990 case CLASS_CODE_USER_PROG1
:
6991 case CLASS_CODE_USER_PROG2
:
6992 case CLASS_CODE_USER_PROG3
:
6993 case CLASS_CODE_USER_PROG4
:
6994 *flow_type
= IP_USER_FLOW
;
7003 static int niu_ethflow_to_class(int flow_type
, u64
*class)
7005 switch (flow_type
) {
7007 *class = CLASS_CODE_TCP_IPV4
;
7010 *class = CLASS_CODE_UDP_IPV4
;
7012 case AH_ESP_V4_FLOW
:
7015 *class = CLASS_CODE_AH_ESP_IPV4
;
7018 *class = CLASS_CODE_SCTP_IPV4
;
7021 *class = CLASS_CODE_TCP_IPV6
;
7024 *class = CLASS_CODE_UDP_IPV6
;
7026 case AH_ESP_V6_FLOW
:
7029 *class = CLASS_CODE_AH_ESP_IPV6
;
7032 *class = CLASS_CODE_SCTP_IPV6
;
7041 static u64
niu_flowkey_to_ethflow(u64 flow_key
)
7045 if (flow_key
& FLOW_KEY_L2DA
)
7046 ethflow
|= RXH_L2DA
;
7047 if (flow_key
& FLOW_KEY_VLAN
)
7048 ethflow
|= RXH_VLAN
;
7049 if (flow_key
& FLOW_KEY_IPSA
)
7050 ethflow
|= RXH_IP_SRC
;
7051 if (flow_key
& FLOW_KEY_IPDA
)
7052 ethflow
|= RXH_IP_DST
;
7053 if (flow_key
& FLOW_KEY_PROTO
)
7054 ethflow
|= RXH_L3_PROTO
;
7055 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
))
7056 ethflow
|= RXH_L4_B_0_1
;
7057 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
))
7058 ethflow
|= RXH_L4_B_2_3
;
7064 static int niu_ethflow_to_flowkey(u64 ethflow
, u64
*flow_key
)
7068 if (ethflow
& RXH_L2DA
)
7069 key
|= FLOW_KEY_L2DA
;
7070 if (ethflow
& RXH_VLAN
)
7071 key
|= FLOW_KEY_VLAN
;
7072 if (ethflow
& RXH_IP_SRC
)
7073 key
|= FLOW_KEY_IPSA
;
7074 if (ethflow
& RXH_IP_DST
)
7075 key
|= FLOW_KEY_IPDA
;
7076 if (ethflow
& RXH_L3_PROTO
)
7077 key
|= FLOW_KEY_PROTO
;
7078 if (ethflow
& RXH_L4_B_0_1
)
7079 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
);
7080 if (ethflow
& RXH_L4_B_2_3
)
7081 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
);
7089 static int niu_get_hash_opts(struct niu
*np
, struct ethtool_rxnfc
*nfc
)
7095 if (!niu_ethflow_to_class(nfc
->flow_type
, &class))
7098 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
7100 nfc
->data
= RXH_DISCARD
;
7102 nfc
->data
= niu_flowkey_to_ethflow(np
->parent
->flow_key
[class -
7103 CLASS_CODE_USER_PROG1
]);
7107 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry
*tp
,
7108 struct ethtool_rx_flow_spec
*fsp
)
7113 tmp
= (tp
->key
[3] & TCAM_V4KEY3_SADDR
) >> TCAM_V4KEY3_SADDR_SHIFT
;
7114 fsp
->h_u
.tcp_ip4_spec
.ip4src
= cpu_to_be32(tmp
);
7116 tmp
= (tp
->key
[3] & TCAM_V4KEY3_DADDR
) >> TCAM_V4KEY3_DADDR_SHIFT
;
7117 fsp
->h_u
.tcp_ip4_spec
.ip4dst
= cpu_to_be32(tmp
);
7119 tmp
= (tp
->key_mask
[3] & TCAM_V4KEY3_SADDR
) >> TCAM_V4KEY3_SADDR_SHIFT
;
7120 fsp
->m_u
.tcp_ip4_spec
.ip4src
= cpu_to_be32(tmp
);
7122 tmp
= (tp
->key_mask
[3] & TCAM_V4KEY3_DADDR
) >> TCAM_V4KEY3_DADDR_SHIFT
;
7123 fsp
->m_u
.tcp_ip4_spec
.ip4dst
= cpu_to_be32(tmp
);
7125 fsp
->h_u
.tcp_ip4_spec
.tos
= (tp
->key
[2] & TCAM_V4KEY2_TOS
) >>
7126 TCAM_V4KEY2_TOS_SHIFT
;
7127 fsp
->m_u
.tcp_ip4_spec
.tos
= (tp
->key_mask
[2] & TCAM_V4KEY2_TOS
) >>
7128 TCAM_V4KEY2_TOS_SHIFT
;
7130 switch (fsp
->flow_type
) {
7134 prt
= ((tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7135 TCAM_V4KEY2_PORT_SPI_SHIFT
) >> 16;
7136 fsp
->h_u
.tcp_ip4_spec
.psrc
= cpu_to_be16(prt
);
7138 prt
= ((tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7139 TCAM_V4KEY2_PORT_SPI_SHIFT
) & 0xffff;
7140 fsp
->h_u
.tcp_ip4_spec
.pdst
= cpu_to_be16(prt
);
7142 prt
= ((tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7143 TCAM_V4KEY2_PORT_SPI_SHIFT
) >> 16;
7144 fsp
->m_u
.tcp_ip4_spec
.psrc
= cpu_to_be16(prt
);
7146 prt
= ((tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7147 TCAM_V4KEY2_PORT_SPI_SHIFT
) & 0xffff;
7148 fsp
->m_u
.tcp_ip4_spec
.pdst
= cpu_to_be16(prt
);
7152 tmp
= (tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7153 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7154 fsp
->h_u
.ah_ip4_spec
.spi
= cpu_to_be32(tmp
);
7156 tmp
= (tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7157 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7158 fsp
->m_u
.ah_ip4_spec
.spi
= cpu_to_be32(tmp
);
7161 tmp
= (tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7162 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7163 fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
= cpu_to_be32(tmp
);
7165 tmp
= (tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7166 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7167 fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
= cpu_to_be32(tmp
);
7169 fsp
->h_u
.usr_ip4_spec
.proto
=
7170 (tp
->key
[2] & TCAM_V4KEY2_PROTO
) >>
7171 TCAM_V4KEY2_PROTO_SHIFT
;
7172 fsp
->m_u
.usr_ip4_spec
.proto
=
7173 (tp
->key_mask
[2] & TCAM_V4KEY2_PROTO
) >>
7174 TCAM_V4KEY2_PROTO_SHIFT
;
7176 fsp
->h_u
.usr_ip4_spec
.ip_ver
= ETH_RX_NFC_IP4
;
7183 static int niu_get_ethtool_tcam_entry(struct niu
*np
,
7184 struct ethtool_rxnfc
*nfc
)
7186 struct niu_parent
*parent
= np
->parent
;
7187 struct niu_tcam_entry
*tp
;
7188 struct ethtool_rx_flow_spec
*fsp
= &nfc
->fs
;
7193 idx
= tcam_get_index(np
, (u16
)nfc
->fs
.location
);
7195 tp
= &parent
->tcam
[idx
];
7197 netdev_info(np
->dev
, "niu%d: entry [%d] invalid for idx[%d]\n",
7198 parent
->index
, (u16
)nfc
->fs
.location
, idx
);
7202 /* fill the flow spec entry */
7203 class = (tp
->key
[0] & TCAM_V4KEY0_CLASS_CODE
) >>
7204 TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7205 ret
= niu_class_to_ethflow(class, &fsp
->flow_type
);
7208 netdev_info(np
->dev
, "niu%d: niu_class_to_ethflow failed\n",
7214 if (fsp
->flow_type
== AH_V4_FLOW
|| fsp
->flow_type
== AH_V6_FLOW
) {
7215 u32 proto
= (tp
->key
[2] & TCAM_V4KEY2_PROTO
) >>
7216 TCAM_V4KEY2_PROTO_SHIFT
;
7217 if (proto
== IPPROTO_ESP
) {
7218 if (fsp
->flow_type
== AH_V4_FLOW
)
7219 fsp
->flow_type
= ESP_V4_FLOW
;
7221 fsp
->flow_type
= ESP_V6_FLOW
;
7225 switch (fsp
->flow_type
) {
7231 niu_get_ip4fs_from_tcam_key(tp
, fsp
);
7238 /* Not yet implemented */
7242 niu_get_ip4fs_from_tcam_key(tp
, fsp
);
7252 if (tp
->assoc_data
& TCAM_ASSOCDATA_DISC
)
7253 fsp
->ring_cookie
= RX_CLS_FLOW_DISC
;
7255 fsp
->ring_cookie
= (tp
->assoc_data
& TCAM_ASSOCDATA_OFFSET
) >>
7256 TCAM_ASSOCDATA_OFFSET_SHIFT
;
7258 /* put the tcam size here */
7259 nfc
->data
= tcam_get_size(np
);
7264 static int niu_get_ethtool_tcam_all(struct niu
*np
,
7265 struct ethtool_rxnfc
*nfc
,
7268 struct niu_parent
*parent
= np
->parent
;
7269 struct niu_tcam_entry
*tp
;
7271 unsigned long flags
;
7274 /* put the tcam size here */
7275 nfc
->data
= tcam_get_size(np
);
7277 niu_lock_parent(np
, flags
);
7278 for (cnt
= 0, i
= 0; i
< nfc
->data
; i
++) {
7279 idx
= tcam_get_index(np
, i
);
7280 tp
= &parent
->tcam
[idx
];
7283 if (cnt
== nfc
->rule_cnt
) {
7290 niu_unlock_parent(np
, flags
);
7292 nfc
->rule_cnt
= cnt
;
7297 static int niu_get_nfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
,
7300 struct niu
*np
= netdev_priv(dev
);
7305 ret
= niu_get_hash_opts(np
, cmd
);
7307 case ETHTOOL_GRXRINGS
:
7308 cmd
->data
= np
->num_rx_rings
;
7310 case ETHTOOL_GRXCLSRLCNT
:
7311 cmd
->rule_cnt
= tcam_get_valid_entry_cnt(np
);
7313 case ETHTOOL_GRXCLSRULE
:
7314 ret
= niu_get_ethtool_tcam_entry(np
, cmd
);
7316 case ETHTOOL_GRXCLSRLALL
:
7317 ret
= niu_get_ethtool_tcam_all(np
, cmd
, rule_locs
);
7327 static int niu_set_hash_opts(struct niu
*np
, struct ethtool_rxnfc
*nfc
)
7331 unsigned long flags
;
7333 if (!niu_ethflow_to_class(nfc
->flow_type
, &class))
7336 if (class < CLASS_CODE_USER_PROG1
||
7337 class > CLASS_CODE_SCTP_IPV6
)
7340 if (nfc
->data
& RXH_DISCARD
) {
7341 niu_lock_parent(np
, flags
);
7342 flow_key
= np
->parent
->tcam_key
[class -
7343 CLASS_CODE_USER_PROG1
];
7344 flow_key
|= TCAM_KEY_DISC
;
7345 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
7346 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
7347 niu_unlock_parent(np
, flags
);
7350 /* Discard was set before, but is not set now */
7351 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
7353 niu_lock_parent(np
, flags
);
7354 flow_key
= np
->parent
->tcam_key
[class -
7355 CLASS_CODE_USER_PROG1
];
7356 flow_key
&= ~TCAM_KEY_DISC
;
7357 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
),
7359 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] =
7361 niu_unlock_parent(np
, flags
);
7365 if (!niu_ethflow_to_flowkey(nfc
->data
, &flow_key
))
7368 niu_lock_parent(np
, flags
);
7369 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
7370 np
->parent
->flow_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
7371 niu_unlock_parent(np
, flags
);
7376 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec
*fsp
,
7377 struct niu_tcam_entry
*tp
,
7378 int l2_rdc_tab
, u64
class)
7381 u32 sip
, dip
, sipm
, dipm
, spi
, spim
;
7382 u16 sport
, dport
, spm
, dpm
;
7384 sip
= be32_to_cpu(fsp
->h_u
.tcp_ip4_spec
.ip4src
);
7385 sipm
= be32_to_cpu(fsp
->m_u
.tcp_ip4_spec
.ip4src
);
7386 dip
= be32_to_cpu(fsp
->h_u
.tcp_ip4_spec
.ip4dst
);
7387 dipm
= be32_to_cpu(fsp
->m_u
.tcp_ip4_spec
.ip4dst
);
7389 tp
->key
[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7390 tp
->key_mask
[0] = TCAM_V4KEY0_CLASS_CODE
;
7391 tp
->key
[1] = (u64
)l2_rdc_tab
<< TCAM_V4KEY1_L2RDCNUM_SHIFT
;
7392 tp
->key_mask
[1] = TCAM_V4KEY1_L2RDCNUM
;
7394 tp
->key
[3] = (u64
)sip
<< TCAM_V4KEY3_SADDR_SHIFT
;
7397 tp
->key_mask
[3] = (u64
)sipm
<< TCAM_V4KEY3_SADDR_SHIFT
;
7398 tp
->key_mask
[3] |= dipm
;
7400 tp
->key
[2] |= ((u64
)fsp
->h_u
.tcp_ip4_spec
.tos
<<
7401 TCAM_V4KEY2_TOS_SHIFT
);
7402 tp
->key_mask
[2] |= ((u64
)fsp
->m_u
.tcp_ip4_spec
.tos
<<
7403 TCAM_V4KEY2_TOS_SHIFT
);
7404 switch (fsp
->flow_type
) {
7408 sport
= be16_to_cpu(fsp
->h_u
.tcp_ip4_spec
.psrc
);
7409 spm
= be16_to_cpu(fsp
->m_u
.tcp_ip4_spec
.psrc
);
7410 dport
= be16_to_cpu(fsp
->h_u
.tcp_ip4_spec
.pdst
);
7411 dpm
= be16_to_cpu(fsp
->m_u
.tcp_ip4_spec
.pdst
);
7413 tp
->key
[2] |= (((u64
)sport
<< 16) | dport
);
7414 tp
->key_mask
[2] |= (((u64
)spm
<< 16) | dpm
);
7415 niu_ethflow_to_l3proto(fsp
->flow_type
, &pid
);
7419 spi
= be32_to_cpu(fsp
->h_u
.ah_ip4_spec
.spi
);
7420 spim
= be32_to_cpu(fsp
->m_u
.ah_ip4_spec
.spi
);
7423 tp
->key_mask
[2] |= spim
;
7424 niu_ethflow_to_l3proto(fsp
->flow_type
, &pid
);
7427 spi
= be32_to_cpu(fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
);
7428 spim
= be32_to_cpu(fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
);
7431 tp
->key_mask
[2] |= spim
;
7432 pid
= fsp
->h_u
.usr_ip4_spec
.proto
;
7438 tp
->key
[2] |= ((u64
)pid
<< TCAM_V4KEY2_PROTO_SHIFT
);
7440 tp
->key_mask
[2] |= TCAM_V4KEY2_PROTO
;
7444 static int niu_add_ethtool_tcam_entry(struct niu
*np
,
7445 struct ethtool_rxnfc
*nfc
)
7447 struct niu_parent
*parent
= np
->parent
;
7448 struct niu_tcam_entry
*tp
;
7449 struct ethtool_rx_flow_spec
*fsp
= &nfc
->fs
;
7450 struct niu_rdc_tables
*rdc_table
= &parent
->rdc_group_cfg
[np
->port
];
7451 int l2_rdc_table
= rdc_table
->first_table_num
;
7454 unsigned long flags
;
7459 idx
= nfc
->fs
.location
;
7460 if (idx
>= tcam_get_size(np
))
7463 if (fsp
->flow_type
== IP_USER_FLOW
) {
7465 int add_usr_cls
= 0;
7466 struct ethtool_usrip4_spec
*uspec
= &fsp
->h_u
.usr_ip4_spec
;
7467 struct ethtool_usrip4_spec
*umask
= &fsp
->m_u
.usr_ip4_spec
;
7469 if (uspec
->ip_ver
!= ETH_RX_NFC_IP4
)
7472 niu_lock_parent(np
, flags
);
7474 for (i
= 0; i
< NIU_L3_PROG_CLS
; i
++) {
7475 if (parent
->l3_cls
[i
]) {
7476 if (uspec
->proto
== parent
->l3_cls_pid
[i
]) {
7477 class = parent
->l3_cls
[i
];
7478 parent
->l3_cls_refcnt
[i
]++;
7483 /* Program new user IP class */
7486 class = CLASS_CODE_USER_PROG1
;
7489 class = CLASS_CODE_USER_PROG2
;
7492 class = CLASS_CODE_USER_PROG3
;
7495 class = CLASS_CODE_USER_PROG4
;
7500 ret
= tcam_user_ip_class_set(np
, class, 0,
7507 ret
= tcam_user_ip_class_enable(np
, class, 1);
7510 parent
->l3_cls
[i
] = class;
7511 parent
->l3_cls_pid
[i
] = uspec
->proto
;
7512 parent
->l3_cls_refcnt
[i
]++;
7518 netdev_info(np
->dev
, "niu%d: %s(): Could not find/insert class for pid %d\n",
7519 parent
->index
, __func__
, uspec
->proto
);
7523 niu_unlock_parent(np
, flags
);
7525 if (!niu_ethflow_to_class(fsp
->flow_type
, &class)) {
7530 niu_lock_parent(np
, flags
);
7532 idx
= tcam_get_index(np
, idx
);
7533 tp
= &parent
->tcam
[idx
];
7535 memset(tp
, 0, sizeof(*tp
));
7537 /* fill in the tcam key and mask */
7538 switch (fsp
->flow_type
) {
7544 niu_get_tcamkey_from_ip4fs(fsp
, tp
, l2_rdc_table
, class);
7551 /* Not yet implemented */
7552 netdev_info(np
->dev
, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7553 parent
->index
, __func__
, fsp
->flow_type
);
7557 niu_get_tcamkey_from_ip4fs(fsp
, tp
, l2_rdc_table
, class);
7560 netdev_info(np
->dev
, "niu%d: In %s(): Unknown flow type %d\n",
7561 parent
->index
, __func__
, fsp
->flow_type
);
7566 /* fill in the assoc data */
7567 if (fsp
->ring_cookie
== RX_CLS_FLOW_DISC
) {
7568 tp
->assoc_data
= TCAM_ASSOCDATA_DISC
;
7570 if (fsp
->ring_cookie
>= np
->num_rx_rings
) {
7571 netdev_info(np
->dev
, "niu%d: In %s(): Invalid RX ring %lld\n",
7572 parent
->index
, __func__
,
7573 (long long)fsp
->ring_cookie
);
7577 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
7578 (fsp
->ring_cookie
<<
7579 TCAM_ASSOCDATA_OFFSET_SHIFT
));
7582 err
= tcam_write(np
, idx
, tp
->key
, tp
->key_mask
);
7587 err
= tcam_assoc_write(np
, idx
, tp
->assoc_data
);
7593 /* validate the entry */
7595 np
->clas
.tcam_valid_entries
++;
7597 niu_unlock_parent(np
, flags
);
7602 static int niu_del_ethtool_tcam_entry(struct niu
*np
, u32 loc
)
7604 struct niu_parent
*parent
= np
->parent
;
7605 struct niu_tcam_entry
*tp
;
7607 unsigned long flags
;
7611 if (loc
>= tcam_get_size(np
))
7614 niu_lock_parent(np
, flags
);
7616 idx
= tcam_get_index(np
, loc
);
7617 tp
= &parent
->tcam
[idx
];
7619 /* if the entry is of a user defined class, then update*/
7620 class = (tp
->key
[0] & TCAM_V4KEY0_CLASS_CODE
) >>
7621 TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7623 if (class >= CLASS_CODE_USER_PROG1
&& class <= CLASS_CODE_USER_PROG4
) {
7625 for (i
= 0; i
< NIU_L3_PROG_CLS
; i
++) {
7626 if (parent
->l3_cls
[i
] == class) {
7627 parent
->l3_cls_refcnt
[i
]--;
7628 if (!parent
->l3_cls_refcnt
[i
]) {
7630 ret
= tcam_user_ip_class_enable(np
,
7635 parent
->l3_cls
[i
] = 0;
7636 parent
->l3_cls_pid
[i
] = 0;
7641 if (i
== NIU_L3_PROG_CLS
) {
7642 netdev_info(np
->dev
, "niu%d: In %s(): Usr class 0x%llx not found\n",
7643 parent
->index
, __func__
,
7644 (unsigned long long)class);
7650 ret
= tcam_flush(np
, idx
);
7654 /* invalidate the entry */
7656 np
->clas
.tcam_valid_entries
--;
7658 niu_unlock_parent(np
, flags
);
7663 static int niu_set_nfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
)
7665 struct niu
*np
= netdev_priv(dev
);
7670 ret
= niu_set_hash_opts(np
, cmd
);
7672 case ETHTOOL_SRXCLSRLINS
:
7673 ret
= niu_add_ethtool_tcam_entry(np
, cmd
);
7675 case ETHTOOL_SRXCLSRLDEL
:
7676 ret
= niu_del_ethtool_tcam_entry(np
, cmd
->fs
.location
);
7686 static const struct {
7687 const char string
[ETH_GSTRING_LEN
];
7688 } niu_xmac_stat_keys
[] = {
7691 { "tx_fifo_errors" },
7692 { "tx_overflow_errors" },
7693 { "tx_max_pkt_size_errors" },
7694 { "tx_underflow_errors" },
7695 { "rx_local_faults" },
7696 { "rx_remote_faults" },
7697 { "rx_link_faults" },
7698 { "rx_align_errors" },
7710 { "rx_code_violations" },
7711 { "rx_len_errors" },
7712 { "rx_crc_errors" },
7713 { "rx_underflows" },
7715 { "pause_off_state" },
7716 { "pause_on_state" },
7717 { "pause_received" },
7720 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7722 static const struct {
7723 const char string
[ETH_GSTRING_LEN
];
7724 } niu_bmac_stat_keys
[] = {
7725 { "tx_underflow_errors" },
7726 { "tx_max_pkt_size_errors" },
7731 { "rx_align_errors" },
7732 { "rx_crc_errors" },
7733 { "rx_len_errors" },
7734 { "pause_off_state" },
7735 { "pause_on_state" },
7736 { "pause_received" },
7739 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7741 static const struct {
7742 const char string
[ETH_GSTRING_LEN
];
7743 } niu_rxchan_stat_keys
[] = {
7751 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7753 static const struct {
7754 const char string
[ETH_GSTRING_LEN
];
7755 } niu_txchan_stat_keys
[] = {
7762 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7764 static void niu_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
7766 struct niu
*np
= netdev_priv(dev
);
7769 if (stringset
!= ETH_SS_STATS
)
7772 if (np
->flags
& NIU_FLAGS_XMAC
) {
7773 memcpy(data
, niu_xmac_stat_keys
,
7774 sizeof(niu_xmac_stat_keys
));
7775 data
+= sizeof(niu_xmac_stat_keys
);
7777 memcpy(data
, niu_bmac_stat_keys
,
7778 sizeof(niu_bmac_stat_keys
));
7779 data
+= sizeof(niu_bmac_stat_keys
);
7781 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
7782 memcpy(data
, niu_rxchan_stat_keys
,
7783 sizeof(niu_rxchan_stat_keys
));
7784 data
+= sizeof(niu_rxchan_stat_keys
);
7786 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
7787 memcpy(data
, niu_txchan_stat_keys
,
7788 sizeof(niu_txchan_stat_keys
));
7789 data
+= sizeof(niu_txchan_stat_keys
);
7793 static int niu_get_sset_count(struct net_device
*dev
, int stringset
)
7795 struct niu
*np
= netdev_priv(dev
);
7797 if (stringset
!= ETH_SS_STATS
)
7800 return (np
->flags
& NIU_FLAGS_XMAC
?
7801 NUM_XMAC_STAT_KEYS
:
7802 NUM_BMAC_STAT_KEYS
) +
7803 (np
->num_rx_rings
* NUM_RXCHAN_STAT_KEYS
) +
7804 (np
->num_tx_rings
* NUM_TXCHAN_STAT_KEYS
);
7807 static void niu_get_ethtool_stats(struct net_device
*dev
,
7808 struct ethtool_stats
*stats
, u64
*data
)
7810 struct niu
*np
= netdev_priv(dev
);
7813 niu_sync_mac_stats(np
);
7814 if (np
->flags
& NIU_FLAGS_XMAC
) {
7815 memcpy(data
, &np
->mac_stats
.xmac
,
7816 sizeof(struct niu_xmac_stats
));
7817 data
+= (sizeof(struct niu_xmac_stats
) / sizeof(u64
));
7819 memcpy(data
, &np
->mac_stats
.bmac
,
7820 sizeof(struct niu_bmac_stats
));
7821 data
+= (sizeof(struct niu_bmac_stats
) / sizeof(u64
));
7823 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
7824 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
7826 niu_sync_rx_discard_stats(np
, rp
, 0);
7828 data
[0] = rp
->rx_channel
;
7829 data
[1] = rp
->rx_packets
;
7830 data
[2] = rp
->rx_bytes
;
7831 data
[3] = rp
->rx_dropped
;
7832 data
[4] = rp
->rx_errors
;
7835 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
7836 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
7838 data
[0] = rp
->tx_channel
;
7839 data
[1] = rp
->tx_packets
;
7840 data
[2] = rp
->tx_bytes
;
7841 data
[3] = rp
->tx_errors
;
7846 static u64
niu_led_state_save(struct niu
*np
)
7848 if (np
->flags
& NIU_FLAGS_XMAC
)
7849 return nr64_mac(XMAC_CONFIG
);
7851 return nr64_mac(BMAC_XIF_CONFIG
);
7854 static void niu_led_state_restore(struct niu
*np
, u64 val
)
7856 if (np
->flags
& NIU_FLAGS_XMAC
)
7857 nw64_mac(XMAC_CONFIG
, val
);
7859 nw64_mac(BMAC_XIF_CONFIG
, val
);
7862 static void niu_force_led(struct niu
*np
, int on
)
7866 if (np
->flags
& NIU_FLAGS_XMAC
) {
7868 bit
= XMAC_CONFIG_FORCE_LED_ON
;
7870 reg
= BMAC_XIF_CONFIG
;
7871 bit
= BMAC_XIF_CONFIG_LINK_LED
;
7874 val
= nr64_mac(reg
);
7882 static int niu_set_phys_id(struct net_device
*dev
,
7883 enum ethtool_phys_id_state state
)
7886 struct niu
*np
= netdev_priv(dev
);
7888 if (!netif_running(dev
))
7892 case ETHTOOL_ID_ACTIVE
:
7893 np
->orig_led_state
= niu_led_state_save(np
);
7894 return 1; /* cycle on/off once per second */
7897 niu_force_led(np
, 1);
7900 case ETHTOOL_ID_OFF
:
7901 niu_force_led(np
, 0);
7904 case ETHTOOL_ID_INACTIVE
:
7905 niu_led_state_restore(np
, np
->orig_led_state
);
7911 static const struct ethtool_ops niu_ethtool_ops
= {
7912 .get_drvinfo
= niu_get_drvinfo
,
7913 .get_link
= ethtool_op_get_link
,
7914 .get_msglevel
= niu_get_msglevel
,
7915 .set_msglevel
= niu_set_msglevel
,
7916 .nway_reset
= niu_nway_reset
,
7917 .get_eeprom_len
= niu_get_eeprom_len
,
7918 .get_eeprom
= niu_get_eeprom
,
7919 .get_settings
= niu_get_settings
,
7920 .set_settings
= niu_set_settings
,
7921 .get_strings
= niu_get_strings
,
7922 .get_sset_count
= niu_get_sset_count
,
7923 .get_ethtool_stats
= niu_get_ethtool_stats
,
7924 .set_phys_id
= niu_set_phys_id
,
7925 .get_rxnfc
= niu_get_nfc
,
7926 .set_rxnfc
= niu_set_nfc
,
7929 static int niu_ldg_assign_ldn(struct niu
*np
, struct niu_parent
*parent
,
7932 if (ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
)
7934 if (ldn
< 0 || ldn
> LDN_MAX
)
7937 parent
->ldg_map
[ldn
] = ldg
;
7939 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
) {
7940 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7941 * the firmware, and we're not supposed to change them.
7942 * Validate the mapping, because if it's wrong we probably
7943 * won't get any interrupts and that's painful to debug.
7945 if (nr64(LDG_NUM(ldn
)) != ldg
) {
7946 dev_err(np
->device
, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7948 (unsigned long long) nr64(LDG_NUM(ldn
)));
7952 nw64(LDG_NUM(ldn
), ldg
);
7957 static int niu_set_ldg_timer_res(struct niu
*np
, int res
)
7959 if (res
< 0 || res
> LDG_TIMER_RES_VAL
)
7963 nw64(LDG_TIMER_RES
, res
);
7968 static int niu_set_ldg_sid(struct niu
*np
, int ldg
, int func
, int vector
)
7970 if ((ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
) ||
7971 (func
< 0 || func
> 3) ||
7972 (vector
< 0 || vector
> 0x1f))
7975 nw64(SID(ldg
), (func
<< SID_FUNC_SHIFT
) | vector
);
7980 static int niu_pci_eeprom_read(struct niu
*np
, u32 addr
)
7982 u64 frame
, frame_base
= (ESPC_PIO_STAT_READ_START
|
7983 (addr
<< ESPC_PIO_STAT_ADDR_SHIFT
));
7986 if (addr
> (ESPC_PIO_STAT_ADDR
>> ESPC_PIO_STAT_ADDR_SHIFT
))
7990 nw64(ESPC_PIO_STAT
, frame
);
7994 frame
= nr64(ESPC_PIO_STAT
);
7995 if (frame
& ESPC_PIO_STAT_READ_END
)
7998 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
7999 dev_err(np
->device
, "EEPROM read timeout frame[%llx]\n",
8000 (unsigned long long) frame
);
8005 nw64(ESPC_PIO_STAT
, frame
);
8009 frame
= nr64(ESPC_PIO_STAT
);
8010 if (frame
& ESPC_PIO_STAT_READ_END
)
8013 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
8014 dev_err(np
->device
, "EEPROM read timeout frame[%llx]\n",
8015 (unsigned long long) frame
);
8019 frame
= nr64(ESPC_PIO_STAT
);
8020 return (frame
& ESPC_PIO_STAT_DATA
) >> ESPC_PIO_STAT_DATA_SHIFT
;
8023 static int niu_pci_eeprom_read16(struct niu
*np
, u32 off
)
8025 int err
= niu_pci_eeprom_read(np
, off
);
8031 err
= niu_pci_eeprom_read(np
, off
+ 1);
8034 val
|= (err
& 0xff);
8039 static int niu_pci_eeprom_read16_swp(struct niu
*np
, u32 off
)
8041 int err
= niu_pci_eeprom_read(np
, off
);
8048 err
= niu_pci_eeprom_read(np
, off
+ 1);
8052 val
|= (err
& 0xff) << 8;
8057 static int niu_pci_vpd_get_propname(struct niu
*np
, u32 off
, char *namebuf
,
8062 for (i
= 0; i
< namebuf_len
; i
++) {
8063 int err
= niu_pci_eeprom_read(np
, off
+ i
);
8070 if (i
>= namebuf_len
)
8076 static void niu_vpd_parse_version(struct niu
*np
)
8078 struct niu_vpd
*vpd
= &np
->vpd
;
8079 int len
= strlen(vpd
->version
) + 1;
8080 const char *s
= vpd
->version
;
8083 for (i
= 0; i
< len
- 5; i
++) {
8084 if (!strncmp(s
+ i
, "FCode ", 6))
8091 sscanf(s
, "%d.%d", &vpd
->fcode_major
, &vpd
->fcode_minor
);
8093 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8094 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8095 vpd
->fcode_major
, vpd
->fcode_minor
);
8096 if (vpd
->fcode_major
> NIU_VPD_MIN_MAJOR
||
8097 (vpd
->fcode_major
== NIU_VPD_MIN_MAJOR
&&
8098 vpd
->fcode_minor
>= NIU_VPD_MIN_MINOR
))
8099 np
->flags
|= NIU_FLAGS_VPD_VALID
;
8102 /* ESPC_PIO_EN_ENABLE must be set */
8103 static int niu_pci_vpd_scan_props(struct niu
*np
, u32 start
, u32 end
)
8105 unsigned int found_mask
= 0;
8106 #define FOUND_MASK_MODEL 0x00000001
8107 #define FOUND_MASK_BMODEL 0x00000002
8108 #define FOUND_MASK_VERS 0x00000004
8109 #define FOUND_MASK_MAC 0x00000008
8110 #define FOUND_MASK_NMAC 0x00000010
8111 #define FOUND_MASK_PHY 0x00000020
8112 #define FOUND_MASK_ALL 0x0000003f
8114 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8115 "VPD_SCAN: start[%x] end[%x]\n", start
, end
);
8116 while (start
< end
) {
8117 int len
, err
, prop_len
;
8122 if (found_mask
== FOUND_MASK_ALL
) {
8123 niu_vpd_parse_version(np
);
8127 err
= niu_pci_eeprom_read(np
, start
+ 2);
8133 prop_len
= niu_pci_eeprom_read(np
, start
+ 4);
8134 err
= niu_pci_vpd_get_propname(np
, start
+ 5, namebuf
, 64);
8140 if (!strcmp(namebuf
, "model")) {
8141 prop_buf
= np
->vpd
.model
;
8142 max_len
= NIU_VPD_MODEL_MAX
;
8143 found_mask
|= FOUND_MASK_MODEL
;
8144 } else if (!strcmp(namebuf
, "board-model")) {
8145 prop_buf
= np
->vpd
.board_model
;
8146 max_len
= NIU_VPD_BD_MODEL_MAX
;
8147 found_mask
|= FOUND_MASK_BMODEL
;
8148 } else if (!strcmp(namebuf
, "version")) {
8149 prop_buf
= np
->vpd
.version
;
8150 max_len
= NIU_VPD_VERSION_MAX
;
8151 found_mask
|= FOUND_MASK_VERS
;
8152 } else if (!strcmp(namebuf
, "local-mac-address")) {
8153 prop_buf
= np
->vpd
.local_mac
;
8155 found_mask
|= FOUND_MASK_MAC
;
8156 } else if (!strcmp(namebuf
, "num-mac-addresses")) {
8157 prop_buf
= &np
->vpd
.mac_num
;
8159 found_mask
|= FOUND_MASK_NMAC
;
8160 } else if (!strcmp(namebuf
, "phy-type")) {
8161 prop_buf
= np
->vpd
.phy_type
;
8162 max_len
= NIU_VPD_PHY_TYPE_MAX
;
8163 found_mask
|= FOUND_MASK_PHY
;
8166 if (max_len
&& prop_len
> max_len
) {
8167 dev_err(np
->device
, "Property '%s' length (%d) is too long\n", namebuf
, prop_len
);
8172 u32 off
= start
+ 5 + err
;
8175 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8176 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8178 for (i
= 0; i
< prop_len
; i
++)
8179 *prop_buf
++ = niu_pci_eeprom_read(np
, off
+ i
);
8188 /* ESPC_PIO_EN_ENABLE must be set */
8189 static void niu_pci_vpd_fetch(struct niu
*np
, u32 start
)
8194 err
= niu_pci_eeprom_read16_swp(np
, start
+ 1);
8200 while (start
+ offset
< ESPC_EEPROM_SIZE
) {
8201 u32 here
= start
+ offset
;
8204 err
= niu_pci_eeprom_read(np
, here
);
8208 err
= niu_pci_eeprom_read16_swp(np
, here
+ 1);
8212 here
= start
+ offset
+ 3;
8213 end
= start
+ offset
+ err
;
8217 err
= niu_pci_vpd_scan_props(np
, here
, end
);
8218 if (err
< 0 || err
== 1)
8223 /* ESPC_PIO_EN_ENABLE must be set */
8224 static u32
niu_pci_vpd_offset(struct niu
*np
)
8226 u32 start
= 0, end
= ESPC_EEPROM_SIZE
, ret
;
8229 while (start
< end
) {
8232 /* ROM header signature? */
8233 err
= niu_pci_eeprom_read16(np
, start
+ 0);
8237 /* Apply offset to PCI data structure. */
8238 err
= niu_pci_eeprom_read16(np
, start
+ 23);
8243 /* Check for "PCIR" signature. */
8244 err
= niu_pci_eeprom_read16(np
, start
+ 0);
8247 err
= niu_pci_eeprom_read16(np
, start
+ 2);
8251 /* Check for OBP image type. */
8252 err
= niu_pci_eeprom_read(np
, start
+ 20);
8256 err
= niu_pci_eeprom_read(np
, ret
+ 2);
8260 start
= ret
+ (err
* 512);
8264 err
= niu_pci_eeprom_read16_swp(np
, start
+ 8);
8269 err
= niu_pci_eeprom_read(np
, ret
+ 0);
8279 static int niu_phy_type_prop_decode(struct niu
*np
, const char *phy_prop
)
8281 if (!strcmp(phy_prop
, "mif")) {
8282 /* 1G copper, MII */
8283 np
->flags
&= ~(NIU_FLAGS_FIBER
|
8285 np
->mac_xcvr
= MAC_XCVR_MII
;
8286 } else if (!strcmp(phy_prop
, "xgf")) {
8287 /* 10G fiber, XPCS */
8288 np
->flags
|= (NIU_FLAGS_10G
|
8290 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8291 } else if (!strcmp(phy_prop
, "pcs")) {
8293 np
->flags
&= ~NIU_FLAGS_10G
;
8294 np
->flags
|= NIU_FLAGS_FIBER
;
8295 np
->mac_xcvr
= MAC_XCVR_PCS
;
8296 } else if (!strcmp(phy_prop
, "xgc")) {
8297 /* 10G copper, XPCS */
8298 np
->flags
|= NIU_FLAGS_10G
;
8299 np
->flags
&= ~NIU_FLAGS_FIBER
;
8300 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8301 } else if (!strcmp(phy_prop
, "xgsd") || !strcmp(phy_prop
, "gsd")) {
8302 /* 10G Serdes or 1G Serdes, default to 10G */
8303 np
->flags
|= NIU_FLAGS_10G
;
8304 np
->flags
&= ~NIU_FLAGS_FIBER
;
8305 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
8306 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8313 static int niu_pci_vpd_get_nports(struct niu
*np
)
8317 if ((!strcmp(np
->vpd
.model
, NIU_QGC_LP_MDL_STR
)) ||
8318 (!strcmp(np
->vpd
.model
, NIU_QGC_PEM_MDL_STR
)) ||
8319 (!strcmp(np
->vpd
.model
, NIU_MARAMBA_MDL_STR
)) ||
8320 (!strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) ||
8321 (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
))) {
8323 } else if ((!strcmp(np
->vpd
.model
, NIU_2XGF_LP_MDL_STR
)) ||
8324 (!strcmp(np
->vpd
.model
, NIU_2XGF_PEM_MDL_STR
)) ||
8325 (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) ||
8326 (!strcmp(np
->vpd
.model
, NIU_2XGF_MRVL_MDL_STR
))) {
8333 static void niu_pci_vpd_validate(struct niu
*np
)
8335 struct net_device
*dev
= np
->dev
;
8336 struct niu_vpd
*vpd
= &np
->vpd
;
8339 if (!is_valid_ether_addr(&vpd
->local_mac
[0])) {
8340 dev_err(np
->device
, "VPD MAC invalid, falling back to SPROM\n");
8342 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
8346 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
8347 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
8348 np
->flags
|= NIU_FLAGS_10G
;
8349 np
->flags
&= ~NIU_FLAGS_FIBER
;
8350 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
8351 np
->mac_xcvr
= MAC_XCVR_PCS
;
8353 np
->flags
|= NIU_FLAGS_FIBER
;
8354 np
->flags
&= ~NIU_FLAGS_10G
;
8356 if (np
->flags
& NIU_FLAGS_10G
)
8357 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8358 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
8359 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
8360 NIU_FLAGS_HOTPLUG_PHY
);
8361 } else if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
8362 dev_err(np
->device
, "Illegal phy string [%s]\n",
8364 dev_err(np
->device
, "Falling back to SPROM\n");
8365 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
8369 memcpy(dev
->dev_addr
, vpd
->local_mac
, ETH_ALEN
);
8371 val8
= dev
->dev_addr
[5];
8372 dev
->dev_addr
[5] += np
->port
;
8373 if (dev
->dev_addr
[5] < val8
)
8377 static int niu_pci_probe_sprom(struct niu
*np
)
8379 struct net_device
*dev
= np
->dev
;
8384 val
= (nr64(ESPC_VER_IMGSZ
) & ESPC_VER_IMGSZ_IMGSZ
);
8385 val
>>= ESPC_VER_IMGSZ_IMGSZ_SHIFT
;
8388 np
->eeprom_len
= len
;
8390 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8391 "SPROM: Image size %llu\n", (unsigned long long)val
);
8394 for (i
= 0; i
< len
; i
++) {
8395 val
= nr64(ESPC_NCR(i
));
8396 sum
+= (val
>> 0) & 0xff;
8397 sum
+= (val
>> 8) & 0xff;
8398 sum
+= (val
>> 16) & 0xff;
8399 sum
+= (val
>> 24) & 0xff;
8401 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8402 "SPROM: Checksum %x\n", (int)(sum
& 0xff));
8403 if ((sum
& 0xff) != 0xab) {
8404 dev_err(np
->device
, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum
& 0xff));
8408 val
= nr64(ESPC_PHY_TYPE
);
8411 val8
= (val
& ESPC_PHY_TYPE_PORT0
) >>
8412 ESPC_PHY_TYPE_PORT0_SHIFT
;
8415 val8
= (val
& ESPC_PHY_TYPE_PORT1
) >>
8416 ESPC_PHY_TYPE_PORT1_SHIFT
;
8419 val8
= (val
& ESPC_PHY_TYPE_PORT2
) >>
8420 ESPC_PHY_TYPE_PORT2_SHIFT
;
8423 val8
= (val
& ESPC_PHY_TYPE_PORT3
) >>
8424 ESPC_PHY_TYPE_PORT3_SHIFT
;
8427 dev_err(np
->device
, "Bogus port number %u\n",
8431 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8432 "SPROM: PHY type %x\n", val8
);
8435 case ESPC_PHY_TYPE_1G_COPPER
:
8436 /* 1G copper, MII */
8437 np
->flags
&= ~(NIU_FLAGS_FIBER
|
8439 np
->mac_xcvr
= MAC_XCVR_MII
;
8442 case ESPC_PHY_TYPE_1G_FIBER
:
8444 np
->flags
&= ~NIU_FLAGS_10G
;
8445 np
->flags
|= NIU_FLAGS_FIBER
;
8446 np
->mac_xcvr
= MAC_XCVR_PCS
;
8449 case ESPC_PHY_TYPE_10G_COPPER
:
8450 /* 10G copper, XPCS */
8451 np
->flags
|= NIU_FLAGS_10G
;
8452 np
->flags
&= ~NIU_FLAGS_FIBER
;
8453 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8456 case ESPC_PHY_TYPE_10G_FIBER
:
8457 /* 10G fiber, XPCS */
8458 np
->flags
|= (NIU_FLAGS_10G
|
8460 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8464 dev_err(np
->device
, "Bogus SPROM phy type %u\n", val8
);
8468 val
= nr64(ESPC_MAC_ADDR0
);
8469 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8470 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val
);
8471 dev
->dev_addr
[0] = (val
>> 0) & 0xff;
8472 dev
->dev_addr
[1] = (val
>> 8) & 0xff;
8473 dev
->dev_addr
[2] = (val
>> 16) & 0xff;
8474 dev
->dev_addr
[3] = (val
>> 24) & 0xff;
8476 val
= nr64(ESPC_MAC_ADDR1
);
8477 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8478 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val
);
8479 dev
->dev_addr
[4] = (val
>> 0) & 0xff;
8480 dev
->dev_addr
[5] = (val
>> 8) & 0xff;
8482 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
8483 dev_err(np
->device
, "SPROM MAC address invalid [ %pM ]\n",
8488 val8
= dev
->dev_addr
[5];
8489 dev
->dev_addr
[5] += np
->port
;
8490 if (dev
->dev_addr
[5] < val8
)
8493 val
= nr64(ESPC_MOD_STR_LEN
);
8494 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8495 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val
);
8499 for (i
= 0; i
< val
; i
+= 4) {
8500 u64 tmp
= nr64(ESPC_NCR(5 + (i
/ 4)));
8502 np
->vpd
.model
[i
+ 3] = (tmp
>> 0) & 0xff;
8503 np
->vpd
.model
[i
+ 2] = (tmp
>> 8) & 0xff;
8504 np
->vpd
.model
[i
+ 1] = (tmp
>> 16) & 0xff;
8505 np
->vpd
.model
[i
+ 0] = (tmp
>> 24) & 0xff;
8507 np
->vpd
.model
[val
] = '\0';
8509 val
= nr64(ESPC_BD_MOD_STR_LEN
);
8510 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8511 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val
);
8515 for (i
= 0; i
< val
; i
+= 4) {
8516 u64 tmp
= nr64(ESPC_NCR(14 + (i
/ 4)));
8518 np
->vpd
.board_model
[i
+ 3] = (tmp
>> 0) & 0xff;
8519 np
->vpd
.board_model
[i
+ 2] = (tmp
>> 8) & 0xff;
8520 np
->vpd
.board_model
[i
+ 1] = (tmp
>> 16) & 0xff;
8521 np
->vpd
.board_model
[i
+ 0] = (tmp
>> 24) & 0xff;
8523 np
->vpd
.board_model
[val
] = '\0';
8526 nr64(ESPC_NUM_PORTS_MACS
) & ESPC_NUM_PORTS_MACS_VAL
;
8527 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8528 "SPROM: NUM_PORTS_MACS[%d]\n", np
->vpd
.mac_num
);
8533 static int niu_get_and_validate_port(struct niu
*np
)
8535 struct niu_parent
*parent
= np
->parent
;
8538 np
->flags
|= NIU_FLAGS_XMAC
;
8540 if (!parent
->num_ports
) {
8541 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
8542 parent
->num_ports
= 2;
8544 parent
->num_ports
= niu_pci_vpd_get_nports(np
);
8545 if (!parent
->num_ports
) {
8546 /* Fall back to SPROM as last resort.
8547 * This will fail on most cards.
8549 parent
->num_ports
= nr64(ESPC_NUM_PORTS_MACS
) &
8550 ESPC_NUM_PORTS_MACS_VAL
;
8552 /* All of the current probing methods fail on
8553 * Maramba on-board parts.
8555 if (!parent
->num_ports
)
8556 parent
->num_ports
= 4;
8561 if (np
->port
>= parent
->num_ports
)
8567 static int phy_record(struct niu_parent
*parent
, struct phy_probe_info
*p
,
8568 int dev_id_1
, int dev_id_2
, u8 phy_port
, int type
)
8570 u32 id
= (dev_id_1
<< 16) | dev_id_2
;
8573 if (dev_id_1
< 0 || dev_id_2
< 0)
8575 if (type
== PHY_TYPE_PMA_PMD
|| type
== PHY_TYPE_PCS
) {
8576 /* Because of the NIU_PHY_ID_MASK being applied, the 8704
8577 * test covers the 8706 as well.
8579 if (((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8704
) &&
8580 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_MRVL88X2011
))
8583 if ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM5464R
)
8587 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8589 type
== PHY_TYPE_PMA_PMD
? "PMA/PMD" :
8590 type
== PHY_TYPE_PCS
? "PCS" : "MII",
8593 if (p
->cur
[type
] >= NIU_MAX_PORTS
) {
8594 pr_err("Too many PHY ports\n");
8598 p
->phy_id
[type
][idx
] = id
;
8599 p
->phy_port
[type
][idx
] = phy_port
;
8600 p
->cur
[type
] = idx
+ 1;
8604 static int port_has_10g(struct phy_probe_info
*p
, int port
)
8608 for (i
= 0; i
< p
->cur
[PHY_TYPE_PMA_PMD
]; i
++) {
8609 if (p
->phy_port
[PHY_TYPE_PMA_PMD
][i
] == port
)
8612 for (i
= 0; i
< p
->cur
[PHY_TYPE_PCS
]; i
++) {
8613 if (p
->phy_port
[PHY_TYPE_PCS
][i
] == port
)
8620 static int count_10g_ports(struct phy_probe_info
*p
, int *lowest
)
8626 for (port
= 8; port
< 32; port
++) {
8627 if (port_has_10g(p
, port
)) {
8637 static int count_1g_ports(struct phy_probe_info
*p
, int *lowest
)
8640 if (p
->cur
[PHY_TYPE_MII
])
8641 *lowest
= p
->phy_port
[PHY_TYPE_MII
][0];
8643 return p
->cur
[PHY_TYPE_MII
];
8646 static void niu_n2_divide_channels(struct niu_parent
*parent
)
8648 int num_ports
= parent
->num_ports
;
8651 for (i
= 0; i
< num_ports
; i
++) {
8652 parent
->rxchan_per_port
[i
] = (16 / num_ports
);
8653 parent
->txchan_per_port
[i
] = (16 / num_ports
);
8655 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8657 parent
->rxchan_per_port
[i
],
8658 parent
->txchan_per_port
[i
]);
8662 static void niu_divide_channels(struct niu_parent
*parent
,
8663 int num_10g
, int num_1g
)
8665 int num_ports
= parent
->num_ports
;
8666 int rx_chans_per_10g
, rx_chans_per_1g
;
8667 int tx_chans_per_10g
, tx_chans_per_1g
;
8668 int i
, tot_rx
, tot_tx
;
8670 if (!num_10g
|| !num_1g
) {
8671 rx_chans_per_10g
= rx_chans_per_1g
=
8672 (NIU_NUM_RXCHAN
/ num_ports
);
8673 tx_chans_per_10g
= tx_chans_per_1g
=
8674 (NIU_NUM_TXCHAN
/ num_ports
);
8676 rx_chans_per_1g
= NIU_NUM_RXCHAN
/ 8;
8677 rx_chans_per_10g
= (NIU_NUM_RXCHAN
-
8678 (rx_chans_per_1g
* num_1g
)) /
8681 tx_chans_per_1g
= NIU_NUM_TXCHAN
/ 6;
8682 tx_chans_per_10g
= (NIU_NUM_TXCHAN
-
8683 (tx_chans_per_1g
* num_1g
)) /
8687 tot_rx
= tot_tx
= 0;
8688 for (i
= 0; i
< num_ports
; i
++) {
8689 int type
= phy_decode(parent
->port_phy
, i
);
8691 if (type
== PORT_TYPE_10G
) {
8692 parent
->rxchan_per_port
[i
] = rx_chans_per_10g
;
8693 parent
->txchan_per_port
[i
] = tx_chans_per_10g
;
8695 parent
->rxchan_per_port
[i
] = rx_chans_per_1g
;
8696 parent
->txchan_per_port
[i
] = tx_chans_per_1g
;
8698 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8700 parent
->rxchan_per_port
[i
],
8701 parent
->txchan_per_port
[i
]);
8702 tot_rx
+= parent
->rxchan_per_port
[i
];
8703 tot_tx
+= parent
->txchan_per_port
[i
];
8706 if (tot_rx
> NIU_NUM_RXCHAN
) {
8707 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8708 parent
->index
, tot_rx
);
8709 for (i
= 0; i
< num_ports
; i
++)
8710 parent
->rxchan_per_port
[i
] = 1;
8712 if (tot_tx
> NIU_NUM_TXCHAN
) {
8713 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8714 parent
->index
, tot_tx
);
8715 for (i
= 0; i
< num_ports
; i
++)
8716 parent
->txchan_per_port
[i
] = 1;
8718 if (tot_rx
< NIU_NUM_RXCHAN
|| tot_tx
< NIU_NUM_TXCHAN
) {
8719 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8720 parent
->index
, tot_rx
, tot_tx
);
8724 static void niu_divide_rdc_groups(struct niu_parent
*parent
,
8725 int num_10g
, int num_1g
)
8727 int i
, num_ports
= parent
->num_ports
;
8728 int rdc_group
, rdc_groups_per_port
;
8729 int rdc_channel_base
;
8732 rdc_groups_per_port
= NIU_NUM_RDC_TABLES
/ num_ports
;
8734 rdc_channel_base
= 0;
8736 for (i
= 0; i
< num_ports
; i
++) {
8737 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[i
];
8738 int grp
, num_channels
= parent
->rxchan_per_port
[i
];
8739 int this_channel_offset
;
8741 tp
->first_table_num
= rdc_group
;
8742 tp
->num_tables
= rdc_groups_per_port
;
8743 this_channel_offset
= 0;
8744 for (grp
= 0; grp
< tp
->num_tables
; grp
++) {
8745 struct rdc_table
*rt
= &tp
->tables
[grp
];
8748 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8749 parent
->index
, i
, tp
->first_table_num
+ grp
);
8750 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++) {
8751 rt
->rxdma_channel
[slot
] =
8752 rdc_channel_base
+ this_channel_offset
;
8754 pr_cont("%d ", rt
->rxdma_channel
[slot
]);
8756 if (++this_channel_offset
== num_channels
)
8757 this_channel_offset
= 0;
8762 parent
->rdc_default
[i
] = rdc_channel_base
;
8764 rdc_channel_base
+= num_channels
;
8765 rdc_group
+= rdc_groups_per_port
;
8769 static int fill_phy_probe_info(struct niu
*np
, struct niu_parent
*parent
,
8770 struct phy_probe_info
*info
)
8772 unsigned long flags
;
8775 memset(info
, 0, sizeof(*info
));
8777 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8778 niu_lock_parent(np
, flags
);
8780 for (port
= 8; port
< 32; port
++) {
8781 int dev_id_1
, dev_id_2
;
8783 dev_id_1
= mdio_read(np
, port
,
8784 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID1
);
8785 dev_id_2
= mdio_read(np
, port
,
8786 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID2
);
8787 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8791 dev_id_1
= mdio_read(np
, port
,
8792 NIU_PCS_DEV_ADDR
, MII_PHYSID1
);
8793 dev_id_2
= mdio_read(np
, port
,
8794 NIU_PCS_DEV_ADDR
, MII_PHYSID2
);
8795 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8799 dev_id_1
= mii_read(np
, port
, MII_PHYSID1
);
8800 dev_id_2
= mii_read(np
, port
, MII_PHYSID2
);
8801 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8806 niu_unlock_parent(np
, flags
);
8811 static int walk_phys(struct niu
*np
, struct niu_parent
*parent
)
8813 struct phy_probe_info
*info
= &parent
->phy_probe_info
;
8814 int lowest_10g
, lowest_1g
;
8815 int num_10g
, num_1g
;
8819 num_10g
= num_1g
= 0;
8821 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
8822 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
8825 parent
->plat_type
= PLAT_TYPE_ATCA_CP3220
;
8826 parent
->num_ports
= 4;
8827 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8828 phy_encode(PORT_TYPE_1G
, 1) |
8829 phy_encode(PORT_TYPE_1G
, 2) |
8830 phy_encode(PORT_TYPE_1G
, 3));
8831 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
8834 parent
->num_ports
= 2;
8835 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8836 phy_encode(PORT_TYPE_10G
, 1));
8837 } else if ((np
->flags
& NIU_FLAGS_XCVR_SERDES
) &&
8838 (parent
->plat_type
== PLAT_TYPE_NIU
)) {
8839 /* this is the Monza case */
8840 if (np
->flags
& NIU_FLAGS_10G
) {
8841 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8842 phy_encode(PORT_TYPE_10G
, 1));
8844 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8845 phy_encode(PORT_TYPE_1G
, 1));
8848 err
= fill_phy_probe_info(np
, parent
, info
);
8852 num_10g
= count_10g_ports(info
, &lowest_10g
);
8853 num_1g
= count_1g_ports(info
, &lowest_1g
);
8855 switch ((num_10g
<< 4) | num_1g
) {
8857 if (lowest_1g
== 10)
8858 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8859 else if (lowest_1g
== 26)
8860 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8862 goto unknown_vg_1g_port
;
8866 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8867 phy_encode(PORT_TYPE_10G
, 1) |
8868 phy_encode(PORT_TYPE_1G
, 2) |
8869 phy_encode(PORT_TYPE_1G
, 3));
8873 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8874 phy_encode(PORT_TYPE_10G
, 1));
8878 val
= phy_encode(PORT_TYPE_10G
, np
->port
);
8882 if (lowest_1g
== 10)
8883 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8884 else if (lowest_1g
== 26)
8885 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8887 goto unknown_vg_1g_port
;
8891 if ((lowest_10g
& 0x7) == 0)
8892 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8893 phy_encode(PORT_TYPE_1G
, 1) |
8894 phy_encode(PORT_TYPE_1G
, 2) |
8895 phy_encode(PORT_TYPE_1G
, 3));
8897 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8898 phy_encode(PORT_TYPE_10G
, 1) |
8899 phy_encode(PORT_TYPE_1G
, 2) |
8900 phy_encode(PORT_TYPE_1G
, 3));
8904 if (lowest_1g
== 10)
8905 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8906 else if (lowest_1g
== 26)
8907 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8909 goto unknown_vg_1g_port
;
8911 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8912 phy_encode(PORT_TYPE_1G
, 1) |
8913 phy_encode(PORT_TYPE_1G
, 2) |
8914 phy_encode(PORT_TYPE_1G
, 3));
8918 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8924 parent
->port_phy
= val
;
8926 if (parent
->plat_type
== PLAT_TYPE_NIU
)
8927 niu_n2_divide_channels(parent
);
8929 niu_divide_channels(parent
, num_10g
, num_1g
);
8931 niu_divide_rdc_groups(parent
, num_10g
, num_1g
);
8936 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g
);
8940 static int niu_probe_ports(struct niu
*np
)
8942 struct niu_parent
*parent
= np
->parent
;
8945 if (parent
->port_phy
== PORT_PHY_UNKNOWN
) {
8946 err
= walk_phys(np
, parent
);
8950 niu_set_ldg_timer_res(np
, 2);
8951 for (i
= 0; i
<= LDN_MAX
; i
++)
8952 niu_ldn_irq_enable(np
, i
, 0);
8955 if (parent
->port_phy
== PORT_PHY_INVALID
)
8961 static int niu_classifier_swstate_init(struct niu
*np
)
8963 struct niu_classifier
*cp
= &np
->clas
;
8965 cp
->tcam_top
= (u16
) np
->port
;
8966 cp
->tcam_sz
= np
->parent
->tcam_num_entries
/ np
->parent
->num_ports
;
8967 cp
->h1_init
= 0xffffffff;
8968 cp
->h2_init
= 0xffff;
8970 return fflp_early_init(np
);
8973 static void niu_link_config_init(struct niu
*np
)
8975 struct niu_link_config
*lp
= &np
->link_config
;
8977 lp
->advertising
= (ADVERTISED_10baseT_Half
|
8978 ADVERTISED_10baseT_Full
|
8979 ADVERTISED_100baseT_Half
|
8980 ADVERTISED_100baseT_Full
|
8981 ADVERTISED_1000baseT_Half
|
8982 ADVERTISED_1000baseT_Full
|
8983 ADVERTISED_10000baseT_Full
|
8984 ADVERTISED_Autoneg
);
8985 lp
->speed
= lp
->active_speed
= SPEED_INVALID
;
8986 lp
->duplex
= DUPLEX_FULL
;
8987 lp
->active_duplex
= DUPLEX_INVALID
;
8990 lp
->loopback_mode
= LOOPBACK_MAC
;
8991 lp
->active_speed
= SPEED_10000
;
8992 lp
->active_duplex
= DUPLEX_FULL
;
8994 lp
->loopback_mode
= LOOPBACK_DISABLED
;
8998 static int niu_init_mac_ipp_pcs_base(struct niu
*np
)
9002 np
->mac_regs
= np
->regs
+ XMAC_PORT0_OFF
;
9003 np
->ipp_off
= 0x00000;
9004 np
->pcs_off
= 0x04000;
9005 np
->xpcs_off
= 0x02000;
9009 np
->mac_regs
= np
->regs
+ XMAC_PORT1_OFF
;
9010 np
->ipp_off
= 0x08000;
9011 np
->pcs_off
= 0x0a000;
9012 np
->xpcs_off
= 0x08000;
9016 np
->mac_regs
= np
->regs
+ BMAC_PORT2_OFF
;
9017 np
->ipp_off
= 0x04000;
9018 np
->pcs_off
= 0x0e000;
9019 np
->xpcs_off
= ~0UL;
9023 np
->mac_regs
= np
->regs
+ BMAC_PORT3_OFF
;
9024 np
->ipp_off
= 0x0c000;
9025 np
->pcs_off
= 0x12000;
9026 np
->xpcs_off
= ~0UL;
9030 dev_err(np
->device
, "Port %u is invalid, cannot compute MAC block offset\n", np
->port
);
9037 static void niu_try_msix(struct niu
*np
, u8
*ldg_num_map
)
9039 struct msix_entry msi_vec
[NIU_NUM_LDG
];
9040 struct niu_parent
*parent
= np
->parent
;
9041 struct pci_dev
*pdev
= np
->pdev
;
9042 int i
, num_irqs
, err
;
9045 first_ldg
= (NIU_NUM_LDG
/ parent
->num_ports
) * np
->port
;
9046 for (i
= 0; i
< (NIU_NUM_LDG
/ parent
->num_ports
); i
++)
9047 ldg_num_map
[i
] = first_ldg
+ i
;
9049 num_irqs
= (parent
->rxchan_per_port
[np
->port
] +
9050 parent
->txchan_per_port
[np
->port
] +
9051 (np
->port
== 0 ? 3 : 1));
9052 BUG_ON(num_irqs
> (NIU_NUM_LDG
/ parent
->num_ports
));
9055 for (i
= 0; i
< num_irqs
; i
++) {
9056 msi_vec
[i
].vector
= 0;
9057 msi_vec
[i
].entry
= i
;
9060 err
= pci_enable_msix(pdev
, msi_vec
, num_irqs
);
9062 np
->flags
&= ~NIU_FLAGS_MSIX
;
9070 np
->flags
|= NIU_FLAGS_MSIX
;
9071 for (i
= 0; i
< num_irqs
; i
++)
9072 np
->ldg
[i
].irq
= msi_vec
[i
].vector
;
9073 np
->num_ldg
= num_irqs
;
9076 static int niu_n2_irq_init(struct niu
*np
, u8
*ldg_num_map
)
9078 #ifdef CONFIG_SPARC64
9079 struct platform_device
*op
= np
->op
;
9080 const u32
*int_prop
;
9083 int_prop
= of_get_property(op
->dev
.of_node
, "interrupts", NULL
);
9087 for (i
= 0; i
< op
->archdata
.num_irqs
; i
++) {
9088 ldg_num_map
[i
] = int_prop
[i
];
9089 np
->ldg
[i
].irq
= op
->archdata
.irqs
[i
];
9092 np
->num_ldg
= op
->archdata
.num_irqs
;
9100 static int niu_ldg_init(struct niu
*np
)
9102 struct niu_parent
*parent
= np
->parent
;
9103 u8 ldg_num_map
[NIU_NUM_LDG
];
9104 int first_chan
, num_chan
;
9105 int i
, err
, ldg_rotor
;
9109 np
->ldg
[0].irq
= np
->dev
->irq
;
9110 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
9111 err
= niu_n2_irq_init(np
, ldg_num_map
);
9115 niu_try_msix(np
, ldg_num_map
);
9118 for (i
= 0; i
< np
->num_ldg
; i
++) {
9119 struct niu_ldg
*lp
= &np
->ldg
[i
];
9121 netif_napi_add(np
->dev
, &lp
->napi
, niu_poll
, 64);
9124 lp
->ldg_num
= ldg_num_map
[i
];
9125 lp
->timer
= 2; /* XXX */
9127 /* On N2 NIU the firmware has setup the SID mappings so they go
9128 * to the correct values that will route the LDG to the proper
9129 * interrupt in the NCU interrupt table.
9131 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
9132 err
= niu_set_ldg_sid(np
, lp
->ldg_num
, port
, i
);
9138 /* We adopt the LDG assignment ordering used by the N2 NIU
9139 * 'interrupt' properties because that simplifies a lot of
9140 * things. This ordering is:
9143 * MIF (if port zero)
9144 * SYSERR (if port zero)
9151 err
= niu_ldg_assign_ldn(np
, parent
, ldg_num_map
[ldg_rotor
],
9157 if (ldg_rotor
== np
->num_ldg
)
9161 err
= niu_ldg_assign_ldn(np
, parent
,
9162 ldg_num_map
[ldg_rotor
],
9168 if (ldg_rotor
== np
->num_ldg
)
9171 err
= niu_ldg_assign_ldn(np
, parent
,
9172 ldg_num_map
[ldg_rotor
],
9178 if (ldg_rotor
== np
->num_ldg
)
9184 for (i
= 0; i
< port
; i
++)
9185 first_chan
+= parent
->rxchan_per_port
[i
];
9186 num_chan
= parent
->rxchan_per_port
[port
];
9188 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
9189 err
= niu_ldg_assign_ldn(np
, parent
,
9190 ldg_num_map
[ldg_rotor
],
9195 if (ldg_rotor
== np
->num_ldg
)
9200 for (i
= 0; i
< port
; i
++)
9201 first_chan
+= parent
->txchan_per_port
[i
];
9202 num_chan
= parent
->txchan_per_port
[port
];
9203 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
9204 err
= niu_ldg_assign_ldn(np
, parent
,
9205 ldg_num_map
[ldg_rotor
],
9210 if (ldg_rotor
== np
->num_ldg
)
9217 static void niu_ldg_free(struct niu
*np
)
9219 if (np
->flags
& NIU_FLAGS_MSIX
)
9220 pci_disable_msix(np
->pdev
);
9223 static int niu_get_of_props(struct niu
*np
)
9225 #ifdef CONFIG_SPARC64
9226 struct net_device
*dev
= np
->dev
;
9227 struct device_node
*dp
;
9228 const char *phy_type
;
9233 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
9234 dp
= np
->op
->dev
.of_node
;
9236 dp
= pci_device_to_OF_node(np
->pdev
);
9238 phy_type
= of_get_property(dp
, "phy-type", &prop_len
);
9240 netdev_err(dev
, "%s: OF node lacks phy-type property\n",
9245 if (!strcmp(phy_type
, "none"))
9248 strcpy(np
->vpd
.phy_type
, phy_type
);
9250 if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
9251 netdev_err(dev
, "%s: Illegal phy string [%s]\n",
9252 dp
->full_name
, np
->vpd
.phy_type
);
9256 mac_addr
= of_get_property(dp
, "local-mac-address", &prop_len
);
9258 netdev_err(dev
, "%s: OF node lacks local-mac-address property\n",
9262 if (prop_len
!= dev
->addr_len
) {
9263 netdev_err(dev
, "%s: OF MAC address prop len (%d) is wrong\n",
9264 dp
->full_name
, prop_len
);
9266 memcpy(dev
->dev_addr
, mac_addr
, dev
->addr_len
);
9267 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
9268 netdev_err(dev
, "%s: OF MAC address is invalid\n",
9270 netdev_err(dev
, "%s: [ %pM ]\n", dp
->full_name
, dev
->dev_addr
);
9274 model
= of_get_property(dp
, "model", &prop_len
);
9277 strcpy(np
->vpd
.model
, model
);
9279 if (of_find_property(dp
, "hot-swappable-phy", &prop_len
)) {
9280 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
9281 NIU_FLAGS_HOTPLUG_PHY
);
9290 static int niu_get_invariants(struct niu
*np
)
9292 int err
, have_props
;
9295 err
= niu_get_of_props(np
);
9301 err
= niu_init_mac_ipp_pcs_base(np
);
9306 err
= niu_get_and_validate_port(np
);
9311 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
9314 nw64(ESPC_PIO_EN
, ESPC_PIO_EN_ENABLE
);
9315 offset
= niu_pci_vpd_offset(np
);
9316 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
9317 "%s() VPD offset [%08x]\n", __func__
, offset
);
9319 niu_pci_vpd_fetch(np
, offset
);
9320 nw64(ESPC_PIO_EN
, 0);
9322 if (np
->flags
& NIU_FLAGS_VPD_VALID
) {
9323 niu_pci_vpd_validate(np
);
9324 err
= niu_get_and_validate_port(np
);
9329 if (!(np
->flags
& NIU_FLAGS_VPD_VALID
)) {
9330 err
= niu_get_and_validate_port(np
);
9333 err
= niu_pci_probe_sprom(np
);
9339 err
= niu_probe_ports(np
);
9345 niu_classifier_swstate_init(np
);
9346 niu_link_config_init(np
);
9348 err
= niu_determine_phy_disposition(np
);
9350 err
= niu_init_link(np
);
9355 static LIST_HEAD(niu_parent_list
);
9356 static DEFINE_MUTEX(niu_parent_lock
);
9357 static int niu_parent_index
;
9359 static ssize_t
show_port_phy(struct device
*dev
,
9360 struct device_attribute
*attr
, char *buf
)
9362 struct platform_device
*plat_dev
= to_platform_device(dev
);
9363 struct niu_parent
*p
= dev_get_platdata(&plat_dev
->dev
);
9364 u32 port_phy
= p
->port_phy
;
9365 char *orig_buf
= buf
;
9368 if (port_phy
== PORT_PHY_UNKNOWN
||
9369 port_phy
== PORT_PHY_INVALID
)
9372 for (i
= 0; i
< p
->num_ports
; i
++) {
9373 const char *type_str
;
9376 type
= phy_decode(port_phy
, i
);
9377 if (type
== PORT_TYPE_10G
)
9382 (i
== 0) ? "%s" : " %s",
9385 buf
+= sprintf(buf
, "\n");
9386 return buf
- orig_buf
;
9389 static ssize_t
show_plat_type(struct device
*dev
,
9390 struct device_attribute
*attr
, char *buf
)
9392 struct platform_device
*plat_dev
= to_platform_device(dev
);
9393 struct niu_parent
*p
= dev_get_platdata(&plat_dev
->dev
);
9394 const char *type_str
;
9396 switch (p
->plat_type
) {
9397 case PLAT_TYPE_ATLAS
:
9403 case PLAT_TYPE_VF_P0
:
9406 case PLAT_TYPE_VF_P1
:
9410 type_str
= "unknown";
9414 return sprintf(buf
, "%s\n", type_str
);
9417 static ssize_t
__show_chan_per_port(struct device
*dev
,
9418 struct device_attribute
*attr
, char *buf
,
9421 struct platform_device
*plat_dev
= to_platform_device(dev
);
9422 struct niu_parent
*p
= dev_get_platdata(&plat_dev
->dev
);
9423 char *orig_buf
= buf
;
9427 arr
= (rx
? p
->rxchan_per_port
: p
->txchan_per_port
);
9429 for (i
= 0; i
< p
->num_ports
; i
++) {
9431 (i
== 0) ? "%d" : " %d",
9434 buf
+= sprintf(buf
, "\n");
9436 return buf
- orig_buf
;
9439 static ssize_t
show_rxchan_per_port(struct device
*dev
,
9440 struct device_attribute
*attr
, char *buf
)
9442 return __show_chan_per_port(dev
, attr
, buf
, 1);
9445 static ssize_t
show_txchan_per_port(struct device
*dev
,
9446 struct device_attribute
*attr
, char *buf
)
9448 return __show_chan_per_port(dev
, attr
, buf
, 1);
9451 static ssize_t
show_num_ports(struct device
*dev
,
9452 struct device_attribute
*attr
, char *buf
)
9454 struct platform_device
*plat_dev
= to_platform_device(dev
);
9455 struct niu_parent
*p
= dev_get_platdata(&plat_dev
->dev
);
9457 return sprintf(buf
, "%d\n", p
->num_ports
);
9460 static struct device_attribute niu_parent_attributes
[] = {
9461 __ATTR(port_phy
, S_IRUGO
, show_port_phy
, NULL
),
9462 __ATTR(plat_type
, S_IRUGO
, show_plat_type
, NULL
),
9463 __ATTR(rxchan_per_port
, S_IRUGO
, show_rxchan_per_port
, NULL
),
9464 __ATTR(txchan_per_port
, S_IRUGO
, show_txchan_per_port
, NULL
),
9465 __ATTR(num_ports
, S_IRUGO
, show_num_ports
, NULL
),
9469 static struct niu_parent
*niu_new_parent(struct niu
*np
,
9470 union niu_parent_id
*id
, u8 ptype
)
9472 struct platform_device
*plat_dev
;
9473 struct niu_parent
*p
;
9476 plat_dev
= platform_device_register_simple("niu-board", niu_parent_index
,
9478 if (IS_ERR(plat_dev
))
9481 for (i
= 0; niu_parent_attributes
[i
].attr
.name
; i
++) {
9482 int err
= device_create_file(&plat_dev
->dev
,
9483 &niu_parent_attributes
[i
]);
9485 goto fail_unregister
;
9488 p
= kzalloc(sizeof(*p
), GFP_KERNEL
);
9490 goto fail_unregister
;
9492 p
->index
= niu_parent_index
++;
9494 plat_dev
->dev
.platform_data
= p
;
9495 p
->plat_dev
= plat_dev
;
9497 memcpy(&p
->id
, id
, sizeof(*id
));
9498 p
->plat_type
= ptype
;
9499 INIT_LIST_HEAD(&p
->list
);
9500 atomic_set(&p
->refcnt
, 0);
9501 list_add(&p
->list
, &niu_parent_list
);
9502 spin_lock_init(&p
->lock
);
9504 p
->rxdma_clock_divider
= 7500;
9506 p
->tcam_num_entries
= NIU_PCI_TCAM_ENTRIES
;
9507 if (p
->plat_type
== PLAT_TYPE_NIU
)
9508 p
->tcam_num_entries
= NIU_NONPCI_TCAM_ENTRIES
;
9510 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
9511 int index
= i
- CLASS_CODE_USER_PROG1
;
9513 p
->tcam_key
[index
] = TCAM_KEY_TSEL
;
9514 p
->flow_key
[index
] = (FLOW_KEY_IPSA
|
9517 (FLOW_KEY_L4_BYTE12
<<
9518 FLOW_KEY_L4_0_SHIFT
) |
9519 (FLOW_KEY_L4_BYTE12
<<
9520 FLOW_KEY_L4_1_SHIFT
));
9523 for (i
= 0; i
< LDN_MAX
+ 1; i
++)
9524 p
->ldg_map
[i
] = LDG_INVALID
;
9529 platform_device_unregister(plat_dev
);
9533 static struct niu_parent
*niu_get_parent(struct niu
*np
,
9534 union niu_parent_id
*id
, u8 ptype
)
9536 struct niu_parent
*p
, *tmp
;
9537 int port
= np
->port
;
9539 mutex_lock(&niu_parent_lock
);
9541 list_for_each_entry(tmp
, &niu_parent_list
, list
) {
9542 if (!memcmp(id
, &tmp
->id
, sizeof(*id
))) {
9548 p
= niu_new_parent(np
, id
, ptype
);
9554 sprintf(port_name
, "port%d", port
);
9555 err
= sysfs_create_link(&p
->plat_dev
->dev
.kobj
,
9559 p
->ports
[port
] = np
;
9560 atomic_inc(&p
->refcnt
);
9563 mutex_unlock(&niu_parent_lock
);
9568 static void niu_put_parent(struct niu
*np
)
9570 struct niu_parent
*p
= np
->parent
;
9574 BUG_ON(!p
|| p
->ports
[port
] != np
);
9576 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
9577 "%s() port[%u]\n", __func__
, port
);
9579 sprintf(port_name
, "port%d", port
);
9581 mutex_lock(&niu_parent_lock
);
9583 sysfs_remove_link(&p
->plat_dev
->dev
.kobj
, port_name
);
9585 p
->ports
[port
] = NULL
;
9588 if (atomic_dec_and_test(&p
->refcnt
)) {
9590 platform_device_unregister(p
->plat_dev
);
9593 mutex_unlock(&niu_parent_lock
);
9596 static void *niu_pci_alloc_coherent(struct device
*dev
, size_t size
,
9597 u64
*handle
, gfp_t flag
)
9602 ret
= dma_alloc_coherent(dev
, size
, &dh
, flag
);
9608 static void niu_pci_free_coherent(struct device
*dev
, size_t size
,
9609 void *cpu_addr
, u64 handle
)
9611 dma_free_coherent(dev
, size
, cpu_addr
, handle
);
9614 static u64
niu_pci_map_page(struct device
*dev
, struct page
*page
,
9615 unsigned long offset
, size_t size
,
9616 enum dma_data_direction direction
)
9618 return dma_map_page(dev
, page
, offset
, size
, direction
);
9621 static void niu_pci_unmap_page(struct device
*dev
, u64 dma_address
,
9622 size_t size
, enum dma_data_direction direction
)
9624 dma_unmap_page(dev
, dma_address
, size
, direction
);
9627 static u64
niu_pci_map_single(struct device
*dev
, void *cpu_addr
,
9629 enum dma_data_direction direction
)
9631 return dma_map_single(dev
, cpu_addr
, size
, direction
);
9634 static void niu_pci_unmap_single(struct device
*dev
, u64 dma_address
,
9636 enum dma_data_direction direction
)
9638 dma_unmap_single(dev
, dma_address
, size
, direction
);
9641 static const struct niu_ops niu_pci_ops
= {
9642 .alloc_coherent
= niu_pci_alloc_coherent
,
9643 .free_coherent
= niu_pci_free_coherent
,
9644 .map_page
= niu_pci_map_page
,
9645 .unmap_page
= niu_pci_unmap_page
,
9646 .map_single
= niu_pci_map_single
,
9647 .unmap_single
= niu_pci_unmap_single
,
9650 static void niu_driver_version(void)
9652 static int niu_version_printed
;
9654 if (niu_version_printed
++ == 0)
9655 pr_info("%s", version
);
9658 static struct net_device
*niu_alloc_and_init(struct device
*gen_dev
,
9659 struct pci_dev
*pdev
,
9660 struct platform_device
*op
,
9661 const struct niu_ops
*ops
, u8 port
)
9663 struct net_device
*dev
;
9666 dev
= alloc_etherdev_mq(sizeof(struct niu
), NIU_NUM_TXCHAN
);
9670 SET_NETDEV_DEV(dev
, gen_dev
);
9672 np
= netdev_priv(dev
);
9676 np
->device
= gen_dev
;
9679 np
->msg_enable
= niu_debug
;
9681 spin_lock_init(&np
->lock
);
9682 INIT_WORK(&np
->reset_task
, niu_reset_task
);
9689 static const struct net_device_ops niu_netdev_ops
= {
9690 .ndo_open
= niu_open
,
9691 .ndo_stop
= niu_close
,
9692 .ndo_start_xmit
= niu_start_xmit
,
9693 .ndo_get_stats64
= niu_get_stats
,
9694 .ndo_set_rx_mode
= niu_set_rx_mode
,
9695 .ndo_validate_addr
= eth_validate_addr
,
9696 .ndo_set_mac_address
= niu_set_mac_addr
,
9697 .ndo_do_ioctl
= niu_ioctl
,
9698 .ndo_tx_timeout
= niu_tx_timeout
,
9699 .ndo_change_mtu
= niu_change_mtu
,
9702 static void niu_assign_netdev_ops(struct net_device
*dev
)
9704 dev
->netdev_ops
= &niu_netdev_ops
;
9705 dev
->ethtool_ops
= &niu_ethtool_ops
;
9706 dev
->watchdog_timeo
= NIU_TX_TIMEOUT
;
9709 static void niu_device_announce(struct niu
*np
)
9711 struct net_device
*dev
= np
->dev
;
9713 pr_info("%s: NIU Ethernet %pM\n", dev
->name
, dev
->dev_addr
);
9715 if (np
->parent
->plat_type
== PLAT_TYPE_ATCA_CP3220
) {
9716 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9718 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
9719 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
9720 (np
->flags
& NIU_FLAGS_FIBER
? "RGMII FIBER" : "SERDES"),
9721 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
9722 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
9725 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9727 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
9728 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
9729 (np
->flags
& NIU_FLAGS_FIBER
? "FIBER" :
9730 (np
->flags
& NIU_FLAGS_XCVR_SERDES
? "SERDES" :
9732 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
9733 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
9738 static void niu_set_basic_features(struct net_device
*dev
)
9740 dev
->hw_features
= NETIF_F_SG
| NETIF_F_HW_CSUM
| NETIF_F_RXHASH
;
9741 dev
->features
|= dev
->hw_features
| NETIF_F_RXCSUM
;
9744 static int niu_pci_init_one(struct pci_dev
*pdev
,
9745 const struct pci_device_id
*ent
)
9747 union niu_parent_id parent_id
;
9748 struct net_device
*dev
;
9753 niu_driver_version();
9755 err
= pci_enable_device(pdev
);
9757 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
9761 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
) ||
9762 !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
9763 dev_err(&pdev
->dev
, "Cannot find proper PCI device base addresses, aborting\n");
9765 goto err_out_disable_pdev
;
9768 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
9770 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
9771 goto err_out_disable_pdev
;
9774 if (!pci_is_pcie(pdev
)) {
9775 dev_err(&pdev
->dev
, "Cannot find PCI Express capability, aborting\n");
9777 goto err_out_free_res
;
9780 dev
= niu_alloc_and_init(&pdev
->dev
, pdev
, NULL
,
9781 &niu_pci_ops
, PCI_FUNC(pdev
->devfn
));
9784 goto err_out_free_res
;
9786 np
= netdev_priv(dev
);
9788 memset(&parent_id
, 0, sizeof(parent_id
));
9789 parent_id
.pci
.domain
= pci_domain_nr(pdev
->bus
);
9790 parent_id
.pci
.bus
= pdev
->bus
->number
;
9791 parent_id
.pci
.device
= PCI_SLOT(pdev
->devfn
);
9793 np
->parent
= niu_get_parent(np
, &parent_id
,
9797 goto err_out_free_dev
;
9800 pcie_capability_clear_and_set_word(pdev
, PCI_EXP_DEVCTL
,
9801 PCI_EXP_DEVCTL_NOSNOOP_EN
,
9802 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
9803 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
|
9804 PCI_EXP_DEVCTL_RELAX_EN
);
9806 dma_mask
= DMA_BIT_MASK(44);
9807 err
= pci_set_dma_mask(pdev
, dma_mask
);
9809 dev
->features
|= NETIF_F_HIGHDMA
;
9810 err
= pci_set_consistent_dma_mask(pdev
, dma_mask
);
9812 dev_err(&pdev
->dev
, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9813 goto err_out_release_parent
;
9817 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
9819 dev_err(&pdev
->dev
, "No usable DMA configuration, aborting\n");
9820 goto err_out_release_parent
;
9824 niu_set_basic_features(dev
);
9826 dev
->priv_flags
|= IFF_UNICAST_FLT
;
9828 np
->regs
= pci_ioremap_bar(pdev
, 0);
9830 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
9832 goto err_out_release_parent
;
9835 pci_set_master(pdev
);
9836 pci_save_state(pdev
);
9838 dev
->irq
= pdev
->irq
;
9840 niu_assign_netdev_ops(dev
);
9842 err
= niu_get_invariants(np
);
9845 dev_err(&pdev
->dev
, "Problem fetching invariants of chip, aborting\n");
9846 goto err_out_iounmap
;
9849 err
= register_netdev(dev
);
9851 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
9852 goto err_out_iounmap
;
9855 pci_set_drvdata(pdev
, dev
);
9857 niu_device_announce(np
);
9867 err_out_release_parent
:
9874 pci_release_regions(pdev
);
9876 err_out_disable_pdev
:
9877 pci_disable_device(pdev
);
9878 pci_set_drvdata(pdev
, NULL
);
9883 static void niu_pci_remove_one(struct pci_dev
*pdev
)
9885 struct net_device
*dev
= pci_get_drvdata(pdev
);
9888 struct niu
*np
= netdev_priv(dev
);
9890 unregister_netdev(dev
);
9901 pci_release_regions(pdev
);
9902 pci_disable_device(pdev
);
9903 pci_set_drvdata(pdev
, NULL
);
9907 static int niu_suspend(struct pci_dev
*pdev
, pm_message_t state
)
9909 struct net_device
*dev
= pci_get_drvdata(pdev
);
9910 struct niu
*np
= netdev_priv(dev
);
9911 unsigned long flags
;
9913 if (!netif_running(dev
))
9916 flush_work(&np
->reset_task
);
9919 del_timer_sync(&np
->timer
);
9921 spin_lock_irqsave(&np
->lock
, flags
);
9922 niu_enable_interrupts(np
, 0);
9923 spin_unlock_irqrestore(&np
->lock
, flags
);
9925 netif_device_detach(dev
);
9927 spin_lock_irqsave(&np
->lock
, flags
);
9929 spin_unlock_irqrestore(&np
->lock
, flags
);
9931 pci_save_state(pdev
);
9936 static int niu_resume(struct pci_dev
*pdev
)
9938 struct net_device
*dev
= pci_get_drvdata(pdev
);
9939 struct niu
*np
= netdev_priv(dev
);
9940 unsigned long flags
;
9943 if (!netif_running(dev
))
9946 pci_restore_state(pdev
);
9948 netif_device_attach(dev
);
9950 spin_lock_irqsave(&np
->lock
, flags
);
9952 err
= niu_init_hw(np
);
9954 np
->timer
.expires
= jiffies
+ HZ
;
9955 add_timer(&np
->timer
);
9956 niu_netif_start(np
);
9959 spin_unlock_irqrestore(&np
->lock
, flags
);
9964 static struct pci_driver niu_pci_driver
= {
9965 .name
= DRV_MODULE_NAME
,
9966 .id_table
= niu_pci_tbl
,
9967 .probe
= niu_pci_init_one
,
9968 .remove
= niu_pci_remove_one
,
9969 .suspend
= niu_suspend
,
9970 .resume
= niu_resume
,
9973 #ifdef CONFIG_SPARC64
9974 static void *niu_phys_alloc_coherent(struct device
*dev
, size_t size
,
9975 u64
*dma_addr
, gfp_t flag
)
9977 unsigned long order
= get_order(size
);
9978 unsigned long page
= __get_free_pages(flag
, order
);
9982 memset((char *)page
, 0, PAGE_SIZE
<< order
);
9983 *dma_addr
= __pa(page
);
9985 return (void *) page
;
9988 static void niu_phys_free_coherent(struct device
*dev
, size_t size
,
9989 void *cpu_addr
, u64 handle
)
9991 unsigned long order
= get_order(size
);
9993 free_pages((unsigned long) cpu_addr
, order
);
9996 static u64
niu_phys_map_page(struct device
*dev
, struct page
*page
,
9997 unsigned long offset
, size_t size
,
9998 enum dma_data_direction direction
)
10000 return page_to_phys(page
) + offset
;
10003 static void niu_phys_unmap_page(struct device
*dev
, u64 dma_address
,
10004 size_t size
, enum dma_data_direction direction
)
10006 /* Nothing to do. */
10009 static u64
niu_phys_map_single(struct device
*dev
, void *cpu_addr
,
10011 enum dma_data_direction direction
)
10013 return __pa(cpu_addr
);
10016 static void niu_phys_unmap_single(struct device
*dev
, u64 dma_address
,
10018 enum dma_data_direction direction
)
10020 /* Nothing to do. */
10023 static const struct niu_ops niu_phys_ops
= {
10024 .alloc_coherent
= niu_phys_alloc_coherent
,
10025 .free_coherent
= niu_phys_free_coherent
,
10026 .map_page
= niu_phys_map_page
,
10027 .unmap_page
= niu_phys_unmap_page
,
10028 .map_single
= niu_phys_map_single
,
10029 .unmap_single
= niu_phys_unmap_single
,
10032 static int niu_of_probe(struct platform_device
*op
)
10034 union niu_parent_id parent_id
;
10035 struct net_device
*dev
;
10040 niu_driver_version();
10042 reg
= of_get_property(op
->dev
.of_node
, "reg", NULL
);
10044 dev_err(&op
->dev
, "%s: No 'reg' property, aborting\n",
10045 op
->dev
.of_node
->full_name
);
10049 dev
= niu_alloc_and_init(&op
->dev
, NULL
, op
,
10050 &niu_phys_ops
, reg
[0] & 0x1);
10055 np
= netdev_priv(dev
);
10057 memset(&parent_id
, 0, sizeof(parent_id
));
10058 parent_id
.of
= of_get_parent(op
->dev
.of_node
);
10060 np
->parent
= niu_get_parent(np
, &parent_id
,
10064 goto err_out_free_dev
;
10067 niu_set_basic_features(dev
);
10069 np
->regs
= of_ioremap(&op
->resource
[1], 0,
10070 resource_size(&op
->resource
[1]),
10073 dev_err(&op
->dev
, "Cannot map device registers, aborting\n");
10075 goto err_out_release_parent
;
10078 np
->vir_regs_1
= of_ioremap(&op
->resource
[2], 0,
10079 resource_size(&op
->resource
[2]),
10081 if (!np
->vir_regs_1
) {
10082 dev_err(&op
->dev
, "Cannot map device vir registers 1, aborting\n");
10084 goto err_out_iounmap
;
10087 np
->vir_regs_2
= of_ioremap(&op
->resource
[3], 0,
10088 resource_size(&op
->resource
[3]),
10090 if (!np
->vir_regs_2
) {
10091 dev_err(&op
->dev
, "Cannot map device vir registers 2, aborting\n");
10093 goto err_out_iounmap
;
10096 niu_assign_netdev_ops(dev
);
10098 err
= niu_get_invariants(np
);
10100 if (err
!= -ENODEV
)
10101 dev_err(&op
->dev
, "Problem fetching invariants of chip, aborting\n");
10102 goto err_out_iounmap
;
10105 err
= register_netdev(dev
);
10107 dev_err(&op
->dev
, "Cannot register net device, aborting\n");
10108 goto err_out_iounmap
;
10111 platform_set_drvdata(op
, dev
);
10113 niu_device_announce(np
);
10118 if (np
->vir_regs_1
) {
10119 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
10120 resource_size(&op
->resource
[2]));
10121 np
->vir_regs_1
= NULL
;
10124 if (np
->vir_regs_2
) {
10125 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
10126 resource_size(&op
->resource
[3]));
10127 np
->vir_regs_2
= NULL
;
10131 of_iounmap(&op
->resource
[1], np
->regs
,
10132 resource_size(&op
->resource
[1]));
10136 err_out_release_parent
:
10137 niu_put_parent(np
);
10146 static int niu_of_remove(struct platform_device
*op
)
10148 struct net_device
*dev
= platform_get_drvdata(op
);
10151 struct niu
*np
= netdev_priv(dev
);
10153 unregister_netdev(dev
);
10155 if (np
->vir_regs_1
) {
10156 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
10157 resource_size(&op
->resource
[2]));
10158 np
->vir_regs_1
= NULL
;
10161 if (np
->vir_regs_2
) {
10162 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
10163 resource_size(&op
->resource
[3]));
10164 np
->vir_regs_2
= NULL
;
10168 of_iounmap(&op
->resource
[1], np
->regs
,
10169 resource_size(&op
->resource
[1]));
10175 niu_put_parent(np
);
10182 static const struct of_device_id niu_match
[] = {
10185 .compatible
= "SUNW,niusl",
10189 MODULE_DEVICE_TABLE(of
, niu_match
);
10191 static struct platform_driver niu_of_driver
= {
10194 .owner
= THIS_MODULE
,
10195 .of_match_table
= niu_match
,
10197 .probe
= niu_of_probe
,
10198 .remove
= niu_of_remove
,
10201 #endif /* CONFIG_SPARC64 */
10203 static int __init
niu_init(void)
10207 BUILD_BUG_ON(PAGE_SIZE
< 4 * 1024);
10209 niu_debug
= netif_msg_init(debug
, NIU_MSG_DEFAULT
);
10211 #ifdef CONFIG_SPARC64
10212 err
= platform_driver_register(&niu_of_driver
);
10216 err
= pci_register_driver(&niu_pci_driver
);
10217 #ifdef CONFIG_SPARC64
10219 platform_driver_unregister(&niu_of_driver
);
10226 static void __exit
niu_exit(void)
10228 pci_unregister_driver(&niu_pci_driver
);
10229 #ifdef CONFIG_SPARC64
10230 platform_driver_unregister(&niu_of_driver
);
10234 module_init(niu_init
);
10235 module_exit(niu_exit
);