4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * Copyright (C) 2013 Cogent Embedded, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <linux/mfd/tmio.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/platform_device.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/regulator/machine.h>
29 #include <linux/smsc911x.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/flash.h>
32 #include <media/soc_camera.h>
33 #include <mach/common.h>
34 #include <mach/irqs.h>
35 #include <mach/r8a7778.h>
36 #include <asm/mach/arch.h>
39 * CN9(Upper side) SCIF/RCAN selection
63 /* Dummy supplies, where voltage doesn't matter */
64 static struct regulator_consumer_supply dummy_supplies
[] = {
65 REGULATOR_SUPPLY("vddvario", "smsc911x"),
66 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
69 static struct smsc911x_platform_config smsc911x_data
= {
70 .irq_polarity
= SMSC911X_IRQ_POLARITY_ACTIVE_LOW
,
71 .irq_type
= SMSC911X_IRQ_TYPE_PUSH_PULL
,
72 .flags
= SMSC911X_USE_32BIT
,
73 .phy_interface
= PHY_INTERFACE_MODE_MII
,
76 static struct resource smsc911x_resources
[] = {
77 DEFINE_RES_MEM(0x18300000, 0x1000),
78 DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
82 static struct rcar_phy_platform_data usb_phy_platform_data __initdata
;
85 static struct sh_mobile_sdhi_info sdhi0_info
= {
86 .tmio_caps
= MMC_CAP_SD_HIGHSPEED
,
87 .tmio_ocr_mask
= MMC_VDD_165_195
| MMC_VDD_32_33
| MMC_VDD_33_34
,
88 .tmio_flags
= TMIO_MMC_HAS_IDLE_WAIT
,
91 static struct sh_eth_plat_data ether_platform_data __initdata
= {
93 .edmac_endian
= EDMAC_LITTLE_ENDIAN
,
94 .phy_interface
= PHY_INTERFACE_MODE_RMII
,
96 * Although the LINK signal is available on the board, it's connected to
97 * the link/activity LED output of the PHY, thus the link disappears and
98 * reappears after each packet. We'd be better off ignoring such signal
99 * and getting the link state from the PHY indirectly.
105 static struct i2c_board_info i2c0_devices
[] = {
107 I2C_BOARD_INFO("rx8581", 0x51),
112 static struct mtd_partition m25p80_spi_flash_partitions
[] = {
120 static struct flash_platform_data spi_flash_data
= {
123 .parts
= m25p80_spi_flash_partitions
,
124 .nr_parts
= ARRAY_SIZE(m25p80_spi_flash_partitions
),
127 static struct spi_board_info spi_board_info
[] __initdata
= {
129 .modalias
= "m25p80",
130 .max_speed_hz
= 104000000,
134 .platform_data
= &spi_flash_data
,
139 static struct sh_mmcif_plat_data sh_mmcif_plat
= {
141 .ocr
= MMC_VDD_165_195
| MMC_VDD_32_33
| MMC_VDD_33_34
,
142 .caps
= MMC_CAP_4_BIT_DATA
|
147 static struct rcar_vin_platform_data vin_platform_data __initdata
= {
148 .flags
= RCAR_VIN_BT656
,
151 /* In the default configuration both decoders reside on I2C bus 0 */
152 #define BOCKW_CAMERA(idx) \
153 static struct i2c_board_info camera##idx##_info = { \
154 I2C_BOARD_INFO("ml86v7667", 0x41 + 2 * (idx)), \
157 static struct soc_camera_link iclink##idx##_ml86v7667 __initdata = { \
159 .i2c_adapter_id = 0, \
160 .board_info = &camera##idx##_info, \
166 static const struct pinctrl_map bockw_pinctrl_map
[] = {
168 PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778",
169 "ether_rmii", "ether"),
171 PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778",
174 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
176 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
179 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
180 "scif0_data_a", "scif0"),
181 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
182 "scif0_ctrl", "scif0"),
184 PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
186 PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
189 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
190 "sdhi0_data4", "sdhi0"),
191 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
192 "sdhi0_ctrl", "sdhi0"),
193 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
194 "sdhi0_cd", "sdhi0"),
195 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
196 "sdhi0_wp", "sdhi0"),
198 PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778",
200 PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778",
201 "vin0_data8", "vin0"),
203 PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778",
205 PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778",
206 "vin1_data8", "vin1"),
209 #define FPGA 0x18200000
211 #define PFC 0xfffc0000
213 static void __init
bockw_init(void)
217 r8a7778_clock_init();
218 r8a7778_init_irq_extpin(1);
219 r8a7778_add_standard_devices();
220 r8a7778_add_usb_phy_device(&usb_phy_platform_data
);
221 r8a7778_add_ether_device(ðer_platform_data
);
222 r8a7778_add_i2c_device(0);
223 r8a7778_add_hspi_device(0);
224 r8a7778_add_mmc_device(&sh_mmcif_plat
);
225 r8a7778_add_vin_device(0, &vin_platform_data
);
226 /* VIN1 has a pin conflict with Ether */
227 if (!IS_ENABLED(CONFIG_SH_ETH
))
228 r8a7778_add_vin_device(1, &vin_platform_data
);
229 platform_device_register_data(&platform_bus
, "soc-camera-pdrv", 0,
231 sizeof(iclink0_ml86v7667
));
232 platform_device_register_data(&platform_bus
, "soc-camera-pdrv", 1,
234 sizeof(iclink1_ml86v7667
));
236 i2c_register_board_info(0, i2c0_devices
,
237 ARRAY_SIZE(i2c0_devices
));
238 spi_register_board_info(spi_board_info
,
239 ARRAY_SIZE(spi_board_info
));
240 pinctrl_register_mappings(bockw_pinctrl_map
,
241 ARRAY_SIZE(bockw_pinctrl_map
));
242 r8a7778_pinmux_init();
245 base
= ioremap_nocache(FPGA
, SZ_1M
);
250 * IRQ0/1 is cascaded interrupt from FPGA.
251 * it should be cared in the future
252 * Now, it is assuming IRQ0 was used only from SMSC.
254 u16 val
= ioread16(base
+ IRQ0MR
);
255 val
&= ~(1 << 4); /* enable SMSC911x */
256 iowrite16(val
, base
+ IRQ0MR
);
259 regulator_register_fixed(0, dummy_supplies
,
260 ARRAY_SIZE(dummy_supplies
));
262 platform_device_register_resndata(
263 &platform_bus
, "smsc911x", -1,
264 smsc911x_resources
, ARRAY_SIZE(smsc911x_resources
),
265 &smsc911x_data
, sizeof(smsc911x_data
));
269 base
= ioremap_nocache(PFC
, 0x200);
274 * SDHI CD/WP pin needs pull-up
276 iowrite32(ioread32(base
+ PUPR4
) | (3 << 26), base
+ PUPR4
);
279 r8a7778_sdhi_init(0, &sdhi0_info
);
283 static const char *bockw_boards_compat_dt
[] __initdata
= {
288 DT_MACHINE_START(BOCKW_DT
, "bockw")
289 .init_early
= r8a7778_init_delay
,
290 .init_irq
= r8a7778_init_irq_dt
,
291 .init_machine
= bockw_init
,
292 .init_time
= shmobile_timer_init
,
293 .dt_compat
= bockw_boards_compat_dt
,
294 .init_late
= r8a7778_init_late
,