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serial8250: Add dl_read()/dl_write() callbacks
[linux-2.6/btrfs-unstable.git] / drivers / tty / serial / 8250 / 8250.c
blob590ee85150bf880296015517e81e59f5161a2b8b
1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
41 #ifdef CONFIG_SPARC
42 #include <linux/sunserialcore.h>
43 #endif
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47
48 #include "8250.h"
49
50 /*
51 * Configuration:
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
59 static struct uart_driver serial8250_reg;
60
61 static int serial_index(struct uart_port *port)
62 {
63 return (serial8250_reg.minor - 64) + port->line;
64 }
65
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
68 /*
69 * Debugging.
70 */
71 #if 0
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
73 #else
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
75 #endif
76
77 #if 0
78 #define DEBUG_INTR(fmt...) printk(fmt)
79 #else
80 #define DEBUG_INTR(fmt...) do { } while (0)
81 #endif
82
83 #define PASS_LIMIT 512
84
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
90 #endif
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
93 #endif
94
95 /*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99 #define CONFIG_HUB6 1
100
101 #include <asm/serial.h>
102 /*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
109 #endif
110
111 static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113 };
114
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
116
117 #ifdef CONFIG_SERIAL_8250_RSA
118
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA */
123
124 struct irq_info {
125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
128 struct list_head *head;
129 };
130
131 #define NR_IRQ_HASH 32 /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
134
135 /*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138 static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
241 },
242 [PORT_RM9000] = {
243 .name = "RM9000",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_OCTEON] = {
250 .name = "OCTEON",
251 .fifo_size = 64,
252 .tx_loadsz = 64,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO,
255 },
256 [PORT_AR7] = {
257 .name = "AR7",
258 .fifo_size = 16,
259 .tx_loadsz = 16,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
263 [PORT_U6_16550A] = {
264 .name = "U6_16550A",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 },
270 [PORT_TEGRA] = {
271 .name = "Tegra",
272 .fifo_size = 32,
273 .tx_loadsz = 8,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
275 UART_FCR_T_TRIG_01,
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
277 },
278 [PORT_XR17D15X] = {
279 .name = "XR17D15X",
280 .fifo_size = 64,
281 .tx_loadsz = 64,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
284 },
285 };
286
287 /* Uart divisor latch read */
288 static int default_dl_read(struct uart_8250_port *up)
289 {
290 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
291 }
292
293 /* Uart divisor latch write */
294 static void default_dl_write(struct uart_8250_port *up, int value)
295 {
296 serial_out(up, UART_DLL, value & 0xff);
297 serial_out(up, UART_DLM, value >> 8 & 0xff);
298 }
299
300 #if defined(CONFIG_MIPS_ALCHEMY)
301 /* Au1x00 haven't got a standard divisor latch */
302 static int _serial_dl_read(struct uart_8250_port *up)
303 {
304 if (up->port.iotype == UPIO_AU)
305 return __raw_readl(up->port.membase + 0x28);
306 else
307 return default_dl_read(up);
308 }
309
310 static void _serial_dl_write(struct uart_8250_port *up, int value)
311 {
312 if (up->port.iotype == UPIO_AU)
313 __raw_writel(value, up->port.membase + 0x28);
314 else
315 default_dl_write(up, value);
316 }
317 #elif defined(CONFIG_SERIAL_8250_RM9K)
318 static int _serial_dl_read(struct uart_8250_port *up)
319 {
320 return (up->port.iotype == UPIO_RM9000) ?
321 (((__raw_readl(up->port.membase + 0x10) << 8) |
322 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
323 default_dl_read(up);
324 }
325
326 static void _serial_dl_write(struct uart_8250_port *up, int value)
327 {
328 if (up->port.iotype == UPIO_RM9000) {
329 __raw_writel(value, up->port.membase + 0x08);
330 __raw_writel(value >> 8, up->port.membase + 0x10);
331 } else {
332 default_dl_write(up, value);
333 }
334 }
335 #else
336 static int _serial_dl_read(struct uart_8250_port *up)
337 {
338 return default_dl_read(up);
339 }
340
341 static void _serial_dl_write(struct uart_8250_port *up, int value)
342 {
343 default_dl_write(up, value);
344 }
345 #endif
346
347 #if defined(CONFIG_MIPS_ALCHEMY)
348
349 /* Au1x00 UART hardware has a weird register layout */
350 static const u8 au_io_in_map[] = {
351 [UART_RX] = 0,
352 [UART_IER] = 2,
353 [UART_IIR] = 3,
354 [UART_LCR] = 5,
355 [UART_MCR] = 6,
356 [UART_LSR] = 7,
357 [UART_MSR] = 8,
358 };
359
360 static const u8 au_io_out_map[] = {
361 [UART_TX] = 1,
362 [UART_IER] = 2,
363 [UART_FCR] = 4,
364 [UART_LCR] = 5,
365 [UART_MCR] = 6,
366 };
367
368 /* sane hardware needs no mapping */
369 static inline int map_8250_in_reg(struct uart_port *p, int offset)
370 {
371 if (p->iotype != UPIO_AU)
372 return offset;
373 return au_io_in_map[offset];
374 }
375
376 static inline int map_8250_out_reg(struct uart_port *p, int offset)
377 {
378 if (p->iotype != UPIO_AU)
379 return offset;
380 return au_io_out_map[offset];
381 }
382
383 #elif defined(CONFIG_SERIAL_8250_RM9K)
384
385 static const u8
386 regmap_in[8] = {
387 [UART_RX] = 0x00,
388 [UART_IER] = 0x0c,
389 [UART_IIR] = 0x14,
390 [UART_LCR] = 0x1c,
391 [UART_MCR] = 0x20,
392 [UART_LSR] = 0x24,
393 [UART_MSR] = 0x28,
394 [UART_SCR] = 0x2c
395 },
396 regmap_out[8] = {
397 [UART_TX] = 0x04,
398 [UART_IER] = 0x0c,
399 [UART_FCR] = 0x18,
400 [UART_LCR] = 0x1c,
401 [UART_MCR] = 0x20,
402 [UART_LSR] = 0x24,
403 [UART_MSR] = 0x28,
404 [UART_SCR] = 0x2c
405 };
406
407 static inline int map_8250_in_reg(struct uart_port *p, int offset)
408 {
409 if (p->iotype != UPIO_RM9000)
410 return offset;
411 return regmap_in[offset];
412 }
413
414 static inline int map_8250_out_reg(struct uart_port *p, int offset)
415 {
416 if (p->iotype != UPIO_RM9000)
417 return offset;
418 return regmap_out[offset];
419 }
420
421 #else
422
423 /* sane hardware needs no mapping */
424 #define map_8250_in_reg(up, offset) (offset)
425 #define map_8250_out_reg(up, offset) (offset)
426
427 #endif
428
429 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
430 {
431 offset = map_8250_in_reg(p, offset) << p->regshift;
432 outb(p->hub6 - 1 + offset, p->iobase);
433 return inb(p->iobase + 1);
434 }
435
436 static void hub6_serial_out(struct uart_port *p, int offset, int value)
437 {
438 offset = map_8250_out_reg(p, offset) << p->regshift;
439 outb(p->hub6 - 1 + offset, p->iobase);
440 outb(value, p->iobase + 1);
441 }
442
443 static unsigned int mem_serial_in(struct uart_port *p, int offset)
444 {
445 offset = map_8250_in_reg(p, offset) << p->regshift;
446 return readb(p->membase + offset);
447 }
448
449 static void mem_serial_out(struct uart_port *p, int offset, int value)
450 {
451 offset = map_8250_out_reg(p, offset) << p->regshift;
452 writeb(value, p->membase + offset);
453 }
454
455 static void mem32_serial_out(struct uart_port *p, int offset, int value)
456 {
457 offset = map_8250_out_reg(p, offset) << p->regshift;
458 writel(value, p->membase + offset);
459 }
460
461 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
462 {
463 offset = map_8250_in_reg(p, offset) << p->regshift;
464 return readl(p->membase + offset);
465 }
466
467 static unsigned int au_serial_in(struct uart_port *p, int offset)
468 {
469 offset = map_8250_in_reg(p, offset) << p->regshift;
470 return __raw_readl(p->membase + offset);
471 }
472
473 static void au_serial_out(struct uart_port *p, int offset, int value)
474 {
475 offset = map_8250_out_reg(p, offset) << p->regshift;
476 __raw_writel(value, p->membase + offset);
477 }
478
479 static unsigned int io_serial_in(struct uart_port *p, int offset)
480 {
481 offset = map_8250_in_reg(p, offset) << p->regshift;
482 return inb(p->iobase + offset);
483 }
484
485 static void io_serial_out(struct uart_port *p, int offset, int value)
486 {
487 offset = map_8250_out_reg(p, offset) << p->regshift;
488 outb(value, p->iobase + offset);
489 }
490
491 static int serial8250_default_handle_irq(struct uart_port *port);
492
493 static void set_io_from_upio(struct uart_port *p)
494 {
495 struct uart_8250_port *up =
496 container_of(p, struct uart_8250_port, port);
497
498 up->dl_read = _serial_dl_read;
499 up->dl_write = _serial_dl_write;
500
501 switch (p->iotype) {
502 case UPIO_HUB6:
503 p->serial_in = hub6_serial_in;
504 p->serial_out = hub6_serial_out;
505 break;
506
507 case UPIO_MEM:
508 p->serial_in = mem_serial_in;
509 p->serial_out = mem_serial_out;
510 break;
511
512 case UPIO_RM9000:
513 case UPIO_MEM32:
514 p->serial_in = mem32_serial_in;
515 p->serial_out = mem32_serial_out;
516 break;
517
518 case UPIO_AU:
519 p->serial_in = au_serial_in;
520 p->serial_out = au_serial_out;
521 break;
522
523 default:
524 p->serial_in = io_serial_in;
525 p->serial_out = io_serial_out;
526 break;
527 }
528 /* Remember loaded iotype */
529 up->cur_iotype = p->iotype;
530 p->handle_irq = serial8250_default_handle_irq;
531 }
532
533 static void
534 serial_port_out_sync(struct uart_port *p, int offset, int value)
535 {
536 switch (p->iotype) {
537 case UPIO_MEM:
538 case UPIO_MEM32:
539 case UPIO_AU:
540 p->serial_out(p, offset, value);
541 p->serial_in(p, UART_LCR); /* safe, no side-effects */
542 break;
543 default:
544 p->serial_out(p, offset, value);
545 }
546 }
547
548 /*
549 * For the 16C950
550 */
551 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
552 {
553 serial_out(up, UART_SCR, offset);
554 serial_out(up, UART_ICR, value);
555 }
556
557 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
558 {
559 unsigned int value;
560
561 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
562 serial_out(up, UART_SCR, offset);
563 value = serial_in(up, UART_ICR);
564 serial_icr_write(up, UART_ACR, up->acr);
565
566 return value;
567 }
568
569 /*
570 * FIFO support.
571 */
572 static void serial8250_clear_fifos(struct uart_8250_port *p)
573 {
574 if (p->capabilities & UART_CAP_FIFO) {
575 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
576 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
577 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
578 serial_out(p, UART_FCR, 0);
579 }
580 }
581
582 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
583 {
584 unsigned char fcr;
585
586 serial8250_clear_fifos(p);
587 fcr = uart_config[p->port.type].fcr;
588 serial_out(p, UART_FCR, fcr);
589 }
590 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
591
592 /*
593 * IER sleep support. UARTs which have EFRs need the "extended
594 * capability" bit enabled. Note that on XR16C850s, we need to
595 * reset LCR to write to IER.
596 */
597 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
598 {
599 if (p->capabilities & UART_CAP_SLEEP) {
600 if (p->capabilities & UART_CAP_EFR) {
601 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
602 serial_out(p, UART_EFR, UART_EFR_ECB);
603 serial_out(p, UART_LCR, 0);
604 }
605 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
606 if (p->capabilities & UART_CAP_EFR) {
607 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
608 serial_out(p, UART_EFR, 0);
609 serial_out(p, UART_LCR, 0);
610 }
611 }
612 }
613
614 #ifdef CONFIG_SERIAL_8250_RSA
615 /*
616 * Attempts to turn on the RSA FIFO. Returns zero on failure.
617 * We set the port uart clock rate if we succeed.
618 */
619 static int __enable_rsa(struct uart_8250_port *up)
620 {
621 unsigned char mode;
622 int result;
623
624 mode = serial_in(up, UART_RSA_MSR);
625 result = mode & UART_RSA_MSR_FIFO;
626
627 if (!result) {
628 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
629 mode = serial_in(up, UART_RSA_MSR);
630 result = mode & UART_RSA_MSR_FIFO;
631 }
632
633 if (result)
634 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
635
636 return result;
637 }
638
639 static void enable_rsa(struct uart_8250_port *up)
640 {
641 if (up->port.type == PORT_RSA) {
642 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
643 spin_lock_irq(&up->port.lock);
644 __enable_rsa(up);
645 spin_unlock_irq(&up->port.lock);
646 }
647 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
648 serial_out(up, UART_RSA_FRR, 0);
649 }
650 }
651
652 /*
653 * Attempts to turn off the RSA FIFO. Returns zero on failure.
654 * It is unknown why interrupts were disabled in here. However,
655 * the caller is expected to preserve this behaviour by grabbing
656 * the spinlock before calling this function.
657 */
658 static void disable_rsa(struct uart_8250_port *up)
659 {
660 unsigned char mode;
661 int result;
662
663 if (up->port.type == PORT_RSA &&
664 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
665 spin_lock_irq(&up->port.lock);
666
667 mode = serial_in(up, UART_RSA_MSR);
668 result = !(mode & UART_RSA_MSR_FIFO);
669
670 if (!result) {
671 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
672 mode = serial_in(up, UART_RSA_MSR);
673 result = !(mode & UART_RSA_MSR_FIFO);
674 }
675
676 if (result)
677 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
678 spin_unlock_irq(&up->port.lock);
679 }
680 }
681 #endif /* CONFIG_SERIAL_8250_RSA */
682
683 /*
684 * This is a quickie test to see how big the FIFO is.
685 * It doesn't work at all the time, more's the pity.
686 */
687 static int size_fifo(struct uart_8250_port *up)
688 {
689 unsigned char old_fcr, old_mcr, old_lcr;
690 unsigned short old_dl;
691 int count;
692
693 old_lcr = serial_in(up, UART_LCR);
694 serial_out(up, UART_LCR, 0);
695 old_fcr = serial_in(up, UART_FCR);
696 old_mcr = serial_in(up, UART_MCR);
697 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
698 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
699 serial_out(up, UART_MCR, UART_MCR_LOOP);
700 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
701 old_dl = serial_dl_read(up);
702 serial_dl_write(up, 0x0001);
703 serial_out(up, UART_LCR, 0x03);
704 for (count = 0; count < 256; count++)
705 serial_out(up, UART_TX, count);
706 mdelay(20);/* FIXME - schedule_timeout */
707 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
708 (count < 256); count++)
709 serial_in(up, UART_RX);
710 serial_out(up, UART_FCR, old_fcr);
711 serial_out(up, UART_MCR, old_mcr);
712 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
713 serial_dl_write(up, old_dl);
714 serial_out(up, UART_LCR, old_lcr);
715
716 return count;
717 }
718
719 /*
720 * Read UART ID using the divisor method - set DLL and DLM to zero
721 * and the revision will be in DLL and device type in DLM. We
722 * preserve the device state across this.
723 */
724 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
725 {
726 unsigned char old_dll, old_dlm, old_lcr;
727 unsigned int id;
728
729 old_lcr = serial_in(p, UART_LCR);
730 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
731
732 old_dll = serial_in(p, UART_DLL);
733 old_dlm = serial_in(p, UART_DLM);
734
735 serial_out(p, UART_DLL, 0);
736 serial_out(p, UART_DLM, 0);
737
738 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
739
740 serial_out(p, UART_DLL, old_dll);
741 serial_out(p, UART_DLM, old_dlm);
742 serial_out(p, UART_LCR, old_lcr);
743
744 return id;
745 }
746
747 /*
748 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
749 * When this function is called we know it is at least a StarTech
750 * 16650 V2, but it might be one of several StarTech UARTs, or one of
751 * its clones. (We treat the broken original StarTech 16650 V1 as a
752 * 16550, and why not? Startech doesn't seem to even acknowledge its
753 * existence.)
754 *
755 * What evil have men's minds wrought...
756 */
757 static void autoconfig_has_efr(struct uart_8250_port *up)
758 {
759 unsigned int id1, id2, id3, rev;
760
761 /*
762 * Everything with an EFR has SLEEP
763 */
764 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
765
766 /*
767 * First we check to see if it's an Oxford Semiconductor UART.
768 *
769 * If we have to do this here because some non-National
770 * Semiconductor clone chips lock up if you try writing to the
771 * LSR register (which serial_icr_read does)
772 */
773
774 /*
775 * Check for Oxford Semiconductor 16C950.
776 *
777 * EFR [4] must be set else this test fails.
778 *
779 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
780 * claims that it's needed for 952 dual UART's (which are not
781 * recommended for new designs).
782 */
783 up->acr = 0;
784 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
785 serial_out(up, UART_EFR, UART_EFR_ECB);
786 serial_out(up, UART_LCR, 0x00);
787 id1 = serial_icr_read(up, UART_ID1);
788 id2 = serial_icr_read(up, UART_ID2);
789 id3 = serial_icr_read(up, UART_ID3);
790 rev = serial_icr_read(up, UART_REV);
791
792 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
793
794 if (id1 == 0x16 && id2 == 0xC9 &&
795 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
796 up->port.type = PORT_16C950;
797
798 /*
799 * Enable work around for the Oxford Semiconductor 952 rev B
800 * chip which causes it to seriously miscalculate baud rates
801 * when DLL is 0.
802 */
803 if (id3 == 0x52 && rev == 0x01)
804 up->bugs |= UART_BUG_QUOT;
805 return;
806 }
807
808 /*
809 * We check for a XR16C850 by setting DLL and DLM to 0, and then
810 * reading back DLL and DLM. The chip type depends on the DLM
811 * value read back:
812 * 0x10 - XR16C850 and the DLL contains the chip revision.
813 * 0x12 - XR16C2850.
814 * 0x14 - XR16C854.
815 */
816 id1 = autoconfig_read_divisor_id(up);
817 DEBUG_AUTOCONF("850id=%04x ", id1);
818
819 id2 = id1 >> 8;
820 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
821 up->port.type = PORT_16850;
822 return;
823 }
824
825 /*
826 * It wasn't an XR16C850.
827 *
828 * We distinguish between the '654 and the '650 by counting
829 * how many bytes are in the FIFO. I'm using this for now,
830 * since that's the technique that was sent to me in the
831 * serial driver update, but I'm not convinced this works.
832 * I've had problems doing this in the past. -TYT
833 */
834 if (size_fifo(up) == 64)
835 up->port.type = PORT_16654;
836 else
837 up->port.type = PORT_16650V2;
838 }
839
840 /*
841 * We detected a chip without a FIFO. Only two fall into
842 * this category - the original 8250 and the 16450. The
843 * 16450 has a scratch register (accessible with LCR=0)
844 */
845 static void autoconfig_8250(struct uart_8250_port *up)
846 {
847 unsigned char scratch, status1, status2;
848
849 up->port.type = PORT_8250;
850
851 scratch = serial_in(up, UART_SCR);
852 serial_out(up, UART_SCR, 0xa5);
853 status1 = serial_in(up, UART_SCR);
854 serial_out(up, UART_SCR, 0x5a);
855 status2 = serial_in(up, UART_SCR);
856 serial_out(up, UART_SCR, scratch);
857
858 if (status1 == 0xa5 && status2 == 0x5a)
859 up->port.type = PORT_16450;
860 }
861
862 static int broken_efr(struct uart_8250_port *up)
863 {
864 /*
865 * Exar ST16C2550 "A2" devices incorrectly detect as
866 * having an EFR, and report an ID of 0x0201. See
867 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
868 */
869 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
870 return 1;
871
872 return 0;
873 }
874
875 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
876 {
877 unsigned char status;
878
879 status = serial_in(up, 0x04); /* EXCR2 */
880 #define PRESL(x) ((x) & 0x30)
881 if (PRESL(status) == 0x10) {
882 /* already in high speed mode */
883 return 0;
884 } else {
885 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
886 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
887 serial_out(up, 0x04, status);
888 }
889 return 1;
890 }
891
892 /*
893 * We know that the chip has FIFOs. Does it have an EFR? The
894 * EFR is located in the same register position as the IIR and
895 * we know the top two bits of the IIR are currently set. The
896 * EFR should contain zero. Try to read the EFR.
897 */
898 static void autoconfig_16550a(struct uart_8250_port *up)
899 {
900 unsigned char status1, status2;
901 unsigned int iersave;
902
903 up->port.type = PORT_16550A;
904 up->capabilities |= UART_CAP_FIFO;
905
906 /*
907 * Check for presence of the EFR when DLAB is set.
908 * Only ST16C650V1 UARTs pass this test.
909 */
910 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
911 if (serial_in(up, UART_EFR) == 0) {
912 serial_out(up, UART_EFR, 0xA8);
913 if (serial_in(up, UART_EFR) != 0) {
914 DEBUG_AUTOCONF("EFRv1 ");
915 up->port.type = PORT_16650;
916 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
917 } else {
918 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
919 }
920 serial_out(up, UART_EFR, 0);
921 return;
922 }
923
924 /*
925 * Maybe it requires 0xbf to be written to the LCR.
926 * (other ST16C650V2 UARTs, TI16C752A, etc)
927 */
928 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
929 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
930 DEBUG_AUTOCONF("EFRv2 ");
931 autoconfig_has_efr(up);
932 return;
933 }
934
935 /*
936 * Check for a National Semiconductor SuperIO chip.
937 * Attempt to switch to bank 2, read the value of the LOOP bit
938 * from EXCR1. Switch back to bank 0, change it in MCR. Then
939 * switch back to bank 2, read it from EXCR1 again and check
940 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
941 */
942 serial_out(up, UART_LCR, 0);
943 status1 = serial_in(up, UART_MCR);
944 serial_out(up, UART_LCR, 0xE0);
945 status2 = serial_in(up, 0x02); /* EXCR1 */
946
947 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
948 serial_out(up, UART_LCR, 0);
949 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
950 serial_out(up, UART_LCR, 0xE0);
951 status2 = serial_in(up, 0x02); /* EXCR1 */
952 serial_out(up, UART_LCR, 0);
953 serial_out(up, UART_MCR, status1);
954
955 if ((status2 ^ status1) & UART_MCR_LOOP) {
956 unsigned short quot;
957
958 serial_out(up, UART_LCR, 0xE0);
959
960 quot = serial_dl_read(up);
961 quot <<= 3;
962
963 if (ns16550a_goto_highspeed(up))
964 serial_dl_write(up, quot);
965
966 serial_out(up, UART_LCR, 0);
967
968 up->port.uartclk = 921600*16;
969 up->port.type = PORT_NS16550A;
970 up->capabilities |= UART_NATSEMI;
971 return;
972 }
973 }
974
975 /*
976 * No EFR. Try to detect a TI16750, which only sets bit 5 of
977 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
978 * Try setting it with and without DLAB set. Cheap clones
979 * set bit 5 without DLAB set.
980 */
981 serial_out(up, UART_LCR, 0);
982 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
983 status1 = serial_in(up, UART_IIR) >> 5;
984 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
985 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
986 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
987 status2 = serial_in(up, UART_IIR) >> 5;
988 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
989 serial_out(up, UART_LCR, 0);
990
991 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
992
993 if (status1 == 6 && status2 == 7) {
994 up->port.type = PORT_16750;
995 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
996 return;
997 }
998
999 /*
1000 * Try writing and reading the UART_IER_UUE bit (b6).
1001 * If it works, this is probably one of the Xscale platform's
1002 * internal UARTs.
1003 * We're going to explicitly set the UUE bit to 0 before
1004 * trying to write and read a 1 just to make sure it's not
1005 * already a 1 and maybe locked there before we even start start.
1006 */
1007 iersave = serial_in(up, UART_IER);
1008 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1009 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1010 /*
1011 * OK it's in a known zero state, try writing and reading
1012 * without disturbing the current state of the other bits.
1013 */
1014 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1015 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1016 /*
1017 * It's an Xscale.
1018 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1019 */
1020 DEBUG_AUTOCONF("Xscale ");
1021 up->port.type = PORT_XSCALE;
1022 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1023 return;
1024 }
1025 } else {
1026 /*
1027 * If we got here we couldn't force the IER_UUE bit to 0.
1028 * Log it and continue.
1029 */
1030 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1031 }
1032 serial_out(up, UART_IER, iersave);
1033
1034 /*
1035 * Exar uarts have EFR in a weird location
1036 */
1037 if (up->port.flags & UPF_EXAR_EFR) {
1038 up->port.type = PORT_XR17D15X;
1039 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1040 }
1041
1042 /*
1043 * We distinguish between 16550A and U6 16550A by counting
1044 * how many bytes are in the FIFO.
1045 */
1046 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1047 up->port.type = PORT_U6_16550A;
1048 up->capabilities |= UART_CAP_AFE;
1049 }
1050 }
1051
1052 /*
1053 * This routine is called by rs_init() to initialize a specific serial
1054 * port. It determines what type of UART chip this serial port is
1055 * using: 8250, 16450, 16550, 16550A. The important question is
1056 * whether or not this UART is a 16550A or not, since this will
1057 * determine whether or not we can use its FIFO features or not.
1058 */
1059 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1060 {
1061 unsigned char status1, scratch, scratch2, scratch3;
1062 unsigned char save_lcr, save_mcr;
1063 struct uart_port *port = &up->port;
1064 unsigned long flags;
1065
1066 if (!port->iobase && !port->mapbase && !port->membase)
1067 return;
1068
1069 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1070 serial_index(port), port->iobase, port->membase);
1071
1072 /*
1073 * We really do need global IRQs disabled here - we're going to
1074 * be frobbing the chips IRQ enable register to see if it exists.
1075 */
1076 spin_lock_irqsave(&port->lock, flags);
1077
1078 up->capabilities = 0;
1079 up->bugs = 0;
1080
1081 if (!(port->flags & UPF_BUGGY_UART)) {
1082 /*
1083 * Do a simple existence test first; if we fail this,
1084 * there's no point trying anything else.
1085 *
1086 * 0x80 is used as a nonsense port to prevent against
1087 * false positives due to ISA bus float. The
1088 * assumption is that 0x80 is a non-existent port;
1089 * which should be safe since include/asm/io.h also
1090 * makes this assumption.
1091 *
1092 * Note: this is safe as long as MCR bit 4 is clear
1093 * and the device is in "PC" mode.
1094 */
1095 scratch = serial_in(up, UART_IER);
1096 serial_out(up, UART_IER, 0);
1097 #ifdef __i386__
1098 outb(0xff, 0x080);
1099 #endif
1100 /*
1101 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1102 * 16C754B) allow only to modify them if an EFR bit is set.
1103 */
1104 scratch2 = serial_in(up, UART_IER) & 0x0f;
1105 serial_out(up, UART_IER, 0x0F);
1106 #ifdef __i386__
1107 outb(0, 0x080);
1108 #endif
1109 scratch3 = serial_in(up, UART_IER) & 0x0f;
1110 serial_out(up, UART_IER, scratch);
1111 if (scratch2 != 0 || scratch3 != 0x0F) {
1112 /*
1113 * We failed; there's nothing here
1114 */
1115 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1116 scratch2, scratch3);
1117 goto out;
1118 }
1119 }
1120
1121 save_mcr = serial_in(up, UART_MCR);
1122 save_lcr = serial_in(up, UART_LCR);
1123
1124 /*
1125 * Check to see if a UART is really there. Certain broken
1126 * internal modems based on the Rockwell chipset fail this
1127 * test, because they apparently don't implement the loopback
1128 * test mode. So this test is skipped on the COM 1 through
1129 * COM 4 ports. This *should* be safe, since no board
1130 * manufacturer would be stupid enough to design a board
1131 * that conflicts with COM 1-4 --- we hope!
1132 */
1133 if (!(port->flags & UPF_SKIP_TEST)) {
1134 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1135 status1 = serial_in(up, UART_MSR) & 0xF0;
1136 serial_out(up, UART_MCR, save_mcr);
1137 if (status1 != 0x90) {
1138 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1139 status1);
1140 goto out;
1141 }
1142 }
1143
1144 /*
1145 * We're pretty sure there's a port here. Lets find out what
1146 * type of port it is. The IIR top two bits allows us to find
1147 * out if it's 8250 or 16450, 16550, 16550A or later. This
1148 * determines what we test for next.
1149 *
1150 * We also initialise the EFR (if any) to zero for later. The
1151 * EFR occupies the same register location as the FCR and IIR.
1152 */
1153 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1154 serial_out(up, UART_EFR, 0);
1155 serial_out(up, UART_LCR, 0);
1156
1157 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1158 scratch = serial_in(up, UART_IIR) >> 6;
1159
1160 DEBUG_AUTOCONF("iir=%d ", scratch);
1161
1162 switch (scratch) {
1163 case 0:
1164 autoconfig_8250(up);
1165 break;
1166 case 1:
1167 port->type = PORT_UNKNOWN;
1168 break;
1169 case 2:
1170 port->type = PORT_16550;
1171 break;
1172 case 3:
1173 autoconfig_16550a(up);
1174 break;
1175 }
1176
1177 #ifdef CONFIG_SERIAL_8250_RSA
1178 /*
1179 * Only probe for RSA ports if we got the region.
1180 */
1181 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1182 int i;
1183
1184 for (i = 0 ; i < probe_rsa_count; ++i) {
1185 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1186 port->type = PORT_RSA;
1187 break;
1188 }
1189 }
1190 }
1191 #endif
1192
1193 serial_out(up, UART_LCR, save_lcr);
1194
1195 if (up->capabilities != uart_config[port->type].flags) {
1196 printk(KERN_WARNING
1197 "ttyS%d: detected caps %08x should be %08x\n",
1198 serial_index(port), up->capabilities,
1199 uart_config[port->type].flags);
1200 }
1201
1202 port->fifosize = uart_config[up->port.type].fifo_size;
1203 up->capabilities = uart_config[port->type].flags;
1204 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1205
1206 if (port->type == PORT_UNKNOWN)
1207 goto out;
1208
1209 /*
1210 * Reset the UART.
1211 */
1212 #ifdef CONFIG_SERIAL_8250_RSA
1213 if (port->type == PORT_RSA)
1214 serial_out(up, UART_RSA_FRR, 0);
1215 #endif
1216 serial_out(up, UART_MCR, save_mcr);
1217 serial8250_clear_fifos(up);
1218 serial_in(up, UART_RX);
1219 if (up->capabilities & UART_CAP_UUE)
1220 serial_out(up, UART_IER, UART_IER_UUE);
1221 else
1222 serial_out(up, UART_IER, 0);
1223
1224 out:
1225 spin_unlock_irqrestore(&port->lock, flags);
1226 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1227 }
1228
1229 static void autoconfig_irq(struct uart_8250_port *up)
1230 {
1231 struct uart_port *port = &up->port;
1232 unsigned char save_mcr, save_ier;
1233 unsigned char save_ICP = 0;
1234 unsigned int ICP = 0;
1235 unsigned long irqs;
1236 int irq;
1237
1238 if (port->flags & UPF_FOURPORT) {
1239 ICP = (port->iobase & 0xfe0) | 0x1f;
1240 save_ICP = inb_p(ICP);
1241 outb_p(0x80, ICP);
1242 inb_p(ICP);
1243 }
1244
1245 /* forget possible initially masked and pending IRQ */
1246 probe_irq_off(probe_irq_on());
1247 save_mcr = serial_in(up, UART_MCR);
1248 save_ier = serial_in(up, UART_IER);
1249 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1250
1251 irqs = probe_irq_on();
1252 serial_out(up, UART_MCR, 0);
1253 udelay(10);
1254 if (port->flags & UPF_FOURPORT) {
1255 serial_out(up, UART_MCR,
1256 UART_MCR_DTR | UART_MCR_RTS);
1257 } else {
1258 serial_out(up, UART_MCR,
1259 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1260 }
1261 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1262 serial_in(up, UART_LSR);
1263 serial_in(up, UART_RX);
1264 serial_in(up, UART_IIR);
1265 serial_in(up, UART_MSR);
1266 serial_out(up, UART_TX, 0xFF);
1267 udelay(20);
1268 irq = probe_irq_off(irqs);
1269
1270 serial_out(up, UART_MCR, save_mcr);
1271 serial_out(up, UART_IER, save_ier);
1272
1273 if (port->flags & UPF_FOURPORT)
1274 outb_p(save_ICP, ICP);
1275
1276 port->irq = (irq > 0) ? irq : 0;
1277 }
1278
1279 static inline void __stop_tx(struct uart_8250_port *p)
1280 {
1281 if (p->ier & UART_IER_THRI) {
1282 p->ier &= ~UART_IER_THRI;
1283 serial_out(p, UART_IER, p->ier);
1284 }
1285 }
1286
1287 static void serial8250_stop_tx(struct uart_port *port)
1288 {
1289 struct uart_8250_port *up =
1290 container_of(port, struct uart_8250_port, port);
1291
1292 __stop_tx(up);
1293
1294 /*
1295 * We really want to stop the transmitter from sending.
1296 */
1297 if (port->type == PORT_16C950) {
1298 up->acr |= UART_ACR_TXDIS;
1299 serial_icr_write(up, UART_ACR, up->acr);
1300 }
1301 }
1302
1303 static void serial8250_start_tx(struct uart_port *port)
1304 {
1305 struct uart_8250_port *up =
1306 container_of(port, struct uart_8250_port, port);
1307
1308 if (!(up->ier & UART_IER_THRI)) {
1309 up->ier |= UART_IER_THRI;
1310 serial_port_out(port, UART_IER, up->ier);
1311
1312 if (up->bugs & UART_BUG_TXEN) {
1313 unsigned char lsr;
1314 lsr = serial_in(up, UART_LSR);
1315 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1316 if ((port->type == PORT_RM9000) ?
1317 (lsr & UART_LSR_THRE) :
1318 (lsr & UART_LSR_TEMT))
1319 serial8250_tx_chars(up);
1320 }
1321 }
1322
1323 /*
1324 * Re-enable the transmitter if we disabled it.
1325 */
1326 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1327 up->acr &= ~UART_ACR_TXDIS;
1328 serial_icr_write(up, UART_ACR, up->acr);
1329 }
1330 }
1331
1332 static void serial8250_stop_rx(struct uart_port *port)
1333 {
1334 struct uart_8250_port *up =
1335 container_of(port, struct uart_8250_port, port);
1336
1337 up->ier &= ~UART_IER_RLSI;
1338 up->port.read_status_mask &= ~UART_LSR_DR;
1339 serial_port_out(port, UART_IER, up->ier);
1340 }
1341
1342 static void serial8250_enable_ms(struct uart_port *port)
1343 {
1344 struct uart_8250_port *up =
1345 container_of(port, struct uart_8250_port, port);
1346
1347 /* no MSR capabilities */
1348 if (up->bugs & UART_BUG_NOMSR)
1349 return;
1350
1351 up->ier |= UART_IER_MSI;
1352 serial_port_out(port, UART_IER, up->ier);
1353 }
1354
1355 /*
1356 * serial8250_rx_chars: processes according to the passed in LSR
1357 * value, and returns the remaining LSR bits not handled
1358 * by this Rx routine.
1359 */
1360 unsigned char
1361 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1362 {
1363 struct uart_port *port = &up->port;
1364 struct tty_struct *tty = port->state->port.tty;
1365 unsigned char ch;
1366 int max_count = 256;
1367 char flag;
1368
1369 do {
1370 if (likely(lsr & UART_LSR_DR))
1371 ch = serial_in(up, UART_RX);
1372 else
1373 /*
1374 * Intel 82571 has a Serial Over Lan device that will
1375 * set UART_LSR_BI without setting UART_LSR_DR when
1376 * it receives a break. To avoid reading from the
1377 * receive buffer without UART_LSR_DR bit set, we
1378 * just force the read character to be 0
1379 */
1380 ch = 0;
1381
1382 flag = TTY_NORMAL;
1383 port->icount.rx++;
1384
1385 lsr |= up->lsr_saved_flags;
1386 up->lsr_saved_flags = 0;
1387
1388 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1389 if (lsr & UART_LSR_BI) {
1390 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1391 port->icount.brk++;
1392 /*
1393 * We do the SysRQ and SAK checking
1394 * here because otherwise the break
1395 * may get masked by ignore_status_mask
1396 * or read_status_mask.
1397 */
1398 if (uart_handle_break(port))
1399 goto ignore_char;
1400 } else if (lsr & UART_LSR_PE)
1401 port->icount.parity++;
1402 else if (lsr & UART_LSR_FE)
1403 port->icount.frame++;
1404 if (lsr & UART_LSR_OE)
1405 port->icount.overrun++;
1406
1407 /*
1408 * Mask off conditions which should be ignored.
1409 */
1410 lsr &= port->read_status_mask;
1411
1412 if (lsr & UART_LSR_BI) {
1413 DEBUG_INTR("handling break....");
1414 flag = TTY_BREAK;
1415 } else if (lsr & UART_LSR_PE)
1416 flag = TTY_PARITY;
1417 else if (lsr & UART_LSR_FE)
1418 flag = TTY_FRAME;
1419 }
1420 if (uart_handle_sysrq_char(port, ch))
1421 goto ignore_char;
1422
1423 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1424
1425 ignore_char:
1426 lsr = serial_in(up, UART_LSR);
1427 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1428 spin_unlock(&port->lock);
1429 tty_flip_buffer_push(tty);
1430 spin_lock(&port->lock);
1431 return lsr;
1432 }
1433 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1434
1435 void serial8250_tx_chars(struct uart_8250_port *up)
1436 {
1437 struct uart_port *port = &up->port;
1438 struct circ_buf *xmit = &port->state->xmit;
1439 int count;
1440
1441 if (port->x_char) {
1442 serial_out(up, UART_TX, port->x_char);
1443 port->icount.tx++;
1444 port->x_char = 0;
1445 return;
1446 }
1447 if (uart_tx_stopped(port)) {
1448 serial8250_stop_tx(port);
1449 return;
1450 }
1451 if (uart_circ_empty(xmit)) {
1452 __stop_tx(up);
1453 return;
1454 }
1455
1456 count = up->tx_loadsz;
1457 do {
1458 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1459 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1460 port->icount.tx++;
1461 if (uart_circ_empty(xmit))
1462 break;
1463 } while (--count > 0);
1464
1465 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1466 uart_write_wakeup(port);
1467
1468 DEBUG_INTR("THRE...");
1469
1470 if (uart_circ_empty(xmit))
1471 __stop_tx(up);
1472 }
1473 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1474
1475 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1476 {
1477 struct uart_port *port = &up->port;
1478 unsigned int status = serial_in(up, UART_MSR);
1479
1480 status |= up->msr_saved_flags;
1481 up->msr_saved_flags = 0;
1482 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1483 port->state != NULL) {
1484 if (status & UART_MSR_TERI)
1485 port->icount.rng++;
1486 if (status & UART_MSR_DDSR)
1487 port->icount.dsr++;
1488 if (status & UART_MSR_DDCD)
1489 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1490 if (status & UART_MSR_DCTS)
1491 uart_handle_cts_change(port, status & UART_MSR_CTS);
1492
1493 wake_up_interruptible(&port->state->port.delta_msr_wait);
1494 }
1495
1496 return status;
1497 }
1498 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1499
1500 /*
1501 * This handles the interrupt from one port.
1502 */
1503 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1504 {
1505 unsigned char status;
1506 unsigned long flags;
1507 struct uart_8250_port *up =
1508 container_of(port, struct uart_8250_port, port);
1509
1510 if (iir & UART_IIR_NO_INT)
1511 return 0;
1512
1513 spin_lock_irqsave(&port->lock, flags);
1514
1515 status = serial_port_in(port, UART_LSR);
1516
1517 DEBUG_INTR("status = %x...", status);
1518
1519 if (status & (UART_LSR_DR | UART_LSR_BI))
1520 status = serial8250_rx_chars(up, status);
1521 serial8250_modem_status(up);
1522 if (status & UART_LSR_THRE)
1523 serial8250_tx_chars(up);
1524
1525 spin_unlock_irqrestore(&port->lock, flags);
1526 return 1;
1527 }
1528 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1529
1530 static int serial8250_default_handle_irq(struct uart_port *port)
1531 {
1532 unsigned int iir = serial_port_in(port, UART_IIR);
1533
1534 return serial8250_handle_irq(port, iir);
1535 }
1536
1537 /*
1538 * This is the serial driver's interrupt routine.
1539 *
1540 * Arjan thinks the old way was overly complex, so it got simplified.
1541 * Alan disagrees, saying that need the complexity to handle the weird
1542 * nature of ISA shared interrupts. (This is a special exception.)
1543 *
1544 * In order to handle ISA shared interrupts properly, we need to check
1545 * that all ports have been serviced, and therefore the ISA interrupt
1546 * line has been de-asserted.
1547 *
1548 * This means we need to loop through all ports. checking that they
1549 * don't have an interrupt pending.
1550 */
1551 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1552 {
1553 struct irq_info *i = dev_id;
1554 struct list_head *l, *end = NULL;
1555 int pass_counter = 0, handled = 0;
1556
1557 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1558
1559 spin_lock(&i->lock);
1560
1561 l = i->head;
1562 do {
1563 struct uart_8250_port *up;
1564 struct uart_port *port;
1565
1566 up = list_entry(l, struct uart_8250_port, list);
1567 port = &up->port;
1568
1569 if (port->handle_irq(port)) {
1570 handled = 1;
1571 end = NULL;
1572 } else if (end == NULL)
1573 end = l;
1574
1575 l = l->next;
1576
1577 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1578 /* If we hit this, we're dead. */
1579 printk_ratelimited(KERN_ERR
1580 "serial8250: too much work for irq%d\n", irq);
1581 break;
1582 }
1583 } while (l != end);
1584
1585 spin_unlock(&i->lock);
1586
1587 DEBUG_INTR("end.\n");
1588
1589 return IRQ_RETVAL(handled);
1590 }
1591
1592 /*
1593 * To support ISA shared interrupts, we need to have one interrupt
1594 * handler that ensures that the IRQ line has been deasserted
1595 * before returning. Failing to do this will result in the IRQ
1596 * line being stuck active, and, since ISA irqs are edge triggered,
1597 * no more IRQs will be seen.
1598 */
1599 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1600 {
1601 spin_lock_irq(&i->lock);
1602
1603 if (!list_empty(i->head)) {
1604 if (i->head == &up->list)
1605 i->head = i->head->next;
1606 list_del(&up->list);
1607 } else {
1608 BUG_ON(i->head != &up->list);
1609 i->head = NULL;
1610 }
1611 spin_unlock_irq(&i->lock);
1612 /* List empty so throw away the hash node */
1613 if (i->head == NULL) {
1614 hlist_del(&i->node);
1615 kfree(i);
1616 }
1617 }
1618
1619 static int serial_link_irq_chain(struct uart_8250_port *up)
1620 {
1621 struct hlist_head *h;
1622 struct hlist_node *n;
1623 struct irq_info *i;
1624 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1625
1626 mutex_lock(&hash_mutex);
1627
1628 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1629
1630 hlist_for_each(n, h) {
1631 i = hlist_entry(n, struct irq_info, node);
1632 if (i->irq == up->port.irq)
1633 break;
1634 }
1635
1636 if (n == NULL) {
1637 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1638 if (i == NULL) {
1639 mutex_unlock(&hash_mutex);
1640 return -ENOMEM;
1641 }
1642 spin_lock_init(&i->lock);
1643 i->irq = up->port.irq;
1644 hlist_add_head(&i->node, h);
1645 }
1646 mutex_unlock(&hash_mutex);
1647
1648 spin_lock_irq(&i->lock);
1649
1650 if (i->head) {
1651 list_add(&up->list, i->head);
1652 spin_unlock_irq(&i->lock);
1653
1654 ret = 0;
1655 } else {
1656 INIT_LIST_HEAD(&up->list);
1657 i->head = &up->list;
1658 spin_unlock_irq(&i->lock);
1659 irq_flags |= up->port.irqflags;
1660 ret = request_irq(up->port.irq, serial8250_interrupt,
1661 irq_flags, "serial", i);
1662 if (ret < 0)
1663 serial_do_unlink(i, up);
1664 }
1665
1666 return ret;
1667 }
1668
1669 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1670 {
1671 struct irq_info *i;
1672 struct hlist_node *n;
1673 struct hlist_head *h;
1674
1675 mutex_lock(&hash_mutex);
1676
1677 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1678
1679 hlist_for_each(n, h) {
1680 i = hlist_entry(n, struct irq_info, node);
1681 if (i->irq == up->port.irq)
1682 break;
1683 }
1684
1685 BUG_ON(n == NULL);
1686 BUG_ON(i->head == NULL);
1687
1688 if (list_empty(i->head))
1689 free_irq(up->port.irq, i);
1690
1691 serial_do_unlink(i, up);
1692 mutex_unlock(&hash_mutex);
1693 }
1694
1695 /*
1696 * This function is used to handle ports that do not have an
1697 * interrupt. This doesn't work very well for 16450's, but gives
1698 * barely passable results for a 16550A. (Although at the expense
1699 * of much CPU overhead).
1700 */
1701 static void serial8250_timeout(unsigned long data)
1702 {
1703 struct uart_8250_port *up = (struct uart_8250_port *)data;
1704
1705 up->port.handle_irq(&up->port);
1706 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1707 }
1708
1709 static void serial8250_backup_timeout(unsigned long data)
1710 {
1711 struct uart_8250_port *up = (struct uart_8250_port *)data;
1712 unsigned int iir, ier = 0, lsr;
1713 unsigned long flags;
1714
1715 spin_lock_irqsave(&up->port.lock, flags);
1716
1717 /*
1718 * Must disable interrupts or else we risk racing with the interrupt
1719 * based handler.
1720 */
1721 if (up->port.irq) {
1722 ier = serial_in(up, UART_IER);
1723 serial_out(up, UART_IER, 0);
1724 }
1725
1726 iir = serial_in(up, UART_IIR);
1727
1728 /*
1729 * This should be a safe test for anyone who doesn't trust the
1730 * IIR bits on their UART, but it's specifically designed for
1731 * the "Diva" UART used on the management processor on many HP
1732 * ia64 and parisc boxes.
1733 */
1734 lsr = serial_in(up, UART_LSR);
1735 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1736 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1737 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1738 (lsr & UART_LSR_THRE)) {
1739 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1740 iir |= UART_IIR_THRI;
1741 }
1742
1743 if (!(iir & UART_IIR_NO_INT))
1744 serial8250_tx_chars(up);
1745
1746 if (up->port.irq)
1747 serial_out(up, UART_IER, ier);
1748
1749 spin_unlock_irqrestore(&up->port.lock, flags);
1750
1751 /* Standard timer interval plus 0.2s to keep the port running */
1752 mod_timer(&up->timer,
1753 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1754 }
1755
1756 static unsigned int serial8250_tx_empty(struct uart_port *port)
1757 {
1758 struct uart_8250_port *up =
1759 container_of(port, struct uart_8250_port, port);
1760 unsigned long flags;
1761 unsigned int lsr;
1762
1763 spin_lock_irqsave(&port->lock, flags);
1764 lsr = serial_port_in(port, UART_LSR);
1765 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1766 spin_unlock_irqrestore(&port->lock, flags);
1767
1768 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1769 }
1770
1771 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1772 {
1773 struct uart_8250_port *up =
1774 container_of(port, struct uart_8250_port, port);
1775 unsigned int status;
1776 unsigned int ret;
1777
1778 status = serial8250_modem_status(up);
1779
1780 ret = 0;
1781 if (status & UART_MSR_DCD)
1782 ret |= TIOCM_CAR;
1783 if (status & UART_MSR_RI)
1784 ret |= TIOCM_RNG;
1785 if (status & UART_MSR_DSR)
1786 ret |= TIOCM_DSR;
1787 if (status & UART_MSR_CTS)
1788 ret |= TIOCM_CTS;
1789 return ret;
1790 }
1791
1792 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1793 {
1794 struct uart_8250_port *up =
1795 container_of(port, struct uart_8250_port, port);
1796 unsigned char mcr = 0;
1797
1798 if (mctrl & TIOCM_RTS)
1799 mcr |= UART_MCR_RTS;
1800 if (mctrl & TIOCM_DTR)
1801 mcr |= UART_MCR_DTR;
1802 if (mctrl & TIOCM_OUT1)
1803 mcr |= UART_MCR_OUT1;
1804 if (mctrl & TIOCM_OUT2)
1805 mcr |= UART_MCR_OUT2;
1806 if (mctrl & TIOCM_LOOP)
1807 mcr |= UART_MCR_LOOP;
1808
1809 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1810
1811 serial_port_out(port, UART_MCR, mcr);
1812 }
1813
1814 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1815 {
1816 struct uart_8250_port *up =
1817 container_of(port, struct uart_8250_port, port);
1818 unsigned long flags;
1819
1820 spin_lock_irqsave(&port->lock, flags);
1821 if (break_state == -1)
1822 up->lcr |= UART_LCR_SBC;
1823 else
1824 up->lcr &= ~UART_LCR_SBC;
1825 serial_port_out(port, UART_LCR, up->lcr);
1826 spin_unlock_irqrestore(&port->lock, flags);
1827 }
1828
1829 /*
1830 * Wait for transmitter & holding register to empty
1831 */
1832 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1833 {
1834 unsigned int status, tmout = 10000;
1835
1836 /* Wait up to 10ms for the character(s) to be sent. */
1837 for (;;) {
1838 status = serial_in(up, UART_LSR);
1839
1840 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1841
1842 if ((status & bits) == bits)
1843 break;
1844 if (--tmout == 0)
1845 break;
1846 udelay(1);
1847 }
1848
1849 /* Wait up to 1s for flow control if necessary */
1850 if (up->port.flags & UPF_CONS_FLOW) {
1851 unsigned int tmout;
1852 for (tmout = 1000000; tmout; tmout--) {
1853 unsigned int msr = serial_in(up, UART_MSR);
1854 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1855 if (msr & UART_MSR_CTS)
1856 break;
1857 udelay(1);
1858 touch_nmi_watchdog();
1859 }
1860 }
1861 }
1862
1863 #ifdef CONFIG_CONSOLE_POLL
1864 /*
1865 * Console polling routines for writing and reading from the uart while
1866 * in an interrupt or debug context.
1867 */
1868
1869 static int serial8250_get_poll_char(struct uart_port *port)
1870 {
1871 unsigned char lsr = serial_port_in(port, UART_LSR);
1872
1873 if (!(lsr & UART_LSR_DR))
1874 return NO_POLL_CHAR;
1875
1876 return serial_port_in(port, UART_RX);
1877 }
1878
1879
1880 static void serial8250_put_poll_char(struct uart_port *port,
1881 unsigned char c)
1882 {
1883 unsigned int ier;
1884 struct uart_8250_port *up =
1885 container_of(port, struct uart_8250_port, port);
1886
1887 /*
1888 * First save the IER then disable the interrupts
1889 */
1890 ier = serial_port_in(port, UART_IER);
1891 if (up->capabilities & UART_CAP_UUE)
1892 serial_port_out(port, UART_IER, UART_IER_UUE);
1893 else
1894 serial_port_out(port, UART_IER, 0);
1895
1896 wait_for_xmitr(up, BOTH_EMPTY);
1897 /*
1898 * Send the character out.
1899 * If a LF, also do CR...
1900 */
1901 serial_port_out(port, UART_TX, c);
1902 if (c == 10) {
1903 wait_for_xmitr(up, BOTH_EMPTY);
1904 serial_port_out(port, UART_TX, 13);
1905 }
1906
1907 /*
1908 * Finally, wait for transmitter to become empty
1909 * and restore the IER
1910 */
1911 wait_for_xmitr(up, BOTH_EMPTY);
1912 serial_port_out(port, UART_IER, ier);
1913 }
1914
1915 #endif /* CONFIG_CONSOLE_POLL */
1916
1917 static int serial8250_startup(struct uart_port *port)
1918 {
1919 struct uart_8250_port *up =
1920 container_of(port, struct uart_8250_port, port);
1921 unsigned long flags;
1922 unsigned char lsr, iir;
1923 int retval;
1924
1925 port->fifosize = uart_config[up->port.type].fifo_size;
1926 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1927 up->capabilities = uart_config[up->port.type].flags;
1928 up->mcr = 0;
1929
1930 if (port->iotype != up->cur_iotype)
1931 set_io_from_upio(port);
1932
1933 if (port->type == PORT_16C950) {
1934 /* Wake up and initialize UART */
1935 up->acr = 0;
1936 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1937 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1938 serial_port_out(port, UART_IER, 0);
1939 serial_port_out(port, UART_LCR, 0);
1940 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1941 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1942 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1943 serial_port_out(port, UART_LCR, 0);
1944 }
1945
1946 #ifdef CONFIG_SERIAL_8250_RSA
1947 /*
1948 * If this is an RSA port, see if we can kick it up to the
1949 * higher speed clock.
1950 */
1951 enable_rsa(up);
1952 #endif
1953
1954 /*
1955 * Clear the FIFO buffers and disable them.
1956 * (they will be reenabled in set_termios())
1957 */
1958 serial8250_clear_fifos(up);
1959
1960 /*
1961 * Clear the interrupt registers.
1962 */
1963 serial_port_in(port, UART_LSR);
1964 serial_port_in(port, UART_RX);
1965 serial_port_in(port, UART_IIR);
1966 serial_port_in(port, UART_MSR);
1967
1968 /*
1969 * At this point, there's no way the LSR could still be 0xff;
1970 * if it is, then bail out, because there's likely no UART
1971 * here.
1972 */
1973 if (!(port->flags & UPF_BUGGY_UART) &&
1974 (serial_port_in(port, UART_LSR) == 0xff)) {
1975 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1976 serial_index(port));
1977 return -ENODEV;
1978 }
1979
1980 /*
1981 * For a XR16C850, we need to set the trigger levels
1982 */
1983 if (port->type == PORT_16850) {
1984 unsigned char fctr;
1985
1986 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1987
1988 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1989 serial_port_out(port, UART_FCTR,
1990 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1991 serial_port_out(port, UART_TRG, UART_TRG_96);
1992 serial_port_out(port, UART_FCTR,
1993 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1994 serial_port_out(port, UART_TRG, UART_TRG_96);
1995
1996 serial_port_out(port, UART_LCR, 0);
1997 }
1998
1999 if (port->irq) {
2000 unsigned char iir1;
2001 /*
2002 * Test for UARTs that do not reassert THRE when the
2003 * transmitter is idle and the interrupt has already
2004 * been cleared. Real 16550s should always reassert
2005 * this interrupt whenever the transmitter is idle and
2006 * the interrupt is enabled. Delays are necessary to
2007 * allow register changes to become visible.
2008 */
2009 spin_lock_irqsave(&port->lock, flags);
2010 if (up->port.irqflags & IRQF_SHARED)
2011 disable_irq_nosync(port->irq);
2012
2013 wait_for_xmitr(up, UART_LSR_THRE);
2014 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2015 udelay(1); /* allow THRE to set */
2016 iir1 = serial_port_in(port, UART_IIR);
2017 serial_port_out(port, UART_IER, 0);
2018 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2019 udelay(1); /* allow a working UART time to re-assert THRE */
2020 iir = serial_port_in(port, UART_IIR);
2021 serial_port_out(port, UART_IER, 0);
2022
2023 if (port->irqflags & IRQF_SHARED)
2024 enable_irq(port->irq);
2025 spin_unlock_irqrestore(&port->lock, flags);
2026
2027 /*
2028 * If the interrupt is not reasserted, or we otherwise
2029 * don't trust the iir, setup a timer to kick the UART
2030 * on a regular basis.
2031 */
2032 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2033 up->port.flags & UPF_BUG_THRE) {
2034 up->bugs |= UART_BUG_THRE;
2035 pr_debug("ttyS%d - using backup timer\n",
2036 serial_index(port));
2037 }
2038 }
2039
2040 /*
2041 * The above check will only give an accurate result the first time
2042 * the port is opened so this value needs to be preserved.
2043 */
2044 if (up->bugs & UART_BUG_THRE) {
2045 up->timer.function = serial8250_backup_timeout;
2046 up->timer.data = (unsigned long)up;
2047 mod_timer(&up->timer, jiffies +
2048 uart_poll_timeout(port) + HZ / 5);
2049 }
2050
2051 /*
2052 * If the "interrupt" for this port doesn't correspond with any
2053 * hardware interrupt, we use a timer-based system. The original
2054 * driver used to do this with IRQ0.
2055 */
2056 if (!port->irq) {
2057 up->timer.data = (unsigned long)up;
2058 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2059 } else {
2060 retval = serial_link_irq_chain(up);
2061 if (retval)
2062 return retval;
2063 }
2064
2065 /*
2066 * Now, initialize the UART
2067 */
2068 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2069
2070 spin_lock_irqsave(&port->lock, flags);
2071 if (up->port.flags & UPF_FOURPORT) {
2072 if (!up->port.irq)
2073 up->port.mctrl |= TIOCM_OUT1;
2074 } else
2075 /*
2076 * Most PC uarts need OUT2 raised to enable interrupts.
2077 */
2078 if (port->irq)
2079 up->port.mctrl |= TIOCM_OUT2;
2080
2081 serial8250_set_mctrl(port, port->mctrl);
2082
2083 /* Serial over Lan (SoL) hack:
2084 Intel 8257x Gigabit ethernet chips have a
2085 16550 emulation, to be used for Serial Over Lan.
2086 Those chips take a longer time than a normal
2087 serial device to signalize that a transmission
2088 data was queued. Due to that, the above test generally
2089 fails. One solution would be to delay the reading of
2090 iir. However, this is not reliable, since the timeout
2091 is variable. So, let's just don't test if we receive
2092 TX irq. This way, we'll never enable UART_BUG_TXEN.
2093 */
2094 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2095 goto dont_test_tx_en;
2096
2097 /*
2098 * Do a quick test to see if we receive an
2099 * interrupt when we enable the TX irq.
2100 */
2101 serial_port_out(port, UART_IER, UART_IER_THRI);
2102 lsr = serial_port_in(port, UART_LSR);
2103 iir = serial_port_in(port, UART_IIR);
2104 serial_port_out(port, UART_IER, 0);
2105
2106 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2107 if (!(up->bugs & UART_BUG_TXEN)) {
2108 up->bugs |= UART_BUG_TXEN;
2109 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2110 serial_index(port));
2111 }
2112 } else {
2113 up->bugs &= ~UART_BUG_TXEN;
2114 }
2115
2116 dont_test_tx_en:
2117 spin_unlock_irqrestore(&port->lock, flags);
2118
2119 /*
2120 * Clear the interrupt registers again for luck, and clear the
2121 * saved flags to avoid getting false values from polling
2122 * routines or the previous session.
2123 */
2124 serial_port_in(port, UART_LSR);
2125 serial_port_in(port, UART_RX);
2126 serial_port_in(port, UART_IIR);
2127 serial_port_in(port, UART_MSR);
2128 up->lsr_saved_flags = 0;
2129 up->msr_saved_flags = 0;
2130
2131 /*
2132 * Finally, enable interrupts. Note: Modem status interrupts
2133 * are set via set_termios(), which will be occurring imminently
2134 * anyway, so we don't enable them here.
2135 */
2136 up->ier = UART_IER_RLSI | UART_IER_RDI;
2137 serial_port_out(port, UART_IER, up->ier);
2138
2139 if (port->flags & UPF_FOURPORT) {
2140 unsigned int icp;
2141 /*
2142 * Enable interrupts on the AST Fourport board
2143 */
2144 icp = (port->iobase & 0xfe0) | 0x01f;
2145 outb_p(0x80, icp);
2146 inb_p(icp);
2147 }
2148
2149 return 0;
2150 }
2151
2152 static void serial8250_shutdown(struct uart_port *port)
2153 {
2154 struct uart_8250_port *up =
2155 container_of(port, struct uart_8250_port, port);
2156 unsigned long flags;
2157
2158 /*
2159 * Disable interrupts from this port
2160 */
2161 up->ier = 0;
2162 serial_port_out(port, UART_IER, 0);
2163
2164 spin_lock_irqsave(&port->lock, flags);
2165 if (port->flags & UPF_FOURPORT) {
2166 /* reset interrupts on the AST Fourport board */
2167 inb((port->iobase & 0xfe0) | 0x1f);
2168 port->mctrl |= TIOCM_OUT1;
2169 } else
2170 port->mctrl &= ~TIOCM_OUT2;
2171
2172 serial8250_set_mctrl(port, port->mctrl);
2173 spin_unlock_irqrestore(&port->lock, flags);
2174
2175 /*
2176 * Disable break condition and FIFOs
2177 */
2178 serial_port_out(port, UART_LCR,
2179 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2180 serial8250_clear_fifos(up);
2181
2182 #ifdef CONFIG_SERIAL_8250_RSA
2183 /*
2184 * Reset the RSA board back to 115kbps compat mode.
2185 */
2186 disable_rsa(up);
2187 #endif
2188
2189 /*
2190 * Read data port to reset things, and then unlink from
2191 * the IRQ chain.
2192 */
2193 serial_port_in(port, UART_RX);
2194
2195 del_timer_sync(&up->timer);
2196 up->timer.function = serial8250_timeout;
2197 if (port->irq)
2198 serial_unlink_irq_chain(up);
2199 }
2200
2201 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2202 {
2203 unsigned int quot;
2204
2205 /*
2206 * Handle magic divisors for baud rates above baud_base on
2207 * SMSC SuperIO chips.
2208 */
2209 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2210 baud == (port->uartclk/4))
2211 quot = 0x8001;
2212 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2213 baud == (port->uartclk/8))
2214 quot = 0x8002;
2215 else
2216 quot = uart_get_divisor(port, baud);
2217
2218 return quot;
2219 }
2220
2221 void
2222 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2223 struct ktermios *old)
2224 {
2225 struct uart_8250_port *up =
2226 container_of(port, struct uart_8250_port, port);
2227 unsigned char cval, fcr = 0;
2228 unsigned long flags;
2229 unsigned int baud, quot;
2230
2231 switch (termios->c_cflag & CSIZE) {
2232 case CS5:
2233 cval = UART_LCR_WLEN5;
2234 break;
2235 case CS6:
2236 cval = UART_LCR_WLEN6;
2237 break;
2238 case CS7:
2239 cval = UART_LCR_WLEN7;
2240 break;
2241 default:
2242 case CS8:
2243 cval = UART_LCR_WLEN8;
2244 break;
2245 }
2246
2247 if (termios->c_cflag & CSTOPB)
2248 cval |= UART_LCR_STOP;
2249 if (termios->c_cflag & PARENB)
2250 cval |= UART_LCR_PARITY;
2251 if (!(termios->c_cflag & PARODD))
2252 cval |= UART_LCR_EPAR;
2253 #ifdef CMSPAR
2254 if (termios->c_cflag & CMSPAR)
2255 cval |= UART_LCR_SPAR;
2256 #endif
2257
2258 /*
2259 * Ask the core to calculate the divisor for us.
2260 */
2261 baud = uart_get_baud_rate(port, termios, old,
2262 port->uartclk / 16 / 0xffff,
2263 port->uartclk / 16);
2264 quot = serial8250_get_divisor(port, baud);
2265
2266 /*
2267 * Oxford Semi 952 rev B workaround
2268 */
2269 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2270 quot++;
2271
2272 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2273 fcr = uart_config[port->type].fcr;
2274 if (baud < 2400) {
2275 fcr &= ~UART_FCR_TRIGGER_MASK;
2276 fcr |= UART_FCR_TRIGGER_1;
2277 }
2278 }
2279
2280 /*
2281 * MCR-based auto flow control. When AFE is enabled, RTS will be
2282 * deasserted when the receive FIFO contains more characters than
2283 * the trigger, or the MCR RTS bit is cleared. In the case where
2284 * the remote UART is not using CTS auto flow control, we must
2285 * have sufficient FIFO entries for the latency of the remote
2286 * UART to respond. IOW, at least 32 bytes of FIFO.
2287 */
2288 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2289 up->mcr &= ~UART_MCR_AFE;
2290 if (termios->c_cflag & CRTSCTS)
2291 up->mcr |= UART_MCR_AFE;
2292 }
2293
2294 /*
2295 * Ok, we're now changing the port state. Do it with
2296 * interrupts disabled.
2297 */
2298 spin_lock_irqsave(&port->lock, flags);
2299
2300 /*
2301 * Update the per-port timeout.
2302 */
2303 uart_update_timeout(port, termios->c_cflag, baud);
2304
2305 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2306 if (termios->c_iflag & INPCK)
2307 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2308 if (termios->c_iflag & (BRKINT | PARMRK))
2309 port->read_status_mask |= UART_LSR_BI;
2310
2311 /*
2312 * Characteres to ignore
2313 */
2314 port->ignore_status_mask = 0;
2315 if (termios->c_iflag & IGNPAR)
2316 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2317 if (termios->c_iflag & IGNBRK) {
2318 port->ignore_status_mask |= UART_LSR_BI;
2319 /*
2320 * If we're ignoring parity and break indicators,
2321 * ignore overruns too (for real raw support).
2322 */
2323 if (termios->c_iflag & IGNPAR)
2324 port->ignore_status_mask |= UART_LSR_OE;
2325 }
2326
2327 /*
2328 * ignore all characters if CREAD is not set
2329 */
2330 if ((termios->c_cflag & CREAD) == 0)
2331 port->ignore_status_mask |= UART_LSR_DR;
2332
2333 /*
2334 * CTS flow control flag and modem status interrupts
2335 */
2336 up->ier &= ~UART_IER_MSI;
2337 if (!(up->bugs & UART_BUG_NOMSR) &&
2338 UART_ENABLE_MS(&up->port, termios->c_cflag))
2339 up->ier |= UART_IER_MSI;
2340 if (up->capabilities & UART_CAP_UUE)
2341 up->ier |= UART_IER_UUE;
2342 if (up->capabilities & UART_CAP_RTOIE)
2343 up->ier |= UART_IER_RTOIE;
2344
2345 serial_port_out(port, UART_IER, up->ier);
2346
2347 if (up->capabilities & UART_CAP_EFR) {
2348 unsigned char efr = 0;
2349 /*
2350 * TI16C752/Startech hardware flow control. FIXME:
2351 * - TI16C752 requires control thresholds to be set.
2352 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2353 */
2354 if (termios->c_cflag & CRTSCTS)
2355 efr |= UART_EFR_CTS;
2356
2357 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2358 if (port->flags & UPF_EXAR_EFR)
2359 serial_port_out(port, UART_XR_EFR, efr);
2360 else
2361 serial_port_out(port, UART_EFR, efr);
2362 }
2363
2364 #ifdef CONFIG_ARCH_OMAP
2365 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2366 if (cpu_is_omap1510() && is_omap_port(up)) {
2367 if (baud == 115200) {
2368 quot = 1;
2369 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2370 } else
2371 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2372 }
2373 #endif
2374
2375 /*
2376 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2377 * otherwise just set DLAB
2378 */
2379 if (up->capabilities & UART_NATSEMI)
2380 serial_port_out(port, UART_LCR, 0xe0);
2381 else
2382 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2383
2384 serial_dl_write(up, quot);
2385
2386 /*
2387 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2388 * is written without DLAB set, this mode will be disabled.
2389 */
2390 if (port->type == PORT_16750)
2391 serial_port_out(port, UART_FCR, fcr);
2392
2393 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
2394 up->lcr = cval; /* Save LCR */
2395 if (port->type != PORT_16750) {
2396 /* emulated UARTs (Lucent Venus 167x) need two steps */
2397 if (fcr & UART_FCR_ENABLE_FIFO)
2398 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2399 serial_port_out(port, UART_FCR, fcr); /* set fcr */
2400 }
2401 serial8250_set_mctrl(port, port->mctrl);
2402 spin_unlock_irqrestore(&port->lock, flags);
2403 /* Don't rewrite B0 */
2404 if (tty_termios_baud_rate(termios))
2405 tty_termios_encode_baud_rate(termios, baud, baud);
2406 }
2407 EXPORT_SYMBOL(serial8250_do_set_termios);
2408
2409 static void
2410 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2411 struct ktermios *old)
2412 {
2413 if (port->set_termios)
2414 port->set_termios(port, termios, old);
2415 else
2416 serial8250_do_set_termios(port, termios, old);
2417 }
2418
2419 static void
2420 serial8250_set_ldisc(struct uart_port *port, int new)
2421 {
2422 if (new == N_PPS) {
2423 port->flags |= UPF_HARDPPS_CD;
2424 serial8250_enable_ms(port);
2425 } else
2426 port->flags &= ~UPF_HARDPPS_CD;
2427 }
2428
2429
2430 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2431 unsigned int oldstate)
2432 {
2433 struct uart_8250_port *p =
2434 container_of(port, struct uart_8250_port, port);
2435
2436 serial8250_set_sleep(p, state != 0);
2437 }
2438 EXPORT_SYMBOL(serial8250_do_pm);
2439
2440 static void
2441 serial8250_pm(struct uart_port *port, unsigned int state,
2442 unsigned int oldstate)
2443 {
2444 if (port->pm)
2445 port->pm(port, state, oldstate);
2446 else
2447 serial8250_do_pm(port, state, oldstate);
2448 }
2449
2450 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2451 {
2452 if (pt->port.iotype == UPIO_AU)
2453 return 0x1000;
2454 #ifdef CONFIG_ARCH_OMAP
2455 if (is_omap_port(pt))
2456 return 0x16 << pt->port.regshift;
2457 #endif
2458 return 8 << pt->port.regshift;
2459 }
2460
2461 /*
2462 * Resource handling.
2463 */
2464 static int serial8250_request_std_resource(struct uart_8250_port *up)
2465 {
2466 unsigned int size = serial8250_port_size(up);
2467 struct uart_port *port = &up->port;
2468 int ret = 0;
2469
2470 switch (port->iotype) {
2471 case UPIO_AU:
2472 case UPIO_TSI:
2473 case UPIO_MEM32:
2474 case UPIO_MEM:
2475 if (!port->mapbase)
2476 break;
2477
2478 if (!request_mem_region(port->mapbase, size, "serial")) {
2479 ret = -EBUSY;
2480 break;
2481 }
2482
2483 if (port->flags & UPF_IOREMAP) {
2484 port->membase = ioremap_nocache(port->mapbase, size);
2485 if (!port->membase) {
2486 release_mem_region(port->mapbase, size);
2487 ret = -ENOMEM;
2488 }
2489 }
2490 break;
2491
2492 case UPIO_HUB6:
2493 case UPIO_PORT:
2494 if (!request_region(port->iobase, size, "serial"))
2495 ret = -EBUSY;
2496 break;
2497 }
2498 return ret;
2499 }
2500
2501 static void serial8250_release_std_resource(struct uart_8250_port *up)
2502 {
2503 unsigned int size = serial8250_port_size(up);
2504 struct uart_port *port = &up->port;
2505
2506 switch (port->iotype) {
2507 case UPIO_AU:
2508 case UPIO_TSI:
2509 case UPIO_MEM32:
2510 case UPIO_MEM:
2511 if (!port->mapbase)
2512 break;
2513
2514 if (port->flags & UPF_IOREMAP) {
2515 iounmap(port->membase);
2516 port->membase = NULL;
2517 }
2518
2519 release_mem_region(port->mapbase, size);
2520 break;
2521
2522 case UPIO_HUB6:
2523 case UPIO_PORT:
2524 release_region(port->iobase, size);
2525 break;
2526 }
2527 }
2528
2529 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2530 {
2531 unsigned long start = UART_RSA_BASE << up->port.regshift;
2532 unsigned int size = 8 << up->port.regshift;
2533 struct uart_port *port = &up->port;
2534 int ret = -EINVAL;
2535
2536 switch (port->iotype) {
2537 case UPIO_HUB6:
2538 case UPIO_PORT:
2539 start += port->iobase;
2540 if (request_region(start, size, "serial-rsa"))
2541 ret = 0;
2542 else
2543 ret = -EBUSY;
2544 break;
2545 }
2546
2547 return ret;
2548 }
2549
2550 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2551 {
2552 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2553 unsigned int size = 8 << up->port.regshift;
2554 struct uart_port *port = &up->port;
2555
2556 switch (port->iotype) {
2557 case UPIO_HUB6:
2558 case UPIO_PORT:
2559 release_region(port->iobase + offset, size);
2560 break;
2561 }
2562 }
2563
2564 static void serial8250_release_port(struct uart_port *port)
2565 {
2566 struct uart_8250_port *up =
2567 container_of(port, struct uart_8250_port, port);
2568
2569 serial8250_release_std_resource(up);
2570 if (port->type == PORT_RSA)
2571 serial8250_release_rsa_resource(up);
2572 }
2573
2574 static int serial8250_request_port(struct uart_port *port)
2575 {
2576 struct uart_8250_port *up =
2577 container_of(port, struct uart_8250_port, port);
2578 int ret = 0;
2579
2580 ret = serial8250_request_std_resource(up);
2581 if (ret == 0 && port->type == PORT_RSA) {
2582 ret = serial8250_request_rsa_resource(up);
2583 if (ret < 0)
2584 serial8250_release_std_resource(up);
2585 }
2586
2587 return ret;
2588 }
2589
2590 static void serial8250_config_port(struct uart_port *port, int flags)
2591 {
2592 struct uart_8250_port *up =
2593 container_of(port, struct uart_8250_port, port);
2594 int probeflags = PROBE_ANY;
2595 int ret;
2596
2597 /*
2598 * Find the region that we can probe for. This in turn
2599 * tells us whether we can probe for the type of port.
2600 */
2601 ret = serial8250_request_std_resource(up);
2602 if (ret < 0)
2603 return;
2604
2605 ret = serial8250_request_rsa_resource(up);
2606 if (ret < 0)
2607 probeflags &= ~PROBE_RSA;
2608
2609 if (port->iotype != up->cur_iotype)
2610 set_io_from_upio(port);
2611
2612 if (flags & UART_CONFIG_TYPE)
2613 autoconfig(up, probeflags);
2614
2615 /* if access method is AU, it is a 16550 with a quirk */
2616 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2617 up->bugs |= UART_BUG_NOMSR;
2618
2619 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2620 autoconfig_irq(up);
2621
2622 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2623 serial8250_release_rsa_resource(up);
2624 if (port->type == PORT_UNKNOWN)
2625 serial8250_release_std_resource(up);
2626 }
2627
2628 static int
2629 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2630 {
2631 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2632 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2633 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2634 ser->type == PORT_STARTECH)
2635 return -EINVAL;
2636 return 0;
2637 }
2638
2639 static const char *
2640 serial8250_type(struct uart_port *port)
2641 {
2642 int type = port->type;
2643
2644 if (type >= ARRAY_SIZE(uart_config))
2645 type = 0;
2646 return uart_config[type].name;
2647 }
2648
2649 static struct uart_ops serial8250_pops = {
2650 .tx_empty = serial8250_tx_empty,
2651 .set_mctrl = serial8250_set_mctrl,
2652 .get_mctrl = serial8250_get_mctrl,
2653 .stop_tx = serial8250_stop_tx,
2654 .start_tx = serial8250_start_tx,
2655 .stop_rx = serial8250_stop_rx,
2656 .enable_ms = serial8250_enable_ms,
2657 .break_ctl = serial8250_break_ctl,
2658 .startup = serial8250_startup,
2659 .shutdown = serial8250_shutdown,
2660 .set_termios = serial8250_set_termios,
2661 .set_ldisc = serial8250_set_ldisc,
2662 .pm = serial8250_pm,
2663 .type = serial8250_type,
2664 .release_port = serial8250_release_port,
2665 .request_port = serial8250_request_port,
2666 .config_port = serial8250_config_port,
2667 .verify_port = serial8250_verify_port,
2668 #ifdef CONFIG_CONSOLE_POLL
2669 .poll_get_char = serial8250_get_poll_char,
2670 .poll_put_char = serial8250_put_poll_char,
2671 #endif
2672 };
2673
2674 static struct uart_8250_port serial8250_ports[UART_NR];
2675
2676 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2677 unsigned short *capabilities);
2678
2679 void serial8250_set_isa_configurator(
2680 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2681 {
2682 serial8250_isa_config = v;
2683 }
2684 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2685
2686 static void __init serial8250_isa_init_ports(void)
2687 {
2688 struct uart_8250_port *up;
2689 static int first = 1;
2690 int i, irqflag = 0;
2691
2692 if (!first)
2693 return;
2694 first = 0;
2695
2696 for (i = 0; i < nr_uarts; i++) {
2697 struct uart_8250_port *up = &serial8250_ports[i];
2698 struct uart_port *port = &up->port;
2699
2700 port->line = i;
2701 spin_lock_init(&port->lock);
2702
2703 init_timer(&up->timer);
2704 up->timer.function = serial8250_timeout;
2705
2706 /*
2707 * ALPHA_KLUDGE_MCR needs to be killed.
2708 */
2709 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2710 up->mcr_force = ALPHA_KLUDGE_MCR;
2711
2712 port->ops = &serial8250_pops;
2713 }
2714
2715 if (share_irqs)
2716 irqflag = IRQF_SHARED;
2717
2718 for (i = 0, up = serial8250_ports;
2719 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2720 i++, up++) {
2721 struct uart_port *port = &up->port;
2722
2723 port->iobase = old_serial_port[i].port;
2724 port->irq = irq_canonicalize(old_serial_port[i].irq);
2725 port->irqflags = old_serial_port[i].irqflags;
2726 port->uartclk = old_serial_port[i].baud_base * 16;
2727 port->flags = old_serial_port[i].flags;
2728 port->hub6 = old_serial_port[i].hub6;
2729 port->membase = old_serial_port[i].iomem_base;
2730 port->iotype = old_serial_port[i].io_type;
2731 port->regshift = old_serial_port[i].iomem_reg_shift;
2732 set_io_from_upio(port);
2733 port->irqflags |= irqflag;
2734 if (serial8250_isa_config != NULL)
2735 serial8250_isa_config(i, &up->port, &up->capabilities);
2736
2737 }
2738 }
2739
2740 static void
2741 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2742 {
2743 up->port.type = type;
2744 up->port.fifosize = uart_config[type].fifo_size;
2745 up->capabilities = uart_config[type].flags;
2746 up->tx_loadsz = uart_config[type].tx_loadsz;
2747 }
2748
2749 static void __init
2750 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2751 {
2752 int i;
2753
2754 for (i = 0; i < nr_uarts; i++) {
2755 struct uart_8250_port *up = &serial8250_ports[i];
2756 up->cur_iotype = 0xFF;
2757 }
2758
2759 serial8250_isa_init_ports();
2760
2761 for (i = 0; i < nr_uarts; i++) {
2762 struct uart_8250_port *up = &serial8250_ports[i];
2763
2764 up->port.dev = dev;
2765
2766 if (up->port.flags & UPF_FIXED_TYPE)
2767 serial8250_init_fixed_type_port(up, up->port.type);
2768
2769 uart_add_one_port(drv, &up->port);
2770 }
2771 }
2772
2773 #ifdef CONFIG_SERIAL_8250_CONSOLE
2774
2775 static void serial8250_console_putchar(struct uart_port *port, int ch)
2776 {
2777 struct uart_8250_port *up =
2778 container_of(port, struct uart_8250_port, port);
2779
2780 wait_for_xmitr(up, UART_LSR_THRE);
2781 serial_port_out(port, UART_TX, ch);
2782 }
2783
2784 /*
2785 * Print a string to the serial port trying not to disturb
2786 * any possible real use of the port...
2787 *
2788 * The console_lock must be held when we get here.
2789 */
2790 static void
2791 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2792 {
2793 struct uart_8250_port *up = &serial8250_ports[co->index];
2794 struct uart_port *port = &up->port;
2795 unsigned long flags;
2796 unsigned int ier;
2797 int locked = 1;
2798
2799 touch_nmi_watchdog();
2800
2801 local_irq_save(flags);
2802 if (port->sysrq) {
2803 /* serial8250_handle_irq() already took the lock */
2804 locked = 0;
2805 } else if (oops_in_progress) {
2806 locked = spin_trylock(&port->lock);
2807 } else
2808 spin_lock(&port->lock);
2809
2810 /*
2811 * First save the IER then disable the interrupts
2812 */
2813 ier = serial_port_in(port, UART_IER);
2814
2815 if (up->capabilities & UART_CAP_UUE)
2816 serial_port_out(port, UART_IER, UART_IER_UUE);
2817 else
2818 serial_port_out(port, UART_IER, 0);
2819
2820 uart_console_write(port, s, count, serial8250_console_putchar);
2821
2822 /*
2823 * Finally, wait for transmitter to become empty
2824 * and restore the IER
2825 */
2826 wait_for_xmitr(up, BOTH_EMPTY);
2827 serial_port_out(port, UART_IER, ier);
2828
2829 /*
2830 * The receive handling will happen properly because the
2831 * receive ready bit will still be set; it is not cleared
2832 * on read. However, modem control will not, we must
2833 * call it if we have saved something in the saved flags
2834 * while processing with interrupts off.
2835 */
2836 if (up->msr_saved_flags)
2837 serial8250_modem_status(up);
2838
2839 if (locked)
2840 spin_unlock(&port->lock);
2841 local_irq_restore(flags);
2842 }
2843
2844 static int __init serial8250_console_setup(struct console *co, char *options)
2845 {
2846 struct uart_port *port;
2847 int baud = 9600;
2848 int bits = 8;
2849 int parity = 'n';
2850 int flow = 'n';
2851
2852 /*
2853 * Check whether an invalid uart number has been specified, and
2854 * if so, search for the first available port that does have
2855 * console support.
2856 */
2857 if (co->index >= nr_uarts)
2858 co->index = 0;
2859 port = &serial8250_ports[co->index].port;
2860 if (!port->iobase && !port->membase)
2861 return -ENODEV;
2862
2863 if (options)
2864 uart_parse_options(options, &baud, &parity, &bits, &flow);
2865
2866 return uart_set_options(port, co, baud, parity, bits, flow);
2867 }
2868
2869 static int serial8250_console_early_setup(void)
2870 {
2871 return serial8250_find_port_for_earlycon();
2872 }
2873
2874 static struct console serial8250_console = {
2875 .name = "ttyS",
2876 .write = serial8250_console_write,
2877 .device = uart_console_device,
2878 .setup = serial8250_console_setup,
2879 .early_setup = serial8250_console_early_setup,
2880 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2881 .index = -1,
2882 .data = &serial8250_reg,
2883 };
2884
2885 static int __init serial8250_console_init(void)
2886 {
2887 if (nr_uarts > UART_NR)
2888 nr_uarts = UART_NR;
2889
2890 serial8250_isa_init_ports();
2891 register_console(&serial8250_console);
2892 return 0;
2893 }
2894 console_initcall(serial8250_console_init);
2895
2896 int serial8250_find_port(struct uart_port *p)
2897 {
2898 int line;
2899 struct uart_port *port;
2900
2901 for (line = 0; line < nr_uarts; line++) {
2902 port = &serial8250_ports[line].port;
2903 if (uart_match_port(p, port))
2904 return line;
2905 }
2906 return -ENODEV;
2907 }
2908
2909 #define SERIAL8250_CONSOLE &serial8250_console
2910 #else
2911 #define SERIAL8250_CONSOLE NULL
2912 #endif
2913
2914 static struct uart_driver serial8250_reg = {
2915 .owner = THIS_MODULE,
2916 .driver_name = "serial",
2917 .dev_name = "ttyS",
2918 .major = TTY_MAJOR,
2919 .minor = 64,
2920 .cons = SERIAL8250_CONSOLE,
2921 };
2922
2923 /*
2924 * early_serial_setup - early registration for 8250 ports
2925 *
2926 * Setup an 8250 port structure prior to console initialisation. Use
2927 * after console initialisation will cause undefined behaviour.
2928 */
2929 int __init early_serial_setup(struct uart_port *port)
2930 {
2931 struct uart_port *p;
2932
2933 if (port->line >= ARRAY_SIZE(serial8250_ports))
2934 return -ENODEV;
2935
2936 serial8250_isa_init_ports();
2937 p = &serial8250_ports[port->line].port;
2938 p->iobase = port->iobase;
2939 p->membase = port->membase;
2940 p->irq = port->irq;
2941 p->irqflags = port->irqflags;
2942 p->uartclk = port->uartclk;
2943 p->fifosize = port->fifosize;
2944 p->regshift = port->regshift;
2945 p->iotype = port->iotype;
2946 p->flags = port->flags;
2947 p->mapbase = port->mapbase;
2948 p->private_data = port->private_data;
2949 p->type = port->type;
2950 p->line = port->line;
2951
2952 set_io_from_upio(p);
2953 if (port->serial_in)
2954 p->serial_in = port->serial_in;
2955 if (port->serial_out)
2956 p->serial_out = port->serial_out;
2957 if (port->handle_irq)
2958 p->handle_irq = port->handle_irq;
2959 else
2960 p->handle_irq = serial8250_default_handle_irq;
2961
2962 return 0;
2963 }
2964
2965 /**
2966 * serial8250_suspend_port - suspend one serial port
2967 * @line: serial line number
2968 *
2969 * Suspend one serial port.
2970 */
2971 void serial8250_suspend_port(int line)
2972 {
2973 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2974 }
2975
2976 /**
2977 * serial8250_resume_port - resume one serial port
2978 * @line: serial line number
2979 *
2980 * Resume one serial port.
2981 */
2982 void serial8250_resume_port(int line)
2983 {
2984 struct uart_8250_port *up = &serial8250_ports[line];
2985 struct uart_port *port = &up->port;
2986
2987 if (up->capabilities & UART_NATSEMI) {
2988 /* Ensure it's still in high speed mode */
2989 serial_port_out(port, UART_LCR, 0xE0);
2990
2991 ns16550a_goto_highspeed(up);
2992
2993 serial_port_out(port, UART_LCR, 0);
2994 port->uartclk = 921600*16;
2995 }
2996 uart_resume_port(&serial8250_reg, port);
2997 }
2998
2999 /*
3000 * Register a set of serial devices attached to a platform device. The
3001 * list is terminated with a zero flags entry, which means we expect
3002 * all entries to have at least UPF_BOOT_AUTOCONF set.
3003 */
3004 static int __devinit serial8250_probe(struct platform_device *dev)
3005 {
3006 struct plat_serial8250_port *p = dev->dev.platform_data;
3007 struct uart_port port;
3008 int ret, i, irqflag = 0;
3009
3010 memset(&port, 0, sizeof(struct uart_port));
3011
3012 if (share_irqs)
3013 irqflag = IRQF_SHARED;
3014
3015 for (i = 0; p && p->flags != 0; p++, i++) {
3016 port.iobase = p->iobase;
3017 port.membase = p->membase;
3018 port.irq = p->irq;
3019 port.irqflags = p->irqflags;
3020 port.uartclk = p->uartclk;
3021 port.regshift = p->regshift;
3022 port.iotype = p->iotype;
3023 port.flags = p->flags;
3024 port.mapbase = p->mapbase;
3025 port.hub6 = p->hub6;
3026 port.private_data = p->private_data;
3027 port.type = p->type;
3028 port.serial_in = p->serial_in;
3029 port.serial_out = p->serial_out;
3030 port.handle_irq = p->handle_irq;
3031 port.handle_break = p->handle_break;
3032 port.set_termios = p->set_termios;
3033 port.pm = p->pm;
3034 port.dev = &dev->dev;
3035 port.irqflags |= irqflag;
3036 ret = serial8250_register_port(&port);
3037 if (ret < 0) {
3038 dev_err(&dev->dev, "unable to register port at index %d "
3039 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3040 p->iobase, (unsigned long long)p->mapbase,
3041 p->irq, ret);
3042 }
3043 }
3044 return 0;
3045 }
3046
3047 /*
3048 * Remove serial ports registered against a platform device.
3049 */
3050 static int __devexit serial8250_remove(struct platform_device *dev)
3051 {
3052 int i;
3053
3054 for (i = 0; i < nr_uarts; i++) {
3055 struct uart_8250_port *up = &serial8250_ports[i];
3056
3057 if (up->port.dev == &dev->dev)
3058 serial8250_unregister_port(i);
3059 }
3060 return 0;
3061 }
3062
3063 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3064 {
3065 int i;
3066
3067 for (i = 0; i < UART_NR; i++) {
3068 struct uart_8250_port *up = &serial8250_ports[i];
3069
3070 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3071 uart_suspend_port(&serial8250_reg, &up->port);
3072 }
3073
3074 return 0;
3075 }
3076
3077 static int serial8250_resume(struct platform_device *dev)
3078 {
3079 int i;
3080
3081 for (i = 0; i < UART_NR; i++) {
3082 struct uart_8250_port *up = &serial8250_ports[i];
3083
3084 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3085 serial8250_resume_port(i);
3086 }
3087
3088 return 0;
3089 }
3090
3091 static struct platform_driver serial8250_isa_driver = {
3092 .probe = serial8250_probe,
3093 .remove = __devexit_p(serial8250_remove),
3094 .suspend = serial8250_suspend,
3095 .resume = serial8250_resume,
3096 .driver = {
3097 .name = "serial8250",
3098 .owner = THIS_MODULE,
3099 },
3100 };
3101
3102 /*
3103 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3104 * in the table in include/asm/serial.h
3105 */
3106 static struct platform_device *serial8250_isa_devs;
3107
3108 /*
3109 * serial8250_register_port and serial8250_unregister_port allows for
3110 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3111 * modems and PCI multiport cards.
3112 */
3113 static DEFINE_MUTEX(serial_mutex);
3114
3115 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3116 {
3117 int i;
3118
3119 /*
3120 * First, find a port entry which matches.
3121 */
3122 for (i = 0; i < nr_uarts; i++)
3123 if (uart_match_port(&serial8250_ports[i].port, port))
3124 return &serial8250_ports[i];
3125
3126 /*
3127 * We didn't find a matching entry, so look for the first
3128 * free entry. We look for one which hasn't been previously
3129 * used (indicated by zero iobase).
3130 */
3131 for (i = 0; i < nr_uarts; i++)
3132 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3133 serial8250_ports[i].port.iobase == 0)
3134 return &serial8250_ports[i];
3135
3136 /*
3137 * That also failed. Last resort is to find any entry which
3138 * doesn't have a real port associated with it.
3139 */
3140 for (i = 0; i < nr_uarts; i++)
3141 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3142 return &serial8250_ports[i];
3143
3144 return NULL;
3145 }
3146
3147 /**
3148 * serial8250_register_port - register a serial port
3149 * @port: serial port template
3150 *
3151 * Configure the serial port specified by the request. If the
3152 * port exists and is in use, it is hung up and unregistered
3153 * first.
3154 *
3155 * The port is then probed and if necessary the IRQ is autodetected
3156 * If this fails an error is returned.
3157 *
3158 * On success the port is ready to use and the line number is returned.
3159 */
3160 int serial8250_register_port(struct uart_port *port)
3161 {
3162 struct uart_8250_port *uart;
3163 int ret = -ENOSPC;
3164
3165 if (port->uartclk == 0)
3166 return -EINVAL;
3167
3168 mutex_lock(&serial_mutex);
3169
3170 uart = serial8250_find_match_or_unused(port);
3171 if (uart) {
3172 uart_remove_one_port(&serial8250_reg, &uart->port);
3173
3174 uart->port.iobase = port->iobase;
3175 uart->port.membase = port->membase;
3176 uart->port.irq = port->irq;
3177 uart->port.irqflags = port->irqflags;
3178 uart->port.uartclk = port->uartclk;
3179 uart->port.fifosize = port->fifosize;
3180 uart->port.regshift = port->regshift;
3181 uart->port.iotype = port->iotype;
3182 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3183 uart->port.mapbase = port->mapbase;
3184 uart->port.private_data = port->private_data;
3185 if (port->dev)
3186 uart->port.dev = port->dev;
3187
3188 if (port->flags & UPF_FIXED_TYPE)
3189 serial8250_init_fixed_type_port(uart, port->type);
3190
3191 set_io_from_upio(&uart->port);
3192 /* Possibly override default I/O functions. */
3193 if (port->serial_in)
3194 uart->port.serial_in = port->serial_in;
3195 if (port->serial_out)
3196 uart->port.serial_out = port->serial_out;
3197 if (port->handle_irq)
3198 uart->port.handle_irq = port->handle_irq;
3199 /* Possibly override set_termios call */
3200 if (port->set_termios)
3201 uart->port.set_termios = port->set_termios;
3202 if (port->pm)
3203 uart->port.pm = port->pm;
3204 if (port->handle_break)
3205 uart->port.handle_break = port->handle_break;
3206
3207 if (serial8250_isa_config != NULL)
3208 serial8250_isa_config(0, &uart->port,
3209 &uart->capabilities);
3210
3211 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3212 if (ret == 0)
3213 ret = uart->port.line;
3214 }
3215 mutex_unlock(&serial_mutex);
3216
3217 return ret;
3218 }
3219 EXPORT_SYMBOL(serial8250_register_port);
3220
3221 /**
3222 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3223 * @line: serial line number
3224 *
3225 * Remove one serial port. This may not be called from interrupt
3226 * context. We hand the port back to the our control.
3227 */
3228 void serial8250_unregister_port(int line)
3229 {
3230 struct uart_8250_port *uart = &serial8250_ports[line];
3231
3232 mutex_lock(&serial_mutex);
3233 uart_remove_one_port(&serial8250_reg, &uart->port);
3234 if (serial8250_isa_devs) {
3235 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3236 uart->port.type = PORT_UNKNOWN;
3237 uart->port.dev = &serial8250_isa_devs->dev;
3238 uart->capabilities = uart_config[uart->port.type].flags;
3239 uart_add_one_port(&serial8250_reg, &uart->port);
3240 } else {
3241 uart->port.dev = NULL;
3242 }
3243 mutex_unlock(&serial_mutex);
3244 }
3245 EXPORT_SYMBOL(serial8250_unregister_port);
3246
3247 static int __init serial8250_init(void)
3248 {
3249 int ret;
3250
3251 if (nr_uarts > UART_NR)
3252 nr_uarts = UART_NR;
3253
3254 printk(KERN_INFO "Serial: 8250/16550 driver, "
3255 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3256 share_irqs ? "en" : "dis");
3257
3258 #ifdef CONFIG_SPARC
3259 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3260 #else
3261 serial8250_reg.nr = UART_NR;
3262 ret = uart_register_driver(&serial8250_reg);
3263 #endif
3264 if (ret)
3265 goto out;
3266
3267 serial8250_isa_devs = platform_device_alloc("serial8250",
3268 PLAT8250_DEV_LEGACY);
3269 if (!serial8250_isa_devs) {
3270 ret = -ENOMEM;
3271 goto unreg_uart_drv;
3272 }
3273
3274 ret = platform_device_add(serial8250_isa_devs);
3275 if (ret)
3276 goto put_dev;
3277
3278 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3279
3280 ret = platform_driver_register(&serial8250_isa_driver);
3281 if (ret == 0)
3282 goto out;
3283
3284 platform_device_del(serial8250_isa_devs);
3285 put_dev:
3286 platform_device_put(serial8250_isa_devs);
3287 unreg_uart_drv:
3288 #ifdef CONFIG_SPARC
3289 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3290 #else
3291 uart_unregister_driver(&serial8250_reg);
3292 #endif
3293 out:
3294 return ret;
3295 }
3296
3297 static void __exit serial8250_exit(void)
3298 {
3299 struct platform_device *isa_dev = serial8250_isa_devs;
3300
3301 /*
3302 * This tells serial8250_unregister_port() not to re-register
3303 * the ports (thereby making serial8250_isa_driver permanently
3304 * in use.)
3305 */
3306 serial8250_isa_devs = NULL;
3307
3308 platform_driver_unregister(&serial8250_isa_driver);
3309 platform_device_unregister(isa_dev);
3310
3311 #ifdef CONFIG_SPARC
3312 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3313 #else
3314 uart_unregister_driver(&serial8250_reg);
3315 #endif
3316 }
3317
3318 module_init(serial8250_init);
3319 module_exit(serial8250_exit);
3320
3321 EXPORT_SYMBOL(serial8250_suspend_port);
3322 EXPORT_SYMBOL(serial8250_resume_port);
3323
3324 MODULE_LICENSE("GPL");
3325 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3326
3327 module_param(share_irqs, uint, 0644);
3328 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3329 " (unsafe)");
3330
3331 module_param(nr_uarts, uint, 0644);
3332 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3333
3334 module_param(skip_txen_test, uint, 0644);
3335 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3336
3337 #ifdef CONFIG_SERIAL_8250_RSA
3338 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3339 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3340 #endif
3341 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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