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ASoC: wm_adsp: Add support for rev 2 firmware file format
[linux-2.6/btrfs-unstable.git] / sound / soc / codecs / wm_adsp.c
blob1c45d67cfb4f6da9fa9fbb325e99b4633526c5f5
1 /*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/list.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/workqueue.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/jack.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33
34 #include <linux/mfd/arizona/registers.h>
35
36 #include "arizona.h"
37 #include "wm_adsp.h"
38
39 #define adsp_crit(_dsp, fmt, ...) \
40 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41 #define adsp_err(_dsp, fmt, ...) \
42 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43 #define adsp_warn(_dsp, fmt, ...) \
44 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45 #define adsp_info(_dsp, fmt, ...) \
46 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
47 #define adsp_dbg(_dsp, fmt, ...) \
48 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
49
50 #define ADSP1_CONTROL_1 0x00
51 #define ADSP1_CONTROL_2 0x02
52 #define ADSP1_CONTROL_3 0x03
53 #define ADSP1_CONTROL_4 0x04
54 #define ADSP1_CONTROL_5 0x06
55 #define ADSP1_CONTROL_6 0x07
56 #define ADSP1_CONTROL_7 0x08
57 #define ADSP1_CONTROL_8 0x09
58 #define ADSP1_CONTROL_9 0x0A
59 #define ADSP1_CONTROL_10 0x0B
60 #define ADSP1_CONTROL_11 0x0C
61 #define ADSP1_CONTROL_12 0x0D
62 #define ADSP1_CONTROL_13 0x0F
63 #define ADSP1_CONTROL_14 0x10
64 #define ADSP1_CONTROL_15 0x11
65 #define ADSP1_CONTROL_16 0x12
66 #define ADSP1_CONTROL_17 0x13
67 #define ADSP1_CONTROL_18 0x14
68 #define ADSP1_CONTROL_19 0x16
69 #define ADSP1_CONTROL_20 0x17
70 #define ADSP1_CONTROL_21 0x18
71 #define ADSP1_CONTROL_22 0x1A
72 #define ADSP1_CONTROL_23 0x1B
73 #define ADSP1_CONTROL_24 0x1C
74 #define ADSP1_CONTROL_25 0x1E
75 #define ADSP1_CONTROL_26 0x20
76 #define ADSP1_CONTROL_27 0x21
77 #define ADSP1_CONTROL_28 0x22
78 #define ADSP1_CONTROL_29 0x23
79 #define ADSP1_CONTROL_30 0x24
80 #define ADSP1_CONTROL_31 0x26
81
82 /*
83 * ADSP1 Control 19
84 */
85 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
88
89
90 /*
91 * ADSP1 Control 30
92 */
93 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
94 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
95 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
96 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
97 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
98 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
99 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
100 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
101 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
102 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
103 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
104 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
105 #define ADSP1_START 0x0001 /* DSP1_START */
106 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
107 #define ADSP1_START_SHIFT 0 /* DSP1_START */
108 #define ADSP1_START_WIDTH 1 /* DSP1_START */
109
110 /*
111 * ADSP1 Control 31
112 */
113 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
114 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
115 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
116
117 #define ADSP2_CONTROL 0x0
118 #define ADSP2_CLOCKING 0x1
119 #define ADSP2_STATUS1 0x4
120 #define ADSP2_WDMA_CONFIG_1 0x30
121 #define ADSP2_WDMA_CONFIG_2 0x31
122 #define ADSP2_RDMA_CONFIG_1 0x34
123
124 /*
125 * ADSP2 Control
126 */
127
128 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
129 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
130 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
131 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
132 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
133 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
134 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
135 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
136 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
137 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
138 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
139 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
140 #define ADSP2_START 0x0001 /* DSP1_START */
141 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
142 #define ADSP2_START_SHIFT 0 /* DSP1_START */
143 #define ADSP2_START_WIDTH 1 /* DSP1_START */
144
145 /*
146 * ADSP2 clocking
147 */
148 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
149 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
150 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
151
152 /*
153 * ADSP2 Status 1
154 */
155 #define ADSP2_RAM_RDY 0x0001
156 #define ADSP2_RAM_RDY_MASK 0x0001
157 #define ADSP2_RAM_RDY_SHIFT 0
158 #define ADSP2_RAM_RDY_WIDTH 1
159
160 struct wm_adsp_buf {
161 struct list_head list;
162 void *buf;
163 };
164
165 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
166 struct list_head *list)
167 {
168 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
169
170 if (buf == NULL)
171 return NULL;
172
173 buf->buf = vmalloc(len);
174 if (!buf->buf) {
175 vfree(buf);
176 return NULL;
177 }
178 memcpy(buf->buf, src, len);
179
180 if (list)
181 list_add_tail(&buf->list, list);
182
183 return buf;
184 }
185
186 static void wm_adsp_buf_free(struct list_head *list)
187 {
188 while (!list_empty(list)) {
189 struct wm_adsp_buf *buf = list_first_entry(list,
190 struct wm_adsp_buf,
191 list);
192 list_del(&buf->list);
193 vfree(buf->buf);
194 kfree(buf);
195 }
196 }
197
198 #define WM_ADSP_NUM_FW 4
199
200 #define WM_ADSP_FW_MBC_VSS 0
201 #define WM_ADSP_FW_TX 1
202 #define WM_ADSP_FW_TX_SPK 2
203 #define WM_ADSP_FW_RX_ANC 3
204
205 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
206 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
207 [WM_ADSP_FW_TX] = "Tx",
208 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
209 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
210 };
211
212 static struct {
213 const char *file;
214 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
215 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
216 [WM_ADSP_FW_TX] = { .file = "tx" },
217 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
218 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
219 };
220
221 struct wm_coeff_ctl_ops {
222 int (*xget)(struct snd_kcontrol *kcontrol,
223 struct snd_ctl_elem_value *ucontrol);
224 int (*xput)(struct snd_kcontrol *kcontrol,
225 struct snd_ctl_elem_value *ucontrol);
226 int (*xinfo)(struct snd_kcontrol *kcontrol,
227 struct snd_ctl_elem_info *uinfo);
228 };
229
230 struct wm_coeff_ctl {
231 const char *name;
232 const char *fw_name;
233 struct wm_adsp_alg_region alg_region;
234 struct wm_coeff_ctl_ops ops;
235 struct wm_adsp *dsp;
236 unsigned int enabled:1;
237 struct list_head list;
238 void *cache;
239 unsigned int offset;
240 size_t len;
241 unsigned int set:1;
242 struct snd_kcontrol *kcontrol;
243 };
244
245 static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
246 struct snd_ctl_elem_value *ucontrol)
247 {
248 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
249 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
250 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
251
252 ucontrol->value.integer.value[0] = dsp[e->shift_l].fw;
253
254 return 0;
255 }
256
257 static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
258 struct snd_ctl_elem_value *ucontrol)
259 {
260 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
261 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
262 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
263
264 if (ucontrol->value.integer.value[0] == dsp[e->shift_l].fw)
265 return 0;
266
267 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
268 return -EINVAL;
269
270 if (dsp[e->shift_l].running)
271 return -EBUSY;
272
273 dsp[e->shift_l].fw = ucontrol->value.integer.value[0];
274
275 return 0;
276 }
277
278 static const struct soc_enum wm_adsp_fw_enum[] = {
279 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
280 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
281 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
282 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
283 };
284
285 const struct snd_kcontrol_new wm_adsp1_fw_controls[] = {
286 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
287 wm_adsp_fw_get, wm_adsp_fw_put),
288 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
289 wm_adsp_fw_get, wm_adsp_fw_put),
290 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
291 wm_adsp_fw_get, wm_adsp_fw_put),
292 };
293 EXPORT_SYMBOL_GPL(wm_adsp1_fw_controls);
294
295 #if IS_ENABLED(CONFIG_SND_SOC_ARIZONA)
296 static const struct soc_enum wm_adsp2_rate_enum[] = {
297 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
298 ARIZONA_DSP1_RATE_SHIFT, 0xf,
299 ARIZONA_RATE_ENUM_SIZE,
300 arizona_rate_text, arizona_rate_val),
301 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
302 ARIZONA_DSP1_RATE_SHIFT, 0xf,
303 ARIZONA_RATE_ENUM_SIZE,
304 arizona_rate_text, arizona_rate_val),
305 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
306 ARIZONA_DSP1_RATE_SHIFT, 0xf,
307 ARIZONA_RATE_ENUM_SIZE,
308 arizona_rate_text, arizona_rate_val),
309 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
310 ARIZONA_DSP1_RATE_SHIFT, 0xf,
311 ARIZONA_RATE_ENUM_SIZE,
312 arizona_rate_text, arizona_rate_val),
313 };
314
315 const struct snd_kcontrol_new wm_adsp2_fw_controls[] = {
316 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
317 wm_adsp_fw_get, wm_adsp_fw_put),
318 SOC_ENUM("DSP1 Rate", wm_adsp2_rate_enum[0]),
319 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
320 wm_adsp_fw_get, wm_adsp_fw_put),
321 SOC_ENUM("DSP2 Rate", wm_adsp2_rate_enum[1]),
322 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
323 wm_adsp_fw_get, wm_adsp_fw_put),
324 SOC_ENUM("DSP3 Rate", wm_adsp2_rate_enum[2]),
325 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
326 wm_adsp_fw_get, wm_adsp_fw_put),
327 SOC_ENUM("DSP4 Rate", wm_adsp2_rate_enum[3]),
328 };
329 EXPORT_SYMBOL_GPL(wm_adsp2_fw_controls);
330 #endif
331
332 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
333 int type)
334 {
335 int i;
336
337 for (i = 0; i < dsp->num_mems; i++)
338 if (dsp->mem[i].type == type)
339 return &dsp->mem[i];
340
341 return NULL;
342 }
343
344 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
345 unsigned int offset)
346 {
347 if (WARN_ON(!mem))
348 return offset;
349 switch (mem->type) {
350 case WMFW_ADSP1_PM:
351 return mem->base + (offset * 3);
352 case WMFW_ADSP1_DM:
353 return mem->base + (offset * 2);
354 case WMFW_ADSP2_XM:
355 return mem->base + (offset * 2);
356 case WMFW_ADSP2_YM:
357 return mem->base + (offset * 2);
358 case WMFW_ADSP1_ZM:
359 return mem->base + (offset * 2);
360 default:
361 WARN(1, "Unknown memory region type");
362 return offset;
363 }
364 }
365
366 static int wm_coeff_info(struct snd_kcontrol *kcontrol,
367 struct snd_ctl_elem_info *uinfo)
368 {
369 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
370
371 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
372 uinfo->count = ctl->len;
373 return 0;
374 }
375
376 static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
377 const void *buf, size_t len)
378 {
379 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
380 const struct wm_adsp_region *mem;
381 struct wm_adsp *dsp = ctl->dsp;
382 void *scratch;
383 int ret;
384 unsigned int reg;
385
386 mem = wm_adsp_find_region(dsp, alg_region->type);
387 if (!mem) {
388 adsp_err(dsp, "No base for region %x\n",
389 alg_region->type);
390 return -EINVAL;
391 }
392
393 reg = ctl->alg_region.base + ctl->offset;
394 reg = wm_adsp_region_to_reg(mem, reg);
395
396 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
397 if (!scratch)
398 return -ENOMEM;
399
400 ret = regmap_raw_write(dsp->regmap, reg, scratch,
401 ctl->len);
402 if (ret) {
403 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
404 ctl->len, reg, ret);
405 kfree(scratch);
406 return ret;
407 }
408 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", ctl->len, reg);
409
410 kfree(scratch);
411
412 return 0;
413 }
414
415 static int wm_coeff_put(struct snd_kcontrol *kcontrol,
416 struct snd_ctl_elem_value *ucontrol)
417 {
418 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
419 char *p = ucontrol->value.bytes.data;
420
421 memcpy(ctl->cache, p, ctl->len);
422
423 ctl->set = 1;
424 if (!ctl->enabled)
425 return 0;
426
427 return wm_coeff_write_control(ctl, p, ctl->len);
428 }
429
430 static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
431 void *buf, size_t len)
432 {
433 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
434 const struct wm_adsp_region *mem;
435 struct wm_adsp *dsp = ctl->dsp;
436 void *scratch;
437 int ret;
438 unsigned int reg;
439
440 mem = wm_adsp_find_region(dsp, alg_region->type);
441 if (!mem) {
442 adsp_err(dsp, "No base for region %x\n",
443 alg_region->type);
444 return -EINVAL;
445 }
446
447 reg = ctl->alg_region.base + ctl->offset;
448 reg = wm_adsp_region_to_reg(mem, reg);
449
450 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
451 if (!scratch)
452 return -ENOMEM;
453
454 ret = regmap_raw_read(dsp->regmap, reg, scratch, ctl->len);
455 if (ret) {
456 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
457 ctl->len, reg, ret);
458 kfree(scratch);
459 return ret;
460 }
461 adsp_dbg(dsp, "Read %zu bytes from %x\n", ctl->len, reg);
462
463 memcpy(buf, scratch, ctl->len);
464 kfree(scratch);
465
466 return 0;
467 }
468
469 static int wm_coeff_get(struct snd_kcontrol *kcontrol,
470 struct snd_ctl_elem_value *ucontrol)
471 {
472 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
473 char *p = ucontrol->value.bytes.data;
474
475 memcpy(p, ctl->cache, ctl->len);
476 return 0;
477 }
478
479 struct wmfw_ctl_work {
480 struct wm_adsp *dsp;
481 struct wm_coeff_ctl *ctl;
482 struct work_struct work;
483 };
484
485 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
486 {
487 struct snd_kcontrol_new *kcontrol;
488 int ret;
489
490 if (!ctl || !ctl->name)
491 return -EINVAL;
492
493 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
494 if (!kcontrol)
495 return -ENOMEM;
496 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
497
498 kcontrol->name = ctl->name;
499 kcontrol->info = wm_coeff_info;
500 kcontrol->get = wm_coeff_get;
501 kcontrol->put = wm_coeff_put;
502 kcontrol->private_value = (unsigned long)ctl;
503
504 ret = snd_soc_add_card_controls(dsp->card,
505 kcontrol, 1);
506 if (ret < 0)
507 goto err_kcontrol;
508
509 kfree(kcontrol);
510
511 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card,
512 ctl->name);
513
514 return 0;
515
516 err_kcontrol:
517 kfree(kcontrol);
518 return ret;
519 }
520
521 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
522 {
523 struct wm_coeff_ctl *ctl;
524 int ret;
525
526 list_for_each_entry(ctl, &dsp->ctl_list, list) {
527 if (!ctl->enabled || ctl->set)
528 continue;
529 ret = wm_coeff_read_control(ctl,
530 ctl->cache,
531 ctl->len);
532 if (ret < 0)
533 return ret;
534 }
535
536 return 0;
537 }
538
539 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
540 {
541 struct wm_coeff_ctl *ctl;
542 int ret;
543
544 list_for_each_entry(ctl, &dsp->ctl_list, list) {
545 if (!ctl->enabled)
546 continue;
547 if (ctl->set) {
548 ret = wm_coeff_write_control(ctl,
549 ctl->cache,
550 ctl->len);
551 if (ret < 0)
552 return ret;
553 }
554 }
555
556 return 0;
557 }
558
559 static void wm_adsp_ctl_work(struct work_struct *work)
560 {
561 struct wmfw_ctl_work *ctl_work = container_of(work,
562 struct wmfw_ctl_work,
563 work);
564
565 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
566 kfree(ctl_work);
567 }
568
569 static int wm_adsp_create_control(struct wm_adsp *dsp,
570 const struct wm_adsp_alg_region *alg_region,
571 unsigned int offset, unsigned int len,
572 const char *subname, unsigned int subname_len)
573 {
574 struct wm_coeff_ctl *ctl;
575 struct wmfw_ctl_work *ctl_work;
576 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
577 char *region_name;
578 int ret;
579
580 switch (alg_region->type) {
581 case WMFW_ADSP1_PM:
582 region_name = "PM";
583 break;
584 case WMFW_ADSP1_DM:
585 region_name = "DM";
586 break;
587 case WMFW_ADSP2_XM:
588 region_name = "XM";
589 break;
590 case WMFW_ADSP2_YM:
591 region_name = "YM";
592 break;
593 case WMFW_ADSP1_ZM:
594 region_name = "ZM";
595 break;
596 default:
597 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
598 return -EINVAL;
599 }
600
601 switch (dsp->fw_ver) {
602 case 0:
603 case 1:
604 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
605 dsp->num, region_name, alg_region->alg);
606 break;
607 default:
608 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
609 "DSP%d%c %.12s %x", dsp->num, *region_name,
610 wm_adsp_fw_text[dsp->fw], alg_region->alg);
611
612 /* Truncate the subname from the start if it is too long */
613 if (subname) {
614 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
615 int skip = 0;
616
617 if (subname_len > avail)
618 skip = subname_len - avail;
619
620 snprintf(name + ret,
621 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
622 subname_len - skip, subname + skip);
623 }
624 break;
625 }
626
627 list_for_each_entry(ctl, &dsp->ctl_list,
628 list) {
629 if (!strcmp(ctl->name, name)) {
630 if (!ctl->enabled)
631 ctl->enabled = 1;
632 return 0;
633 }
634 }
635
636 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
637 if (!ctl)
638 return -ENOMEM;
639 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
640 ctl->alg_region = *alg_region;
641 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
642 if (!ctl->name) {
643 ret = -ENOMEM;
644 goto err_ctl;
645 }
646 ctl->enabled = 1;
647 ctl->set = 0;
648 ctl->ops.xget = wm_coeff_get;
649 ctl->ops.xput = wm_coeff_put;
650 ctl->dsp = dsp;
651
652 ctl->offset = offset;
653 if (len > 512) {
654 adsp_warn(dsp, "Truncating control %s from %d\n",
655 ctl->name, len);
656 len = 512;
657 }
658 ctl->len = len;
659 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
660 if (!ctl->cache) {
661 ret = -ENOMEM;
662 goto err_ctl_name;
663 }
664
665 list_add(&ctl->list, &dsp->ctl_list);
666
667 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
668 if (!ctl_work) {
669 ret = -ENOMEM;
670 goto err_ctl_cache;
671 }
672
673 ctl_work->dsp = dsp;
674 ctl_work->ctl = ctl;
675 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
676 schedule_work(&ctl_work->work);
677
678 return 0;
679
680 err_ctl_cache:
681 kfree(ctl->cache);
682 err_ctl_name:
683 kfree(ctl->name);
684 err_ctl:
685 kfree(ctl);
686
687 return ret;
688 }
689
690 struct wm_coeff_parsed_alg {
691 int id;
692 const u8 *name;
693 int name_len;
694 int ncoeff;
695 };
696
697 struct wm_coeff_parsed_coeff {
698 int offset;
699 int mem_type;
700 const u8 *name;
701 int name_len;
702 int ctl_type;
703 int flags;
704 int len;
705 };
706
707 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
708 {
709 int length;
710
711 switch (bytes) {
712 case 1:
713 length = **pos;
714 break;
715 case 2:
716 length = le16_to_cpu(*((u16 *)*pos));
717 break;
718 default:
719 return 0;
720 }
721
722 if (str)
723 *str = *pos + bytes;
724
725 *pos += ((length + bytes) + 3) & ~0x03;
726
727 return length;
728 }
729
730 static int wm_coeff_parse_int(int bytes, const u8 **pos)
731 {
732 int val = 0;
733
734 switch (bytes) {
735 case 2:
736 val = le16_to_cpu(*((u16 *)*pos));
737 break;
738 case 4:
739 val = le32_to_cpu(*((u32 *)*pos));
740 break;
741 default:
742 break;
743 }
744
745 *pos += bytes;
746
747 return val;
748 }
749
750 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
751 struct wm_coeff_parsed_alg *blk)
752 {
753 const struct wmfw_adsp_alg_data *raw;
754
755 switch (dsp->fw_ver) {
756 case 0:
757 case 1:
758 raw = (const struct wmfw_adsp_alg_data *)*data;
759 *data = raw->data;
760
761 blk->id = le32_to_cpu(raw->id);
762 blk->name = raw->name;
763 blk->name_len = strlen(raw->name);
764 blk->ncoeff = le32_to_cpu(raw->ncoeff);
765 break;
766 default:
767 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
768 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
769 &blk->name);
770 wm_coeff_parse_string(sizeof(u16), data, NULL);
771 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
772 break;
773 }
774
775 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
776 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
777 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
778 }
779
780 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
781 struct wm_coeff_parsed_coeff *blk)
782 {
783 const struct wmfw_adsp_coeff_data *raw;
784 const u8 *tmp;
785 int length;
786
787 switch (dsp->fw_ver) {
788 case 0:
789 case 1:
790 raw = (const struct wmfw_adsp_coeff_data *)*data;
791 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
792
793 blk->offset = le16_to_cpu(raw->hdr.offset);
794 blk->mem_type = le16_to_cpu(raw->hdr.type);
795 blk->name = raw->name;
796 blk->name_len = strlen(raw->name);
797 blk->ctl_type = le16_to_cpu(raw->ctl_type);
798 blk->flags = le16_to_cpu(raw->flags);
799 blk->len = le32_to_cpu(raw->len);
800 break;
801 default:
802 tmp = *data;
803 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
804 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
805 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
806 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
807 &blk->name);
808 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
809 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
810 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
811 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
812 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
813
814 *data = *data + sizeof(raw->hdr) + length;
815 break;
816 }
817
818 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
819 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
820 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
821 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
822 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
823 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
824 }
825
826 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
827 const struct wmfw_region *region)
828 {
829 struct wm_adsp_alg_region alg_region = {};
830 struct wm_coeff_parsed_alg alg_blk;
831 struct wm_coeff_parsed_coeff coeff_blk;
832 const u8 *data = region->data;
833 int i, ret;
834
835 wm_coeff_parse_alg(dsp, &data, &alg_blk);
836 for (i = 0; i < alg_blk.ncoeff; i++) {
837 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
838
839 switch (coeff_blk.ctl_type) {
840 case SNDRV_CTL_ELEM_TYPE_BYTES:
841 break;
842 default:
843 adsp_err(dsp, "Unknown control type: %d\n",
844 coeff_blk.ctl_type);
845 return -EINVAL;
846 }
847
848 alg_region.type = coeff_blk.mem_type;
849 alg_region.alg = alg_blk.id;
850
851 ret = wm_adsp_create_control(dsp, &alg_region,
852 coeff_blk.offset,
853 coeff_blk.len,
854 coeff_blk.name,
855 coeff_blk.name_len);
856 if (ret < 0)
857 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
858 coeff_blk.name_len, coeff_blk.name, ret);
859 }
860
861 return 0;
862 }
863
864 static int wm_adsp_load(struct wm_adsp *dsp)
865 {
866 LIST_HEAD(buf_list);
867 const struct firmware *firmware;
868 struct regmap *regmap = dsp->regmap;
869 unsigned int pos = 0;
870 const struct wmfw_header *header;
871 const struct wmfw_adsp1_sizes *adsp1_sizes;
872 const struct wmfw_adsp2_sizes *adsp2_sizes;
873 const struct wmfw_footer *footer;
874 const struct wmfw_region *region;
875 const struct wm_adsp_region *mem;
876 const char *region_name;
877 char *file, *text;
878 struct wm_adsp_buf *buf;
879 unsigned int reg;
880 int regions = 0;
881 int ret, offset, type, sizes;
882
883 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
884 if (file == NULL)
885 return -ENOMEM;
886
887 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
888 wm_adsp_fw[dsp->fw].file);
889 file[PAGE_SIZE - 1] = '\0';
890
891 ret = request_firmware(&firmware, file, dsp->dev);
892 if (ret != 0) {
893 adsp_err(dsp, "Failed to request '%s'\n", file);
894 goto out;
895 }
896 ret = -EINVAL;
897
898 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
899 if (pos >= firmware->size) {
900 adsp_err(dsp, "%s: file too short, %zu bytes\n",
901 file, firmware->size);
902 goto out_fw;
903 }
904
905 header = (void*)&firmware->data[0];
906
907 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
908 adsp_err(dsp, "%s: invalid magic\n", file);
909 goto out_fw;
910 }
911
912 switch (header->ver) {
913 case 0:
914 case 1:
915 case 2:
916 break;
917 default:
918 adsp_err(dsp, "%s: unknown file format %d\n",
919 file, header->ver);
920 goto out_fw;
921 }
922
923 adsp_info(dsp, "Firmware version: %d\n", header->ver);
924 dsp->fw_ver = header->ver;
925
926 if (header->core != dsp->type) {
927 adsp_err(dsp, "%s: invalid core %d != %d\n",
928 file, header->core, dsp->type);
929 goto out_fw;
930 }
931
932 switch (dsp->type) {
933 case WMFW_ADSP1:
934 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
935 adsp1_sizes = (void *)&(header[1]);
936 footer = (void *)&(adsp1_sizes[1]);
937 sizes = sizeof(*adsp1_sizes);
938
939 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
940 file, le32_to_cpu(adsp1_sizes->dm),
941 le32_to_cpu(adsp1_sizes->pm),
942 le32_to_cpu(adsp1_sizes->zm));
943 break;
944
945 case WMFW_ADSP2:
946 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
947 adsp2_sizes = (void *)&(header[1]);
948 footer = (void *)&(adsp2_sizes[1]);
949 sizes = sizeof(*adsp2_sizes);
950
951 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
952 file, le32_to_cpu(adsp2_sizes->xm),
953 le32_to_cpu(adsp2_sizes->ym),
954 le32_to_cpu(adsp2_sizes->pm),
955 le32_to_cpu(adsp2_sizes->zm));
956 break;
957
958 default:
959 WARN(1, "Unknown DSP type");
960 goto out_fw;
961 }
962
963 if (le32_to_cpu(header->len) != sizeof(*header) +
964 sizes + sizeof(*footer)) {
965 adsp_err(dsp, "%s: unexpected header length %d\n",
966 file, le32_to_cpu(header->len));
967 goto out_fw;
968 }
969
970 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
971 le64_to_cpu(footer->timestamp));
972
973 while (pos < firmware->size &&
974 pos - firmware->size > sizeof(*region)) {
975 region = (void *)&(firmware->data[pos]);
976 region_name = "Unknown";
977 reg = 0;
978 text = NULL;
979 offset = le32_to_cpu(region->offset) & 0xffffff;
980 type = be32_to_cpu(region->type) & 0xff;
981 mem = wm_adsp_find_region(dsp, type);
982
983 switch (type) {
984 case WMFW_NAME_TEXT:
985 region_name = "Firmware name";
986 text = kzalloc(le32_to_cpu(region->len) + 1,
987 GFP_KERNEL);
988 break;
989 case WMFW_ALGORITHM_DATA:
990 region_name = "Algorithm";
991 ret = wm_adsp_parse_coeff(dsp, region);
992 if (ret != 0)
993 goto out_fw;
994 break;
995 case WMFW_INFO_TEXT:
996 region_name = "Information";
997 text = kzalloc(le32_to_cpu(region->len) + 1,
998 GFP_KERNEL);
999 break;
1000 case WMFW_ABSOLUTE:
1001 region_name = "Absolute";
1002 reg = offset;
1003 break;
1004 case WMFW_ADSP1_PM:
1005 region_name = "PM";
1006 reg = wm_adsp_region_to_reg(mem, offset);
1007 break;
1008 case WMFW_ADSP1_DM:
1009 region_name = "DM";
1010 reg = wm_adsp_region_to_reg(mem, offset);
1011 break;
1012 case WMFW_ADSP2_XM:
1013 region_name = "XM";
1014 reg = wm_adsp_region_to_reg(mem, offset);
1015 break;
1016 case WMFW_ADSP2_YM:
1017 region_name = "YM";
1018 reg = wm_adsp_region_to_reg(mem, offset);
1019 break;
1020 case WMFW_ADSP1_ZM:
1021 region_name = "ZM";
1022 reg = wm_adsp_region_to_reg(mem, offset);
1023 break;
1024 default:
1025 adsp_warn(dsp,
1026 "%s.%d: Unknown region type %x at %d(%x)\n",
1027 file, regions, type, pos, pos);
1028 break;
1029 }
1030
1031 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1032 regions, le32_to_cpu(region->len), offset,
1033 region_name);
1034
1035 if (text) {
1036 memcpy(text, region->data, le32_to_cpu(region->len));
1037 adsp_info(dsp, "%s: %s\n", file, text);
1038 kfree(text);
1039 }
1040
1041 if (reg) {
1042 buf = wm_adsp_buf_alloc(region->data,
1043 le32_to_cpu(region->len),
1044 &buf_list);
1045 if (!buf) {
1046 adsp_err(dsp, "Out of memory\n");
1047 ret = -ENOMEM;
1048 goto out_fw;
1049 }
1050
1051 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1052 le32_to_cpu(region->len));
1053 if (ret != 0) {
1054 adsp_err(dsp,
1055 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1056 file, regions,
1057 le32_to_cpu(region->len), offset,
1058 region_name, ret);
1059 goto out_fw;
1060 }
1061 }
1062
1063 pos += le32_to_cpu(region->len) + sizeof(*region);
1064 regions++;
1065 }
1066
1067 ret = regmap_async_complete(regmap);
1068 if (ret != 0) {
1069 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1070 goto out_fw;
1071 }
1072
1073 if (pos > firmware->size)
1074 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1075 file, regions, pos - firmware->size);
1076
1077 out_fw:
1078 regmap_async_complete(regmap);
1079 wm_adsp_buf_free(&buf_list);
1080 release_firmware(firmware);
1081 out:
1082 kfree(file);
1083
1084 return ret;
1085 }
1086
1087 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1088 const struct wm_adsp_alg_region *alg_region)
1089 {
1090 struct wm_coeff_ctl *ctl;
1091
1092 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1093 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1094 alg_region->alg == ctl->alg_region.alg &&
1095 alg_region->type == ctl->alg_region.type) {
1096 ctl->alg_region.base = alg_region->base;
1097 }
1098 }
1099 }
1100
1101 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
1102 unsigned int pos, unsigned int len)
1103 {
1104 void *alg;
1105 int ret;
1106 __be32 val;
1107
1108 if (n_algs == 0) {
1109 adsp_err(dsp, "No algorithms\n");
1110 return ERR_PTR(-EINVAL);
1111 }
1112
1113 if (n_algs > 1024) {
1114 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
1115 return ERR_PTR(-EINVAL);
1116 }
1117
1118 /* Read the terminator first to validate the length */
1119 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1120 if (ret != 0) {
1121 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1122 ret);
1123 return ERR_PTR(ret);
1124 }
1125
1126 if (be32_to_cpu(val) != 0xbedead)
1127 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1128 pos + len, be32_to_cpu(val));
1129
1130 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1131 if (!alg)
1132 return ERR_PTR(-ENOMEM);
1133
1134 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1135 if (ret != 0) {
1136 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1137 ret);
1138 kfree(alg);
1139 return ERR_PTR(ret);
1140 }
1141
1142 return alg;
1143 }
1144
1145 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1146 int type, __be32 id,
1147 __be32 base)
1148 {
1149 struct wm_adsp_alg_region *alg_region;
1150
1151 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1152 if (!alg_region)
1153 return ERR_PTR(-ENOMEM);
1154
1155 alg_region->type = type;
1156 alg_region->alg = be32_to_cpu(id);
1157 alg_region->base = be32_to_cpu(base);
1158
1159 list_add_tail(&alg_region->list, &dsp->alg_regions);
1160
1161 if (dsp->fw_ver > 0)
1162 wm_adsp_ctl_fixup_base(dsp, alg_region);
1163
1164 return alg_region;
1165 }
1166
1167 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1168 {
1169 struct wmfw_adsp1_id_hdr adsp1_id;
1170 struct wmfw_adsp1_alg_hdr *adsp1_alg;
1171 struct wm_adsp_alg_region *alg_region;
1172 const struct wm_adsp_region *mem;
1173 unsigned int pos, len;
1174 size_t n_algs;
1175 int i, ret;
1176
1177 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1178 if (WARN_ON(!mem))
1179 return -EINVAL;
1180
1181 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1182 sizeof(adsp1_id));
1183 if (ret != 0) {
1184 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1185 ret);
1186 return ret;
1187 }
1188
1189 n_algs = be32_to_cpu(adsp1_id.n_algs);
1190 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1191 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1192 dsp->fw_id,
1193 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1194 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1195 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
1196 n_algs);
1197
1198 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1199 adsp1_id.fw.id, adsp1_id.zm);
1200 if (IS_ERR(alg_region))
1201 return PTR_ERR(alg_region);
1202
1203 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1204 adsp1_id.fw.id, adsp1_id.dm);
1205 if (IS_ERR(alg_region))
1206 return PTR_ERR(alg_region);
1207
1208 pos = sizeof(adsp1_id) / 2;
1209 len = (sizeof(*adsp1_alg) * n_algs) / 2;
1210
1211 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
1212 if (IS_ERR(adsp1_alg))
1213 return PTR_ERR(adsp1_alg);
1214
1215 for (i = 0; i < n_algs; i++) {
1216 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1217 i, be32_to_cpu(adsp1_alg[i].alg.id),
1218 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1219 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1220 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1221 be32_to_cpu(adsp1_alg[i].dm),
1222 be32_to_cpu(adsp1_alg[i].zm));
1223
1224 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1225 adsp1_alg[i].alg.id,
1226 adsp1_alg[i].dm);
1227 if (IS_ERR(alg_region)) {
1228 ret = PTR_ERR(alg_region);
1229 goto out;
1230 }
1231 if (dsp->fw_ver == 0) {
1232 if (i + 1 < n_algs) {
1233 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1234 len -= be32_to_cpu(adsp1_alg[i].dm);
1235 len *= 4;
1236 wm_adsp_create_control(dsp, alg_region, 0,
1237 len, NULL, 0);
1238 } else {
1239 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1240 be32_to_cpu(adsp1_alg[i].alg.id));
1241 }
1242 }
1243
1244 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1245 adsp1_alg[i].alg.id,
1246 adsp1_alg[i].zm);
1247 if (IS_ERR(alg_region)) {
1248 ret = PTR_ERR(alg_region);
1249 goto out;
1250 }
1251 if (dsp->fw_ver == 0) {
1252 if (i + 1 < n_algs) {
1253 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1254 len -= be32_to_cpu(adsp1_alg[i].zm);
1255 len *= 4;
1256 wm_adsp_create_control(dsp, alg_region, 0,
1257 len, NULL, 0);
1258 } else {
1259 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1260 be32_to_cpu(adsp1_alg[i].alg.id));
1261 }
1262 }
1263 }
1264
1265 out:
1266 kfree(adsp1_alg);
1267 return ret;
1268 }
1269
1270 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1271 {
1272 struct wmfw_adsp2_id_hdr adsp2_id;
1273 struct wmfw_adsp2_alg_hdr *adsp2_alg;
1274 struct wm_adsp_alg_region *alg_region;
1275 const struct wm_adsp_region *mem;
1276 unsigned int pos, len;
1277 size_t n_algs;
1278 int i, ret;
1279
1280 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1281 if (WARN_ON(!mem))
1282 return -EINVAL;
1283
1284 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1285 sizeof(adsp2_id));
1286 if (ret != 0) {
1287 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1288 ret);
1289 return ret;
1290 }
1291
1292 n_algs = be32_to_cpu(adsp2_id.n_algs);
1293 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
1294 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1295 dsp->fw_id,
1296 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
1297 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
1298 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
1299 n_algs);
1300
1301 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1302 adsp2_id.fw.id, adsp2_id.xm);
1303 if (IS_ERR(alg_region))
1304 return PTR_ERR(alg_region);
1305
1306 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1307 adsp2_id.fw.id, adsp2_id.ym);
1308 if (IS_ERR(alg_region))
1309 return PTR_ERR(alg_region);
1310
1311 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1312 adsp2_id.fw.id, adsp2_id.zm);
1313 if (IS_ERR(alg_region))
1314 return PTR_ERR(alg_region);
1315
1316 pos = sizeof(adsp2_id) / 2;
1317 len = (sizeof(*adsp2_alg) * n_algs) / 2;
1318
1319 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
1320 if (IS_ERR(adsp2_alg))
1321 return PTR_ERR(adsp2_alg);
1322
1323 for (i = 0; i < n_algs; i++) {
1324 adsp_info(dsp,
1325 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1326 i, be32_to_cpu(adsp2_alg[i].alg.id),
1327 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1328 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1329 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1330 be32_to_cpu(adsp2_alg[i].xm),
1331 be32_to_cpu(adsp2_alg[i].ym),
1332 be32_to_cpu(adsp2_alg[i].zm));
1333
1334 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1335 adsp2_alg[i].alg.id,
1336 adsp2_alg[i].xm);
1337 if (IS_ERR(alg_region)) {
1338 ret = PTR_ERR(alg_region);
1339 goto out;
1340 }
1341 if (dsp->fw_ver == 0) {
1342 if (i + 1 < n_algs) {
1343 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1344 len -= be32_to_cpu(adsp2_alg[i].xm);
1345 len *= 4;
1346 wm_adsp_create_control(dsp, alg_region, 0,
1347 len, NULL, 0);
1348 } else {
1349 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1350 be32_to_cpu(adsp2_alg[i].alg.id));
1351 }
1352 }
1353
1354 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1355 adsp2_alg[i].alg.id,
1356 adsp2_alg[i].ym);
1357 if (IS_ERR(alg_region)) {
1358 ret = PTR_ERR(alg_region);
1359 goto out;
1360 }
1361 if (dsp->fw_ver == 0) {
1362 if (i + 1 < n_algs) {
1363 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1364 len -= be32_to_cpu(adsp2_alg[i].ym);
1365 len *= 4;
1366 wm_adsp_create_control(dsp, alg_region, 0,
1367 len, NULL, 0);
1368 } else {
1369 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1370 be32_to_cpu(adsp2_alg[i].alg.id));
1371 }
1372 }
1373
1374 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1375 adsp2_alg[i].alg.id,
1376 adsp2_alg[i].zm);
1377 if (IS_ERR(alg_region)) {
1378 ret = PTR_ERR(alg_region);
1379 goto out;
1380 }
1381 if (dsp->fw_ver == 0) {
1382 if (i + 1 < n_algs) {
1383 len = be32_to_cpu(adsp2_alg[i + 1].zm);
1384 len -= be32_to_cpu(adsp2_alg[i].zm);
1385 len *= 4;
1386 wm_adsp_create_control(dsp, alg_region, 0,
1387 len, NULL, 0);
1388 } else {
1389 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1390 be32_to_cpu(adsp2_alg[i].alg.id));
1391 }
1392 }
1393 }
1394
1395 out:
1396 kfree(adsp2_alg);
1397 return ret;
1398 }
1399
1400 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1401 {
1402 LIST_HEAD(buf_list);
1403 struct regmap *regmap = dsp->regmap;
1404 struct wmfw_coeff_hdr *hdr;
1405 struct wmfw_coeff_item *blk;
1406 const struct firmware *firmware;
1407 const struct wm_adsp_region *mem;
1408 struct wm_adsp_alg_region *alg_region;
1409 const char *region_name;
1410 int ret, pos, blocks, type, offset, reg;
1411 char *file;
1412 struct wm_adsp_buf *buf;
1413
1414 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1415 if (file == NULL)
1416 return -ENOMEM;
1417
1418 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1419 wm_adsp_fw[dsp->fw].file);
1420 file[PAGE_SIZE - 1] = '\0';
1421
1422 ret = request_firmware(&firmware, file, dsp->dev);
1423 if (ret != 0) {
1424 adsp_warn(dsp, "Failed to request '%s'\n", file);
1425 ret = 0;
1426 goto out;
1427 }
1428 ret = -EINVAL;
1429
1430 if (sizeof(*hdr) >= firmware->size) {
1431 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1432 file, firmware->size);
1433 goto out_fw;
1434 }
1435
1436 hdr = (void*)&firmware->data[0];
1437 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1438 adsp_err(dsp, "%s: invalid magic\n", file);
1439 goto out_fw;
1440 }
1441
1442 switch (be32_to_cpu(hdr->rev) & 0xff) {
1443 case 1:
1444 break;
1445 default:
1446 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1447 file, be32_to_cpu(hdr->rev) & 0xff);
1448 ret = -EINVAL;
1449 goto out_fw;
1450 }
1451
1452 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1453 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1454 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1455 le32_to_cpu(hdr->ver) & 0xff);
1456
1457 pos = le32_to_cpu(hdr->len);
1458
1459 blocks = 0;
1460 while (pos < firmware->size &&
1461 pos - firmware->size > sizeof(*blk)) {
1462 blk = (void*)(&firmware->data[pos]);
1463
1464 type = le16_to_cpu(blk->type);
1465 offset = le16_to_cpu(blk->offset);
1466
1467 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1468 file, blocks, le32_to_cpu(blk->id),
1469 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1470 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1471 le32_to_cpu(blk->ver) & 0xff);
1472 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1473 file, blocks, le32_to_cpu(blk->len), offset, type);
1474
1475 reg = 0;
1476 region_name = "Unknown";
1477 switch (type) {
1478 case (WMFW_NAME_TEXT << 8):
1479 case (WMFW_INFO_TEXT << 8):
1480 break;
1481 case (WMFW_ABSOLUTE << 8):
1482 /*
1483 * Old files may use this for global
1484 * coefficients.
1485 */
1486 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1487 offset == 0) {
1488 region_name = "global coefficients";
1489 mem = wm_adsp_find_region(dsp, type);
1490 if (!mem) {
1491 adsp_err(dsp, "No ZM\n");
1492 break;
1493 }
1494 reg = wm_adsp_region_to_reg(mem, 0);
1495
1496 } else {
1497 region_name = "register";
1498 reg = offset;
1499 }
1500 break;
1501
1502 case WMFW_ADSP1_DM:
1503 case WMFW_ADSP1_ZM:
1504 case WMFW_ADSP2_XM:
1505 case WMFW_ADSP2_YM:
1506 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1507 file, blocks, le32_to_cpu(blk->len),
1508 type, le32_to_cpu(blk->id));
1509
1510 mem = wm_adsp_find_region(dsp, type);
1511 if (!mem) {
1512 adsp_err(dsp, "No base for region %x\n", type);
1513 break;
1514 }
1515
1516 reg = 0;
1517 list_for_each_entry(alg_region,
1518 &dsp->alg_regions, list) {
1519 if (le32_to_cpu(blk->id) == alg_region->alg &&
1520 type == alg_region->type) {
1521 reg = alg_region->base;
1522 reg = wm_adsp_region_to_reg(mem,
1523 reg);
1524 reg += offset;
1525 break;
1526 }
1527 }
1528
1529 if (reg == 0)
1530 adsp_err(dsp, "No %x for algorithm %x\n",
1531 type, le32_to_cpu(blk->id));
1532 break;
1533
1534 default:
1535 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1536 file, blocks, type, pos);
1537 break;
1538 }
1539
1540 if (reg) {
1541 buf = wm_adsp_buf_alloc(blk->data,
1542 le32_to_cpu(blk->len),
1543 &buf_list);
1544 if (!buf) {
1545 adsp_err(dsp, "Out of memory\n");
1546 ret = -ENOMEM;
1547 goto out_fw;
1548 }
1549
1550 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1551 file, blocks, le32_to_cpu(blk->len),
1552 reg);
1553 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1554 le32_to_cpu(blk->len));
1555 if (ret != 0) {
1556 adsp_err(dsp,
1557 "%s.%d: Failed to write to %x in %s: %d\n",
1558 file, blocks, reg, region_name, ret);
1559 }
1560 }
1561
1562 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
1563 blocks++;
1564 }
1565
1566 ret = regmap_async_complete(regmap);
1567 if (ret != 0)
1568 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1569
1570 if (pos > firmware->size)
1571 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1572 file, blocks, pos - firmware->size);
1573
1574 out_fw:
1575 regmap_async_complete(regmap);
1576 release_firmware(firmware);
1577 wm_adsp_buf_free(&buf_list);
1578 out:
1579 kfree(file);
1580 return ret;
1581 }
1582
1583 int wm_adsp1_init(struct wm_adsp *dsp)
1584 {
1585 INIT_LIST_HEAD(&dsp->alg_regions);
1586
1587 return 0;
1588 }
1589 EXPORT_SYMBOL_GPL(wm_adsp1_init);
1590
1591 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1592 struct snd_kcontrol *kcontrol,
1593 int event)
1594 {
1595 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1596 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1597 struct wm_adsp *dsp = &dsps[w->shift];
1598 struct wm_adsp_alg_region *alg_region;
1599 struct wm_coeff_ctl *ctl;
1600 int ret;
1601 int val;
1602
1603 dsp->card = codec->component.card;
1604
1605 switch (event) {
1606 case SND_SOC_DAPM_POST_PMU:
1607 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1608 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1609
1610 /*
1611 * For simplicity set the DSP clock rate to be the
1612 * SYSCLK rate rather than making it configurable.
1613 */
1614 if(dsp->sysclk_reg) {
1615 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1616 if (ret != 0) {
1617 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1618 ret);
1619 return ret;
1620 }
1621
1622 val = (val & dsp->sysclk_mask)
1623 >> dsp->sysclk_shift;
1624
1625 ret = regmap_update_bits(dsp->regmap,
1626 dsp->base + ADSP1_CONTROL_31,
1627 ADSP1_CLK_SEL_MASK, val);
1628 if (ret != 0) {
1629 adsp_err(dsp, "Failed to set clock rate: %d\n",
1630 ret);
1631 return ret;
1632 }
1633 }
1634
1635 ret = wm_adsp_load(dsp);
1636 if (ret != 0)
1637 goto err;
1638
1639 ret = wm_adsp1_setup_algs(dsp);
1640 if (ret != 0)
1641 goto err;
1642
1643 ret = wm_adsp_load_coeff(dsp);
1644 if (ret != 0)
1645 goto err;
1646
1647 /* Initialize caches for enabled and unset controls */
1648 ret = wm_coeff_init_control_caches(dsp);
1649 if (ret != 0)
1650 goto err;
1651
1652 /* Sync set controls */
1653 ret = wm_coeff_sync_controls(dsp);
1654 if (ret != 0)
1655 goto err;
1656
1657 /* Start the core running */
1658 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1659 ADSP1_CORE_ENA | ADSP1_START,
1660 ADSP1_CORE_ENA | ADSP1_START);
1661 break;
1662
1663 case SND_SOC_DAPM_PRE_PMD:
1664 /* Halt the core */
1665 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1666 ADSP1_CORE_ENA | ADSP1_START, 0);
1667
1668 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
1669 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
1670
1671 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1672 ADSP1_SYS_ENA, 0);
1673
1674 list_for_each_entry(ctl, &dsp->ctl_list, list)
1675 ctl->enabled = 0;
1676
1677 while (!list_empty(&dsp->alg_regions)) {
1678 alg_region = list_first_entry(&dsp->alg_regions,
1679 struct wm_adsp_alg_region,
1680 list);
1681 list_del(&alg_region->list);
1682 kfree(alg_region);
1683 }
1684 break;
1685
1686 default:
1687 break;
1688 }
1689
1690 return 0;
1691
1692 err:
1693 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1694 ADSP1_SYS_ENA, 0);
1695 return ret;
1696 }
1697 EXPORT_SYMBOL_GPL(wm_adsp1_event);
1698
1699 static int wm_adsp2_ena(struct wm_adsp *dsp)
1700 {
1701 unsigned int val;
1702 int ret, count;
1703
1704 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
1705 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
1706 if (ret != 0)
1707 return ret;
1708
1709 /* Wait for the RAM to start, should be near instantaneous */
1710 for (count = 0; count < 10; ++count) {
1711 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
1712 &val);
1713 if (ret != 0)
1714 return ret;
1715
1716 if (val & ADSP2_RAM_RDY)
1717 break;
1718
1719 msleep(1);
1720 }
1721
1722 if (!(val & ADSP2_RAM_RDY)) {
1723 adsp_err(dsp, "Failed to start DSP RAM\n");
1724 return -EBUSY;
1725 }
1726
1727 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
1728
1729 return 0;
1730 }
1731
1732 static void wm_adsp2_boot_work(struct work_struct *work)
1733 {
1734 struct wm_adsp *dsp = container_of(work,
1735 struct wm_adsp,
1736 boot_work);
1737 int ret;
1738 unsigned int val;
1739
1740 /*
1741 * For simplicity set the DSP clock rate to be the
1742 * SYSCLK rate rather than making it configurable.
1743 */
1744 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1745 if (ret != 0) {
1746 adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
1747 return;
1748 }
1749 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1750 >> ARIZONA_SYSCLK_FREQ_SHIFT;
1751
1752 ret = regmap_update_bits_async(dsp->regmap,
1753 dsp->base + ADSP2_CLOCKING,
1754 ADSP2_CLK_SEL_MASK, val);
1755 if (ret != 0) {
1756 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
1757 return;
1758 }
1759
1760 if (dsp->dvfs) {
1761 ret = regmap_read(dsp->regmap,
1762 dsp->base + ADSP2_CLOCKING, &val);
1763 if (ret != 0) {
1764 adsp_err(dsp, "Failed to read clocking: %d\n", ret);
1765 return;
1766 }
1767
1768 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
1769 ret = regulator_enable(dsp->dvfs);
1770 if (ret != 0) {
1771 adsp_err(dsp,
1772 "Failed to enable supply: %d\n",
1773 ret);
1774 return;
1775 }
1776
1777 ret = regulator_set_voltage(dsp->dvfs,
1778 1800000,
1779 1800000);
1780 if (ret != 0) {
1781 adsp_err(dsp,
1782 "Failed to raise supply: %d\n",
1783 ret);
1784 return;
1785 }
1786 }
1787 }
1788
1789 ret = wm_adsp2_ena(dsp);
1790 if (ret != 0)
1791 return;
1792
1793 ret = wm_adsp_load(dsp);
1794 if (ret != 0)
1795 goto err;
1796
1797 ret = wm_adsp2_setup_algs(dsp);
1798 if (ret != 0)
1799 goto err;
1800
1801 ret = wm_adsp_load_coeff(dsp);
1802 if (ret != 0)
1803 goto err;
1804
1805 /* Initialize caches for enabled and unset controls */
1806 ret = wm_coeff_init_control_caches(dsp);
1807 if (ret != 0)
1808 goto err;
1809
1810 /* Sync set controls */
1811 ret = wm_coeff_sync_controls(dsp);
1812 if (ret != 0)
1813 goto err;
1814
1815 dsp->running = true;
1816
1817 return;
1818
1819 err:
1820 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1821 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1822 }
1823
1824 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
1825 struct snd_kcontrol *kcontrol, int event)
1826 {
1827 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1828 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1829 struct wm_adsp *dsp = &dsps[w->shift];
1830
1831 dsp->card = codec->component.card;
1832
1833 switch (event) {
1834 case SND_SOC_DAPM_PRE_PMU:
1835 queue_work(system_unbound_wq, &dsp->boot_work);
1836 break;
1837 default:
1838 break;
1839 }
1840
1841 return 0;
1842 }
1843 EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
1844
1845 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
1846 struct snd_kcontrol *kcontrol, int event)
1847 {
1848 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1849 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1850 struct wm_adsp *dsp = &dsps[w->shift];
1851 struct wm_adsp_alg_region *alg_region;
1852 struct wm_coeff_ctl *ctl;
1853 int ret;
1854
1855 switch (event) {
1856 case SND_SOC_DAPM_POST_PMU:
1857 flush_work(&dsp->boot_work);
1858
1859 if (!dsp->running)
1860 return -EIO;
1861
1862 ret = regmap_update_bits(dsp->regmap,
1863 dsp->base + ADSP2_CONTROL,
1864 ADSP2_CORE_ENA | ADSP2_START,
1865 ADSP2_CORE_ENA | ADSP2_START);
1866 if (ret != 0)
1867 goto err;
1868 break;
1869
1870 case SND_SOC_DAPM_PRE_PMD:
1871 dsp->running = false;
1872
1873 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1874 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1875 ADSP2_START, 0);
1876
1877 /* Make sure DMAs are quiesced */
1878 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1879 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1880 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1881
1882 if (dsp->dvfs) {
1883 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1884 1800000);
1885 if (ret != 0)
1886 adsp_warn(dsp,
1887 "Failed to lower supply: %d\n",
1888 ret);
1889
1890 ret = regulator_disable(dsp->dvfs);
1891 if (ret != 0)
1892 adsp_err(dsp,
1893 "Failed to enable supply: %d\n",
1894 ret);
1895 }
1896
1897 list_for_each_entry(ctl, &dsp->ctl_list, list)
1898 ctl->enabled = 0;
1899
1900 while (!list_empty(&dsp->alg_regions)) {
1901 alg_region = list_first_entry(&dsp->alg_regions,
1902 struct wm_adsp_alg_region,
1903 list);
1904 list_del(&alg_region->list);
1905 kfree(alg_region);
1906 }
1907
1908 adsp_dbg(dsp, "Shutdown complete\n");
1909 break;
1910
1911 default:
1912 break;
1913 }
1914
1915 return 0;
1916 err:
1917 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1918 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1919 return ret;
1920 }
1921 EXPORT_SYMBOL_GPL(wm_adsp2_event);
1922
1923 int wm_adsp2_init(struct wm_adsp *dsp, bool dvfs)
1924 {
1925 int ret;
1926
1927 /*
1928 * Disable the DSP memory by default when in reset for a small
1929 * power saving.
1930 */
1931 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1932 ADSP2_MEM_ENA, 0);
1933 if (ret != 0) {
1934 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
1935 return ret;
1936 }
1937
1938 INIT_LIST_HEAD(&dsp->alg_regions);
1939 INIT_LIST_HEAD(&dsp->ctl_list);
1940 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
1941
1942 if (dvfs) {
1943 dsp->dvfs = devm_regulator_get(dsp->dev, "DCVDD");
1944 if (IS_ERR(dsp->dvfs)) {
1945 ret = PTR_ERR(dsp->dvfs);
1946 adsp_err(dsp, "Failed to get DCVDD: %d\n", ret);
1947 return ret;
1948 }
1949
1950 ret = regulator_enable(dsp->dvfs);
1951 if (ret != 0) {
1952 adsp_err(dsp, "Failed to enable DCVDD: %d\n", ret);
1953 return ret;
1954 }
1955
1956 ret = regulator_set_voltage(dsp->dvfs, 1200000, 1800000);
1957 if (ret != 0) {
1958 adsp_err(dsp, "Failed to initialise DVFS: %d\n", ret);
1959 return ret;
1960 }
1961
1962 ret = regulator_disable(dsp->dvfs);
1963 if (ret != 0) {
1964 adsp_err(dsp, "Failed to disable DCVDD: %d\n", ret);
1965 return ret;
1966 }
1967 }
1968
1969 return 0;
1970 }
1971 EXPORT_SYMBOL_GPL(wm_adsp2_init);
1972
1973 MODULE_LICENSE("GPL v2");
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