drivers/reset/reset-zynq.c

   1 /*
   2  * Copyright (c) 2015, National Instruments Corp.
   3  *
   4  * Xilinx Zynq Reset controller driver
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/of.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/reset-controller.h>
  23 #include <linux/regmap.h>
  24 #include <linux/types.h>
  25
  26 struct zynq_reset_data {
  27         struct regmap *slcr;
  28         struct reset_controller_dev rcdev;
  29         u32 offset;
  30 };
  31
  32 #define to_zynq_reset_data(p)           \
  33         container_of((p), struct zynq_reset_data, rcdev)
  34
  35 static int zynq_reset_assert(struct reset_controller_dev *rcdev,
  36                              unsigned long id)
  37 {
  38         struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
  39
  40         int bank = id / BITS_PER_LONG;
  41         int offset = id % BITS_PER_LONG;
  42
  43         pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
  44                  bank, offset);
  45
  46         return regmap_update_bits(priv->slcr,
  47                                   priv->offset + (bank * 4),
  48                                   BIT(offset),
  49                                   BIT(offset));
  50 }
  51
  52 static int zynq_reset_deassert(struct reset_controller_dev *rcdev,
  53                                unsigned long id)
  54 {
  55         struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
  56
  57         int bank = id / BITS_PER_LONG;
  58         int offset = id % BITS_PER_LONG;
  59
  60         pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
  61                  bank, offset);
  62
  63         return regmap_update_bits(priv->slcr,
  64                                   priv->offset + (bank * 4),
  65                                   BIT(offset),
  66                                   ~BIT(offset));
  67 }
  68
  69 static int zynq_reset_status(struct reset_controller_dev *rcdev,
  70                              unsigned long id)
  71 {
  72         struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
  73
  74         int bank = id / BITS_PER_LONG;
  75         int offset = id % BITS_PER_LONG;
  76         int ret;
  77         u32 reg;
  78
  79         pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
  80                  bank, offset);
  81
  82         ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg);
  83         if (ret)
  84                 return ret;
  85
  86         return !!(reg & BIT(offset));
  87 }
  88
  89 static const struct reset_control_ops zynq_reset_ops = {
  90         .assert         = zynq_reset_assert,
  91         .deassert       = zynq_reset_deassert,
  92         .status         = zynq_reset_status,
  93 };
  94
  95 static int zynq_reset_probe(struct platform_device *pdev)
  96 {
  97         struct resource *res;
  98         struct zynq_reset_data *priv;
  99
 100         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 101         if (!priv)
 102                 return -ENOMEM;
 103         platform_set_drvdata(pdev, priv);
 104
 105         priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 106                                                      "syscon");
 107         if (IS_ERR(priv->slcr)) {
 108                 dev_err(&pdev->dev, "unable to get zynq-slcr regmap");
 109                 return PTR_ERR(priv->slcr);
 110         }
 111
 112         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 113         if (!res) {
 114                 dev_err(&pdev->dev, "missing IO resource\n");
 115                 return -ENODEV;
 116         }
 117
 118         priv->offset = res->start;
 119
 120         priv->rcdev.owner = THIS_MODULE;
 121         priv->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_LONG;
 122         priv->rcdev.ops = &zynq_reset_ops;
 123         priv->rcdev.of_node = pdev->dev.of_node;
 124
 125         return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
 126 }
 127
 128 static const struct of_device_id zynq_reset_dt_ids[] = {
 129         { .compatible = "xlnx,zynq-reset", },
 130         { /* sentinel */ },
 131 };
 132
 133 static struct platform_driver zynq_reset_driver = {
 134         .probe  = zynq_reset_probe,
 135         .driver = {
 136                 .name           = KBUILD_MODNAME,
 137                 .of_match_table = zynq_reset_dt_ids,
 138         },
 139 };
 140 module_platform_driver(zynq_reset_driver);
 141
 142 MODULE_LICENSE("GPL v2");
 143 MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
 144 MODULE_DESCRIPTION("Zynq Reset Controller Driver");