[PATCH] tpm_bios: securityfs error checking fix
[linux-2.6/btrfs-unstable.git] / include / asm-m32r / m32r.h
blobb133ca61acf197247921d7cb3f9f434452dfdb76
1 #ifndef _ASM_M32R_M32R_H_
2 #define _ASM_M32R_M32R_H_
4 /*
5 * Renesas M32R processor
7 * Copyright (C) 2003, 2004 Renesas Technology Corp.
8 */
10 #include <linux/config.h>
12 /* Chip type */
13 #if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP)
14 #include <asm/m32r_mp_fpga.h>
15 #elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
16 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
17 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
18 #include <asm/m32102.h>
19 #endif
21 /* Platform type */
22 #if defined(CONFIG_PLAT_M32700UT)
23 #include <asm/m32700ut/m32700ut_pld.h>
24 #include <asm/m32700ut/m32700ut_lan.h>
25 #include <asm/m32700ut/m32700ut_lcd.h>
26 #endif /* CONFIG_PLAT_M32700UT */
28 #if defined(CONFIG_PLAT_OPSPUT)
29 #include <asm/opsput/opsput_pld.h>
30 #include <asm/opsput/opsput_lan.h>
31 #include <asm/opsput/opsput_lcd.h>
32 #endif /* CONFIG_PLAT_OPSPUT */
34 #if defined(CONFIG_PLAT_MAPPI2)
35 #include <asm/mappi2/mappi2_pld.h>
36 #endif /* CONFIG_PLAT_MAPPI2 */
38 #if defined(CONFIG_PLAT_MAPPI3)
39 #include <asm/mappi3/mappi3_pld.h>
40 #endif /* CONFIG_PLAT_MAPPI3 */
42 #if defined(CONFIG_PLAT_USRV)
43 #include <asm/m32700ut/m32700ut_pld.h>
44 #endif
46 #if defined(CONFIG_PLAT_M32104UT)
47 #include <asm/m32104ut/m32104ut_pld.h>
48 #endif /* CONFIG_PLAT_M32104 */
51 * M32R Register
55 * MMU Register
58 #define MMU_REG_BASE (0xffff0000)
59 #define ITLB_BASE (0xfe000000)
60 #define DTLB_BASE (0xfe000800)
62 #define NR_TLB_ENTRIES CONFIG_TLB_ENTRIES
64 #define MATM MMU_REG_BASE /* MMU Address Translation Mode
65 Register */
66 #define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
67 #define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
68 #define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
69 #define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
70 Address Register */
71 #define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
72 Number Register */
73 #define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
74 #define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
75 Register */
76 #define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
77 #define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for
78 Instruciton */
79 #define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */
81 #define MATM_offset (MATM - MMU_REG_BASE)
82 #define MPSZ_offset (MPSZ - MMU_REG_BASE)
83 #define MASID_offset (MASID - MMU_REG_BASE)
84 #define MESTS_offset (MESTS - MMU_REG_BASE)
85 #define MDEVA_offset (MDEVA - MMU_REG_BASE)
86 #define MDEVP_offset (MDEVP - MMU_REG_BASE)
87 #define MPTB_offset (MPTB - MMU_REG_BASE)
88 #define MSVA_offset (MSVA - MMU_REG_BASE)
89 #define MTOP_offset (MTOP - MMU_REG_BASE)
90 #define MIDXI_offset (MIDXI - MMU_REG_BASE)
91 #define MIDXD_offset (MIDXD - MMU_REG_BASE)
93 #define MESTS_IT (1 << 0) /* Instruction TLB miss */
94 #define MESTS_IA (1 << 1) /* Instruction Access Exception */
95 #define MESTS_DT (1 << 4) /* Operand TLB miss */
96 #define MESTS_DA (1 << 5) /* Operand Access Exception */
97 #define MESTS_DRW (1 << 6) /* Operand Write Exception Flag */
100 * PSW (Processor Status Word)
103 /* PSW bit */
104 #define M32R_PSW_BIT_SM (7) /* Stack Mode */
105 #define M32R_PSW_BIT_IE (6) /* Interrupt Enable */
106 #define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */
107 #define M32R_PSW_BIT_C (0) /* Condition */
108 #define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */
109 #define M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */
110 #define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */
111 #define M32R_PSW_BIT_BC (0+8) /* Backup Condition */
113 /* PSW bit map */
114 #define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */
115 #define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */
116 #define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */
117 #define M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */
118 #define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */
119 #define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */
120 #define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */
121 #define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */
124 * Direct address to SFR
127 #include <asm/page.h>
128 #ifdef CONFIG_MMU
129 #define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000)
130 #else
131 #define NONCACHE_OFFSET __PAGE_OFFSET
132 #endif /* CONFIG_MMU */
134 #define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET
135 #define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET
136 #define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET
137 #define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET
138 #define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET
139 #define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET
141 #endif /* _ASM_M32R_M32R_H_ */