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Merge git://git.infradead.org/iommu-2.6
[linux-2.6/btrfs-unstable.git] / drivers / pci / intel-iommu.c
blob23e56a564e05056a208ac41d98828d32987865b7
1 /*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
22 */
23
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <asm/cacheflush.h>
40 #include <asm/iommu.h>
41 #include "pci.h"
42
43 #define ROOT_SIZE VTD_PAGE_SIZE
44 #define CONTEXT_SIZE VTD_PAGE_SIZE
45
46 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
47 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
48
49 #define IOAPIC_RANGE_START (0xfee00000)
50 #define IOAPIC_RANGE_END (0xfeefffff)
51 #define IOVA_START_ADDR (0x1000)
52
53 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
54
55 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
56
57 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
58 #define DMA_32BIT_PFN IOVA_PFN(DMA_32BIT_MASK)
59 #define DMA_64BIT_PFN IOVA_PFN(DMA_64BIT_MASK)
60
61 /* global iommu list, set NULL for ignored DMAR units */
62 static struct intel_iommu **g_iommus;
63
64 static int rwbf_quirk;
65
66 /*
67 * 0: Present
68 * 1-11: Reserved
69 * 12-63: Context Ptr (12 - (haw-1))
70 * 64-127: Reserved
71 */
72 struct root_entry {
73 u64 val;
74 u64 rsvd1;
75 };
76 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
77 static inline bool root_present(struct root_entry *root)
78 {
79 return (root->val & 1);
80 }
81 static inline void set_root_present(struct root_entry *root)
82 {
83 root->val |= 1;
84 }
85 static inline void set_root_value(struct root_entry *root, unsigned long value)
86 {
87 root->val |= value & VTD_PAGE_MASK;
88 }
89
90 static inline struct context_entry *
91 get_context_addr_from_root(struct root_entry *root)
92 {
93 return (struct context_entry *)
94 (root_present(root)?phys_to_virt(
95 root->val & VTD_PAGE_MASK) :
96 NULL);
97 }
98
99 /*
100 * low 64 bits:
101 * 0: present
102 * 1: fault processing disable
103 * 2-3: translation type
104 * 12-63: address space root
105 * high 64 bits:
106 * 0-2: address width
107 * 3-6: aval
108 * 8-23: domain id
109 */
110 struct context_entry {
111 u64 lo;
112 u64 hi;
113 };
114
115 static inline bool context_present(struct context_entry *context)
116 {
117 return (context->lo & 1);
118 }
119 static inline void context_set_present(struct context_entry *context)
120 {
121 context->lo |= 1;
122 }
123
124 static inline void context_set_fault_enable(struct context_entry *context)
125 {
126 context->lo &= (((u64)-1) << 2) | 1;
127 }
128
129 #define CONTEXT_TT_MULTI_LEVEL 0
130
131 static inline void context_set_translation_type(struct context_entry *context,
132 unsigned long value)
133 {
134 context->lo &= (((u64)-1) << 4) | 3;
135 context->lo |= (value & 3) << 2;
136 }
137
138 static inline void context_set_address_root(struct context_entry *context,
139 unsigned long value)
140 {
141 context->lo |= value & VTD_PAGE_MASK;
142 }
143
144 static inline void context_set_address_width(struct context_entry *context,
145 unsigned long value)
146 {
147 context->hi |= value & 7;
148 }
149
150 static inline void context_set_domain_id(struct context_entry *context,
151 unsigned long value)
152 {
153 context->hi |= (value & ((1 << 16) - 1)) << 8;
154 }
155
156 static inline void context_clear_entry(struct context_entry *context)
157 {
158 context->lo = 0;
159 context->hi = 0;
160 }
161
162 /*
163 * 0: readable
164 * 1: writable
165 * 2-6: reserved
166 * 7: super page
167 * 8-10: available
168 * 11: snoop behavior
169 * 12-63: Host physcial address
170 */
171 struct dma_pte {
172 u64 val;
173 };
174
175 static inline void dma_clear_pte(struct dma_pte *pte)
176 {
177 pte->val = 0;
178 }
179
180 static inline void dma_set_pte_readable(struct dma_pte *pte)
181 {
182 pte->val |= DMA_PTE_READ;
183 }
184
185 static inline void dma_set_pte_writable(struct dma_pte *pte)
186 {
187 pte->val |= DMA_PTE_WRITE;
188 }
189
190 static inline void dma_set_pte_snp(struct dma_pte *pte)
191 {
192 pte->val |= DMA_PTE_SNP;
193 }
194
195 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
196 {
197 pte->val = (pte->val & ~3) | (prot & 3);
198 }
199
200 static inline u64 dma_pte_addr(struct dma_pte *pte)
201 {
202 return (pte->val & VTD_PAGE_MASK);
203 }
204
205 static inline void dma_set_pte_addr(struct dma_pte *pte, u64 addr)
206 {
207 pte->val |= (addr & VTD_PAGE_MASK);
208 }
209
210 static inline bool dma_pte_present(struct dma_pte *pte)
211 {
212 return (pte->val & 3) != 0;
213 }
214
215 /* devices under the same p2p bridge are owned in one domain */
216 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
217
218 /* domain represents a virtual machine, more than one devices
219 * across iommus may be owned in one domain, e.g. kvm guest.
220 */
221 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
222
223 struct dmar_domain {
224 int id; /* domain id */
225 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
226
227 struct list_head devices; /* all devices' list */
228 struct iova_domain iovad; /* iova's that belong to this domain */
229
230 struct dma_pte *pgd; /* virtual address */
231 spinlock_t mapping_lock; /* page table lock */
232 int gaw; /* max guest address width */
233
234 /* adjusted guest address width, 0 is level 2 30-bit */
235 int agaw;
236
237 int flags; /* flags to find out type of domain */
238
239 int iommu_coherency;/* indicate coherency of iommu access */
240 int iommu_snooping; /* indicate snooping control feature*/
241 int iommu_count; /* reference count of iommu */
242 spinlock_t iommu_lock; /* protect iommu set in domain */
243 u64 max_addr; /* maximum mapped address */
244 };
245
246 /* PCI domain-device relationship */
247 struct device_domain_info {
248 struct list_head link; /* link to domain siblings */
249 struct list_head global; /* link to global list */
250 u8 bus; /* PCI bus numer */
251 u8 devfn; /* PCI devfn number */
252 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
253 struct dmar_domain *domain; /* pointer to domain */
254 };
255
256 static void flush_unmaps_timeout(unsigned long data);
257
258 DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
259
260 #define HIGH_WATER_MARK 250
261 struct deferred_flush_tables {
262 int next;
263 struct iova *iova[HIGH_WATER_MARK];
264 struct dmar_domain *domain[HIGH_WATER_MARK];
265 };
266
267 static struct deferred_flush_tables *deferred_flush;
268
269 /* bitmap for indexing intel_iommus */
270 static int g_num_of_iommus;
271
272 static DEFINE_SPINLOCK(async_umap_flush_lock);
273 static LIST_HEAD(unmaps_to_do);
274
275 static int timer_on;
276 static long list_size;
277
278 static void domain_remove_dev_info(struct dmar_domain *domain);
279
280 #ifdef CONFIG_DMAR_DEFAULT_ON
281 int dmar_disabled = 0;
282 #else
283 int dmar_disabled = 1;
284 #endif /*CONFIG_DMAR_DEFAULT_ON*/
285
286 static int __initdata dmar_map_gfx = 1;
287 static int dmar_forcedac;
288 static int intel_iommu_strict;
289
290 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
291 static DEFINE_SPINLOCK(device_domain_lock);
292 static LIST_HEAD(device_domain_list);
293
294 static struct iommu_ops intel_iommu_ops;
295
296 static int __init intel_iommu_setup(char *str)
297 {
298 if (!str)
299 return -EINVAL;
300 while (*str) {
301 if (!strncmp(str, "on", 2)) {
302 dmar_disabled = 0;
303 printk(KERN_INFO "Intel-IOMMU: enabled\n");
304 } else if (!strncmp(str, "off", 3)) {
305 dmar_disabled = 1;
306 printk(KERN_INFO "Intel-IOMMU: disabled\n");
307 } else if (!strncmp(str, "igfx_off", 8)) {
308 dmar_map_gfx = 0;
309 printk(KERN_INFO
310 "Intel-IOMMU: disable GFX device mapping\n");
311 } else if (!strncmp(str, "forcedac", 8)) {
312 printk(KERN_INFO
313 "Intel-IOMMU: Forcing DAC for PCI devices\n");
314 dmar_forcedac = 1;
315 } else if (!strncmp(str, "strict", 6)) {
316 printk(KERN_INFO
317 "Intel-IOMMU: disable batched IOTLB flush\n");
318 intel_iommu_strict = 1;
319 }
320
321 str += strcspn(str, ",");
322 while (*str == ',')
323 str++;
324 }
325 return 0;
326 }
327 __setup("intel_iommu=", intel_iommu_setup);
328
329 static struct kmem_cache *iommu_domain_cache;
330 static struct kmem_cache *iommu_devinfo_cache;
331 static struct kmem_cache *iommu_iova_cache;
332
333 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
334 {
335 unsigned int flags;
336 void *vaddr;
337
338 /* trying to avoid low memory issues */
339 flags = current->flags & PF_MEMALLOC;
340 current->flags |= PF_MEMALLOC;
341 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
342 current->flags &= (~PF_MEMALLOC | flags);
343 return vaddr;
344 }
345
346
347 static inline void *alloc_pgtable_page(void)
348 {
349 unsigned int flags;
350 void *vaddr;
351
352 /* trying to avoid low memory issues */
353 flags = current->flags & PF_MEMALLOC;
354 current->flags |= PF_MEMALLOC;
355 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
356 current->flags &= (~PF_MEMALLOC | flags);
357 return vaddr;
358 }
359
360 static inline void free_pgtable_page(void *vaddr)
361 {
362 free_page((unsigned long)vaddr);
363 }
364
365 static inline void *alloc_domain_mem(void)
366 {
367 return iommu_kmem_cache_alloc(iommu_domain_cache);
368 }
369
370 static void free_domain_mem(void *vaddr)
371 {
372 kmem_cache_free(iommu_domain_cache, vaddr);
373 }
374
375 static inline void * alloc_devinfo_mem(void)
376 {
377 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
378 }
379
380 static inline void free_devinfo_mem(void *vaddr)
381 {
382 kmem_cache_free(iommu_devinfo_cache, vaddr);
383 }
384
385 struct iova *alloc_iova_mem(void)
386 {
387 return iommu_kmem_cache_alloc(iommu_iova_cache);
388 }
389
390 void free_iova_mem(struct iova *iova)
391 {
392 kmem_cache_free(iommu_iova_cache, iova);
393 }
394
395
396 static inline int width_to_agaw(int width);
397
398 /* calculate agaw for each iommu.
399 * "SAGAW" may be different across iommus, use a default agaw, and
400 * get a supported less agaw for iommus that don't support the default agaw.
401 */
402 int iommu_calculate_agaw(struct intel_iommu *iommu)
403 {
404 unsigned long sagaw;
405 int agaw = -1;
406
407 sagaw = cap_sagaw(iommu->cap);
408 for (agaw = width_to_agaw(DEFAULT_DOMAIN_ADDRESS_WIDTH);
409 agaw >= 0; agaw--) {
410 if (test_bit(agaw, &sagaw))
411 break;
412 }
413
414 return agaw;
415 }
416
417 /* in native case, each domain is related to only one iommu */
418 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
419 {
420 int iommu_id;
421
422 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
423
424 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
425 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
426 return NULL;
427
428 return g_iommus[iommu_id];
429 }
430
431 static void domain_update_iommu_coherency(struct dmar_domain *domain)
432 {
433 int i;
434
435 domain->iommu_coherency = 1;
436
437 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
438 for (; i < g_num_of_iommus; ) {
439 if (!ecap_coherent(g_iommus[i]->ecap)) {
440 domain->iommu_coherency = 0;
441 break;
442 }
443 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
444 }
445 }
446
447 static void domain_update_iommu_snooping(struct dmar_domain *domain)
448 {
449 int i;
450
451 domain->iommu_snooping = 1;
452
453 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
454 for (; i < g_num_of_iommus; ) {
455 if (!ecap_sc_support(g_iommus[i]->ecap)) {
456 domain->iommu_snooping = 0;
457 break;
458 }
459 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
460 }
461 }
462
463 /* Some capabilities may be different across iommus */
464 static void domain_update_iommu_cap(struct dmar_domain *domain)
465 {
466 domain_update_iommu_coherency(domain);
467 domain_update_iommu_snooping(domain);
468 }
469
470 static struct intel_iommu *device_to_iommu(u8 bus, u8 devfn)
471 {
472 struct dmar_drhd_unit *drhd = NULL;
473 int i;
474
475 for_each_drhd_unit(drhd) {
476 if (drhd->ignored)
477 continue;
478
479 for (i = 0; i < drhd->devices_cnt; i++)
480 if (drhd->devices[i] &&
481 drhd->devices[i]->bus->number == bus &&
482 drhd->devices[i]->devfn == devfn)
483 return drhd->iommu;
484
485 if (drhd->include_all)
486 return drhd->iommu;
487 }
488
489 return NULL;
490 }
491
492 static void domain_flush_cache(struct dmar_domain *domain,
493 void *addr, int size)
494 {
495 if (!domain->iommu_coherency)
496 clflush_cache_range(addr, size);
497 }
498
499 /* Gets context entry for a given bus and devfn */
500 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
501 u8 bus, u8 devfn)
502 {
503 struct root_entry *root;
504 struct context_entry *context;
505 unsigned long phy_addr;
506 unsigned long flags;
507
508 spin_lock_irqsave(&iommu->lock, flags);
509 root = &iommu->root_entry[bus];
510 context = get_context_addr_from_root(root);
511 if (!context) {
512 context = (struct context_entry *)alloc_pgtable_page();
513 if (!context) {
514 spin_unlock_irqrestore(&iommu->lock, flags);
515 return NULL;
516 }
517 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
518 phy_addr = virt_to_phys((void *)context);
519 set_root_value(root, phy_addr);
520 set_root_present(root);
521 __iommu_flush_cache(iommu, root, sizeof(*root));
522 }
523 spin_unlock_irqrestore(&iommu->lock, flags);
524 return &context[devfn];
525 }
526
527 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
528 {
529 struct root_entry *root;
530 struct context_entry *context;
531 int ret;
532 unsigned long flags;
533
534 spin_lock_irqsave(&iommu->lock, flags);
535 root = &iommu->root_entry[bus];
536 context = get_context_addr_from_root(root);
537 if (!context) {
538 ret = 0;
539 goto out;
540 }
541 ret = context_present(&context[devfn]);
542 out:
543 spin_unlock_irqrestore(&iommu->lock, flags);
544 return ret;
545 }
546
547 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
548 {
549 struct root_entry *root;
550 struct context_entry *context;
551 unsigned long flags;
552
553 spin_lock_irqsave(&iommu->lock, flags);
554 root = &iommu->root_entry[bus];
555 context = get_context_addr_from_root(root);
556 if (context) {
557 context_clear_entry(&context[devfn]);
558 __iommu_flush_cache(iommu, &context[devfn], \
559 sizeof(*context));
560 }
561 spin_unlock_irqrestore(&iommu->lock, flags);
562 }
563
564 static void free_context_table(struct intel_iommu *iommu)
565 {
566 struct root_entry *root;
567 int i;
568 unsigned long flags;
569 struct context_entry *context;
570
571 spin_lock_irqsave(&iommu->lock, flags);
572 if (!iommu->root_entry) {
573 goto out;
574 }
575 for (i = 0; i < ROOT_ENTRY_NR; i++) {
576 root = &iommu->root_entry[i];
577 context = get_context_addr_from_root(root);
578 if (context)
579 free_pgtable_page(context);
580 }
581 free_pgtable_page(iommu->root_entry);
582 iommu->root_entry = NULL;
583 out:
584 spin_unlock_irqrestore(&iommu->lock, flags);
585 }
586
587 /* page table handling */
588 #define LEVEL_STRIDE (9)
589 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
590
591 static inline int agaw_to_level(int agaw)
592 {
593 return agaw + 2;
594 }
595
596 static inline int agaw_to_width(int agaw)
597 {
598 return 30 + agaw * LEVEL_STRIDE;
599
600 }
601
602 static inline int width_to_agaw(int width)
603 {
604 return (width - 30) / LEVEL_STRIDE;
605 }
606
607 static inline unsigned int level_to_offset_bits(int level)
608 {
609 return (12 + (level - 1) * LEVEL_STRIDE);
610 }
611
612 static inline int address_level_offset(u64 addr, int level)
613 {
614 return ((addr >> level_to_offset_bits(level)) & LEVEL_MASK);
615 }
616
617 static inline u64 level_mask(int level)
618 {
619 return ((u64)-1 << level_to_offset_bits(level));
620 }
621
622 static inline u64 level_size(int level)
623 {
624 return ((u64)1 << level_to_offset_bits(level));
625 }
626
627 static inline u64 align_to_level(u64 addr, int level)
628 {
629 return ((addr + level_size(level) - 1) & level_mask(level));
630 }
631
632 static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr)
633 {
634 int addr_width = agaw_to_width(domain->agaw);
635 struct dma_pte *parent, *pte = NULL;
636 int level = agaw_to_level(domain->agaw);
637 int offset;
638 unsigned long flags;
639
640 BUG_ON(!domain->pgd);
641
642 addr &= (((u64)1) << addr_width) - 1;
643 parent = domain->pgd;
644
645 spin_lock_irqsave(&domain->mapping_lock, flags);
646 while (level > 0) {
647 void *tmp_page;
648
649 offset = address_level_offset(addr, level);
650 pte = &parent[offset];
651 if (level == 1)
652 break;
653
654 if (!dma_pte_present(pte)) {
655 tmp_page = alloc_pgtable_page();
656
657 if (!tmp_page) {
658 spin_unlock_irqrestore(&domain->mapping_lock,
659 flags);
660 return NULL;
661 }
662 domain_flush_cache(domain, tmp_page, PAGE_SIZE);
663 dma_set_pte_addr(pte, virt_to_phys(tmp_page));
664 /*
665 * high level table always sets r/w, last level page
666 * table control read/write
667 */
668 dma_set_pte_readable(pte);
669 dma_set_pte_writable(pte);
670 domain_flush_cache(domain, pte, sizeof(*pte));
671 }
672 parent = phys_to_virt(dma_pte_addr(pte));
673 level--;
674 }
675
676 spin_unlock_irqrestore(&domain->mapping_lock, flags);
677 return pte;
678 }
679
680 /* return address's pte at specific level */
681 static struct dma_pte *dma_addr_level_pte(struct dmar_domain *domain, u64 addr,
682 int level)
683 {
684 struct dma_pte *parent, *pte = NULL;
685 int total = agaw_to_level(domain->agaw);
686 int offset;
687
688 parent = domain->pgd;
689 while (level <= total) {
690 offset = address_level_offset(addr, total);
691 pte = &parent[offset];
692 if (level == total)
693 return pte;
694
695 if (!dma_pte_present(pte))
696 break;
697 parent = phys_to_virt(dma_pte_addr(pte));
698 total--;
699 }
700 return NULL;
701 }
702
703 /* clear one page's page table */
704 static void dma_pte_clear_one(struct dmar_domain *domain, u64 addr)
705 {
706 struct dma_pte *pte = NULL;
707
708 /* get last level pte */
709 pte = dma_addr_level_pte(domain, addr, 1);
710
711 if (pte) {
712 dma_clear_pte(pte);
713 domain_flush_cache(domain, pte, sizeof(*pte));
714 }
715 }
716
717 /* clear last level pte, a tlb flush should be followed */
718 static void dma_pte_clear_range(struct dmar_domain *domain, u64 start, u64 end)
719 {
720 int addr_width = agaw_to_width(domain->agaw);
721 int npages;
722
723 start &= (((u64)1) << addr_width) - 1;
724 end &= (((u64)1) << addr_width) - 1;
725 /* in case it's partial page */
726 start = PAGE_ALIGN(start);
727 end &= PAGE_MASK;
728 npages = (end - start) / VTD_PAGE_SIZE;
729
730 /* we don't need lock here, nobody else touches the iova range */
731 while (npages--) {
732 dma_pte_clear_one(domain, start);
733 start += VTD_PAGE_SIZE;
734 }
735 }
736
737 /* free page table pages. last level pte should already be cleared */
738 static void dma_pte_free_pagetable(struct dmar_domain *domain,
739 u64 start, u64 end)
740 {
741 int addr_width = agaw_to_width(domain->agaw);
742 struct dma_pte *pte;
743 int total = agaw_to_level(domain->agaw);
744 int level;
745 u64 tmp;
746
747 start &= (((u64)1) << addr_width) - 1;
748 end &= (((u64)1) << addr_width) - 1;
749
750 /* we don't need lock here, nobody else touches the iova range */
751 level = 2;
752 while (level <= total) {
753 tmp = align_to_level(start, level);
754 if (tmp >= end || (tmp + level_size(level) > end))
755 return;
756
757 while (tmp < end) {
758 pte = dma_addr_level_pte(domain, tmp, level);
759 if (pte) {
760 free_pgtable_page(
761 phys_to_virt(dma_pte_addr(pte)));
762 dma_clear_pte(pte);
763 domain_flush_cache(domain, pte, sizeof(*pte));
764 }
765 tmp += level_size(level);
766 }
767 level++;
768 }
769 /* free pgd */
770 if (start == 0 && end >= ((((u64)1) << addr_width) - 1)) {
771 free_pgtable_page(domain->pgd);
772 domain->pgd = NULL;
773 }
774 }
775
776 /* iommu handling */
777 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
778 {
779 struct root_entry *root;
780 unsigned long flags;
781
782 root = (struct root_entry *)alloc_pgtable_page();
783 if (!root)
784 return -ENOMEM;
785
786 __iommu_flush_cache(iommu, root, ROOT_SIZE);
787
788 spin_lock_irqsave(&iommu->lock, flags);
789 iommu->root_entry = root;
790 spin_unlock_irqrestore(&iommu->lock, flags);
791
792 return 0;
793 }
794
795 static void iommu_set_root_entry(struct intel_iommu *iommu)
796 {
797 void *addr;
798 u32 cmd, sts;
799 unsigned long flag;
800
801 addr = iommu->root_entry;
802
803 spin_lock_irqsave(&iommu->register_lock, flag);
804 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
805
806 cmd = iommu->gcmd | DMA_GCMD_SRTP;
807 writel(cmd, iommu->reg + DMAR_GCMD_REG);
808
809 /* Make sure hardware complete it */
810 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
811 readl, (sts & DMA_GSTS_RTPS), sts);
812
813 spin_unlock_irqrestore(&iommu->register_lock, flag);
814 }
815
816 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
817 {
818 u32 val;
819 unsigned long flag;
820
821 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
822 return;
823 val = iommu->gcmd | DMA_GCMD_WBF;
824
825 spin_lock_irqsave(&iommu->register_lock, flag);
826 writel(val, iommu->reg + DMAR_GCMD_REG);
827
828 /* Make sure hardware complete it */
829 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
830 readl, (!(val & DMA_GSTS_WBFS)), val);
831
832 spin_unlock_irqrestore(&iommu->register_lock, flag);
833 }
834
835 /* return value determine if we need a write buffer flush */
836 static int __iommu_flush_context(struct intel_iommu *iommu,
837 u16 did, u16 source_id, u8 function_mask, u64 type,
838 int non_present_entry_flush)
839 {
840 u64 val = 0;
841 unsigned long flag;
842
843 /*
844 * In the non-present entry flush case, if hardware doesn't cache
845 * non-present entry we do nothing and if hardware cache non-present
846 * entry, we flush entries of domain 0 (the domain id is used to cache
847 * any non-present entries)
848 */
849 if (non_present_entry_flush) {
850 if (!cap_caching_mode(iommu->cap))
851 return 1;
852 else
853 did = 0;
854 }
855
856 switch (type) {
857 case DMA_CCMD_GLOBAL_INVL:
858 val = DMA_CCMD_GLOBAL_INVL;
859 break;
860 case DMA_CCMD_DOMAIN_INVL:
861 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
862 break;
863 case DMA_CCMD_DEVICE_INVL:
864 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
865 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
866 break;
867 default:
868 BUG();
869 }
870 val |= DMA_CCMD_ICC;
871
872 spin_lock_irqsave(&iommu->register_lock, flag);
873 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
874
875 /* Make sure hardware complete it */
876 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
877 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
878
879 spin_unlock_irqrestore(&iommu->register_lock, flag);
880
881 /* flush context entry will implicitly flush write buffer */
882 return 0;
883 }
884
885 /* return value determine if we need a write buffer flush */
886 static int __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
887 u64 addr, unsigned int size_order, u64 type,
888 int non_present_entry_flush)
889 {
890 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
891 u64 val = 0, val_iva = 0;
892 unsigned long flag;
893
894 /*
895 * In the non-present entry flush case, if hardware doesn't cache
896 * non-present entry we do nothing and if hardware cache non-present
897 * entry, we flush entries of domain 0 (the domain id is used to cache
898 * any non-present entries)
899 */
900 if (non_present_entry_flush) {
901 if (!cap_caching_mode(iommu->cap))
902 return 1;
903 else
904 did = 0;
905 }
906
907 switch (type) {
908 case DMA_TLB_GLOBAL_FLUSH:
909 /* global flush doesn't need set IVA_REG */
910 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
911 break;
912 case DMA_TLB_DSI_FLUSH:
913 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
914 break;
915 case DMA_TLB_PSI_FLUSH:
916 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
917 /* Note: always flush non-leaf currently */
918 val_iva = size_order | addr;
919 break;
920 default:
921 BUG();
922 }
923 /* Note: set drain read/write */
924 #if 0
925 /*
926 * This is probably to be super secure.. Looks like we can
927 * ignore it without any impact.
928 */
929 if (cap_read_drain(iommu->cap))
930 val |= DMA_TLB_READ_DRAIN;
931 #endif
932 if (cap_write_drain(iommu->cap))
933 val |= DMA_TLB_WRITE_DRAIN;
934
935 spin_lock_irqsave(&iommu->register_lock, flag);
936 /* Note: Only uses first TLB reg currently */
937 if (val_iva)
938 dmar_writeq(iommu->reg + tlb_offset, val_iva);
939 dmar_writeq(iommu->reg + tlb_offset + 8, val);
940
941 /* Make sure hardware complete it */
942 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
943 dmar_readq, (!(val & DMA_TLB_IVT)), val);
944
945 spin_unlock_irqrestore(&iommu->register_lock, flag);
946
947 /* check IOTLB invalidation granularity */
948 if (DMA_TLB_IAIG(val) == 0)
949 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
950 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
951 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
952 (unsigned long long)DMA_TLB_IIRG(type),
953 (unsigned long long)DMA_TLB_IAIG(val));
954 /* flush iotlb entry will implicitly flush write buffer */
955 return 0;
956 }
957
958 static int iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
959 u64 addr, unsigned int pages, int non_present_entry_flush)
960 {
961 unsigned int mask;
962
963 BUG_ON(addr & (~VTD_PAGE_MASK));
964 BUG_ON(pages == 0);
965
966 /* Fallback to domain selective flush if no PSI support */
967 if (!cap_pgsel_inv(iommu->cap))
968 return iommu->flush.flush_iotlb(iommu, did, 0, 0,
969 DMA_TLB_DSI_FLUSH,
970 non_present_entry_flush);
971
972 /*
973 * PSI requires page size to be 2 ^ x, and the base address is naturally
974 * aligned to the size
975 */
976 mask = ilog2(__roundup_pow_of_two(pages));
977 /* Fallback to domain selective flush if size is too big */
978 if (mask > cap_max_amask_val(iommu->cap))
979 return iommu->flush.flush_iotlb(iommu, did, 0, 0,
980 DMA_TLB_DSI_FLUSH, non_present_entry_flush);
981
982 return iommu->flush.flush_iotlb(iommu, did, addr, mask,
983 DMA_TLB_PSI_FLUSH,
984 non_present_entry_flush);
985 }
986
987 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
988 {
989 u32 pmen;
990 unsigned long flags;
991
992 spin_lock_irqsave(&iommu->register_lock, flags);
993 pmen = readl(iommu->reg + DMAR_PMEN_REG);
994 pmen &= ~DMA_PMEN_EPM;
995 writel(pmen, iommu->reg + DMAR_PMEN_REG);
996
997 /* wait for the protected region status bit to clear */
998 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
999 readl, !(pmen & DMA_PMEN_PRS), pmen);
1000
1001 spin_unlock_irqrestore(&iommu->register_lock, flags);
1002 }
1003
1004 static int iommu_enable_translation(struct intel_iommu *iommu)
1005 {
1006 u32 sts;
1007 unsigned long flags;
1008
1009 spin_lock_irqsave(&iommu->register_lock, flags);
1010 writel(iommu->gcmd|DMA_GCMD_TE, iommu->reg + DMAR_GCMD_REG);
1011
1012 /* Make sure hardware complete it */
1013 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1014 readl, (sts & DMA_GSTS_TES), sts);
1015
1016 iommu->gcmd |= DMA_GCMD_TE;
1017 spin_unlock_irqrestore(&iommu->register_lock, flags);
1018 return 0;
1019 }
1020
1021 static int iommu_disable_translation(struct intel_iommu *iommu)
1022 {
1023 u32 sts;
1024 unsigned long flag;
1025
1026 spin_lock_irqsave(&iommu->register_lock, flag);
1027 iommu->gcmd &= ~DMA_GCMD_TE;
1028 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1029
1030 /* Make sure hardware complete it */
1031 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1032 readl, (!(sts & DMA_GSTS_TES)), sts);
1033
1034 spin_unlock_irqrestore(&iommu->register_lock, flag);
1035 return 0;
1036 }
1037
1038
1039 static int iommu_init_domains(struct intel_iommu *iommu)
1040 {
1041 unsigned long ndomains;
1042 unsigned long nlongs;
1043
1044 ndomains = cap_ndoms(iommu->cap);
1045 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1046 nlongs = BITS_TO_LONGS(ndomains);
1047
1048 /* TBD: there might be 64K domains,
1049 * consider other allocation for future chip
1050 */
1051 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1052 if (!iommu->domain_ids) {
1053 printk(KERN_ERR "Allocating domain id array failed\n");
1054 return -ENOMEM;
1055 }
1056 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1057 GFP_KERNEL);
1058 if (!iommu->domains) {
1059 printk(KERN_ERR "Allocating domain array failed\n");
1060 kfree(iommu->domain_ids);
1061 return -ENOMEM;
1062 }
1063
1064 spin_lock_init(&iommu->lock);
1065
1066 /*
1067 * if Caching mode is set, then invalid translations are tagged
1068 * with domainid 0. Hence we need to pre-allocate it.
1069 */
1070 if (cap_caching_mode(iommu->cap))
1071 set_bit(0, iommu->domain_ids);
1072 return 0;
1073 }
1074
1075
1076 static void domain_exit(struct dmar_domain *domain);
1077 static void vm_domain_exit(struct dmar_domain *domain);
1078
1079 void free_dmar_iommu(struct intel_iommu *iommu)
1080 {
1081 struct dmar_domain *domain;
1082 int i;
1083 unsigned long flags;
1084
1085 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1086 for (; i < cap_ndoms(iommu->cap); ) {
1087 domain = iommu->domains[i];
1088 clear_bit(i, iommu->domain_ids);
1089
1090 spin_lock_irqsave(&domain->iommu_lock, flags);
1091 if (--domain->iommu_count == 0) {
1092 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1093 vm_domain_exit(domain);
1094 else
1095 domain_exit(domain);
1096 }
1097 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1098
1099 i = find_next_bit(iommu->domain_ids,
1100 cap_ndoms(iommu->cap), i+1);
1101 }
1102
1103 if (iommu->gcmd & DMA_GCMD_TE)
1104 iommu_disable_translation(iommu);
1105
1106 if (iommu->irq) {
1107 set_irq_data(iommu->irq, NULL);
1108 /* This will mask the irq */
1109 free_irq(iommu->irq, iommu);
1110 destroy_irq(iommu->irq);
1111 }
1112
1113 kfree(iommu->domains);
1114 kfree(iommu->domain_ids);
1115
1116 g_iommus[iommu->seq_id] = NULL;
1117
1118 /* if all iommus are freed, free g_iommus */
1119 for (i = 0; i < g_num_of_iommus; i++) {
1120 if (g_iommus[i])
1121 break;
1122 }
1123
1124 if (i == g_num_of_iommus)
1125 kfree(g_iommus);
1126
1127 /* free context mapping */
1128 free_context_table(iommu);
1129 }
1130
1131 static struct dmar_domain * iommu_alloc_domain(struct intel_iommu *iommu)
1132 {
1133 unsigned long num;
1134 unsigned long ndomains;
1135 struct dmar_domain *domain;
1136 unsigned long flags;
1137
1138 domain = alloc_domain_mem();
1139 if (!domain)
1140 return NULL;
1141
1142 ndomains = cap_ndoms(iommu->cap);
1143
1144 spin_lock_irqsave(&iommu->lock, flags);
1145 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1146 if (num >= ndomains) {
1147 spin_unlock_irqrestore(&iommu->lock, flags);
1148 free_domain_mem(domain);
1149 printk(KERN_ERR "IOMMU: no free domain ids\n");
1150 return NULL;
1151 }
1152
1153 set_bit(num, iommu->domain_ids);
1154 domain->id = num;
1155 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1156 set_bit(iommu->seq_id, &domain->iommu_bmp);
1157 domain->flags = 0;
1158 iommu->domains[num] = domain;
1159 spin_unlock_irqrestore(&iommu->lock, flags);
1160
1161 return domain;
1162 }
1163
1164 static void iommu_free_domain(struct dmar_domain *domain)
1165 {
1166 unsigned long flags;
1167 struct intel_iommu *iommu;
1168
1169 iommu = domain_get_iommu(domain);
1170
1171 spin_lock_irqsave(&iommu->lock, flags);
1172 clear_bit(domain->id, iommu->domain_ids);
1173 spin_unlock_irqrestore(&iommu->lock, flags);
1174 }
1175
1176 static struct iova_domain reserved_iova_list;
1177 static struct lock_class_key reserved_alloc_key;
1178 static struct lock_class_key reserved_rbtree_key;
1179
1180 static void dmar_init_reserved_ranges(void)
1181 {
1182 struct pci_dev *pdev = NULL;
1183 struct iova *iova;
1184 int i;
1185 u64 addr, size;
1186
1187 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1188
1189 lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1190 &reserved_alloc_key);
1191 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1192 &reserved_rbtree_key);
1193
1194 /* IOAPIC ranges shouldn't be accessed by DMA */
1195 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1196 IOVA_PFN(IOAPIC_RANGE_END));
1197 if (!iova)
1198 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1199
1200 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1201 for_each_pci_dev(pdev) {
1202 struct resource *r;
1203
1204 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1205 r = &pdev->resource[i];
1206 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1207 continue;
1208 addr = r->start;
1209 addr &= PAGE_MASK;
1210 size = r->end - addr;
1211 size = PAGE_ALIGN(size);
1212 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(addr),
1213 IOVA_PFN(size + addr) - 1);
1214 if (!iova)
1215 printk(KERN_ERR "Reserve iova failed\n");
1216 }
1217 }
1218
1219 }
1220
1221 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1222 {
1223 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1224 }
1225
1226 static inline int guestwidth_to_adjustwidth(int gaw)
1227 {
1228 int agaw;
1229 int r = (gaw - 12) % 9;
1230
1231 if (r == 0)
1232 agaw = gaw;
1233 else
1234 agaw = gaw + 9 - r;
1235 if (agaw > 64)
1236 agaw = 64;
1237 return agaw;
1238 }
1239
1240 static int domain_init(struct dmar_domain *domain, int guest_width)
1241 {
1242 struct intel_iommu *iommu;
1243 int adjust_width, agaw;
1244 unsigned long sagaw;
1245
1246 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1247 spin_lock_init(&domain->mapping_lock);
1248 spin_lock_init(&domain->iommu_lock);
1249
1250 domain_reserve_special_ranges(domain);
1251
1252 /* calculate AGAW */
1253 iommu = domain_get_iommu(domain);
1254 if (guest_width > cap_mgaw(iommu->cap))
1255 guest_width = cap_mgaw(iommu->cap);
1256 domain->gaw = guest_width;
1257 adjust_width = guestwidth_to_adjustwidth(guest_width);
1258 agaw = width_to_agaw(adjust_width);
1259 sagaw = cap_sagaw(iommu->cap);
1260 if (!test_bit(agaw, &sagaw)) {
1261 /* hardware doesn't support it, choose a bigger one */
1262 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1263 agaw = find_next_bit(&sagaw, 5, agaw);
1264 if (agaw >= 5)
1265 return -ENODEV;
1266 }
1267 domain->agaw = agaw;
1268 INIT_LIST_HEAD(&domain->devices);
1269
1270 if (ecap_coherent(iommu->ecap))
1271 domain->iommu_coherency = 1;
1272 else
1273 domain->iommu_coherency = 0;
1274
1275 if (ecap_sc_support(iommu->ecap))
1276 domain->iommu_snooping = 1;
1277 else
1278 domain->iommu_snooping = 0;
1279
1280 domain->iommu_count = 1;
1281
1282 /* always allocate the top pgd */
1283 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1284 if (!domain->pgd)
1285 return -ENOMEM;
1286 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1287 return 0;
1288 }
1289
1290 static void domain_exit(struct dmar_domain *domain)
1291 {
1292 u64 end;
1293
1294 /* Domain 0 is reserved, so dont process it */
1295 if (!domain)
1296 return;
1297
1298 domain_remove_dev_info(domain);
1299 /* destroy iovas */
1300 put_iova_domain(&domain->iovad);
1301 end = DOMAIN_MAX_ADDR(domain->gaw);
1302 end = end & (~PAGE_MASK);
1303
1304 /* clear ptes */
1305 dma_pte_clear_range(domain, 0, end);
1306
1307 /* free page tables */
1308 dma_pte_free_pagetable(domain, 0, end);
1309
1310 iommu_free_domain(domain);
1311 free_domain_mem(domain);
1312 }
1313
1314 static int domain_context_mapping_one(struct dmar_domain *domain,
1315 u8 bus, u8 devfn)
1316 {
1317 struct context_entry *context;
1318 unsigned long flags;
1319 struct intel_iommu *iommu;
1320 struct dma_pte *pgd;
1321 unsigned long num;
1322 unsigned long ndomains;
1323 int id;
1324 int agaw;
1325
1326 pr_debug("Set context mapping for %02x:%02x.%d\n",
1327 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1328 BUG_ON(!domain->pgd);
1329
1330 iommu = device_to_iommu(bus, devfn);
1331 if (!iommu)
1332 return -ENODEV;
1333
1334 context = device_to_context_entry(iommu, bus, devfn);
1335 if (!context)
1336 return -ENOMEM;
1337 spin_lock_irqsave(&iommu->lock, flags);
1338 if (context_present(context)) {
1339 spin_unlock_irqrestore(&iommu->lock, flags);
1340 return 0;
1341 }
1342
1343 id = domain->id;
1344 pgd = domain->pgd;
1345
1346 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) {
1347 int found = 0;
1348
1349 /* find an available domain id for this device in iommu */
1350 ndomains = cap_ndoms(iommu->cap);
1351 num = find_first_bit(iommu->domain_ids, ndomains);
1352 for (; num < ndomains; ) {
1353 if (iommu->domains[num] == domain) {
1354 id = num;
1355 found = 1;
1356 break;
1357 }
1358 num = find_next_bit(iommu->domain_ids,
1359 cap_ndoms(iommu->cap), num+1);
1360 }
1361
1362 if (found == 0) {
1363 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1364 if (num >= ndomains) {
1365 spin_unlock_irqrestore(&iommu->lock, flags);
1366 printk(KERN_ERR "IOMMU: no free domain ids\n");
1367 return -EFAULT;
1368 }
1369
1370 set_bit(num, iommu->domain_ids);
1371 iommu->domains[num] = domain;
1372 id = num;
1373 }
1374
1375 /* Skip top levels of page tables for
1376 * iommu which has less agaw than default.
1377 */
1378 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1379 pgd = phys_to_virt(dma_pte_addr(pgd));
1380 if (!dma_pte_present(pgd)) {
1381 spin_unlock_irqrestore(&iommu->lock, flags);
1382 return -ENOMEM;
1383 }
1384 }
1385 }
1386
1387 context_set_domain_id(context, id);
1388 context_set_address_width(context, iommu->agaw);
1389 context_set_address_root(context, virt_to_phys(pgd));
1390 context_set_translation_type(context, CONTEXT_TT_MULTI_LEVEL);
1391 context_set_fault_enable(context);
1392 context_set_present(context);
1393 domain_flush_cache(domain, context, sizeof(*context));
1394
1395 /* it's a non-present to present mapping */
1396 if (iommu->flush.flush_context(iommu, domain->id,
1397 (((u16)bus) << 8) | devfn, DMA_CCMD_MASK_NOBIT,
1398 DMA_CCMD_DEVICE_INVL, 1))
1399 iommu_flush_write_buffer(iommu);
1400 else
1401 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH, 0);
1402
1403 spin_unlock_irqrestore(&iommu->lock, flags);
1404
1405 spin_lock_irqsave(&domain->iommu_lock, flags);
1406 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1407 domain->iommu_count++;
1408 domain_update_iommu_cap(domain);
1409 }
1410 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1411 return 0;
1412 }
1413
1414 static int
1415 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev)
1416 {
1417 int ret;
1418 struct pci_dev *tmp, *parent;
1419
1420 ret = domain_context_mapping_one(domain, pdev->bus->number,
1421 pdev->devfn);
1422 if (ret)
1423 return ret;
1424
1425 /* dependent device mapping */
1426 tmp = pci_find_upstream_pcie_bridge(pdev);
1427 if (!tmp)
1428 return 0;
1429 /* Secondary interface's bus number and devfn 0 */
1430 parent = pdev->bus->self;
1431 while (parent != tmp) {
1432 ret = domain_context_mapping_one(domain, parent->bus->number,
1433 parent->devfn);
1434 if (ret)
1435 return ret;
1436 parent = parent->bus->self;
1437 }
1438 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1439 return domain_context_mapping_one(domain,
1440 tmp->subordinate->number, 0);
1441 else /* this is a legacy PCI bridge */
1442 return domain_context_mapping_one(domain,
1443 tmp->bus->number, tmp->devfn);
1444 }
1445
1446 static int domain_context_mapped(struct pci_dev *pdev)
1447 {
1448 int ret;
1449 struct pci_dev *tmp, *parent;
1450 struct intel_iommu *iommu;
1451
1452 iommu = device_to_iommu(pdev->bus->number, pdev->devfn);
1453 if (!iommu)
1454 return -ENODEV;
1455
1456 ret = device_context_mapped(iommu,
1457 pdev->bus->number, pdev->devfn);
1458 if (!ret)
1459 return ret;
1460 /* dependent device mapping */
1461 tmp = pci_find_upstream_pcie_bridge(pdev);
1462 if (!tmp)
1463 return ret;
1464 /* Secondary interface's bus number and devfn 0 */
1465 parent = pdev->bus->self;
1466 while (parent != tmp) {
1467 ret = device_context_mapped(iommu, parent->bus->number,
1468 parent->devfn);
1469 if (!ret)
1470 return ret;
1471 parent = parent->bus->self;
1472 }
1473 if (tmp->is_pcie)
1474 return device_context_mapped(iommu,
1475 tmp->subordinate->number, 0);
1476 else
1477 return device_context_mapped(iommu,
1478 tmp->bus->number, tmp->devfn);
1479 }
1480
1481 static int
1482 domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
1483 u64 hpa, size_t size, int prot)
1484 {
1485 u64 start_pfn, end_pfn;
1486 struct dma_pte *pte;
1487 int index;
1488 int addr_width = agaw_to_width(domain->agaw);
1489
1490 hpa &= (((u64)1) << addr_width) - 1;
1491
1492 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1493 return -EINVAL;
1494 iova &= PAGE_MASK;
1495 start_pfn = ((u64)hpa) >> VTD_PAGE_SHIFT;
1496 end_pfn = (VTD_PAGE_ALIGN(((u64)hpa) + size)) >> VTD_PAGE_SHIFT;
1497 index = 0;
1498 while (start_pfn < end_pfn) {
1499 pte = addr_to_dma_pte(domain, iova + VTD_PAGE_SIZE * index);
1500 if (!pte)
1501 return -ENOMEM;
1502 /* We don't need lock here, nobody else
1503 * touches the iova range
1504 */
1505 BUG_ON(dma_pte_addr(pte));
1506 dma_set_pte_addr(pte, start_pfn << VTD_PAGE_SHIFT);
1507 dma_set_pte_prot(pte, prot);
1508 if (prot & DMA_PTE_SNP)
1509 dma_set_pte_snp(pte);
1510 domain_flush_cache(domain, pte, sizeof(*pte));
1511 start_pfn++;
1512 index++;
1513 }
1514 return 0;
1515 }
1516
1517 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1518 {
1519 if (!iommu)
1520 return;
1521
1522 clear_context_table(iommu, bus, devfn);
1523 iommu->flush.flush_context(iommu, 0, 0, 0,
1524 DMA_CCMD_GLOBAL_INVL, 0);
1525 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1526 DMA_TLB_GLOBAL_FLUSH, 0);
1527 }
1528
1529 static void domain_remove_dev_info(struct dmar_domain *domain)
1530 {
1531 struct device_domain_info *info;
1532 unsigned long flags;
1533 struct intel_iommu *iommu;
1534
1535 spin_lock_irqsave(&device_domain_lock, flags);
1536 while (!list_empty(&domain->devices)) {
1537 info = list_entry(domain->devices.next,
1538 struct device_domain_info, link);
1539 list_del(&info->link);
1540 list_del(&info->global);
1541 if (info->dev)
1542 info->dev->dev.archdata.iommu = NULL;
1543 spin_unlock_irqrestore(&device_domain_lock, flags);
1544
1545 iommu = device_to_iommu(info->bus, info->devfn);
1546 iommu_detach_dev(iommu, info->bus, info->devfn);
1547 free_devinfo_mem(info);
1548
1549 spin_lock_irqsave(&device_domain_lock, flags);
1550 }
1551 spin_unlock_irqrestore(&device_domain_lock, flags);
1552 }
1553
1554 /*
1555 * find_domain
1556 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1557 */
1558 static struct dmar_domain *
1559 find_domain(struct pci_dev *pdev)
1560 {
1561 struct device_domain_info *info;
1562
1563 /* No lock here, assumes no domain exit in normal case */
1564 info = pdev->dev.archdata.iommu;
1565 if (info)
1566 return info->domain;
1567 return NULL;
1568 }
1569
1570 /* domain is initialized */
1571 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1572 {
1573 struct dmar_domain *domain, *found = NULL;
1574 struct intel_iommu *iommu;
1575 struct dmar_drhd_unit *drhd;
1576 struct device_domain_info *info, *tmp;
1577 struct pci_dev *dev_tmp;
1578 unsigned long flags;
1579 int bus = 0, devfn = 0;
1580
1581 domain = find_domain(pdev);
1582 if (domain)
1583 return domain;
1584
1585 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1586 if (dev_tmp) {
1587 if (dev_tmp->is_pcie) {
1588 bus = dev_tmp->subordinate->number;
1589 devfn = 0;
1590 } else {
1591 bus = dev_tmp->bus->number;
1592 devfn = dev_tmp->devfn;
1593 }
1594 spin_lock_irqsave(&device_domain_lock, flags);
1595 list_for_each_entry(info, &device_domain_list, global) {
1596 if (info->bus == bus && info->devfn == devfn) {
1597 found = info->domain;
1598 break;
1599 }
1600 }
1601 spin_unlock_irqrestore(&device_domain_lock, flags);
1602 /* pcie-pci bridge already has a domain, uses it */
1603 if (found) {
1604 domain = found;
1605 goto found_domain;
1606 }
1607 }
1608
1609 /* Allocate new domain for the device */
1610 drhd = dmar_find_matched_drhd_unit(pdev);
1611 if (!drhd) {
1612 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1613 pci_name(pdev));
1614 return NULL;
1615 }
1616 iommu = drhd->iommu;
1617
1618 domain = iommu_alloc_domain(iommu);
1619 if (!domain)
1620 goto error;
1621
1622 if (domain_init(domain, gaw)) {
1623 domain_exit(domain);
1624 goto error;
1625 }
1626
1627 /* register pcie-to-pci device */
1628 if (dev_tmp) {
1629 info = alloc_devinfo_mem();
1630 if (!info) {
1631 domain_exit(domain);
1632 goto error;
1633 }
1634 info->bus = bus;
1635 info->devfn = devfn;
1636 info->dev = NULL;
1637 info->domain = domain;
1638 /* This domain is shared by devices under p2p bridge */
1639 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1640
1641 /* pcie-to-pci bridge already has a domain, uses it */
1642 found = NULL;
1643 spin_lock_irqsave(&device_domain_lock, flags);
1644 list_for_each_entry(tmp, &device_domain_list, global) {
1645 if (tmp->bus == bus && tmp->devfn == devfn) {
1646 found = tmp->domain;
1647 break;
1648 }
1649 }
1650 if (found) {
1651 free_devinfo_mem(info);
1652 domain_exit(domain);
1653 domain = found;
1654 } else {
1655 list_add(&info->link, &domain->devices);
1656 list_add(&info->global, &device_domain_list);
1657 }
1658 spin_unlock_irqrestore(&device_domain_lock, flags);
1659 }
1660
1661 found_domain:
1662 info = alloc_devinfo_mem();
1663 if (!info)
1664 goto error;
1665 info->bus = pdev->bus->number;
1666 info->devfn = pdev->devfn;
1667 info->dev = pdev;
1668 info->domain = domain;
1669 spin_lock_irqsave(&device_domain_lock, flags);
1670 /* somebody is fast */
1671 found = find_domain(pdev);
1672 if (found != NULL) {
1673 spin_unlock_irqrestore(&device_domain_lock, flags);
1674 if (found != domain) {
1675 domain_exit(domain);
1676 domain = found;
1677 }
1678 free_devinfo_mem(info);
1679 return domain;
1680 }
1681 list_add(&info->link, &domain->devices);
1682 list_add(&info->global, &device_domain_list);
1683 pdev->dev.archdata.iommu = info;
1684 spin_unlock_irqrestore(&device_domain_lock, flags);
1685 return domain;
1686 error:
1687 /* recheck it here, maybe others set it */
1688 return find_domain(pdev);
1689 }
1690
1691 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1692 unsigned long long start,
1693 unsigned long long end)
1694 {
1695 struct dmar_domain *domain;
1696 unsigned long size;
1697 unsigned long long base;
1698 int ret;
1699
1700 printk(KERN_INFO
1701 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1702 pci_name(pdev), start, end);
1703 /* page table init */
1704 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1705 if (!domain)
1706 return -ENOMEM;
1707
1708 /* The address might not be aligned */
1709 base = start & PAGE_MASK;
1710 size = end - base;
1711 size = PAGE_ALIGN(size);
1712 if (!reserve_iova(&domain->iovad, IOVA_PFN(base),
1713 IOVA_PFN(base + size) - 1)) {
1714 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1715 ret = -ENOMEM;
1716 goto error;
1717 }
1718
1719 pr_debug("Mapping reserved region %lx@%llx for %s\n",
1720 size, base, pci_name(pdev));
1721 /*
1722 * RMRR range might have overlap with physical memory range,
1723 * clear it first
1724 */
1725 dma_pte_clear_range(domain, base, base + size);
1726
1727 ret = domain_page_mapping(domain, base, base, size,
1728 DMA_PTE_READ|DMA_PTE_WRITE);
1729 if (ret)
1730 goto error;
1731
1732 /* context entry init */
1733 ret = domain_context_mapping(domain, pdev);
1734 if (!ret)
1735 return 0;
1736 error:
1737 domain_exit(domain);
1738 return ret;
1739
1740 }
1741
1742 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1743 struct pci_dev *pdev)
1744 {
1745 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1746 return 0;
1747 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1748 rmrr->end_address + 1);
1749 }
1750
1751 #ifdef CONFIG_DMAR_GFX_WA
1752 struct iommu_prepare_data {
1753 struct pci_dev *pdev;
1754 int ret;
1755 };
1756
1757 static int __init iommu_prepare_work_fn(unsigned long start_pfn,
1758 unsigned long end_pfn, void *datax)
1759 {
1760 struct iommu_prepare_data *data;
1761
1762 data = (struct iommu_prepare_data *)datax;
1763
1764 data->ret = iommu_prepare_identity_map(data->pdev,
1765 start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
1766 return data->ret;
1767
1768 }
1769
1770 static int __init iommu_prepare_with_active_regions(struct pci_dev *pdev)
1771 {
1772 int nid;
1773 struct iommu_prepare_data data;
1774
1775 data.pdev = pdev;
1776 data.ret = 0;
1777
1778 for_each_online_node(nid) {
1779 work_with_active_regions(nid, iommu_prepare_work_fn, &data);
1780 if (data.ret)
1781 return data.ret;
1782 }
1783 return data.ret;
1784 }
1785
1786 static void __init iommu_prepare_gfx_mapping(void)
1787 {
1788 struct pci_dev *pdev = NULL;
1789 int ret;
1790
1791 for_each_pci_dev(pdev) {
1792 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO ||
1793 !IS_GFX_DEVICE(pdev))
1794 continue;
1795 printk(KERN_INFO "IOMMU: gfx device %s 1-1 mapping\n",
1796 pci_name(pdev));
1797 ret = iommu_prepare_with_active_regions(pdev);
1798 if (ret)
1799 printk(KERN_ERR "IOMMU: mapping reserved region failed\n");
1800 }
1801 }
1802 #else /* !CONFIG_DMAR_GFX_WA */
1803 static inline void iommu_prepare_gfx_mapping(void)
1804 {
1805 return;
1806 }
1807 #endif
1808
1809 #ifdef CONFIG_DMAR_FLOPPY_WA
1810 static inline void iommu_prepare_isa(void)
1811 {
1812 struct pci_dev *pdev;
1813 int ret;
1814
1815 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1816 if (!pdev)
1817 return;
1818
1819 printk(KERN_INFO "IOMMU: Prepare 0-16M unity mapping for LPC\n");
1820 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1821
1822 if (ret)
1823 printk(KERN_ERR "IOMMU: Failed to create 0-64M identity map, "
1824 "floppy might not work\n");
1825
1826 }
1827 #else
1828 static inline void iommu_prepare_isa(void)
1829 {
1830 return;
1831 }
1832 #endif /* !CONFIG_DMAR_FLPY_WA */
1833
1834 static int __init init_dmars(void)
1835 {
1836 struct dmar_drhd_unit *drhd;
1837 struct dmar_rmrr_unit *rmrr;
1838 struct pci_dev *pdev;
1839 struct intel_iommu *iommu;
1840 int i, ret;
1841
1842 /*
1843 * for each drhd
1844 * allocate root
1845 * initialize and program root entry to not present
1846 * endfor
1847 */
1848 for_each_drhd_unit(drhd) {
1849 g_num_of_iommus++;
1850 /*
1851 * lock not needed as this is only incremented in the single
1852 * threaded kernel __init code path all other access are read
1853 * only
1854 */
1855 }
1856
1857 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
1858 GFP_KERNEL);
1859 if (!g_iommus) {
1860 printk(KERN_ERR "Allocating global iommu array failed\n");
1861 ret = -ENOMEM;
1862 goto error;
1863 }
1864
1865 deferred_flush = kzalloc(g_num_of_iommus *
1866 sizeof(struct deferred_flush_tables), GFP_KERNEL);
1867 if (!deferred_flush) {
1868 kfree(g_iommus);
1869 ret = -ENOMEM;
1870 goto error;
1871 }
1872
1873 for_each_drhd_unit(drhd) {
1874 if (drhd->ignored)
1875 continue;
1876
1877 iommu = drhd->iommu;
1878 g_iommus[iommu->seq_id] = iommu;
1879
1880 ret = iommu_init_domains(iommu);
1881 if (ret)
1882 goto error;
1883
1884 /*
1885 * TBD:
1886 * we could share the same root & context tables
1887 * amoung all IOMMU's. Need to Split it later.
1888 */
1889 ret = iommu_alloc_root_entry(iommu);
1890 if (ret) {
1891 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
1892 goto error;
1893 }
1894 }
1895
1896 /*
1897 * Start from the sane iommu hardware state.
1898 */
1899 for_each_drhd_unit(drhd) {
1900 if (drhd->ignored)
1901 continue;
1902
1903 iommu = drhd->iommu;
1904
1905 /*
1906 * If the queued invalidation is already initialized by us
1907 * (for example, while enabling interrupt-remapping) then
1908 * we got the things already rolling from a sane state.
1909 */
1910 if (iommu->qi)
1911 continue;
1912
1913 /*
1914 * Clear any previous faults.
1915 */
1916 dmar_fault(-1, iommu);
1917 /*
1918 * Disable queued invalidation if supported and already enabled
1919 * before OS handover.
1920 */
1921 dmar_disable_qi(iommu);
1922 }
1923
1924 for_each_drhd_unit(drhd) {
1925 if (drhd->ignored)
1926 continue;
1927
1928 iommu = drhd->iommu;
1929
1930 if (dmar_enable_qi(iommu)) {
1931 /*
1932 * Queued Invalidate not enabled, use Register Based
1933 * Invalidate
1934 */
1935 iommu->flush.flush_context = __iommu_flush_context;
1936 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
1937 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
1938 "invalidation\n",
1939 (unsigned long long)drhd->reg_base_addr);
1940 } else {
1941 iommu->flush.flush_context = qi_flush_context;
1942 iommu->flush.flush_iotlb = qi_flush_iotlb;
1943 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
1944 "invalidation\n",
1945 (unsigned long long)drhd->reg_base_addr);
1946 }
1947 }
1948
1949 /*
1950 * For each rmrr
1951 * for each dev attached to rmrr
1952 * do
1953 * locate drhd for dev, alloc domain for dev
1954 * allocate free domain
1955 * allocate page table entries for rmrr
1956 * if context not allocated for bus
1957 * allocate and init context
1958 * set present in root table for this bus
1959 * init context with domain, translation etc
1960 * endfor
1961 * endfor
1962 */
1963 for_each_rmrr_units(rmrr) {
1964 for (i = 0; i < rmrr->devices_cnt; i++) {
1965 pdev = rmrr->devices[i];
1966 /* some BIOS lists non-exist devices in DMAR table */
1967 if (!pdev)
1968 continue;
1969 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
1970 if (ret)
1971 printk(KERN_ERR
1972 "IOMMU: mapping reserved region failed\n");
1973 }
1974 }
1975
1976 iommu_prepare_gfx_mapping();
1977
1978 iommu_prepare_isa();
1979
1980 /*
1981 * for each drhd
1982 * enable fault log
1983 * global invalidate context cache
1984 * global invalidate iotlb
1985 * enable translation
1986 */
1987 for_each_drhd_unit(drhd) {
1988 if (drhd->ignored)
1989 continue;
1990 iommu = drhd->iommu;
1991
1992 iommu_flush_write_buffer(iommu);
1993
1994 ret = dmar_set_interrupt(iommu);
1995 if (ret)
1996 goto error;
1997
1998 iommu_set_root_entry(iommu);
1999
2000 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL,
2001 0);
2002 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH,
2003 0);
2004 iommu_disable_protect_mem_regions(iommu);
2005
2006 ret = iommu_enable_translation(iommu);
2007 if (ret)
2008 goto error;
2009 }
2010
2011 return 0;
2012 error:
2013 for_each_drhd_unit(drhd) {
2014 if (drhd->ignored)
2015 continue;
2016 iommu = drhd->iommu;
2017 free_iommu(iommu);
2018 }
2019 kfree(g_iommus);
2020 return ret;
2021 }
2022
2023 static inline u64 aligned_size(u64 host_addr, size_t size)
2024 {
2025 u64 addr;
2026 addr = (host_addr & (~PAGE_MASK)) + size;
2027 return PAGE_ALIGN(addr);
2028 }
2029
2030 struct iova *
2031 iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
2032 {
2033 struct iova *piova;
2034
2035 /* Make sure it's in range */
2036 end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
2037 if (!size || (IOVA_START_ADDR + size > end))
2038 return NULL;
2039
2040 piova = alloc_iova(&domain->iovad,
2041 size >> PAGE_SHIFT, IOVA_PFN(end), 1);
2042 return piova;
2043 }
2044
2045 static struct iova *
2046 __intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
2047 size_t size, u64 dma_mask)
2048 {
2049 struct pci_dev *pdev = to_pci_dev(dev);
2050 struct iova *iova = NULL;
2051
2052 if (dma_mask <= DMA_32BIT_MASK || dmar_forcedac)
2053 iova = iommu_alloc_iova(domain, size, dma_mask);
2054 else {
2055 /*
2056 * First try to allocate an io virtual address in
2057 * DMA_32BIT_MASK and if that fails then try allocating
2058 * from higher range
2059 */
2060 iova = iommu_alloc_iova(domain, size, DMA_32BIT_MASK);
2061 if (!iova)
2062 iova = iommu_alloc_iova(domain, size, dma_mask);
2063 }
2064
2065 if (!iova) {
2066 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
2067 return NULL;
2068 }
2069
2070 return iova;
2071 }
2072
2073 static struct dmar_domain *
2074 get_valid_domain_for_dev(struct pci_dev *pdev)
2075 {
2076 struct dmar_domain *domain;
2077 int ret;
2078
2079 domain = get_domain_for_dev(pdev,
2080 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2081 if (!domain) {
2082 printk(KERN_ERR
2083 "Allocating domain for %s failed", pci_name(pdev));
2084 return NULL;
2085 }
2086
2087 /* make sure context mapping is ok */
2088 if (unlikely(!domain_context_mapped(pdev))) {
2089 ret = domain_context_mapping(domain, pdev);
2090 if (ret) {
2091 printk(KERN_ERR
2092 "Domain context map for %s failed",
2093 pci_name(pdev));
2094 return NULL;
2095 }
2096 }
2097
2098 return domain;
2099 }
2100
2101 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2102 size_t size, int dir, u64 dma_mask)
2103 {
2104 struct pci_dev *pdev = to_pci_dev(hwdev);
2105 struct dmar_domain *domain;
2106 phys_addr_t start_paddr;
2107 struct iova *iova;
2108 int prot = 0;
2109 int ret;
2110 struct intel_iommu *iommu;
2111
2112 BUG_ON(dir == DMA_NONE);
2113 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2114 return paddr;
2115
2116 domain = get_valid_domain_for_dev(pdev);
2117 if (!domain)
2118 return 0;
2119
2120 iommu = domain_get_iommu(domain);
2121 size = aligned_size((u64)paddr, size);
2122
2123 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2124 if (!iova)
2125 goto error;
2126
2127 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2128
2129 /*
2130 * Check if DMAR supports zero-length reads on write only
2131 * mappings..
2132 */
2133 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2134 !cap_zlr(iommu->cap))
2135 prot |= DMA_PTE_READ;
2136 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2137 prot |= DMA_PTE_WRITE;
2138 /*
2139 * paddr - (paddr + size) might be partial page, we should map the whole
2140 * page. Note: if two part of one page are separately mapped, we
2141 * might have two guest_addr mapping to the same host paddr, but this
2142 * is not a big problem
2143 */
2144 ret = domain_page_mapping(domain, start_paddr,
2145 ((u64)paddr) & PAGE_MASK, size, prot);
2146 if (ret)
2147 goto error;
2148
2149 /* it's a non-present to present mapping */
2150 ret = iommu_flush_iotlb_psi(iommu, domain->id,
2151 start_paddr, size >> VTD_PAGE_SHIFT, 1);
2152 if (ret)
2153 iommu_flush_write_buffer(iommu);
2154
2155 return start_paddr + ((u64)paddr & (~PAGE_MASK));
2156
2157 error:
2158 if (iova)
2159 __free_iova(&domain->iovad, iova);
2160 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2161 pci_name(pdev), size, (unsigned long long)paddr, dir);
2162 return 0;
2163 }
2164
2165 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2166 unsigned long offset, size_t size,
2167 enum dma_data_direction dir,
2168 struct dma_attrs *attrs)
2169 {
2170 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2171 dir, to_pci_dev(dev)->dma_mask);
2172 }
2173
2174 static void flush_unmaps(void)
2175 {
2176 int i, j;
2177
2178 timer_on = 0;
2179
2180 /* just flush them all */
2181 for (i = 0; i < g_num_of_iommus; i++) {
2182 struct intel_iommu *iommu = g_iommus[i];
2183 if (!iommu)
2184 continue;
2185
2186 if (deferred_flush[i].next) {
2187 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2188 DMA_TLB_GLOBAL_FLUSH, 0);
2189 for (j = 0; j < deferred_flush[i].next; j++) {
2190 __free_iova(&deferred_flush[i].domain[j]->iovad,
2191 deferred_flush[i].iova[j]);
2192 }
2193 deferred_flush[i].next = 0;
2194 }
2195 }
2196
2197 list_size = 0;
2198 }
2199
2200 static void flush_unmaps_timeout(unsigned long data)
2201 {
2202 unsigned long flags;
2203
2204 spin_lock_irqsave(&async_umap_flush_lock, flags);
2205 flush_unmaps();
2206 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2207 }
2208
2209 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2210 {
2211 unsigned long flags;
2212 int next, iommu_id;
2213 struct intel_iommu *iommu;
2214
2215 spin_lock_irqsave(&async_umap_flush_lock, flags);
2216 if (list_size == HIGH_WATER_MARK)
2217 flush_unmaps();
2218
2219 iommu = domain_get_iommu(dom);
2220 iommu_id = iommu->seq_id;
2221
2222 next = deferred_flush[iommu_id].next;
2223 deferred_flush[iommu_id].domain[next] = dom;
2224 deferred_flush[iommu_id].iova[next] = iova;
2225 deferred_flush[iommu_id].next++;
2226
2227 if (!timer_on) {
2228 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2229 timer_on = 1;
2230 }
2231 list_size++;
2232 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2233 }
2234
2235 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2236 size_t size, enum dma_data_direction dir,
2237 struct dma_attrs *attrs)
2238 {
2239 struct pci_dev *pdev = to_pci_dev(dev);
2240 struct dmar_domain *domain;
2241 unsigned long start_addr;
2242 struct iova *iova;
2243 struct intel_iommu *iommu;
2244
2245 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2246 return;
2247 domain = find_domain(pdev);
2248 BUG_ON(!domain);
2249
2250 iommu = domain_get_iommu(domain);
2251
2252 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2253 if (!iova)
2254 return;
2255
2256 start_addr = iova->pfn_lo << PAGE_SHIFT;
2257 size = aligned_size((u64)dev_addr, size);
2258
2259 pr_debug("Device %s unmapping: %zx@%llx\n",
2260 pci_name(pdev), size, (unsigned long long)start_addr);
2261
2262 /* clear the whole page */
2263 dma_pte_clear_range(domain, start_addr, start_addr + size);
2264 /* free page tables */
2265 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2266 if (intel_iommu_strict) {
2267 if (iommu_flush_iotlb_psi(iommu,
2268 domain->id, start_addr, size >> VTD_PAGE_SHIFT, 0))
2269 iommu_flush_write_buffer(iommu);
2270 /* free iova */
2271 __free_iova(&domain->iovad, iova);
2272 } else {
2273 add_unmap(domain, iova);
2274 /*
2275 * queue up the release of the unmap to save the 1/6th of the
2276 * cpu used up by the iotlb flush operation...
2277 */
2278 }
2279 }
2280
2281 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2282 int dir)
2283 {
2284 intel_unmap_page(dev, dev_addr, size, dir, NULL);
2285 }
2286
2287 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2288 dma_addr_t *dma_handle, gfp_t flags)
2289 {
2290 void *vaddr;
2291 int order;
2292
2293 size = PAGE_ALIGN(size);
2294 order = get_order(size);
2295 flags &= ~(GFP_DMA | GFP_DMA32);
2296
2297 vaddr = (void *)__get_free_pages(flags, order);
2298 if (!vaddr)
2299 return NULL;
2300 memset(vaddr, 0, size);
2301
2302 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2303 DMA_BIDIRECTIONAL,
2304 hwdev->coherent_dma_mask);
2305 if (*dma_handle)
2306 return vaddr;
2307 free_pages((unsigned long)vaddr, order);
2308 return NULL;
2309 }
2310
2311 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2312 dma_addr_t dma_handle)
2313 {
2314 int order;
2315
2316 size = PAGE_ALIGN(size);
2317 order = get_order(size);
2318
2319 intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2320 free_pages((unsigned long)vaddr, order);
2321 }
2322
2323 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2324 int nelems, enum dma_data_direction dir,
2325 struct dma_attrs *attrs)
2326 {
2327 int i;
2328 struct pci_dev *pdev = to_pci_dev(hwdev);
2329 struct dmar_domain *domain;
2330 unsigned long start_addr;
2331 struct iova *iova;
2332 size_t size = 0;
2333 phys_addr_t addr;
2334 struct scatterlist *sg;
2335 struct intel_iommu *iommu;
2336
2337 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2338 return;
2339
2340 domain = find_domain(pdev);
2341 BUG_ON(!domain);
2342
2343 iommu = domain_get_iommu(domain);
2344
2345 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2346 if (!iova)
2347 return;
2348 for_each_sg(sglist, sg, nelems, i) {
2349 addr = page_to_phys(sg_page(sg)) + sg->offset;
2350 size += aligned_size((u64)addr, sg->length);
2351 }
2352
2353 start_addr = iova->pfn_lo << PAGE_SHIFT;
2354
2355 /* clear the whole page */
2356 dma_pte_clear_range(domain, start_addr, start_addr + size);
2357 /* free page tables */
2358 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2359
2360 if (iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2361 size >> VTD_PAGE_SHIFT, 0))
2362 iommu_flush_write_buffer(iommu);
2363
2364 /* free iova */
2365 __free_iova(&domain->iovad, iova);
2366 }
2367
2368 static int intel_nontranslate_map_sg(struct device *hddev,
2369 struct scatterlist *sglist, int nelems, int dir)
2370 {
2371 int i;
2372 struct scatterlist *sg;
2373
2374 for_each_sg(sglist, sg, nelems, i) {
2375 BUG_ON(!sg_page(sg));
2376 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2377 sg->dma_length = sg->length;
2378 }
2379 return nelems;
2380 }
2381
2382 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2383 enum dma_data_direction dir, struct dma_attrs *attrs)
2384 {
2385 phys_addr_t addr;
2386 int i;
2387 struct pci_dev *pdev = to_pci_dev(hwdev);
2388 struct dmar_domain *domain;
2389 size_t size = 0;
2390 int prot = 0;
2391 size_t offset = 0;
2392 struct iova *iova = NULL;
2393 int ret;
2394 struct scatterlist *sg;
2395 unsigned long start_addr;
2396 struct intel_iommu *iommu;
2397
2398 BUG_ON(dir == DMA_NONE);
2399 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2400 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2401
2402 domain = get_valid_domain_for_dev(pdev);
2403 if (!domain)
2404 return 0;
2405
2406 iommu = domain_get_iommu(domain);
2407
2408 for_each_sg(sglist, sg, nelems, i) {
2409 addr = page_to_phys(sg_page(sg)) + sg->offset;
2410 size += aligned_size((u64)addr, sg->length);
2411 }
2412
2413 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2414 if (!iova) {
2415 sglist->dma_length = 0;
2416 return 0;
2417 }
2418
2419 /*
2420 * Check if DMAR supports zero-length reads on write only
2421 * mappings..
2422 */
2423 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2424 !cap_zlr(iommu->cap))
2425 prot |= DMA_PTE_READ;
2426 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2427 prot |= DMA_PTE_WRITE;
2428
2429 start_addr = iova->pfn_lo << PAGE_SHIFT;
2430 offset = 0;
2431 for_each_sg(sglist, sg, nelems, i) {
2432 addr = page_to_phys(sg_page(sg)) + sg->offset;
2433 size = aligned_size((u64)addr, sg->length);
2434 ret = domain_page_mapping(domain, start_addr + offset,
2435 ((u64)addr) & PAGE_MASK,
2436 size, prot);
2437 if (ret) {
2438 /* clear the page */
2439 dma_pte_clear_range(domain, start_addr,
2440 start_addr + offset);
2441 /* free page tables */
2442 dma_pte_free_pagetable(domain, start_addr,
2443 start_addr + offset);
2444 /* free iova */
2445 __free_iova(&domain->iovad, iova);
2446 return 0;
2447 }
2448 sg->dma_address = start_addr + offset +
2449 ((u64)addr & (~PAGE_MASK));
2450 sg->dma_length = sg->length;
2451 offset += size;
2452 }
2453
2454 /* it's a non-present to present mapping */
2455 if (iommu_flush_iotlb_psi(iommu, domain->id,
2456 start_addr, offset >> VTD_PAGE_SHIFT, 1))
2457 iommu_flush_write_buffer(iommu);
2458 return nelems;
2459 }
2460
2461 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2462 {
2463 return !dma_addr;
2464 }
2465
2466 struct dma_map_ops intel_dma_ops = {
2467 .alloc_coherent = intel_alloc_coherent,
2468 .free_coherent = intel_free_coherent,
2469 .map_sg = intel_map_sg,
2470 .unmap_sg = intel_unmap_sg,
2471 .map_page = intel_map_page,
2472 .unmap_page = intel_unmap_page,
2473 .mapping_error = intel_mapping_error,
2474 };
2475
2476 static inline int iommu_domain_cache_init(void)
2477 {
2478 int ret = 0;
2479
2480 iommu_domain_cache = kmem_cache_create("iommu_domain",
2481 sizeof(struct dmar_domain),
2482 0,
2483 SLAB_HWCACHE_ALIGN,
2484
2485 NULL);
2486 if (!iommu_domain_cache) {
2487 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2488 ret = -ENOMEM;
2489 }
2490
2491 return ret;
2492 }
2493
2494 static inline int iommu_devinfo_cache_init(void)
2495 {
2496 int ret = 0;
2497
2498 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2499 sizeof(struct device_domain_info),
2500 0,
2501 SLAB_HWCACHE_ALIGN,
2502 NULL);
2503 if (!iommu_devinfo_cache) {
2504 printk(KERN_ERR "Couldn't create devinfo cache\n");
2505 ret = -ENOMEM;
2506 }
2507
2508 return ret;
2509 }
2510
2511 static inline int iommu_iova_cache_init(void)
2512 {
2513 int ret = 0;
2514
2515 iommu_iova_cache = kmem_cache_create("iommu_iova",
2516 sizeof(struct iova),
2517 0,
2518 SLAB_HWCACHE_ALIGN,
2519 NULL);
2520 if (!iommu_iova_cache) {
2521 printk(KERN_ERR "Couldn't create iova cache\n");
2522 ret = -ENOMEM;
2523 }
2524
2525 return ret;
2526 }
2527
2528 static int __init iommu_init_mempool(void)
2529 {
2530 int ret;
2531 ret = iommu_iova_cache_init();
2532 if (ret)
2533 return ret;
2534
2535 ret = iommu_domain_cache_init();
2536 if (ret)
2537 goto domain_error;
2538
2539 ret = iommu_devinfo_cache_init();
2540 if (!ret)
2541 return ret;
2542
2543 kmem_cache_destroy(iommu_domain_cache);
2544 domain_error:
2545 kmem_cache_destroy(iommu_iova_cache);
2546
2547 return -ENOMEM;
2548 }
2549
2550 static void __init iommu_exit_mempool(void)
2551 {
2552 kmem_cache_destroy(iommu_devinfo_cache);
2553 kmem_cache_destroy(iommu_domain_cache);
2554 kmem_cache_destroy(iommu_iova_cache);
2555
2556 }
2557
2558 static void __init init_no_remapping_devices(void)
2559 {
2560 struct dmar_drhd_unit *drhd;
2561
2562 for_each_drhd_unit(drhd) {
2563 if (!drhd->include_all) {
2564 int i;
2565 for (i = 0; i < drhd->devices_cnt; i++)
2566 if (drhd->devices[i] != NULL)
2567 break;
2568 /* ignore DMAR unit if no pci devices exist */
2569 if (i == drhd->devices_cnt)
2570 drhd->ignored = 1;
2571 }
2572 }
2573
2574 if (dmar_map_gfx)
2575 return;
2576
2577 for_each_drhd_unit(drhd) {
2578 int i;
2579 if (drhd->ignored || drhd->include_all)
2580 continue;
2581
2582 for (i = 0; i < drhd->devices_cnt; i++)
2583 if (drhd->devices[i] &&
2584 !IS_GFX_DEVICE(drhd->devices[i]))
2585 break;
2586
2587 if (i < drhd->devices_cnt)
2588 continue;
2589
2590 /* bypass IOMMU if it is just for gfx devices */
2591 drhd->ignored = 1;
2592 for (i = 0; i < drhd->devices_cnt; i++) {
2593 if (!drhd->devices[i])
2594 continue;
2595 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
2596 }
2597 }
2598 }
2599
2600 int __init intel_iommu_init(void)
2601 {
2602 int ret = 0;
2603
2604 if (dmar_table_init())
2605 return -ENODEV;
2606
2607 if (dmar_dev_scope_init())
2608 return -ENODEV;
2609
2610 /*
2611 * Check the need for DMA-remapping initialization now.
2612 * Above initialization will also be used by Interrupt-remapping.
2613 */
2614 if (no_iommu || swiotlb || dmar_disabled)
2615 return -ENODEV;
2616
2617 iommu_init_mempool();
2618 dmar_init_reserved_ranges();
2619
2620 init_no_remapping_devices();
2621
2622 ret = init_dmars();
2623 if (ret) {
2624 printk(KERN_ERR "IOMMU: dmar init failed\n");
2625 put_iova_domain(&reserved_iova_list);
2626 iommu_exit_mempool();
2627 return ret;
2628 }
2629 printk(KERN_INFO
2630 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
2631
2632 init_timer(&unmap_timer);
2633 force_iommu = 1;
2634 dma_ops = &intel_dma_ops;
2635
2636 register_iommu(&intel_iommu_ops);
2637
2638 return 0;
2639 }
2640
2641 static int vm_domain_add_dev_info(struct dmar_domain *domain,
2642 struct pci_dev *pdev)
2643 {
2644 struct device_domain_info *info;
2645 unsigned long flags;
2646
2647 info = alloc_devinfo_mem();
2648 if (!info)
2649 return -ENOMEM;
2650
2651 info->bus = pdev->bus->number;
2652 info->devfn = pdev->devfn;
2653 info->dev = pdev;
2654 info->domain = domain;
2655
2656 spin_lock_irqsave(&device_domain_lock, flags);
2657 list_add(&info->link, &domain->devices);
2658 list_add(&info->global, &device_domain_list);
2659 pdev->dev.archdata.iommu = info;
2660 spin_unlock_irqrestore(&device_domain_lock, flags);
2661
2662 return 0;
2663 }
2664
2665 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
2666 struct pci_dev *pdev)
2667 {
2668 struct pci_dev *tmp, *parent;
2669
2670 if (!iommu || !pdev)
2671 return;
2672
2673 /* dependent device detach */
2674 tmp = pci_find_upstream_pcie_bridge(pdev);
2675 /* Secondary interface's bus number and devfn 0 */
2676 if (tmp) {
2677 parent = pdev->bus->self;
2678 while (parent != tmp) {
2679 iommu_detach_dev(iommu, parent->bus->number,
2680 parent->devfn);
2681 parent = parent->bus->self;
2682 }
2683 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
2684 iommu_detach_dev(iommu,
2685 tmp->subordinate->number, 0);
2686 else /* this is a legacy PCI bridge */
2687 iommu_detach_dev(iommu,
2688 tmp->bus->number, tmp->devfn);
2689 }
2690 }
2691
2692 static void vm_domain_remove_one_dev_info(struct dmar_domain *domain,
2693 struct pci_dev *pdev)
2694 {
2695 struct device_domain_info *info;
2696 struct intel_iommu *iommu;
2697 unsigned long flags;
2698 int found = 0;
2699 struct list_head *entry, *tmp;
2700
2701 iommu = device_to_iommu(pdev->bus->number, pdev->devfn);
2702 if (!iommu)
2703 return;
2704
2705 spin_lock_irqsave(&device_domain_lock, flags);
2706 list_for_each_safe(entry, tmp, &domain->devices) {
2707 info = list_entry(entry, struct device_domain_info, link);
2708 if (info->bus == pdev->bus->number &&
2709 info->devfn == pdev->devfn) {
2710 list_del(&info->link);
2711 list_del(&info->global);
2712 if (info->dev)
2713 info->dev->dev.archdata.iommu = NULL;
2714 spin_unlock_irqrestore(&device_domain_lock, flags);
2715
2716 iommu_detach_dev(iommu, info->bus, info->devfn);
2717 iommu_detach_dependent_devices(iommu, pdev);
2718 free_devinfo_mem(info);
2719
2720 spin_lock_irqsave(&device_domain_lock, flags);
2721
2722 if (found)
2723 break;
2724 else
2725 continue;
2726 }
2727
2728 /* if there is no other devices under the same iommu
2729 * owned by this domain, clear this iommu in iommu_bmp
2730 * update iommu count and coherency
2731 */
2732 if (device_to_iommu(info->bus, info->devfn) == iommu)
2733 found = 1;
2734 }
2735
2736 if (found == 0) {
2737 unsigned long tmp_flags;
2738 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
2739 clear_bit(iommu->seq_id, &domain->iommu_bmp);
2740 domain->iommu_count--;
2741 domain_update_iommu_cap(domain);
2742 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
2743 }
2744
2745 spin_unlock_irqrestore(&device_domain_lock, flags);
2746 }
2747
2748 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
2749 {
2750 struct device_domain_info *info;
2751 struct intel_iommu *iommu;
2752 unsigned long flags1, flags2;
2753
2754 spin_lock_irqsave(&device_domain_lock, flags1);
2755 while (!list_empty(&domain->devices)) {
2756 info = list_entry(domain->devices.next,
2757 struct device_domain_info, link);
2758 list_del(&info->link);
2759 list_del(&info->global);
2760 if (info->dev)
2761 info->dev->dev.archdata.iommu = NULL;
2762
2763 spin_unlock_irqrestore(&device_domain_lock, flags1);
2764
2765 iommu = device_to_iommu(info->bus, info->devfn);
2766 iommu_detach_dev(iommu, info->bus, info->devfn);
2767 iommu_detach_dependent_devices(iommu, info->dev);
2768
2769 /* clear this iommu in iommu_bmp, update iommu count
2770 * and capabilities
2771 */
2772 spin_lock_irqsave(&domain->iommu_lock, flags2);
2773 if (test_and_clear_bit(iommu->seq_id,
2774 &domain->iommu_bmp)) {
2775 domain->iommu_count--;
2776 domain_update_iommu_cap(domain);
2777 }
2778 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
2779
2780 free_devinfo_mem(info);
2781 spin_lock_irqsave(&device_domain_lock, flags1);
2782 }
2783 spin_unlock_irqrestore(&device_domain_lock, flags1);
2784 }
2785
2786 /* domain id for virtual machine, it won't be set in context */
2787 static unsigned long vm_domid;
2788
2789 static int vm_domain_min_agaw(struct dmar_domain *domain)
2790 {
2791 int i;
2792 int min_agaw = domain->agaw;
2793
2794 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
2795 for (; i < g_num_of_iommus; ) {
2796 if (min_agaw > g_iommus[i]->agaw)
2797 min_agaw = g_iommus[i]->agaw;
2798
2799 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
2800 }
2801
2802 return min_agaw;
2803 }
2804
2805 static struct dmar_domain *iommu_alloc_vm_domain(void)
2806 {
2807 struct dmar_domain *domain;
2808
2809 domain = alloc_domain_mem();
2810 if (!domain)
2811 return NULL;
2812
2813 domain->id = vm_domid++;
2814 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
2815 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
2816
2817 return domain;
2818 }
2819
2820 static int vm_domain_init(struct dmar_domain *domain, int guest_width)
2821 {
2822 int adjust_width;
2823
2824 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
2825 spin_lock_init(&domain->mapping_lock);
2826 spin_lock_init(&domain->iommu_lock);
2827
2828 domain_reserve_special_ranges(domain);
2829
2830 /* calculate AGAW */
2831 domain->gaw = guest_width;
2832 adjust_width = guestwidth_to_adjustwidth(guest_width);
2833 domain->agaw = width_to_agaw(adjust_width);
2834
2835 INIT_LIST_HEAD(&domain->devices);
2836
2837 domain->iommu_count = 0;
2838 domain->iommu_coherency = 0;
2839 domain->max_addr = 0;
2840
2841 /* always allocate the top pgd */
2842 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
2843 if (!domain->pgd)
2844 return -ENOMEM;
2845 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
2846 return 0;
2847 }
2848
2849 static void iommu_free_vm_domain(struct dmar_domain *domain)
2850 {
2851 unsigned long flags;
2852 struct dmar_drhd_unit *drhd;
2853 struct intel_iommu *iommu;
2854 unsigned long i;
2855 unsigned long ndomains;
2856
2857 for_each_drhd_unit(drhd) {
2858 if (drhd->ignored)
2859 continue;
2860 iommu = drhd->iommu;
2861
2862 ndomains = cap_ndoms(iommu->cap);
2863 i = find_first_bit(iommu->domain_ids, ndomains);
2864 for (; i < ndomains; ) {
2865 if (iommu->domains[i] == domain) {
2866 spin_lock_irqsave(&iommu->lock, flags);
2867 clear_bit(i, iommu->domain_ids);
2868 iommu->domains[i] = NULL;
2869 spin_unlock_irqrestore(&iommu->lock, flags);
2870 break;
2871 }
2872 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
2873 }
2874 }
2875 }
2876
2877 static void vm_domain_exit(struct dmar_domain *domain)
2878 {
2879 u64 end;
2880
2881 /* Domain 0 is reserved, so dont process it */
2882 if (!domain)
2883 return;
2884
2885 vm_domain_remove_all_dev_info(domain);
2886 /* destroy iovas */
2887 put_iova_domain(&domain->iovad);
2888 end = DOMAIN_MAX_ADDR(domain->gaw);
2889 end = end & (~VTD_PAGE_MASK);
2890
2891 /* clear ptes */
2892 dma_pte_clear_range(domain, 0, end);
2893
2894 /* free page tables */
2895 dma_pte_free_pagetable(domain, 0, end);
2896
2897 iommu_free_vm_domain(domain);
2898 free_domain_mem(domain);
2899 }
2900
2901 static int intel_iommu_domain_init(struct iommu_domain *domain)
2902 {
2903 struct dmar_domain *dmar_domain;
2904
2905 dmar_domain = iommu_alloc_vm_domain();
2906 if (!dmar_domain) {
2907 printk(KERN_ERR
2908 "intel_iommu_domain_init: dmar_domain == NULL\n");
2909 return -ENOMEM;
2910 }
2911 if (vm_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2912 printk(KERN_ERR
2913 "intel_iommu_domain_init() failed\n");
2914 vm_domain_exit(dmar_domain);
2915 return -ENOMEM;
2916 }
2917 domain->priv = dmar_domain;
2918
2919 return 0;
2920 }
2921
2922 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
2923 {
2924 struct dmar_domain *dmar_domain = domain->priv;
2925
2926 domain->priv = NULL;
2927 vm_domain_exit(dmar_domain);
2928 }
2929
2930 static int intel_iommu_attach_device(struct iommu_domain *domain,
2931 struct device *dev)
2932 {
2933 struct dmar_domain *dmar_domain = domain->priv;
2934 struct pci_dev *pdev = to_pci_dev(dev);
2935 struct intel_iommu *iommu;
2936 int addr_width;
2937 u64 end;
2938 int ret;
2939
2940 /* normally pdev is not mapped */
2941 if (unlikely(domain_context_mapped(pdev))) {
2942 struct dmar_domain *old_domain;
2943
2944 old_domain = find_domain(pdev);
2945 if (old_domain) {
2946 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
2947 vm_domain_remove_one_dev_info(old_domain, pdev);
2948 else
2949 domain_remove_dev_info(old_domain);
2950 }
2951 }
2952
2953 iommu = device_to_iommu(pdev->bus->number, pdev->devfn);
2954 if (!iommu)
2955 return -ENODEV;
2956
2957 /* check if this iommu agaw is sufficient for max mapped address */
2958 addr_width = agaw_to_width(iommu->agaw);
2959 end = DOMAIN_MAX_ADDR(addr_width);
2960 end = end & VTD_PAGE_MASK;
2961 if (end < dmar_domain->max_addr) {
2962 printk(KERN_ERR "%s: iommu agaw (%d) is not "
2963 "sufficient for the mapped address (%llx)\n",
2964 __func__, iommu->agaw, dmar_domain->max_addr);
2965 return -EFAULT;
2966 }
2967
2968 ret = domain_context_mapping(dmar_domain, pdev);
2969 if (ret)
2970 return ret;
2971
2972 ret = vm_domain_add_dev_info(dmar_domain, pdev);
2973 return ret;
2974 }
2975
2976 static void intel_iommu_detach_device(struct iommu_domain *domain,
2977 struct device *dev)
2978 {
2979 struct dmar_domain *dmar_domain = domain->priv;
2980 struct pci_dev *pdev = to_pci_dev(dev);
2981
2982 vm_domain_remove_one_dev_info(dmar_domain, pdev);
2983 }
2984
2985 static int intel_iommu_map_range(struct iommu_domain *domain,
2986 unsigned long iova, phys_addr_t hpa,
2987 size_t size, int iommu_prot)
2988 {
2989 struct dmar_domain *dmar_domain = domain->priv;
2990 u64 max_addr;
2991 int addr_width;
2992 int prot = 0;
2993 int ret;
2994
2995 if (iommu_prot & IOMMU_READ)
2996 prot |= DMA_PTE_READ;
2997 if (iommu_prot & IOMMU_WRITE)
2998 prot |= DMA_PTE_WRITE;
2999 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3000 prot |= DMA_PTE_SNP;
3001
3002 max_addr = (iova & VTD_PAGE_MASK) + VTD_PAGE_ALIGN(size);
3003 if (dmar_domain->max_addr < max_addr) {
3004 int min_agaw;
3005 u64 end;
3006
3007 /* check if minimum agaw is sufficient for mapped address */
3008 min_agaw = vm_domain_min_agaw(dmar_domain);
3009 addr_width = agaw_to_width(min_agaw);
3010 end = DOMAIN_MAX_ADDR(addr_width);
3011 end = end & VTD_PAGE_MASK;
3012 if (end < max_addr) {
3013 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3014 "sufficient for the mapped address (%llx)\n",
3015 __func__, min_agaw, max_addr);
3016 return -EFAULT;
3017 }
3018 dmar_domain->max_addr = max_addr;
3019 }
3020
3021 ret = domain_page_mapping(dmar_domain, iova, hpa, size, prot);
3022 return ret;
3023 }
3024
3025 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3026 unsigned long iova, size_t size)
3027 {
3028 struct dmar_domain *dmar_domain = domain->priv;
3029 dma_addr_t base;
3030
3031 /* The address might not be aligned */
3032 base = iova & VTD_PAGE_MASK;
3033 size = VTD_PAGE_ALIGN(size);
3034 dma_pte_clear_range(dmar_domain, base, base + size);
3035
3036 if (dmar_domain->max_addr == base + size)
3037 dmar_domain->max_addr = base;
3038 }
3039
3040 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3041 unsigned long iova)
3042 {
3043 struct dmar_domain *dmar_domain = domain->priv;
3044 struct dma_pte *pte;
3045 u64 phys = 0;
3046
3047 pte = addr_to_dma_pte(dmar_domain, iova);
3048 if (pte)
3049 phys = dma_pte_addr(pte);
3050
3051 return phys;
3052 }
3053
3054 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3055 unsigned long cap)
3056 {
3057 struct dmar_domain *dmar_domain = domain->priv;
3058
3059 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3060 return dmar_domain->iommu_snooping;
3061
3062 return 0;
3063 }
3064
3065 static struct iommu_ops intel_iommu_ops = {
3066 .domain_init = intel_iommu_domain_init,
3067 .domain_destroy = intel_iommu_domain_destroy,
3068 .attach_dev = intel_iommu_attach_device,
3069 .detach_dev = intel_iommu_detach_device,
3070 .map = intel_iommu_map_range,
3071 .unmap = intel_iommu_unmap_range,
3072 .iova_to_phys = intel_iommu_iova_to_phys,
3073 .domain_has_cap = intel_iommu_domain_has_cap,
3074 };
3075
3076 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3077 {
3078 /*
3079 * Mobile 4 Series Chipset neglects to set RWBF capability,
3080 * but needs it:
3081 */
3082 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3083 rwbf_quirk = 1;
3084 }
3085
3086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
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