arch/arm/mach-imx/mm-imx5.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License.  You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  *
  11  * Create static mapping between physical to virtual memory.
  12  */
  13
  14 #include <linux/mm.h>
  15 #include <linux/init.h>
  16 #include <linux/clk.h>
  17 #include <linux/pinctrl/machine.h>
  18
  19 #include <asm/mach/map.h>
  20
  21 #include "common.h"
  22 #include "devices/devices-common.h"
  23 #include "hardware.h"
  24 #include "iomux-v3.h"
  25
  26 /*
  27  * Define the MX51 memory map.
  28  */
  29 static struct map_desc mx51_io_desc[] __initdata = {
  30         imx_map_entry(MX51, TZIC, MT_DEVICE),
  31         imx_map_entry(MX51, IRAM, MT_DEVICE),
  32         imx_map_entry(MX51, AIPS1, MT_DEVICE),
  33         imx_map_entry(MX51, SPBA0, MT_DEVICE),
  34         imx_map_entry(MX51, AIPS2, MT_DEVICE),
  35 };
  36
  37 /*
  38  * Define the MX53 memory map.
  39  */
  40 static struct map_desc mx53_io_desc[] __initdata = {
  41         imx_map_entry(MX53, TZIC, MT_DEVICE),
  42         imx_map_entry(MX53, AIPS1, MT_DEVICE),
  43         imx_map_entry(MX53, SPBA0, MT_DEVICE),
  44         imx_map_entry(MX53, AIPS2, MT_DEVICE),
  45 };
  46
  47 /*
  48  * This function initializes the memory map. It is called during the
  49  * system startup to create static physical to virtual memory mappings
  50  * for the IO modules.
  51  */
  52 void __init mx51_map_io(void)
  53 {
  54         iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
  55 }
  56
  57 void __init mx53_map_io(void)
  58 {
  59         iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
  60 }
  61
  62 /*
  63  * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
  64  * the Freescale marketing division. However this did not remove the
  65  * hardware from the chip which still needs to be configured for proper
  66  * IPU support.
  67  */
  68 static void __init imx51_ipu_mipi_setup(void)
  69 {
  70         void __iomem *hsc_addr;
  71         hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
  72
  73         /* setup MIPI module to legacy mode */
  74         __raw_writel(0xf00, hsc_addr);
  75
  76         /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
  77         __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
  78                 hsc_addr + 0x800);
  79 }
  80
  81 void __init imx51_init_early(void)
  82 {
  83         imx51_ipu_mipi_setup();
  84         mxc_set_cpu_type(MXC_CPU_MX51);
  85         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
  86         imx_src_init();
  87 }
  88
  89 void __init imx53_init_early(void)
  90 {
  91         mxc_set_cpu_type(MXC_CPU_MX53);
  92         mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
  93         imx_src_init();
  94 }
  95
  96 void __init mx51_init_irq(void)
  97 {
  98         tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
  99 }
 100
 101 void __init mx53_init_irq(void)
 102 {
 103         tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
 104 }
 105
 106 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
 107         .ap_2_ap_addr = 642,
 108         .uart_2_mcu_addr = 817,
 109         .mcu_2_app_addr = 747,
 110         .mcu_2_shp_addr = 961,
 111         .ata_2_mcu_addr = 1473,
 112         .mcu_2_ata_addr = 1392,
 113         .app_2_per_addr = 1033,
 114         .app_2_mcu_addr = 683,
 115         .shp_2_per_addr = 1251,
 116         .shp_2_mcu_addr = 892,
 117 };
 118
 119 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
 120         .fw_name = "sdma-imx51.bin",
 121         .script_addrs = &imx51_sdma_script,
 122 };
 123
 124 static const struct resource imx51_audmux_res[] __initconst = {
 125         DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
 126 };
 127
 128 void __init imx51_soc_init(void)
 129 {
 130         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
 131         mxc_device_init();
 132
 133         /* i.mx51 has the i.mx35 type gpio */
 134         mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
 135         mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
 136         mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
 137         mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
 138
 139         pinctrl_provide_dummies();
 140
 141         /* i.mx51 has the i.mx35 type sdma */
 142         imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
 143
 144         /* Setup AIPS registers */
 145         imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
 146         imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
 147
 148         /* i.mx51 has the i.mx31 type audmux */
 149         platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
 150                                         ARRAY_SIZE(imx51_audmux_res));
 151 }
 152
 153 void __init imx51_init_late(void)
 154 {
 155         mx51_neon_fixup();
 156         imx51_pm_init();
 157 }
 158
 159 void __init imx53_init_late(void)
 160 {
 161         imx53_pm_init();
 162 }