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powerpc: dts: P1010: Add endianness property to flexcan node
[linux-2.6/btrfs-unstable.git] / drivers / rtc / rtc-at91sam9.c
blob7418a763ce5202b37f96b0cf26863400aa953982
1 /*
2 * "RTT as Real Time Clock" driver for AT91SAM9 SoC family
3 *
4 * (C) 2007 Michel Benoit
5 *
6 * Based on rtc-at91rm9200.c by Rick Bronson
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioctl.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/rtc.h>
25 #include <linux/slab.h>
26 #include <linux/suspend.h>
27 #include <linux/time.h>
28
29 /*
30 * This driver uses two configurable hardware resources that live in the
31 * AT91SAM9 backup power domain (intended to be powered at all times)
32 * to implement the Real Time Clock interfaces
33 *
34 * - A "Real-time Timer" (RTT) counts up in seconds from a base time.
35 * We can't assign the counter value (CRTV) ... but we can reset it.
36 *
37 * - One of the "General Purpose Backup Registers" (GPBRs) holds the
38 * base time, normally an offset from the beginning of the POSIX
39 * epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the
40 * local timezone's offset.
41 *
42 * The RTC's value is the RTT counter plus that offset. The RTC's alarm
43 * is likewise a base (ALMV) plus that offset.
44 *
45 * Not all RTTs will be used as RTCs; some systems have multiple RTTs to
46 * choose from, or a "real" RTC module. All systems have multiple GPBR
47 * registers available, likewise usable for more than "RTC" support.
48 */
49
50 #define AT91_RTT_MR 0x00 /* Real-time Mode Register */
51 #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
52 #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
53 #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
54 #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
55
56 #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
57 #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
58
59 #define AT91_RTT_VR 0x08 /* Real-time Value Register */
60 #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
61
62 #define AT91_RTT_SR 0x0c /* Real-time Status Register */
63 #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
64 #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
65
66 /*
67 * We store ALARM_DISABLED in ALMV to record that no alarm is set.
68 * It's also the reset value for that field.
69 */
70 #define ALARM_DISABLED ((u32)~0)
71
72
73 struct sam9_rtc {
74 void __iomem *rtt;
75 struct rtc_device *rtcdev;
76 u32 imr;
77 struct regmap *gpbr;
78 unsigned int gpbr_offset;
79 int irq;
80 struct clk *sclk;
81 bool suspended;
82 unsigned long events;
83 spinlock_t lock;
84 };
85
86 #define rtt_readl(rtc, field) \
87 readl((rtc)->rtt + AT91_RTT_ ## field)
88 #define rtt_writel(rtc, field, val) \
89 writel((val), (rtc)->rtt + AT91_RTT_ ## field)
90
91 static inline unsigned int gpbr_readl(struct sam9_rtc *rtc)
92 {
93 unsigned int val;
94
95 regmap_read(rtc->gpbr, rtc->gpbr_offset, &val);
96
97 return val;
98 }
99
100 static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val)
101 {
102 regmap_write(rtc->gpbr, rtc->gpbr_offset, val);
103 }
104
105 /*
106 * Read current time and date in RTC
107 */
108 static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
109 {
110 struct sam9_rtc *rtc = dev_get_drvdata(dev);
111 u32 secs, secs2;
112 u32 offset;
113
114 /* read current time offset */
115 offset = gpbr_readl(rtc);
116 if (offset == 0)
117 return -EILSEQ;
118
119 /* reread the counter to help sync the two clock domains */
120 secs = rtt_readl(rtc, VR);
121 secs2 = rtt_readl(rtc, VR);
122 if (secs != secs2)
123 secs = rtt_readl(rtc, VR);
124
125 rtc_time_to_tm(offset + secs, tm);
126
127 dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readtime",
128 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
129 tm->tm_hour, tm->tm_min, tm->tm_sec);
130
131 return 0;
132 }
133
134 /*
135 * Set current time and date in RTC
136 */
137 static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
138 {
139 struct sam9_rtc *rtc = dev_get_drvdata(dev);
140 int err;
141 u32 offset, alarm, mr;
142 unsigned long secs;
143
144 dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "settime",
145 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
146 tm->tm_hour, tm->tm_min, tm->tm_sec);
147
148 err = rtc_tm_to_time(tm, &secs);
149 if (err != 0)
150 return err;
151
152 mr = rtt_readl(rtc, MR);
153
154 /* disable interrupts */
155 rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
156
157 /* read current time offset */
158 offset = gpbr_readl(rtc);
159
160 /* store the new base time in a battery backup register */
161 secs += 1;
162 gpbr_writel(rtc, secs);
163
164 /* adjust the alarm time for the new base */
165 alarm = rtt_readl(rtc, AR);
166 if (alarm != ALARM_DISABLED) {
167 if (offset > secs) {
168 /* time jumped backwards, increase time until alarm */
169 alarm += (offset - secs);
170 } else if ((alarm + offset) > secs) {
171 /* time jumped forwards, decrease time until alarm */
172 alarm -= (secs - offset);
173 } else {
174 /* time jumped past the alarm, disable alarm */
175 alarm = ALARM_DISABLED;
176 mr &= ~AT91_RTT_ALMIEN;
177 }
178 rtt_writel(rtc, AR, alarm);
179 }
180
181 /* reset the timer, and re-enable interrupts */
182 rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST);
183
184 return 0;
185 }
186
187 static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
188 {
189 struct sam9_rtc *rtc = dev_get_drvdata(dev);
190 struct rtc_time *tm = &alrm->time;
191 u32 alarm = rtt_readl(rtc, AR);
192 u32 offset;
193
194 offset = gpbr_readl(rtc);
195 if (offset == 0)
196 return -EILSEQ;
197
198 memset(alrm, 0, sizeof(*alrm));
199 if (alarm != ALARM_DISABLED && offset != 0) {
200 rtc_time_to_tm(offset + alarm, tm);
201
202 dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readalarm",
203 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
204 tm->tm_hour, tm->tm_min, tm->tm_sec);
205
206 if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN)
207 alrm->enabled = 1;
208 }
209
210 return 0;
211 }
212
213 static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
214 {
215 struct sam9_rtc *rtc = dev_get_drvdata(dev);
216 struct rtc_time *tm = &alrm->time;
217 unsigned long secs;
218 u32 offset;
219 u32 mr;
220 int err;
221
222 err = rtc_tm_to_time(tm, &secs);
223 if (err != 0)
224 return err;
225
226 offset = gpbr_readl(rtc);
227 if (offset == 0) {
228 /* time is not set */
229 return -EILSEQ;
230 }
231 mr = rtt_readl(rtc, MR);
232 rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
233
234 /* alarm in the past? finish and leave disabled */
235 if (secs <= offset) {
236 rtt_writel(rtc, AR, ALARM_DISABLED);
237 return 0;
238 }
239
240 /* else set alarm and maybe enable it */
241 rtt_writel(rtc, AR, secs - offset);
242 if (alrm->enabled)
243 rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
244
245 dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "setalarm",
246 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour,
247 tm->tm_min, tm->tm_sec);
248
249 return 0;
250 }
251
252 static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
253 {
254 struct sam9_rtc *rtc = dev_get_drvdata(dev);
255 u32 mr = rtt_readl(rtc, MR);
256
257 dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr);
258 if (enabled)
259 rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
260 else
261 rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
262 return 0;
263 }
264
265 /*
266 * Provide additional RTC information in /proc/driver/rtc
267 */
268 static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
269 {
270 struct sam9_rtc *rtc = dev_get_drvdata(dev);
271 u32 mr = rtt_readl(rtc, MR);
272
273 seq_printf(seq, "update_IRQ\t: %s\n",
274 (mr & AT91_RTT_RTTINCIEN) ? "yes" : "no");
275 return 0;
276 }
277
278 static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc)
279 {
280 u32 sr, mr;
281
282 /* Shared interrupt may be for another device. Note: reading
283 * SR clears it, so we must only read it in this irq handler!
284 */
285 mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
286 sr = rtt_readl(rtc, SR) & (mr >> 16);
287 if (!sr)
288 return IRQ_NONE;
289
290 /* alarm status */
291 if (sr & AT91_RTT_ALMS)
292 rtc->events |= (RTC_AF | RTC_IRQF);
293
294 /* timer update/increment */
295 if (sr & AT91_RTT_RTTINC)
296 rtc->events |= (RTC_UF | RTC_IRQF);
297
298 return IRQ_HANDLED;
299 }
300
301 static void at91_rtc_flush_events(struct sam9_rtc *rtc)
302 {
303 if (!rtc->events)
304 return;
305
306 rtc_update_irq(rtc->rtcdev, 1, rtc->events);
307 rtc->events = 0;
308
309 pr_debug("%s: num=%ld, events=0x%02lx\n", __func__,
310 rtc->events >> 8, rtc->events & 0x000000FF);
311 }
312
313 /*
314 * IRQ handler for the RTC
315 */
316 static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc)
317 {
318 struct sam9_rtc *rtc = _rtc;
319 int ret;
320
321 spin_lock(&rtc->lock);
322
323 ret = at91_rtc_cache_events(rtc);
324
325 /* We're called in suspended state */
326 if (rtc->suspended) {
327 /* Mask irqs coming from this peripheral */
328 rtt_writel(rtc, MR,
329 rtt_readl(rtc, MR) &
330 ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
331 /* Trigger a system wakeup */
332 pm_system_wakeup();
333 } else {
334 at91_rtc_flush_events(rtc);
335 }
336
337 spin_unlock(&rtc->lock);
338
339 return ret;
340 }
341
342 static const struct rtc_class_ops at91_rtc_ops = {
343 .read_time = at91_rtc_readtime,
344 .set_time = at91_rtc_settime,
345 .read_alarm = at91_rtc_readalarm,
346 .set_alarm = at91_rtc_setalarm,
347 .proc = at91_rtc_proc,
348 .alarm_irq_enable = at91_rtc_alarm_irq_enable,
349 };
350
351 static const struct regmap_config gpbr_regmap_config = {
352 .reg_bits = 32,
353 .val_bits = 32,
354 .reg_stride = 4,
355 };
356
357 /*
358 * Initialize and install RTC driver
359 */
360 static int at91_rtc_probe(struct platform_device *pdev)
361 {
362 struct resource *r;
363 struct sam9_rtc *rtc;
364 int ret, irq;
365 u32 mr;
366 unsigned int sclk_rate;
367
368 irq = platform_get_irq(pdev, 0);
369 if (irq < 0) {
370 dev_err(&pdev->dev, "failed to get interrupt resource\n");
371 return irq;
372 }
373
374 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
375 if (!rtc)
376 return -ENOMEM;
377
378 spin_lock_init(&rtc->lock);
379 rtc->irq = irq;
380
381 /* platform setup code should have handled this; sigh */
382 if (!device_can_wakeup(&pdev->dev))
383 device_init_wakeup(&pdev->dev, 1);
384
385 platform_set_drvdata(pdev, rtc);
386
387 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
388 rtc->rtt = devm_ioremap_resource(&pdev->dev, r);
389 if (IS_ERR(rtc->rtt))
390 return PTR_ERR(rtc->rtt);
391
392 if (!pdev->dev.of_node) {
393 /*
394 * TODO: Remove this code chunk when removing non DT board
395 * support. Remember to remove the gpbr_regmap_config
396 * variable too.
397 */
398 void __iomem *gpbr;
399
400 r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
401 gpbr = devm_ioremap_resource(&pdev->dev, r);
402 if (IS_ERR(gpbr))
403 return PTR_ERR(gpbr);
404
405 rtc->gpbr = regmap_init_mmio(NULL, gpbr,
406 &gpbr_regmap_config);
407 } else {
408 struct of_phandle_args args;
409
410 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
411 "atmel,rtt-rtc-time-reg", 1, 0,
412 &args);
413 if (ret)
414 return ret;
415
416 rtc->gpbr = syscon_node_to_regmap(args.np);
417 rtc->gpbr_offset = args.args[0];
418 }
419
420 if (IS_ERR(rtc->gpbr)) {
421 dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n");
422 return -ENOMEM;
423 }
424
425 rtc->sclk = devm_clk_get(&pdev->dev, NULL);
426 if (IS_ERR(rtc->sclk))
427 return PTR_ERR(rtc->sclk);
428
429 ret = clk_prepare_enable(rtc->sclk);
430 if (ret) {
431 dev_err(&pdev->dev, "Could not enable slow clock\n");
432 return ret;
433 }
434
435 sclk_rate = clk_get_rate(rtc->sclk);
436 if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) {
437 dev_err(&pdev->dev, "Invalid slow clock rate\n");
438 ret = -EINVAL;
439 goto err_clk;
440 }
441
442 mr = rtt_readl(rtc, MR);
443
444 /* unless RTT is counting at 1 Hz, re-initialize it */
445 if ((mr & AT91_RTT_RTPRES) != sclk_rate) {
446 mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES);
447 gpbr_writel(rtc, 0);
448 }
449
450 /* disable all interrupts (same as on shutdown path) */
451 mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
452 rtt_writel(rtc, MR, mr);
453
454 rtc->rtcdev = devm_rtc_device_register(&pdev->dev, pdev->name,
455 &at91_rtc_ops, THIS_MODULE);
456 if (IS_ERR(rtc->rtcdev)) {
457 ret = PTR_ERR(rtc->rtcdev);
458 goto err_clk;
459 }
460
461 /* register irq handler after we know what name we'll use */
462 ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt,
463 IRQF_SHARED | IRQF_COND_SUSPEND,
464 dev_name(&rtc->rtcdev->dev), rtc);
465 if (ret) {
466 dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
467 goto err_clk;
468 }
469
470 /* NOTE: sam9260 rev A silicon has a ROM bug which resets the
471 * RTT on at least some reboots. If you have that chip, you must
472 * initialize the time from some external source like a GPS, wall
473 * clock, discrete RTC, etc
474 */
475
476 if (gpbr_readl(rtc) == 0)
477 dev_warn(&pdev->dev, "%s: SET TIME!\n",
478 dev_name(&rtc->rtcdev->dev));
479
480 return 0;
481
482 err_clk:
483 clk_disable_unprepare(rtc->sclk);
484
485 return ret;
486 }
487
488 /*
489 * Disable and remove the RTC driver
490 */
491 static int at91_rtc_remove(struct platform_device *pdev)
492 {
493 struct sam9_rtc *rtc = platform_get_drvdata(pdev);
494 u32 mr = rtt_readl(rtc, MR);
495
496 /* disable all interrupts */
497 rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
498
499 clk_disable_unprepare(rtc->sclk);
500
501 return 0;
502 }
503
504 static void at91_rtc_shutdown(struct platform_device *pdev)
505 {
506 struct sam9_rtc *rtc = platform_get_drvdata(pdev);
507 u32 mr = rtt_readl(rtc, MR);
508
509 rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
510 rtt_writel(rtc, MR, mr & ~rtc->imr);
511 }
512
513 #ifdef CONFIG_PM_SLEEP
514
515 /* AT91SAM9 RTC Power management control */
516
517 static int at91_rtc_suspend(struct device *dev)
518 {
519 struct sam9_rtc *rtc = dev_get_drvdata(dev);
520 u32 mr = rtt_readl(rtc, MR);
521
522 /*
523 * This IRQ is shared with DBGU and other hardware which isn't
524 * necessarily a wakeup event source.
525 */
526 rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
527 if (rtc->imr) {
528 if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) {
529 unsigned long flags;
530
531 enable_irq_wake(rtc->irq);
532 spin_lock_irqsave(&rtc->lock, flags);
533 rtc->suspended = true;
534 spin_unlock_irqrestore(&rtc->lock, flags);
535 /* don't let RTTINC cause wakeups */
536 if (mr & AT91_RTT_RTTINCIEN)
537 rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
538 } else
539 rtt_writel(rtc, MR, mr & ~rtc->imr);
540 }
541
542 return 0;
543 }
544
545 static int at91_rtc_resume(struct device *dev)
546 {
547 struct sam9_rtc *rtc = dev_get_drvdata(dev);
548 u32 mr;
549
550 if (rtc->imr) {
551 unsigned long flags;
552
553 if (device_may_wakeup(dev))
554 disable_irq_wake(rtc->irq);
555 mr = rtt_readl(rtc, MR);
556 rtt_writel(rtc, MR, mr | rtc->imr);
557
558 spin_lock_irqsave(&rtc->lock, flags);
559 rtc->suspended = false;
560 at91_rtc_cache_events(rtc);
561 at91_rtc_flush_events(rtc);
562 spin_unlock_irqrestore(&rtc->lock, flags);
563 }
564
565 return 0;
566 }
567 #endif
568
569 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
570
571 #ifdef CONFIG_OF
572 static const struct of_device_id at91_rtc_dt_ids[] = {
573 { .compatible = "atmel,at91sam9260-rtt" },
574 { /* sentinel */ }
575 };
576 MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
577 #endif
578
579 static struct platform_driver at91_rtc_driver = {
580 .probe = at91_rtc_probe,
581 .remove = at91_rtc_remove,
582 .shutdown = at91_rtc_shutdown,
583 .driver = {
584 .name = "rtc-at91sam9",
585 .pm = &at91_rtc_pm_ops,
586 .of_match_table = of_match_ptr(at91_rtc_dt_ids),
587 },
588 };
589
590 module_platform_driver(at91_rtc_driver);
591
592 MODULE_AUTHOR("Michel Benoit");
593 MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x");
594 MODULE_LICENSE("GPL");
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