drivers/cpufreq/imx6q-cpufreq.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/cpu.h>
  11 #include <linux/cpufreq.h>
  12 #include <linux/err.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/pm_opp.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19
  20 #define PU_SOC_VOLTAGE_NORMAL   1250000
  21 #define PU_SOC_VOLTAGE_HIGH     1275000
  22 #define FREQ_1P2_GHZ            1200000000
  23
  24 static struct regulator *arm_reg;
  25 static struct regulator *pu_reg;
  26 static struct regulator *soc_reg;
  27
  28 enum IMX6_CPUFREQ_CLKS {
  29         ARM,
  30         PLL1_SYS,
  31         STEP,
  32         PLL1_SW,
  33         PLL2_PFD2_396M,
  34         /* MX6UL requires two more clks */
  35         PLL2_BUS,
  36         SECONDARY_SEL,
  37 };
  38 #define IMX6Q_CPUFREQ_CLK_NUM           5
  39 #define IMX6UL_CPUFREQ_CLK_NUM          7
  40
  41 static int num_clks;
  42 static struct clk_bulk_data clks[] = {
  43         { .id = "arm" },
  44         { .id = "pll1_sys" },
  45         { .id = "step" },
  46         { .id = "pll1_sw" },
  47         { .id = "pll2_pfd2_396m" },
  48         { .id = "pll2_bus" },
  49         { .id = "secondary_sel" },
  50 };
  51
  52 static struct device *cpu_dev;
  53 static bool free_opp;
  54 static struct cpufreq_frequency_table *freq_table;
  55 static unsigned int max_freq;
  56 static unsigned int transition_latency;
  57
  58 static u32 *imx6_soc_volt;
  59 static u32 soc_opp_count;
  60
  61 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
  62 {
  63         struct dev_pm_opp *opp;
  64         unsigned long freq_hz, volt, volt_old;
  65         unsigned int old_freq, new_freq;
  66         bool pll1_sys_temp_enabled = false;
  67         int ret;
  68
  69         new_freq = freq_table[index].frequency;
  70         freq_hz = new_freq * 1000;
  71         old_freq = clk_get_rate(clks[ARM].clk) / 1000;
  72
  73         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
  74         if (IS_ERR(opp)) {
  75                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  76                 return PTR_ERR(opp);
  77         }
  78
  79         volt = dev_pm_opp_get_voltage(opp);
  80         dev_pm_opp_put(opp);
  81
  82         volt_old = regulator_get_voltage(arm_reg);
  83
  84         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  85                 old_freq / 1000, volt_old / 1000,
  86                 new_freq / 1000, volt / 1000);
  87
  88         /* scaling up?  scale voltage before frequency */
  89         if (new_freq > old_freq) {
  90                 if (!IS_ERR(pu_reg)) {
  91                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
  92                         if (ret) {
  93                                 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
  94                                 return ret;
  95                         }
  96                 }
  97                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
  98                 if (ret) {
  99                         dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
 100                         return ret;
 101                 }
 102                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 103                 if (ret) {
 104                         dev_err(cpu_dev,
 105                                 "failed to scale vddarm up: %d\n", ret);
 106                         return ret;
 107                 }
 108         }
 109
 110         /*
 111          * The setpoints are selected per PLL/PDF frequencies, so we need to
 112          * reprogram PLL for frequency scaling.  The procedure of reprogramming
 113          * PLL1 is as below.
 114          * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
 115          * flow is slightly different from other i.MX6 OSC.
 116          * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
 117          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
 118          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
 119          *  - Disable pll2_pfd2_396m_clk
 120          */
 121         if (of_machine_is_compatible("fsl,imx6ul") ||
 122             of_machine_is_compatible("fsl,imx6ull")) {
 123                 /*
 124                  * When changing pll1_sw_clk's parent to pll1_sys_clk,
 125                  * CPU may run at higher than 528MHz, this will lead to
 126                  * the system unstable if the voltage is lower than the
 127                  * voltage of 528MHz, so lower the CPU frequency to one
 128                  * half before changing CPU frequency.
 129                  */
 130                 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
 131                 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
 132                 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
 133                         clk_set_parent(clks[SECONDARY_SEL].clk,
 134                                        clks[PLL2_BUS].clk);
 135                 else
 136                         clk_set_parent(clks[SECONDARY_SEL].clk,
 137                                        clks[PLL2_PFD2_396M].clk);
 138                 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
 139                 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
 140                 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
 141                         clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
 142                         clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
 143                 }
 144         } else {
 145                 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
 146                 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
 147                 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
 148                         clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
 149                         clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
 150                 } else {
 151                         /* pll1_sys needs to be enabled for divider rate change to work. */
 152                         pll1_sys_temp_enabled = true;
 153                         clk_prepare_enable(clks[PLL1_SYS].clk);
 154                 }
 155         }
 156
 157         /* Ensure the arm clock divider is what we expect */
 158         ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
 159         if (ret) {
 160                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
 161                 regulator_set_voltage_tol(arm_reg, volt_old, 0);
 162                 return ret;
 163         }
 164
 165         /* PLL1 is only needed until after ARM-PODF is set. */
 166         if (pll1_sys_temp_enabled)
 167                 clk_disable_unprepare(clks[PLL1_SYS].clk);
 168
 169         /* scaling down?  scale voltage after frequency */
 170         if (new_freq < old_freq) {
 171                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 172                 if (ret) {
 173                         dev_warn(cpu_dev,
 174                                  "failed to scale vddarm down: %d\n", ret);
 175                         ret = 0;
 176                 }
 177                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
 178                 if (ret) {
 179                         dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
 180                         ret = 0;
 181                 }
 182                 if (!IS_ERR(pu_reg)) {
 183                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
 184                         if (ret) {
 185                                 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
 186                                 ret = 0;
 187                         }
 188                 }
 189         }
 190
 191         return 0;
 192 }
 193
 194 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
 195 {
 196         int ret;
 197
 198         policy->clk = clks[ARM].clk;
 199         ret = cpufreq_generic_init(policy, freq_table, transition_latency);
 200         policy->suspend_freq = max_freq;
 201
 202         return ret;
 203 }
 204
 205 static struct cpufreq_driver imx6q_cpufreq_driver = {
 206         .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
 207         .verify = cpufreq_generic_frequency_table_verify,
 208         .target_index = imx6q_set_target,
 209         .get = cpufreq_generic_get,
 210         .init = imx6q_cpufreq_init,
 211         .name = "imx6q-cpufreq",
 212         .attr = cpufreq_generic_attr,
 213         .suspend = cpufreq_generic_suspend,
 214 };
 215
 216 #define OCOTP_CFG3                      0x440
 217 #define OCOTP_CFG3_SPEED_SHIFT          16
 218 #define OCOTP_CFG3_SPEED_1P2GHZ         0x3
 219 #define OCOTP_CFG3_SPEED_996MHZ         0x2
 220 #define OCOTP_CFG3_SPEED_852MHZ         0x1
 221
 222 static void imx6q_opp_check_speed_grading(struct device *dev)
 223 {
 224         struct device_node *np;
 225         void __iomem *base;
 226         u32 val;
 227
 228         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
 229         if (!np)
 230                 return;
 231
 232         base = of_iomap(np, 0);
 233         if (!base) {
 234                 dev_err(dev, "failed to map ocotp\n");
 235                 goto put_node;
 236         }
 237
 238         /*
 239          * SPEED_GRADING[1:0] defines the max speed of ARM:
 240          * 2b'11: 1200000000Hz;
 241          * 2b'10: 996000000Hz;
 242          * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
 243          * 2b'00: 792000000Hz;
 244          * We need to set the max speed of ARM according to fuse map.
 245          */
 246         val = readl_relaxed(base + OCOTP_CFG3);
 247         val >>= OCOTP_CFG3_SPEED_SHIFT;
 248         val &= 0x3;
 249
 250         if (val < OCOTP_CFG3_SPEED_996MHZ)
 251                 if (dev_pm_opp_disable(dev, 996000000))
 252                         dev_warn(dev, "failed to disable 996MHz OPP\n");
 253
 254         if (of_machine_is_compatible("fsl,imx6q") ||
 255             of_machine_is_compatible("fsl,imx6qp")) {
 256                 if (val != OCOTP_CFG3_SPEED_852MHZ)
 257                         if (dev_pm_opp_disable(dev, 852000000))
 258                                 dev_warn(dev, "failed to disable 852MHz OPP\n");
 259                 if (val != OCOTP_CFG3_SPEED_1P2GHZ)
 260                         if (dev_pm_opp_disable(dev, 1200000000))
 261                                 dev_warn(dev, "failed to disable 1.2GHz OPP\n");
 262         }
 263         iounmap(base);
 264 put_node:
 265         of_node_put(np);
 266 }
 267
 268 #define OCOTP_CFG3_6UL_SPEED_696MHZ     0x2
 269 #define OCOTP_CFG3_6ULL_SPEED_792MHZ    0x2
 270 #define OCOTP_CFG3_6ULL_SPEED_900MHZ    0x3
 271
 272 static void imx6ul_opp_check_speed_grading(struct device *dev)
 273 {
 274         struct device_node *np;
 275         void __iomem *base;
 276         u32 val;
 277
 278         np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
 279         if (!np)
 280                 return;
 281
 282         base = of_iomap(np, 0);
 283         if (!base) {
 284                 dev_err(dev, "failed to map ocotp\n");
 285                 goto put_node;
 286         }
 287
 288         /*
 289          * Speed GRADING[1:0] defines the max speed of ARM:
 290          * 2b'00: Reserved;
 291          * 2b'01: 528000000Hz;
 292          * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
 293          * 2b'11: 900000000Hz on i.MX6ULL only;
 294          * We need to set the max speed of ARM according to fuse map.
 295          */
 296         val = readl_relaxed(base + OCOTP_CFG3);
 297         val >>= OCOTP_CFG3_SPEED_SHIFT;
 298         val &= 0x3;
 299
 300         if (of_machine_is_compatible("fsl,imx6ul")) {
 301                 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
 302                         if (dev_pm_opp_disable(dev, 696000000))
 303                                 dev_warn(dev, "failed to disable 696MHz OPP\n");
 304         }
 305
 306         if (of_machine_is_compatible("fsl,imx6ull")) {
 307                 if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
 308                         if (dev_pm_opp_disable(dev, 792000000))
 309                                 dev_warn(dev, "failed to disable 792MHz OPP\n");
 310
 311                 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
 312                         if (dev_pm_opp_disable(dev, 900000000))
 313                                 dev_warn(dev, "failed to disable 900MHz OPP\n");
 314         }
 315
 316         iounmap(base);
 317 put_node:
 318         of_node_put(np);
 319 }
 320
 321 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 322 {
 323         struct device_node *np;
 324         struct dev_pm_opp *opp;
 325         unsigned long min_volt, max_volt;
 326         int num, ret;
 327         const struct property *prop;
 328         const __be32 *val;
 329         u32 nr, i, j;
 330
 331         cpu_dev = get_cpu_device(0);
 332         if (!cpu_dev) {
 333                 pr_err("failed to get cpu0 device\n");
 334                 return -ENODEV;
 335         }
 336
 337         np = of_node_get(cpu_dev->of_node);
 338         if (!np) {
 339                 dev_err(cpu_dev, "failed to find cpu0 node\n");
 340                 return -ENOENT;
 341         }
 342
 343         if (of_machine_is_compatible("fsl,imx6ul") ||
 344             of_machine_is_compatible("fsl,imx6ull"))
 345                 num_clks = IMX6UL_CPUFREQ_CLK_NUM;
 346         else
 347                 num_clks = IMX6Q_CPUFREQ_CLK_NUM;
 348
 349         ret = clk_bulk_get(cpu_dev, num_clks, clks);
 350         if (ret)
 351                 goto put_node;
 352
 353         arm_reg = regulator_get(cpu_dev, "arm");
 354         pu_reg = regulator_get_optional(cpu_dev, "pu");
 355         soc_reg = regulator_get(cpu_dev, "soc");
 356         if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
 357                         PTR_ERR(soc_reg) == -EPROBE_DEFER ||
 358                         PTR_ERR(pu_reg) == -EPROBE_DEFER) {
 359                 ret = -EPROBE_DEFER;
 360                 dev_dbg(cpu_dev, "regulators not ready, defer\n");
 361                 goto put_reg;
 362         }
 363         if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
 364                 dev_err(cpu_dev, "failed to get regulators\n");
 365                 ret = -ENOENT;
 366                 goto put_reg;
 367         }
 368
 369         ret = dev_pm_opp_of_add_table(cpu_dev);
 370         if (ret < 0) {
 371                 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
 372                 goto put_reg;
 373         }
 374
 375         if (of_machine_is_compatible("fsl,imx6ul") ||
 376             of_machine_is_compatible("fsl,imx6ull"))
 377                 imx6ul_opp_check_speed_grading(cpu_dev);
 378         else
 379                 imx6q_opp_check_speed_grading(cpu_dev);
 380
 381         /* Because we have added the OPPs here, we must free them */
 382         free_opp = true;
 383         num = dev_pm_opp_get_opp_count(cpu_dev);
 384         if (num < 0) {
 385                 ret = num;
 386                 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
 387                 goto out_free_opp;
 388         }
 389
 390         ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
 391         if (ret) {
 392                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
 393                 goto out_free_opp;
 394         }
 395
 396         /* Make imx6_soc_volt array's size same as arm opp number */
 397         imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
 398                                      GFP_KERNEL);
 399         if (imx6_soc_volt == NULL) {
 400                 ret = -ENOMEM;
 401                 goto free_freq_table;
 402         }
 403
 404         prop = of_find_property(np, "fsl,soc-operating-points", NULL);
 405         if (!prop || !prop->value)
 406                 goto soc_opp_out;
 407
 408         /*
 409          * Each OPP is a set of tuples consisting of frequency and
 410          * voltage like <freq-kHz vol-uV>.
 411          */
 412         nr = prop->length / sizeof(u32);
 413         if (nr % 2 || (nr / 2) < num)
 414                 goto soc_opp_out;
 415
 416         for (j = 0; j < num; j++) {
 417                 val = prop->value;
 418                 for (i = 0; i < nr / 2; i++) {
 419                         unsigned long freq = be32_to_cpup(val++);
 420                         unsigned long volt = be32_to_cpup(val++);
 421                         if (freq_table[j].frequency == freq) {
 422                                 imx6_soc_volt[soc_opp_count++] = volt;
 423                                 break;
 424                         }
 425                 }
 426         }
 427
 428 soc_opp_out:
 429         /* use fixed soc opp volt if no valid soc opp info found in dtb */
 430         if (soc_opp_count != num) {
 431                 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
 432                 for (j = 0; j < num; j++)
 433                         imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
 434                 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
 435                         imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
 436         }
 437
 438         if (of_property_read_u32(np, "clock-latency", &transition_latency))
 439                 transition_latency = CPUFREQ_ETERNAL;
 440
 441         /*
 442          * Calculate the ramp time for max voltage change in the
 443          * VDDSOC and VDDPU regulators.
 444          */
 445         ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 446         if (ret > 0)
 447                 transition_latency += ret * 1000;
 448         if (!IS_ERR(pu_reg)) {
 449                 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 450                 if (ret > 0)
 451                         transition_latency += ret * 1000;
 452         }
 453
 454         /*
 455          * OPP is maintained in order of increasing frequency, and
 456          * freq_table initialised from OPP is therefore sorted in the
 457          * same order.
 458          */
 459         max_freq = freq_table[--num].frequency;
 460         opp = dev_pm_opp_find_freq_exact(cpu_dev,
 461                                   freq_table[0].frequency * 1000, true);
 462         min_volt = dev_pm_opp_get_voltage(opp);
 463         dev_pm_opp_put(opp);
 464         opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
 465         max_volt = dev_pm_opp_get_voltage(opp);
 466         dev_pm_opp_put(opp);
 467
 468         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
 469         if (ret > 0)
 470                 transition_latency += ret * 1000;
 471
 472         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
 473         if (ret) {
 474                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
 475                 goto free_freq_table;
 476         }
 477
 478         of_node_put(np);
 479         return 0;
 480
 481 free_freq_table:
 482         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 483 out_free_opp:
 484         if (free_opp)
 485                 dev_pm_opp_of_remove_table(cpu_dev);
 486 put_reg:
 487         if (!IS_ERR(arm_reg))
 488                 regulator_put(arm_reg);
 489         if (!IS_ERR(pu_reg))
 490                 regulator_put(pu_reg);
 491         if (!IS_ERR(soc_reg))
 492                 regulator_put(soc_reg);
 493
 494         clk_bulk_put(num_clks, clks);
 495 put_node:
 496         of_node_put(np);
 497
 498         return ret;
 499 }
 500
 501 static int imx6q_cpufreq_remove(struct platform_device *pdev)
 502 {
 503         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
 504         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 505         if (free_opp)
 506                 dev_pm_opp_of_remove_table(cpu_dev);
 507         regulator_put(arm_reg);
 508         if (!IS_ERR(pu_reg))
 509                 regulator_put(pu_reg);
 510         regulator_put(soc_reg);
 511
 512         clk_bulk_put(num_clks, clks);
 513
 514         return 0;
 515 }
 516
 517 static struct platform_driver imx6q_cpufreq_platdrv = {
 518         .driver = {
 519                 .name   = "imx6q-cpufreq",
 520         },
 521         .probe          = imx6q_cpufreq_probe,
 522         .remove         = imx6q_cpufreq_remove,
 523 };
 524 module_platform_driver(imx6q_cpufreq_platdrv);
 525
 526 MODULE_ALIAS("platform:imx6q-cpufreq");
 527 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
 528 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
 529 MODULE_LICENSE("GPL");