sound/soc/ux500/ux500_msp_i2s.h

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2012
   3  *
   4  * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
   5  *         for ST-Ericsson.
   6  *
   7  * License terms:
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  */
  13
  14
  15 #ifndef UX500_MSP_I2S_H
  16 #define UX500_MSP_I2S_H
  17
  18 #include <linux/platform_device.h>
  19 #include <linux/platform_data/asoc-ux500-msp.h>
  20
  21 #define MSP_INPUT_FREQ_APB 48000000
  22
  23 /*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono),
  24  *   32 bits accesses (stereo).
  25  ***/
  26 enum msp_stereo_mode {
  27         MSP_MONO,
  28         MSP_STEREO
  29 };
  30
  31 /* Direction (Transmit/Receive mode) */
  32 enum msp_direction {
  33         MSP_TX = 1,
  34         MSP_RX = 2
  35 };
  36
  37 /* Transmit and receive configuration register */
  38 #define MSP_BIG_ENDIAN           0x00000000
  39 #define MSP_LITTLE_ENDIAN        0x00001000
  40 #define MSP_UNEXPECTED_FS_ABORT  0x00000000
  41 #define MSP_UNEXPECTED_FS_IGNORE 0x00008000
  42 #define MSP_NON_MODE_BIT_MASK    0x00009000
  43
  44 /* Global configuration register */
  45 #define RX_ENABLE             0x00000001
  46 #define RX_FIFO_ENABLE        0x00000002
  47 #define RX_SYNC_SRG           0x00000010
  48 #define RX_CLK_POL_RISING     0x00000020
  49 #define RX_CLK_SEL_SRG        0x00000040
  50 #define TX_ENABLE             0x00000100
  51 #define TX_FIFO_ENABLE        0x00000200
  52 #define TX_SYNC_SRG_PROG      0x00001800
  53 #define TX_SYNC_SRG_AUTO      0x00001000
  54 #define TX_CLK_POL_RISING     0x00002000
  55 #define TX_CLK_SEL_SRG        0x00004000
  56 #define TX_EXTRA_DELAY_ENABLE 0x00008000
  57 #define SRG_ENABLE            0x00010000
  58 #define FRAME_GEN_ENABLE      0x00100000
  59 #define SRG_CLK_SEL_APB       0x00000000
  60 #define RX_FIFO_SYNC_HI       0x00000000
  61 #define TX_FIFO_SYNC_HI       0x00000000
  62 #define SPI_CLK_MODE_NORMAL   0x00000000
  63
  64 #define MSP_FRAME_SIZE_AUTO -1
  65
  66 #define MSP_DR          0x00
  67 #define MSP_GCR         0x04
  68 #define MSP_TCF         0x08
  69 #define MSP_RCF         0x0c
  70 #define MSP_SRG         0x10
  71 #define MSP_FLR         0x14
  72 #define MSP_DMACR       0x18
  73
  74 #define MSP_IMSC        0x20
  75 #define MSP_RIS         0x24
  76 #define MSP_MIS         0x28
  77 #define MSP_ICR         0x2c
  78 #define MSP_MCR         0x30
  79 #define MSP_RCV         0x34
  80 #define MSP_RCM         0x38
  81
  82 #define MSP_TCE0        0x40
  83 #define MSP_TCE1        0x44
  84 #define MSP_TCE2        0x48
  85 #define MSP_TCE3        0x4c
  86
  87 #define MSP_RCE0        0x60
  88 #define MSP_RCE1        0x64
  89 #define MSP_RCE2        0x68
  90 #define MSP_RCE3        0x6c
  91 #define MSP_IODLY       0x70
  92
  93 #define MSP_ITCR        0x80
  94 #define MSP_ITIP        0x84
  95 #define MSP_ITOP        0x88
  96 #define MSP_TSTDR       0x8c
  97
  98 #define MSP_PID0        0xfe0
  99 #define MSP_PID1        0xfe4
 100 #define MSP_PID2        0xfe8
 101 #define MSP_PID3        0xfec
 102
 103 #define MSP_CID0        0xff0
 104 #define MSP_CID1        0xff4
 105 #define MSP_CID2        0xff8
 106 #define MSP_CID3        0xffc
 107
 108 /* Protocol dependant parameters list */
 109 #define RX_ENABLE_MASK          BIT(0)
 110 #define RX_FIFO_ENABLE_MASK     BIT(1)
 111 #define RX_FSYNC_MASK           BIT(2)
 112 #define DIRECT_COMPANDING_MASK  BIT(3)
 113 #define RX_SYNC_SEL_MASK        BIT(4)
 114 #define RX_CLK_POL_MASK         BIT(5)
 115 #define RX_CLK_SEL_MASK         BIT(6)
 116 #define LOOPBACK_MASK           BIT(7)
 117 #define TX_ENABLE_MASK          BIT(8)
 118 #define TX_FIFO_ENABLE_MASK     BIT(9)
 119 #define TX_FSYNC_MASK           BIT(10)
 120 #define TX_MSP_TDR_TSR          BIT(11)
 121 #define TX_SYNC_SEL_MASK        (BIT(12) | BIT(11))
 122 #define TX_CLK_POL_MASK         BIT(13)
 123 #define TX_CLK_SEL_MASK         BIT(14)
 124 #define TX_EXTRA_DELAY_MASK     BIT(15)
 125 #define SRG_ENABLE_MASK         BIT(16)
 126 #define SRG_CLK_POL_MASK        BIT(17)
 127 #define SRG_CLK_SEL_MASK        (BIT(19) | BIT(18))
 128 #define FRAME_GEN_EN_MASK       BIT(20)
 129 #define SPI_CLK_MODE_MASK       (BIT(22) | BIT(21))
 130 #define SPI_BURST_MODE_MASK     BIT(23)
 131
 132 #define RXEN_SHIFT              0
 133 #define RFFEN_SHIFT             1
 134 #define RFSPOL_SHIFT            2
 135 #define DCM_SHIFT               3
 136 #define RFSSEL_SHIFT            4
 137 #define RCKPOL_SHIFT            5
 138 #define RCKSEL_SHIFT            6
 139 #define LBM_SHIFT               7
 140 #define TXEN_SHIFT              8
 141 #define TFFEN_SHIFT             9
 142 #define TFSPOL_SHIFT            10
 143 #define TFSSEL_SHIFT            11
 144 #define TCKPOL_SHIFT            13
 145 #define TCKSEL_SHIFT            14
 146 #define TXDDL_SHIFT             15
 147 #define SGEN_SHIFT              16
 148 #define SCKPOL_SHIFT            17
 149 #define SCKSEL_SHIFT            18
 150 #define FGEN_SHIFT              20
 151 #define SPICKM_SHIFT            21
 152 #define TBSWAP_SHIFT            28
 153
 154 #define RCKPOL_MASK             BIT(0)
 155 #define TCKPOL_MASK             BIT(0)
 156 #define SPICKM_MASK             (BIT(1) | BIT(0))
 157 #define MSP_RX_CLKPOL_BIT(n)     ((n & RCKPOL_MASK) << RCKPOL_SHIFT)
 158 #define MSP_TX_CLKPOL_BIT(n)     ((n & TCKPOL_MASK) << TCKPOL_SHIFT)
 159
 160 #define P1ELEN_SHIFT            0
 161 #define P1FLEN_SHIFT            3
 162 #define DTYP_SHIFT              10
 163 #define ENDN_SHIFT              12
 164 #define DDLY_SHIFT              13
 165 #define FSIG_SHIFT              15
 166 #define P2ELEN_SHIFT            16
 167 #define P2FLEN_SHIFT            19
 168 #define P2SM_SHIFT              26
 169 #define P2EN_SHIFT              27
 170 #define FSYNC_SHIFT             15
 171
 172 #define P1ELEN_MASK             0x00000007
 173 #define P2ELEN_MASK             0x00070000
 174 #define P1FLEN_MASK             0x00000378
 175 #define P2FLEN_MASK             0x03780000
 176 #define DDLY_MASK               0x00003000
 177 #define DTYP_MASK               0x00000600
 178 #define P2SM_MASK               0x04000000
 179 #define P2EN_MASK               0x08000000
 180 #define ENDN_MASK               0x00001000
 181 #define TFSPOL_MASK             0x00000400
 182 #define TBSWAP_MASK             0x30000000
 183 #define COMPANDING_MODE_MASK    0x00000c00
 184 #define FSYNC_MASK              0x00008000
 185
 186 #define MSP_P1_ELEM_LEN_BITS(n)         (n & P1ELEN_MASK)
 187 #define MSP_P2_ELEM_LEN_BITS(n)         (((n) << P2ELEN_SHIFT) & P2ELEN_MASK)
 188 #define MSP_P1_FRAME_LEN_BITS(n)        (((n) << P1FLEN_SHIFT) & P1FLEN_MASK)
 189 #define MSP_P2_FRAME_LEN_BITS(n)        (((n) << P2FLEN_SHIFT) & P2FLEN_MASK)
 190 #define MSP_DATA_DELAY_BITS(n)          (((n) << DDLY_SHIFT) & DDLY_MASK)
 191 #define MSP_DATA_TYPE_BITS(n)           (((n) << DTYP_SHIFT) & DTYP_MASK)
 192 #define MSP_P2_START_MODE_BIT(n)        ((n << P2SM_SHIFT) & P2SM_MASK)
 193 #define MSP_P2_ENABLE_BIT(n)            ((n << P2EN_SHIFT) & P2EN_MASK)
 194 #define MSP_SET_ENDIANNES_BIT(n)        ((n << ENDN_SHIFT) & ENDN_MASK)
 195 #define MSP_FSYNC_POL(n)                ((n << TFSPOL_SHIFT) & TFSPOL_MASK)
 196 #define MSP_DATA_WORD_SWAP(n)           ((n << TBSWAP_SHIFT) & TBSWAP_MASK)
 197 #define MSP_SET_COMPANDING_MODE(n)      ((n << DTYP_SHIFT) & \
 198                                                 COMPANDING_MODE_MASK)
 199 #define MSP_SET_FSYNC_IGNORE(n)         ((n << FSYNC_SHIFT) & FSYNC_MASK)
 200
 201 /* Flag register */
 202 #define RX_BUSY                 BIT(0)
 203 #define RX_FIFO_EMPTY           BIT(1)
 204 #define RX_FIFO_FULL            BIT(2)
 205 #define TX_BUSY                 BIT(3)
 206 #define TX_FIFO_EMPTY           BIT(4)
 207 #define TX_FIFO_FULL            BIT(5)
 208
 209 #define RBUSY_SHIFT             0
 210 #define RFE_SHIFT               1
 211 #define RFU_SHIFT               2
 212 #define TBUSY_SHIFT             3
 213 #define TFE_SHIFT               4
 214 #define TFU_SHIFT               5
 215
 216 /* Multichannel control register */
 217 #define RMCEN_SHIFT             0
 218 #define RMCSF_SHIFT             1
 219 #define RCMPM_SHIFT             3
 220 #define TMCEN_SHIFT             5
 221 #define TNCSF_SHIFT             6
 222
 223 /* Sample rate generator register */
 224 #define SCKDIV_SHIFT            0
 225 #define FRWID_SHIFT             10
 226 #define FRPER_SHIFT             16
 227
 228 #define SCK_DIV_MASK            0x0000003FF
 229 #define FRAME_WIDTH_BITS(n)     (((n) << FRWID_SHIFT)  & 0x0000FC00)
 230 #define FRAME_PERIOD_BITS(n)    (((n) << FRPER_SHIFT) & 0x1FFF0000)
 231
 232 /* DMA controller register */
 233 #define RX_DMA_ENABLE           BIT(0)
 234 #define TX_DMA_ENABLE           BIT(1)
 235
 236 #define RDMAE_SHIFT             0
 237 #define TDMAE_SHIFT             1
 238
 239 /* Interrupt Register */
 240 #define RX_SERVICE_INT          BIT(0)
 241 #define RX_OVERRUN_ERROR_INT    BIT(1)
 242 #define RX_FSYNC_ERR_INT        BIT(2)
 243 #define RX_FSYNC_INT            BIT(3)
 244 #define TX_SERVICE_INT          BIT(4)
 245 #define TX_UNDERRUN_ERR_INT     BIT(5)
 246 #define TX_FSYNC_ERR_INT        BIT(6)
 247 #define TX_FSYNC_INT            BIT(7)
 248 #define ALL_INT                 0x000000ff
 249
 250 /* MSP test control register */
 251 #define MSP_ITCR_ITEN           BIT(0)
 252 #define MSP_ITCR_TESTFIFO       BIT(1)
 253
 254 #define RMCEN_BIT   0
 255 #define RMCSF_BIT   1
 256 #define RCMPM_BIT   3
 257 #define TMCEN_BIT   5
 258 #define TNCSF_BIT   6
 259
 260 /* Single or dual phase mode */
 261 enum msp_phase_mode {
 262         MSP_SINGLE_PHASE,
 263         MSP_DUAL_PHASE
 264 };
 265
 266 /* Frame length */
 267 enum msp_frame_length {
 268         MSP_FRAME_LEN_1 = 0,
 269         MSP_FRAME_LEN_2 = 1,
 270         MSP_FRAME_LEN_4 = 3,
 271         MSP_FRAME_LEN_8 = 7,
 272         MSP_FRAME_LEN_12 = 11,
 273         MSP_FRAME_LEN_16 = 15,
 274         MSP_FRAME_LEN_20 = 19,
 275         MSP_FRAME_LEN_32 = 31,
 276         MSP_FRAME_LEN_48 = 47,
 277         MSP_FRAME_LEN_64 = 63
 278 };
 279
 280 /* Element length */
 281 enum msp_elem_length {
 282         MSP_ELEM_LEN_8 = 0,
 283         MSP_ELEM_LEN_10 = 1,
 284         MSP_ELEM_LEN_12 = 2,
 285         MSP_ELEM_LEN_14 = 3,
 286         MSP_ELEM_LEN_16 = 4,
 287         MSP_ELEM_LEN_20 = 5,
 288         MSP_ELEM_LEN_24 = 6,
 289         MSP_ELEM_LEN_32 = 7
 290 };
 291
 292 enum msp_data_xfer_width {
 293         MSP_DATA_TRANSFER_WIDTH_BYTE,
 294         MSP_DATA_TRANSFER_WIDTH_HALFWORD,
 295         MSP_DATA_TRANSFER_WIDTH_WORD
 296 };
 297
 298 enum msp_frame_sync {
 299         MSP_FSYNC_UNIGNORE = 0,
 300         MSP_FSYNC_IGNORE = 1,
 301 };
 302
 303 enum msp_phase2_start_mode {
 304         MSP_PHASE2_START_MODE_IMEDIATE,
 305         MSP_PHASE2_START_MODE_FSYNC
 306 };
 307
 308 enum msp_btf {
 309         MSP_BTF_MS_BIT_FIRST = 0,
 310         MSP_BTF_LS_BIT_FIRST = 1
 311 };
 312
 313 enum msp_fsync_pol {
 314         MSP_FSYNC_POL_ACT_HI = 0,
 315         MSP_FSYNC_POL_ACT_LO = 1
 316 };
 317
 318 /* Data delay (in bit clock cycles) */
 319 enum msp_delay {
 320         MSP_DELAY_0 = 0,
 321         MSP_DELAY_1 = 1,
 322         MSP_DELAY_2 = 2,
 323         MSP_DELAY_3 = 3
 324 };
 325
 326 /* Configurations of clocks (transmit, receive or sample rate generator) */
 327 enum msp_edge {
 328         MSP_FALLING_EDGE = 0,
 329         MSP_RISING_EDGE = 1,
 330 };
 331
 332 enum msp_hws {
 333         MSP_SWAP_NONE = 0,
 334         MSP_SWAP_BYTE_PER_WORD = 1,
 335         MSP_SWAP_BYTE_PER_HALF_WORD = 2,
 336         MSP_SWAP_HALF_WORD_PER_WORD = 3
 337 };
 338
 339 enum msp_compress_mode {
 340         MSP_COMPRESS_MODE_LINEAR = 0,
 341         MSP_COMPRESS_MODE_MU_LAW = 2,
 342         MSP_COMPRESS_MODE_A_LAW = 3
 343 };
 344
 345 enum msp_expand_mode {
 346         MSP_EXPAND_MODE_LINEAR = 0,
 347         MSP_EXPAND_MODE_LINEAR_SIGNED = 1,
 348         MSP_EXPAND_MODE_MU_LAW = 2,
 349         MSP_EXPAND_MODE_A_LAW = 3
 350 };
 351
 352 #define MSP_FRAME_PERIOD_IN_MONO_MODE 256
 353 #define MSP_FRAME_PERIOD_IN_STEREO_MODE 32
 354 #define MSP_FRAME_WIDTH_IN_STEREO_MODE 16
 355
 356 enum msp_protocol {
 357         MSP_I2S_PROTOCOL,
 358         MSP_PCM_PROTOCOL,
 359         MSP_PCM_COMPAND_PROTOCOL,
 360         MSP_INVALID_PROTOCOL
 361 };
 362
 363 /*
 364  * No of registers to backup during
 365  * suspend resume
 366  */
 367 #define MAX_MSP_BACKUP_REGS 36
 368
 369 enum i2s_direction_t {
 370         MSP_DIR_TX = 0x01,
 371         MSP_DIR_RX = 0x02,
 372 };
 373
 374 enum msp_data_size {
 375         MSP_DATA_BITS_DEFAULT = -1,
 376         MSP_DATA_BITS_8 = 0x00,
 377         MSP_DATA_BITS_10,
 378         MSP_DATA_BITS_12,
 379         MSP_DATA_BITS_14,
 380         MSP_DATA_BITS_16,
 381         MSP_DATA_BITS_20,
 382         MSP_DATA_BITS_24,
 383         MSP_DATA_BITS_32,
 384 };
 385
 386 enum msp_state {
 387         MSP_STATE_IDLE = 0,
 388         MSP_STATE_CONFIGURED = 1,
 389         MSP_STATE_RUNNING = 2,
 390 };
 391
 392 enum msp_rx_comparison_enable_mode {
 393         MSP_COMPARISON_DISABLED = 0,
 394         MSP_COMPARISON_NONEQUAL_ENABLED = 2,
 395         MSP_COMPARISON_EQUAL_ENABLED = 3
 396 };
 397
 398 struct msp_multichannel_config {
 399         bool rx_multichannel_enable;
 400         bool tx_multichannel_enable;
 401         enum msp_rx_comparison_enable_mode rx_comparison_enable_mode;
 402         u8 padding;
 403         u32 comparison_value;
 404         u32 comparison_mask;
 405         u32 rx_channel_0_enable;
 406         u32 rx_channel_1_enable;
 407         u32 rx_channel_2_enable;
 408         u32 rx_channel_3_enable;
 409         u32 tx_channel_0_enable;
 410         u32 tx_channel_1_enable;
 411         u32 tx_channel_2_enable;
 412         u32 tx_channel_3_enable;
 413 };
 414
 415 struct msp_protdesc {
 416         u32 rx_phase_mode;
 417         u32 tx_phase_mode;
 418         u32 rx_phase2_start_mode;
 419         u32 tx_phase2_start_mode;
 420         u32 rx_byte_order;
 421         u32 tx_byte_order;
 422         u32 rx_frame_len_1;
 423         u32 rx_frame_len_2;
 424         u32 tx_frame_len_1;
 425         u32 tx_frame_len_2;
 426         u32 rx_elem_len_1;
 427         u32 rx_elem_len_2;
 428         u32 tx_elem_len_1;
 429         u32 tx_elem_len_2;
 430         u32 rx_data_delay;
 431         u32 tx_data_delay;
 432         u32 rx_clk_pol;
 433         u32 tx_clk_pol;
 434         u32 rx_fsync_pol;
 435         u32 tx_fsync_pol;
 436         u32 rx_half_word_swap;
 437         u32 tx_half_word_swap;
 438         u32 compression_mode;
 439         u32 expansion_mode;
 440         u32 frame_sync_ignore;
 441         u32 frame_period;
 442         u32 frame_width;
 443         u32 clocks_per_frame;
 444 };
 445
 446 struct ux500_msp_config {
 447         unsigned int f_inputclk;
 448         unsigned int rx_clk_sel;
 449         unsigned int tx_clk_sel;
 450         unsigned int srg_clk_sel;
 451         unsigned int rx_fsync_pol;
 452         unsigned int tx_fsync_pol;
 453         unsigned int rx_fsync_sel;
 454         unsigned int tx_fsync_sel;
 455         unsigned int rx_fifo_config;
 456         unsigned int tx_fifo_config;
 457         unsigned int loopback_enable;
 458         unsigned int tx_data_enable;
 459         unsigned int default_protdesc;
 460         struct msp_protdesc protdesc;
 461         int multichannel_configured;
 462         struct msp_multichannel_config multichannel_config;
 463         unsigned int direction;
 464         unsigned int protocol;
 465         unsigned int frame_freq;
 466         enum msp_data_size data_size;
 467         unsigned int def_elem_len;
 468         unsigned int iodelay;
 469 };
 470
 471 struct ux500_msp_dma_params {
 472         unsigned int data_size;
 473         dma_addr_t tx_rx_addr;
 474         struct stedma40_chan_cfg *dma_cfg;
 475 };
 476
 477 struct ux500_msp {
 478         enum msp_i2s_id id;
 479         void __iomem *registers;
 480         struct device *dev;
 481         struct ux500_msp_dma_params playback_dma_data;
 482         struct ux500_msp_dma_params capture_dma_data;
 483         enum msp_state msp_state;
 484         int def_elem_len;
 485         unsigned int dir_busy;
 486         int loopback_enable;
 487         unsigned int f_bitclk;
 488 };
 489
 490 struct msp_i2s_platform_data;
 491 int ux500_msp_i2s_init_msp(struct platform_device *pdev,
 492                         struct ux500_msp **msp_p,
 493                         struct msp_i2s_platform_data *platform_data);
 494 void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev,
 495                         struct ux500_msp *msp);
 496 int ux500_msp_i2s_open(struct ux500_msp *msp, struct ux500_msp_config *config);
 497 int ux500_msp_i2s_close(struct ux500_msp *msp,
 498                         unsigned int dir);
 499 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd,
 500                         int direction);
 501
 502 #endif