| blob | 7f17cd14839ba5413abdcee9666ac5a77b0a62c7 |
1 /*
2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
3 All rights reserved.
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
8 * Redistributions of source code must retain the above copyright notice,
9 this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 this list of conditions and the following disclaimer in the documentation
12 and/or other materials provided with the distribution.
13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works
14 nor the names of its contributors may be used to endorse or promote
15 products derived from this software without specific prior written
16 permission.
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 POSSIBILITY OF SUCH DAMAGE.
30 DRXJ specific implementation of DRX driver
31 authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
33 The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was
34 written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
36 This program is free software; you can redistribute it and/or modify
37 it under the terms of the GNU General Public License as published by
38 the Free Software Foundation; either version 2 of the License, or
39 (at your option) any later version.
41 This program is distributed in the hope that it will be useful,
42 but WITHOUT ANY WARRANTY; without even the implied warranty of
43 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45 GNU General Public License for more details.
47 You should have received a copy of the GNU General Public License
48 along with this program; if not, write to the Free Software
49 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
50 */
52 /*-----------------------------------------------------------------------------
53 INCLUDE FILES
54 ----------------------------------------------------------------------------*/
58 #include <linux/module.h>
59 #include <linux/init.h>
60 #include <linux/string.h>
61 #include <linux/slab.h>
69 /*============================================================================*/
70 /*=== DEFINES ================================================================*/
71 /*============================================================================*/
75 /**
76 * \brief Maximum u32 value.
77 */
78 #ifndef MAX_U32
79 #define MAX_U32 ((u32) (0xFFFFFFFFL))
80 #endif
82 /* Customer configurable hardware settings, etc */
83 #ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
84 #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
85 #endif
87 #ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
88 #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
89 #endif
91 #ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH
92 #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06
93 #endif
95 #ifndef OOB_CRX_DRIVE_STRENGTH
96 #define OOB_CRX_DRIVE_STRENGTH 0x02
97 #endif
99 #ifndef OOB_DRX_DRIVE_STRENGTH
100 #define OOB_DRX_DRIVE_STRENGTH 0x02
101 #endif
102 /**** START DJCOMBO patches to DRXJ registermap constants *********************/
103 /**** registermap 200706071303 from drxj **************************************/
104 #define ATV_TOP_CR_AMP_TH_FM 0x0
105 #define ATV_TOP_CR_AMP_TH_L 0xA
106 #define ATV_TOP_CR_AMP_TH_LP 0xA
107 #define ATV_TOP_CR_AMP_TH_BG 0x8
108 #define ATV_TOP_CR_AMP_TH_DK 0x8
109 #define ATV_TOP_CR_AMP_TH_I 0x8
110 #define ATV_TOP_CR_CONT_CR_D_MN 0x18
111 #define ATV_TOP_CR_CONT_CR_D_FM 0x0
112 #define ATV_TOP_CR_CONT_CR_D_L 0x20
113 #define ATV_TOP_CR_CONT_CR_D_LP 0x20
114 #define ATV_TOP_CR_CONT_CR_D_BG 0x18
115 #define ATV_TOP_CR_CONT_CR_D_DK 0x18
116 #define ATV_TOP_CR_CONT_CR_D_I 0x18
117 #define ATV_TOP_CR_CONT_CR_I_MN 0x80
118 #define ATV_TOP_CR_CONT_CR_I_FM 0x0
119 #define ATV_TOP_CR_CONT_CR_I_L 0x80
120 #define ATV_TOP_CR_CONT_CR_I_LP 0x80
121 #define ATV_TOP_CR_CONT_CR_I_BG 0x80
122 #define ATV_TOP_CR_CONT_CR_I_DK 0x80
123 #define ATV_TOP_CR_CONT_CR_I_I 0x80
124 #define ATV_TOP_CR_CONT_CR_P_MN 0x4
125 #define ATV_TOP_CR_CONT_CR_P_FM 0x0
126 #define ATV_TOP_CR_CONT_CR_P_L 0x4
127 #define ATV_TOP_CR_CONT_CR_P_LP 0x4
128 #define ATV_TOP_CR_CONT_CR_P_BG 0x4
129 #define ATV_TOP_CR_CONT_CR_P_DK 0x4
130 #define ATV_TOP_CR_CONT_CR_P_I 0x4
131 #define ATV_TOP_CR_OVM_TH_MN 0xA0
132 #define ATV_TOP_CR_OVM_TH_FM 0x0
133 #define ATV_TOP_CR_OVM_TH_L 0xA0
134 #define ATV_TOP_CR_OVM_TH_LP 0xA0
135 #define ATV_TOP_CR_OVM_TH_BG 0xA0
136 #define ATV_TOP_CR_OVM_TH_DK 0xA0
137 #define ATV_TOP_CR_OVM_TH_I 0xA0
138 #define ATV_TOP_EQU0_EQU_C0_FM 0x0
139 #define ATV_TOP_EQU0_EQU_C0_L 0x3
140 #define ATV_TOP_EQU0_EQU_C0_LP 0x3
141 #define ATV_TOP_EQU0_EQU_C0_BG 0x7
142 #define ATV_TOP_EQU0_EQU_C0_DK 0x0
143 #define ATV_TOP_EQU0_EQU_C0_I 0x3
144 #define ATV_TOP_EQU1_EQU_C1_FM 0x0
145 #define ATV_TOP_EQU1_EQU_C1_L 0x1F6
146 #define ATV_TOP_EQU1_EQU_C1_LP 0x1F6
147 #define ATV_TOP_EQU1_EQU_C1_BG 0x197
148 #define ATV_TOP_EQU1_EQU_C1_DK 0x198
149 #define ATV_TOP_EQU1_EQU_C1_I 0x1F6
150 #define ATV_TOP_EQU2_EQU_C2_FM 0x0
151 #define ATV_TOP_EQU2_EQU_C2_L 0x28
152 #define ATV_TOP_EQU2_EQU_C2_LP 0x28
153 #define ATV_TOP_EQU2_EQU_C2_BG 0xC5
154 #define ATV_TOP_EQU2_EQU_C2_DK 0xB0
155 #define ATV_TOP_EQU2_EQU_C2_I 0x28
156 #define ATV_TOP_EQU3_EQU_C3_FM 0x0
157 #define ATV_TOP_EQU3_EQU_C3_L 0x192
158 #define ATV_TOP_EQU3_EQU_C3_LP 0x192
159 #define ATV_TOP_EQU3_EQU_C3_BG 0x12E
160 #define ATV_TOP_EQU3_EQU_C3_DK 0x18E
161 #define ATV_TOP_EQU3_EQU_C3_I 0x192
162 #define ATV_TOP_STD_MODE_MN 0x0
163 #define ATV_TOP_STD_MODE_FM 0x1
164 #define ATV_TOP_STD_MODE_L 0x0
165 #define ATV_TOP_STD_MODE_LP 0x0
166 #define ATV_TOP_STD_MODE_BG 0x0
167 #define ATV_TOP_STD_MODE_DK 0x0
168 #define ATV_TOP_STD_MODE_I 0x0
169 #define ATV_TOP_STD_VID_POL_MN 0x0
170 #define ATV_TOP_STD_VID_POL_FM 0x0
171 #define ATV_TOP_STD_VID_POL_L 0x2
172 #define ATV_TOP_STD_VID_POL_LP 0x2
173 #define ATV_TOP_STD_VID_POL_BG 0x0
174 #define ATV_TOP_STD_VID_POL_DK 0x0
175 #define ATV_TOP_STD_VID_POL_I 0x0
176 #define ATV_TOP_VID_AMP_MN 0x380
177 #define ATV_TOP_VID_AMP_FM 0x0
178 #define ATV_TOP_VID_AMP_L 0xF50
179 #define ATV_TOP_VID_AMP_LP 0xF50
180 #define ATV_TOP_VID_AMP_BG 0x380
181 #define ATV_TOP_VID_AMP_DK 0x394
182 #define ATV_TOP_VID_AMP_I 0x3D8
183 #define IQM_CF_OUT_ENA_OFDM__M 0x4
184 #define IQM_FS_ADJ_SEL_B_QAM 0x1
185 #define IQM_FS_ADJ_SEL_B_OFF 0x0
186 #define IQM_FS_ADJ_SEL_B_VSB 0x2
187 #define IQM_RC_ADJ_SEL_B_OFF 0x0
188 #define IQM_RC_ADJ_SEL_B_QAM 0x1
189 #define IQM_RC_ADJ_SEL_B_VSB 0x2
190 /**** END DJCOMBO patches to DRXJ registermap *********************************/
194 /* #define DRX_DEBUG */
195 #ifdef DRX_DEBUG
196 #include <stdio.h>
197 #endif
199 /*-----------------------------------------------------------------------------
200 ENUMS
201 ----------------------------------------------------------------------------*/
203 /*-----------------------------------------------------------------------------
204 DEFINES
205 ----------------------------------------------------------------------------*/
206 #ifndef DRXJ_WAKE_UP_KEY
207 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
208 #endif
210 /**
211 * \def DRXJ_DEF_I2C_ADDR
212 * \brief Default I2C addres of a demodulator instance.
213 */
214 #define DRXJ_DEF_I2C_ADDR (0x52)
216 /**
217 * \def DRXJ_DEF_DEMOD_DEV_ID
218 * \brief Default device identifier of a demodultor instance.
219 */
220 #define DRXJ_DEF_DEMOD_DEV_ID (1)
222 /**
223 * \def DRXJ_SCAN_TIMEOUT
224 * \brief Timeout value for waiting on demod lock during channel scan (millisec).
225 */
226 #define DRXJ_SCAN_TIMEOUT 1000
228 /**
229 * \def DRXJ_DAP
230 * \brief Name of structure containing all data access protocol functions.
231 */
232 #define DRXJ_DAP drx_dap_drxj_funct_g
234 /**
235 * \def HI_I2C_DELAY
236 * \brief HI timing delay for I2C timing (in nano seconds)
237 *
238 * Used to compute HI_CFG_DIV
239 */
240 #define HI_I2C_DELAY 42
242 /**
243 * \def HI_I2C_BRIDGE_DELAY
244 * \brief HI timing delay for I2C timing (in nano seconds)
245 *
246 * Used to compute HI_CFG_BDL
247 */
248 #define HI_I2C_BRIDGE_DELAY 750
250 /**
251 * \brief Time Window for MER and SER Measurement in Units of Segment duration.
252 */
253 #define VSB_TOP_MEASUREMENT_PERIOD 64
254 #define SYMBOLS_PER_SEGMENT 832
256 /**
257 * \brief bit rate and segment rate constants used for SER and BER.
258 */
259 /* values taken from the QAM microcode */
260 #define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0
261 #define DRXJ_QAM_SL_SIG_POWER_QPSK 32768
262 #define DRXJ_QAM_SL_SIG_POWER_QAM8 24576
263 #define DRXJ_QAM_SL_SIG_POWER_QAM16 40960
264 #define DRXJ_QAM_SL_SIG_POWER_QAM32 20480
265 #define DRXJ_QAM_SL_SIG_POWER_QAM64 43008
266 #define DRXJ_QAM_SL_SIG_POWER_QAM128 20992
267 #define DRXJ_QAM_SL_SIG_POWER_QAM256 43520
268 /**
269 * \brief Min supported symbolrates.
270 */
271 #ifndef DRXJ_QAM_SYMBOLRATE_MIN
272 #define DRXJ_QAM_SYMBOLRATE_MIN (520000)
273 #endif
275 /**
276 * \brief Max supported symbolrates.
277 */
278 #ifndef DRXJ_QAM_SYMBOLRATE_MAX
279 #define DRXJ_QAM_SYMBOLRATE_MAX (7233000)
280 #endif
282 /**
283 * \def DRXJ_QAM_MAX_WAITTIME
284 * \brief Maximal wait time for QAM auto constellation in ms
285 */
286 #ifndef DRXJ_QAM_MAX_WAITTIME
287 #define DRXJ_QAM_MAX_WAITTIME 900
288 #endif
290 #ifndef DRXJ_QAM_FEC_LOCK_WAITTIME
291 #define DRXJ_QAM_FEC_LOCK_WAITTIME 150
292 #endif
294 #ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME
295 #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200
296 #endif
298 /**
299 * \def SCU status and results
300 * \brief SCU
301 */
302 #define DRX_SCU_READY 0
307 /**
308 * \def DRX_AUD_MAX_DEVIATION
309 * \brief Needed for calculation of prescale feature in AUD
310 */
311 #ifndef DRXJ_AUD_MAX_FM_DEVIATION
313 #endif
315 /**
316 * \brief Needed for calculation of NICAM prescale feature in AUD
317 */
318 #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE
320 #endif
322 /**
323 * \brief Needed for calculation of NICAM prescale feature in AUD
324 */
325 #ifndef DRXJ_AUD_MAX_WAITTIME
327 #endif
329 /* ATV config changed flags */
330 #define DRXJ_ATV_CHANGED_COEF (0x00000001UL)
331 #define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL)
332 #define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL)
333 #define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL)
334 #define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL)
336 /* UIO define */
337 #define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0
338 #define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1
340 /*
341 * MICROCODE RELATED DEFINES
342 */
344 /* Magic word for checking correct Endianess of microcode data */
347 /* CRC flag in ucode header, flags field. */
348 #define DRX_UCODE_CRC_FLAG (0x0001)
350 /*
351 * Maximum size of buffer used to verify the microcode.
352 * Must be an even number
353 */
354 #define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE)
356 #if DRX_UCODE_MAX_BUF_SIZE & 1
357 #error DRX_UCODE_MAX_BUF_SIZE must be an even number
358 #endif
360 /*
361 * Power mode macros
362 */
364 #define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \
365 (mode == DRX_POWER_MODE_10) || \
366 (mode == DRX_POWER_MODE_11) || \
367 (mode == DRX_POWER_MODE_12) || \
368 (mode == DRX_POWER_MODE_13) || \
369 (mode == DRX_POWER_MODE_14) || \
370 (mode == DRX_POWER_MODE_15) || \
371 (mode == DRX_POWER_MODE_16) || \
372 (mode == DRX_POWER_DOWN))
374 /* Pin safe mode macro */
375 #define DRXJ_PIN_SAFE_MODE 0x0000
376 /*============================================================================*/
377 /*=== GLOBAL VARIABLEs =======================================================*/
378 /*============================================================================*/
379 /**
380 */
382 /**
383 * \brief Temporary register definitions.
384 * (register definitions that are not yet available in register master)
385 */
387 /******************************************************************************/
388 /* Audio block 0x103 is write only. To avoid shadowing in driver accessing */
389 /* RAM adresses directly. This must be READ ONLY to avoid problems. */
390 /* Writing to the interface adresses is more than only writing the RAM */
391 /* locations */
392 /******************************************************************************/
393 /**
394 * \brief RAM location of MODUS registers
395 */
396 #define AUD_DEM_RAM_MODUS_HI__A 0x10204A3
397 #define AUD_DEM_RAM_MODUS_HI__M 0xF000
399 #define AUD_DEM_RAM_MODUS_LO__A 0x10204A4
400 #define AUD_DEM_RAM_MODUS_LO__M 0x0FFF
402 /**
403 * \brief RAM location of I2S config registers
404 */
405 #define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1
406 #define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2
408 /**
409 * \brief RAM location of DCO config registers
410 */
411 #define AUD_DEM_RAM_DCO_B_HI__A 0x1020461
412 #define AUD_DEM_RAM_DCO_B_LO__A 0x1020462
413 #define AUD_DEM_RAM_DCO_A_HI__A 0x1020463
414 #define AUD_DEM_RAM_DCO_A_LO__A 0x1020464
416 /**
417 * \brief RAM location of Threshold registers
418 */
419 #define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A
420 #define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB
421 #define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6
423 /**
424 * \brief RAM location of Carrier Threshold registers
425 */
426 #define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF
427 #define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0
429 /**
430 * \brief FM Matrix register fix
431 */
432 #ifdef AUD_DEM_WR_FM_MATRIX__A
433 #undef AUD_DEM_WR_FM_MATRIX__A
434 #endif
435 #define AUD_DEM_WR_FM_MATRIX__A 0x105006F
437 /*============================================================================*/
438 /**
439 * \brief Defines required for audio
440 */
441 #define AUD_VOLUME_ZERO_DB 115
442 #define AUD_VOLUME_DB_MIN -60
443 #define AUD_VOLUME_DB_MAX 12
444 #define AUD_CARRIER_STRENGTH_QP_0DB 0x4000
445 #define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421
446 #define AUD_MAX_AVC_REF_LEVEL 15
447 #define AUD_I2S_FREQUENCY_MAX 48000UL
448 #define AUD_I2S_FREQUENCY_MIN 12000UL
449 #define AUD_RDS_ARRAY_SIZE 18
451 /**
452 * \brief Needed for calculation of prescale feature in AUD
453 */
454 #ifndef DRX_AUD_MAX_FM_DEVIATION
456 #endif
458 /**
459 * \brief Needed for calculation of NICAM prescale feature in AUD
460 */
461 #ifndef DRX_AUD_MAX_NICAM_PRESCALE
463 #endif
465 /*============================================================================*/
466 /* Values for I2S Master/Slave pin configurations */
467 #define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004
468 #define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008
469 #define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004
470 #define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000
472 #define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003
473 #define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008
474 #define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003
475 #define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008
477 #define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004
478 #define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008
479 #define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004
480 #define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000
482 /*============================================================================*/
483 /*=== REGISTER ACCESS MACROS =================================================*/
484 /*============================================================================*/
486 /**
487 * This macro is used to create byte arrays for block writes.
488 * Block writes speed up I2C traffic between host and demod.
489 * The macro takes care of the required byte order in a 16 bits word.
490 * x -> lowbyte(x), highbyte(x)
491 */
492 #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
493 ((u8)((((u16)x)>>8)&0xFF))
494 /**
495 * This macro is used to convert byte array to 16 bit register value for block read.
496 * Block read speed up I2C traffic between host and demod.
497 * The macro takes care of the required byte order in a 16 bits word.
498 */
499 #define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8)))
501 /*============================================================================*/
502 /*=== MISC DEFINES ===========================================================*/
503 /*============================================================================*/
505 /*============================================================================*/
506 /*=== HI COMMAND RELATED DEFINES =============================================*/
507 /*============================================================================*/
509 /**
510 * \brief General maximum number of retries for ucode command interfaces
511 */
512 #define DRXJ_MAX_RETRIES (100)
514 /*============================================================================*/
515 /*=== STANDARD RELATED MACROS ================================================*/
516 /*============================================================================*/
518 #define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \
519 (std == DRX_STANDARD_PAL_SECAM_DK) || \
520 (std == DRX_STANDARD_PAL_SECAM_I) || \
521 (std == DRX_STANDARD_PAL_SECAM_L) || \
522 (std == DRX_STANDARD_PAL_SECAM_LP) || \
523 (std == DRX_STANDARD_NTSC) || \
524 (std == DRX_STANDARD_FM))
526 #define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \
527 (std == DRX_STANDARD_ITU_B) || \
528 (std == DRX_STANDARD_ITU_C) || \
529 (std == DRX_STANDARD_ITU_D))
531 /*-----------------------------------------------------------------------------
532 GLOBAL VARIABLES
533 ----------------------------------------------------------------------------*/
534 /*
535 * DRXJ DAP structures
536 */
539 u32 addr,
540 u16 datasize,
544 u32 waddr,
545 u32 raddr,
549 u32 waddr,
550 u32 raddr,
554 u32 waddr,
555 u32 raddr,
559 u32 addr,
563 u32 addr,
567 u32 addr,
571 u32 addr,
572 u16 datasize,
576 u32 addr,
580 u32 addr,
584 u32 addr,
587 /* The version structure of this protocol implementation */
598 drx_dap_drxj_version_text /**< version as text string */
599 };
601 /* The structure containing the protocol interface */
615 };
628 /* tuner settings */
630 /* standard/channel settings */
637 /* signal quality information: */
638 /* default values taken from the QAM Programming guide */
639 /* fec_bits_desired should not be less than 4000000 */
650 /* HI configuration */
656 /* UIO configuartion */
661 /* FS setting */
664 /* RC setting */
666 /* AUD information */
667 /* false, * flagSetAUDdone */
668 /* false, * detectedRDS */
669 /* true, * flagASDRequest */
670 /* false, * flagHDevClear */
671 /* false, * flagHDevSet */
672 /* (u16) 0xFFF, * rdsLastCount */
674 /* ATV configuartion */
676 /* shadow of ATV_TOP_EQU0__A */
678 ATV_TOP_EQU0_EQU_C0_FM,
679 ATV_TOP_EQU0_EQU_C0_L,
680 ATV_TOP_EQU0_EQU_C0_LP,
681 ATV_TOP_EQU0_EQU_C0_BG,
682 ATV_TOP_EQU0_EQU_C0_DK,
683 ATV_TOP_EQU0_EQU_C0_I},
684 /* shadow of ATV_TOP_EQU1__A */
686 ATV_TOP_EQU1_EQU_C1_FM,
687 ATV_TOP_EQU1_EQU_C1_L,
688 ATV_TOP_EQU1_EQU_C1_LP,
689 ATV_TOP_EQU1_EQU_C1_BG,
690 ATV_TOP_EQU1_EQU_C1_DK,
691 ATV_TOP_EQU1_EQU_C1_I},
692 /* shadow of ATV_TOP_EQU2__A */
694 ATV_TOP_EQU2_EQU_C2_FM,
695 ATV_TOP_EQU2_EQU_C2_L,
696 ATV_TOP_EQU2_EQU_C2_LP,
697 ATV_TOP_EQU2_EQU_C2_BG,
698 ATV_TOP_EQU2_EQU_C2_DK,
699 ATV_TOP_EQU2_EQU_C2_I},
700 /* shadow of ATV_TOP_EQU3__A */
702 ATV_TOP_EQU3_EQU_C3_FM,
703 ATV_TOP_EQU3_EQU_C3_L,
704 ATV_TOP_EQU3_EQU_C3_LP,
705 ATV_TOP_EQU3_EQU_C3_BG,
706 ATV_TOP_EQU3_EQU_C3_DK,
707 ATV_TOP_EQU3_EQU_C3_I},
723 },
733 },
743 },
753 },
760 },
765 },
767 /* Version information */
768 #ifndef _CH_
769 {
772 },
773 {
775 DRX_MODULE_UNKNOWN,
781 },
783 DRX_MODULE_UNKNOWN,
789 }
790 },
791 {
795 },
799 }
800 },
801 #endif
803 /* Tracking filter setting for OOB */
804 {
820 /* Pre SAW & Agc configuration for ATV */
821 {
825 },
835 },
845 },
857 {
859 },
860 };
862 /**
863 * \var drxj_default_addr_g
864 * \brief Default I2C address and device identifier.
865 */
868 DRXJ_DEF_DEMOD_DEV_ID /* device id */
869 };
871 /**
872 * \var drxj_default_comm_attr_g
873 * \brief Default common attributes of a drxj demodulator instance.
874 */
885 {
886 /* MPEG output configuration */
896 be used, otherwise clockrate will
897 adapt to the bitrate of the TS */
899 static clockrate is selected */
900 DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */
901 },
902 /* Initilisations below can be ommited, they require no user input and
903 are initialy 0, NULL or false. The compiler will initialize them to these
904 values when ommited. */
907 /* SCAN */
920 /* Power management */
921 DRX_POWER_UP,
923 /* Tuner */
933 },
940 };
942 /**
943 * \var drxj_default_demod_g
944 * \brief Default drxj demodulator instance.
945 */
951 };
953 /**
954 * \brief Default audio data structure for DRK demodulator instance.
955 *
956 * This structure is DRXK specific.
957 *
958 */
963 /* i2sdata */
964 {
970 DRX_I2S_FORMAT_WS_WITH_DATA /* format */
971 },
972 /* volume */
973 {
982 },
984 /* ass_thresholds */
985 {
989 },
990 /* carrier */
991 {
992 /* a */
993 {
998 },
999 /* b */
1000 {
1005 },
1007 },
1008 /* mixer */
1009 {
1012 DRX_AUD_FM_MATRIX_SOUND_A /* matrix_fm */
1013 },
1017 /* prescale */
1018 {
1020 DRX_AUD_MAX_NICAM_PRESCALE /* nicam_gain */
1021 },
1026 };
1028 /*-----------------------------------------------------------------------------
1029 STRUCTURES
1030 ----------------------------------------------------------------------------*/
1032 u16 eq_mse;
1033 u8 eq_mode;
1034 u8 eq_ctrl;
1035 u8 eq_stat;
1036 };
1038 /* HI command */
1040 u16 cmd;
1041 u16 param1;
1042 u16 param2;
1043 u16 param3;
1044 u16 param4;
1045 u16 param5;
1046 u16 param6;
1047 };
1049 /*============================================================================*/
1050 /*=== MICROCODE RELATED STRUCTURES ===========================================*/
1051 /*============================================================================*/
1053 /**
1054 * struct drxu_code_block_hdr - Structure of the microcode block headers
1055 *
1056 * @addr: Destination address of the data in this block
1057 * @size: Size of the block data following this header counted in
1058 * 16 bits words
1059 * @CRC: CRC value of the data block, only valid if CRC flag is
1060 * set.
1061 */
1063 u32 addr;
1064 u16 size;
1065 u16 flags;
1066 u16 CRC;
1067 };
1069 /*-----------------------------------------------------------------------------
1070 FUNCTIONS
1071 ----------------------------------------------------------------------------*/
1072 /* Some prototypes */
1073 static int
1077 static int
1080 static int
1085 #if 0
1088 static int
1090 #endif
1092 static int
1095 static int
1098 /*============================================================================*/
1099 /*============================================================================*/
1100 /*== HELPER FUNCTIONS ==*/
1101 /*============================================================================*/
1102 /*============================================================================*/
1104 #if 0
1105 /**
1106 * \fn void mult32(u32 a, u32 b, u32 *h, u32 *l)
1107 * \brief 32bitsx32bits signed multiplication
1108 * \param a 32 bits multiplicant, typecast from signed to unisgned
1109 * \param b 32 bits multiplier, typecast from signed to unisgned
1110 * \param h pointer to high part 64 bits result, typecast from signed to unisgned
1111 * \param l pointer to low part 64 bits result
1112 *
1113 * For the 2n+n addition a + b:
1114 * if a >= 0, then h += 0 (sign extension = 0)
1115 * but if a < 0, then h += 2^n-1 ==> h -= 1.
1116 *
1117 * Also, if a + b < 2^n, then a + b >= a && a + b >= b
1118 * but if a + b >= 2^n, then R = a + b - 2^n,
1119 * and because a < 2^n && b < 2*n ==> R < a && R < b.
1120 * Therefore, to detect overflow, simply compare the addition result with
1121 * one of the operands; if the result is smaller, overflow has occurred and
1122 * h must be incremented.
1123 *
1124 * Booth multiplication uses additions and subtractions to reduce the number
1125 * of iterations. This is done by taking three subsequent bits abc and calculating
1126 * the following multiplication factor: -2a + b + c. This factor is multiplied
1127 * by the second operand and added to the result. Next, the first operand is
1128 * shifted two bits (hence one of the three bits is reused) and the process
1129 * repeated. The last iteration has only two bits left, but we simply add
1130 * a zero to the end.
1131 *
1132 * Hence: (n=4)
1133 * 1 * a = 0 * 4a + 1 * a
1134 * 2 * a = 1 * 4a - 2 * a
1135 * 3 * a = 1 * 4a - 1 * a
1136 * -1 * a = 0 * 4a - 1 * a
1137 * -5 * a = -1 * 4a - 1 * a
1138 *
1139 * etc.
1140 *
1141 * Note that the function is type size independent. Any unsigned integer type
1142 * can be substituted for booth_t.
1143 *
1144 */
1146 #define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof(u32) * 8 - 1))) != 0)
1149 {
1153 /* n/2 iterations; shift operand a left two bits after each iteration. */
1154 /* This automatically appends a zero to the operand for the last iteration. */
1156 /* Shift result left two bits */
1160 /* Take the first three bits of operand a for the Booth conversion: */
1161 /* 0, 7: do nothing */
1162 /* 1, 2: add b */
1163 /* 3 : add 2b */
1164 /* 4 : subtract 2b */
1165 /* 5, 6: subtract b */
1179 (-
1181 b))));
1187 (-
1189 b))));
1191 }
1192 }
1193 }
1194 #endif
1196 /*============================================================================*/
1198 /*
1199 * \fn u32 frac28(u32 N, u32 D)
1200 * \brief Compute: (1<<28)*N/D
1201 * \param N 32 bits
1202 * \param D 32 bits
1203 * \return (1<<28)*N/D
1204 * This function is used to avoid floating-point calculations as they may
1205 * not be present on the target platform.
1207 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
1208 * fraction used for setting the Frequency Shifter registers.
1209 * N and D can hold numbers up to width: 28-bits.
1210 * The 4 bits integer part and the 28 bits fractional part are calculated.
1212 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
1214 * N: 0...(1<<28)-1 = 268435454
1215 * D: 0...(1<<28)-1
1216 * Q: 0...(1<<32)-1
1217 */
1219 {
1226 will be visible in the result */
1228 /* division using radix 16, 7 nibbles in the result */
1232 }
1233 /* rounding */
1235 Q1++;
1238 }
1240 /**
1241 * \fn u32 log1_times100( u32 x)
1242 * \brief Compute: 100*log10(x)
1243 * \param x 32 bits
1244 * \return 100*log10(x)
1245 *
1246 * 100*log10(x)
1247 * = 100*(log2(x)/log2(10)))
1248 * = (100*(2^15)*log2(x))/((2^15)*log2(10))
1249 * = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2
1250 * = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2
1251 * = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2
1252 *
1253 * where y = 2^k and 1<= (x/y) < 2
1254 */
1257 {
1260 /*
1261 log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n ))
1262 0 <= n < ((1<<INDEXWIDTH)+1)
1263 */
1299 };
1310 /* Scale x (normalize) */
1311 /* computing y in log(x/y) = log(x) - log(y) */
1317 }
1323 }
1324 }
1325 /*
1326 Now x has binary point between bit[scale] and bit[scale-1]
1327 and 1.0 <= x < 2.0 */
1329 /* correction for divison: log(x) = log(x/y)+log(y) */
1332 /* remove integer part */
1334 /* get index */
1336 /* compute delta (x-a) */
1338 /* compute log, multiplication ( d* (.. )) must be within range ! */
1341 /* Conver to log10() */
1344 /* rounding */
1346 r++;
1350 }
1352 /**
1353 * \fn u32 frac_times1e6( u16 N, u32 D)
1354 * \brief Compute: (N/D) * 1000000.
1355 * \param N nominator 16-bits.
1356 * \param D denominator 32-bits.
1357 * \return u32
1358 * \retval ((N/D) * 1000000), 32 bits
1359 *
1360 * No check on D=0!
1361 */
1363 {
1367 /*
1368 frac = (N * 1000000) / D
1369 To let it fit in a 32 bits computation:
1370 frac = (N * (1000000 >> 4)) / (D >> 4)
1371 This would result in a problem in case D < 16 (div by 0).
1372 So we do it more elaborate as shown below.
1373 */
1381 frac++;
1384 }
1386 /*============================================================================*/
1388 #if 0
1389 /**
1390 * \brief Compute: 100 * 10^( gd_b / 200 ).
1391 * \param u32 gd_b Gain in 0.1dB
1392 * \return u32 Gainfactor in 0.01 resolution
1393 *
1394 */
1396 {
1402 /* start with factors 2 (6.02dB) */
1405 /* Result max overflow if > log2( maxu32 / 2e4 ) ~= 17.7 */
1407 }
1410 /* calculate remaining factor,
1411 poly approximation of 10^(gd_b/200):
1413 y = 1E-04x2 + 0.0106x + 1.0026
1415 max deviation < 0.005 for range x = [0 ... 60]
1416 */
1418 /* using 1e-4 for poly calculation */
1423 /* multiply by remaining factor */
1426 /* conversion from 1e-4 to 1e-2 */
1428 }
1430 #define FRAC_FLOOR 0
1431 #define FRAC_CEIL 1
1432 #define FRAC_ROUND 2
1433 /**
1434 * \fn u32 frac( u32 N, u32 D, u16 RC )
1435 * \brief Compute: N/D.
1436 * \param N nominator 32-bits.
1437 * \param D denominator 32-bits.
1438 * \param RC-result correction: 0-floor; 1-ceil; 2-round
1439 * \return u32
1440 * \retval N/D, 32 bits
1441 *
1442 * If D=0 returns 0
1443 */
1445 {
1455 }
1472 }
1473 }
1475 /* result correction if needed */
1477 /* ceil the result */
1478 /*(remainder is not zero -> value behind decimal point exists) */
1479 frac++;
1480 }
1482 /* remainder is bigger from D/2 -> round the result */
1483 frac++;
1484 }
1485 }
1488 }
1489 #endif
1491 /**
1492 * \brief Values for NICAM prescaler gain. Computed from dB to integer
1493 * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20).
1494 *
1495 */
1501 };
1503 /*============================================================================*/
1504 /*== END HELPER FUNCTIONS ==*/
1505 /*============================================================================*/
1507 /*============================================================================*/
1508 /*============================================================================*/
1509 /*== DRXJ DAP FUNCTIONS ==*/
1510 /*============================================================================*/
1511 /*============================================================================*/
1513 /*
1514 This layer takes care of some device specific register access protocols:
1515 -conversion to short address format
1516 -access to audio block
1517 This layer is placed between the drx_dap_fasi and the rest of the drxj
1518 specific implementation. This layer can use address map knowledge whereas
1519 dap_fasi may not use memory map knowledge.
1521 * For audio currently only 16 bits read and write register access is
1522 supported. More is not needed. RMW and 32 or 8 bit access on audio
1523 registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast
1524 single/multi master) will be ignored.
1526 TODO: check ignoring single/multimaster is ok for AUD access ?
1527 */
1529 #define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false)
1531 /*============================================================================*/
1533 /**
1534 * \fn bool is_handled_by_aud_tr_if( u32 addr )
1535 * \brief Check if this address is handled by the audio token ring interface.
1536 * \param addr
1537 * \return bool
1538 * \retval true Yes, handled by audio token ring interface
1539 * \retval false No, not handled by audio token ring interface
1540 *
1541 */
1542 static
1544 {
1551 }
1554 }
1556 /*============================================================================*/
1559 u32 addr,
1560 u16 datasize,
1562 {
1565 }
1567 /*============================================================================*/
1570 u32 waddr,
1571 u32 raddr,
1573 {
1575 waddr,
1577 }
1579 /*============================================================================*/
1581 /**
1582 * \fn int drxj_dap_rm_write_reg16short
1583 * \brief Read modify write 16 bits audio register using short format only.
1584 * \param dev_addr
1585 * \param waddr Address to write to
1586 * \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A)
1587 * \param wdata Data to write
1588 * \param rdata Buffer for data to read
1589 * \return int
1590 * \retval 0 Succes
1591 * \retval -EIO Timeout, I2C error, illegal bank
1592 *
1593 * 16 bits register read modify write access using short addressing format only.
1594 * Requires knowledge of the registermap, thus device dependent.
1595 * Using DAP FASI directly to avoid endless recursion of RMWs to audio registers.
1596 *
1597 */
1599 /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
1600 See comments drxj_dap_read_modify_write_reg16 */
1601 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)
1603 u32 waddr,
1604 u32 raddr,
1606 {
1612 /* Set RMW flag */
1614 SIO_HI_RA_RAM_S0_FLG_ACC__A,
1615 SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M,
1618 /* Write new data: triggers RMW */
1621 }
1623 /* Read old data */
1626 }
1628 /* Reset RMW flag */
1630 SIO_HI_RA_RAM_S0_FLG_ACC__A,
1632 }
1635 }
1636 #endif
1638 /*============================================================================*/
1641 u32 waddr,
1642 u32 raddr,
1644 {
1645 /* TODO: correct short/long addressing format decision,
1646 now long format has higher prio then short because short also
1647 needs virt bnks (not impl yet) for certain audio registers */
1648 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1650 waddr,
1652 #else
1654 #endif
1655 }
1657 /*============================================================================*/
1660 u32 waddr,
1661 u32 raddr,
1663 {
1665 waddr,
1667 }
1669 /*============================================================================*/
1672 u32 addr,
1674 {
1676 }
1678 /*============================================================================*/
1680 /**
1681 * \fn int drxj_dap_read_aud_reg16
1682 * \brief Read 16 bits audio register
1683 * \param dev_addr
1684 * \param addr
1685 * \param data
1686 * \return int
1687 * \retval 0 Succes
1688 * \retval -EIO Timeout, I2C error, illegal bank
1689 *
1690 * 16 bits register read access via audio token ring interface.
1691 *
1692 */
1695 {
1702 /* No read possible for bank 3, return with error */
1708 /* Force reset write bit */
1711 /* Set up read */
1714 /* RMW to aud TR IF until request is granted or timeout */
1716 addr,
1717 SIO_HI_RA_RAM_S0_RMWBUF__A,
1728 }
1731 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
1733 AUD_TOP_TR_CTR_FIFO_FULL_FULL));
1736 /* Wait for read ready status or timeout */
1741 AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) {
1743 AUD_TOP_TR_CTR__A,
1753 }
1755 }
1757 /* Read value */
1760 AUD_TOP_TR_RD_REG__A,
1761 SIO_HI_RA_RAM_S0_RMWBUF__A,
1764 }
1766 /*============================================================================*/
1769 u32 addr,
1771 {
1774 /* Check param */
1780 else
1785 }
1787 /*============================================================================*/
1790 u32 addr,
1792 {
1794 }
1796 /*============================================================================*/
1799 u32 addr,
1800 u16 datasize,
1802 {
1805 }
1807 /*============================================================================*/
1810 u32 addr,
1812 {
1814 }
1816 /*============================================================================*/
1818 /**
1819 * \fn int drxj_dap_write_aud_reg16
1820 * \brief Write 16 bits audio register
1821 * \param dev_addr
1822 * \param addr
1823 * \param data
1824 * \return int
1825 * \retval 0 Succes
1826 * \retval -EIO Timeout, I2C error, illegal bank
1827 *
1828 * 16 bits register write access via audio token ring interface.
1829 *
1830 */
1833 {
1836 /* No write possible for bank 2, return with error */
1846 /* Force write bit */
1850 /* RMW to aud TR IF until request is granted or timeout */
1852 addr,
1853 SIO_HI_RA_RAM_S0_RMWBUF__A,
1863 }
1866 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
1868 AUD_TOP_TR_CTR_FIFO_FULL_FULL));
1873 }
1875 /*============================================================================*/
1878 u32 addr,
1880 {
1883 /* Check param */
1889 else
1894 }
1896 /*============================================================================*/
1899 u32 addr,
1901 {
1903 }
1905 /*============================================================================*/
1907 /* Free data ram in SIO HI */
1908 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
1909 #define SIO_HI_RA_RAM_USR_END__A 0x420060
1911 #define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
1912 #define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
1913 #define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
1914 #define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
1916 /**
1917 * \fn int drxj_dap_atomic_read_write_block()
1918 * \brief Basic access routine for atomic read or write access
1919 * \param dev_addr pointer to i2c dev address
1920 * \param addr destination/source address
1921 * \param datasize size of data buffer in bytes
1922 * \param data pointer to data buffer
1923 * \return int
1924 * \retval 0 Succes
1925 * \retval -EIO Timeout, I2C error, illegal bank
1926 *
1927 */
1928 static
1930 u32 addr,
1931 u16 datasize,
1933 {
1936 u16 word;
1940 /* Parameter check */
1944 /* Set up HI parameters to read or write n bytes */
1954 else
1961 /* write data to buffer */
1969 }
1970 }
1976 }
1979 /* read data from buffer */
1986 }
1987 }
1991 rw_error:
1994 }
1996 /*============================================================================*/
1998 /**
1999 * \fn int drxj_dap_atomic_read_reg32()
2000 * \brief Atomic read of 32 bits words
2001 */
2002 static
2004 u32 addr,
2006 {
2031 }
2033 /*============================================================================*/
2035 /*============================================================================*/
2036 /*== END DRXJ DAP FUNCTIONS ==*/
2037 /*============================================================================*/
2039 /*============================================================================*/
2040 /*============================================================================*/
2041 /*== HOST INTERFACE FUNCTIONS ==*/
2042 /*============================================================================*/
2043 /*============================================================================*/
2045 /**
2046 * \fn int hi_cfg_command()
2047 * \brief Configure HI with settings stored in the demod structure.
2048 * \param demod Demodulator.
2049 * \return int.
2050 *
2051 * This routine was created because to much orthogonal settings have
2052 * been put into one HI API function (configure). Especially the I2C bridge
2053 * enable/disable should not need re-configuration of the HI.
2054 *
2055 */
2057 {
2077 }
2079 /* Reset power down flag (set one call only) */
2084 rw_error:
2086 }
2088 /**
2089 * \fn int hi_command()
2090 * \brief Configure HI with settings stored in the demod structure.
2091 * \param dev_addr I2C address.
2092 * \param cmd HI command.
2093 * \param result HI command result.
2094 * \return int.
2095 *
2096 * Sends command to HI
2097 *
2098 */
2099 static int
2101 {
2107 /* Write parameters */
2116 }
2121 }
2126 }
2131 }
2132 /* fallthrough */
2138 }
2143 }
2144 /* fallthrough */
2146 /* No parameters */
2152 }
2154 /* Write command */
2159 }
2164 /* Detect power down to ommit reading result */
2170 /* Wait until command rdy */
2172 nr_retries++;
2176 }
2182 }
2185 /* Read result */
2190 }
2192 }
2193 /* if ( powerdown_cmd == true ) */
2195 rw_error:
2197 }
2199 /**
2200 * \fn int init_hi( const struct drx_demod_instance *demod )
2201 * \brief Initialise and configurate HI.
2202 * \param demod pointer to demod data.
2203 * \return int Return status.
2204 * \retval 0 Success.
2205 * \retval -EIO Failure.
2206 *
2207 * Needs to know Psys (System Clock period) and Posc (Osc Clock period)
2208 * Need to store configuration in driver because of the way I2C
2209 * bridging is controlled.
2210 *
2211 */
2213 {
2223 /* PATCH for bug 5003, HI ucode v3.1.0 */
2228 }
2230 /* Timing div, 250ns/Psys */
2231 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2234 /* Clipping */
2237 /* Bridge delay, uses oscilator clock */
2238 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2239 /* SDA brdige delay */
2243 /* Clipping */
2246 /* SCL bridge delay, same as SDA for now */
2248 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B);
2249 /* Wakeup key, setting the read flag (as suggest in the documentation) does
2250 not always result into a working solution (barebones worked VI2C failed).
2251 Not setting the bit works in all cases . */
2253 /* port/bridge/power down ctrl */
2255 /* transit mode time out delay and watch dog divider */
2262 }
2266 rw_error:
2268 }
2270 /*============================================================================*/
2271 /*== END HOST INTERFACE FUNCTIONS ==*/
2272 /*============================================================================*/
2274 /*============================================================================*/
2275 /*============================================================================*/
2276 /*== AUXILIARY FUNCTIONS ==*/
2277 /*============================================================================*/
2278 /*============================================================================*/
2280 /**
2281 * \fn int get_device_capabilities()
2282 * \brief Get and store device capabilities.
2283 * \param demod Pointer to demodulator instance.
2284 * \return int.
2285 * \return 0 Success
2286 * \retval -EIO Failure
2287 *
2288 * Depending on pulldowns on MDx pins the following internals are set:
2289 * * common_attr->osc_clock_freq
2290 * * ext_attr->has_lna
2291 * * ext_attr->has_ntsc
2292 * * ext_attr->has_btsc
2293 * * ext_attr->has_oob
2294 *
2295 */
2297 {
2314 }
2319 }
2324 }
2328 /* ignore (bypass ?) */
2331 /* 27 MHz */
2335 /* 20.25 MHz */
2339 /* 4 MHz */
2344 }
2346 /*
2347 Determine device capabilities
2348 Based on pinning v47
2349 */
2354 }
2363 }
2368 }
2374 }
2476 /* Unknown device variant */
2479 }
2482 rw_error:
2484 }
2486 /**
2487 * \fn int power_up_device()
2488 * \brief Power up device.
2489 * \param demod Pointer to demodulator instance.
2490 * \return int.
2491 * \return 0 Success
2492 * \retval -EIO Failure, I2C or max retries reached
2493 *
2494 */
2496 #ifndef DRXJ_MAX_RETRIES_POWERUP
2497 #define DRXJ_MAX_RETRIES_POWERUP 10
2498 #endif
2501 {
2511 /*
2512 * I2C access may fail in this case: no ack
2513 * dummy write must be used to wake uop device, dummy read must be used to
2514 * reset HI state machine (avoiding actual writes)
2515 */
2522 retry_count++;
2528 /* Need some recovery time .... */
2535 }
2537 /*----------------------------------------------------------------------------*/
2538 /* MPEG Output Configuration Functions - begin */
2539 /*----------------------------------------------------------------------------*/
2540 /**
2541 * \fn int ctrl_set_cfg_mpeg_output()
2542 * \brief Set MPEG output configuration of the device.
2543 * \param devmod Pointer to demodulator instance.
2544 * \param cfg_data Pointer to mpeg output configuaration.
2545 * \return int.
2546 *
2547 * Configure MPEG output parameters.
2548 *
2549 */
2550 static int
2551 ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
2552 {
2564 /* data mask for the output data byte */
2565 u16 invert_data_mask =
2571 /* check arguments */
2580 /* quick and dirty patch to set MPEG incase current std is not
2581 producing MPEG */
2589 /* not an MPEG producing std, just store MPEG cfg */
2604 }
2610 }
2622 }
2627 }
2632 }
2637 }
2642 }
2643 /* Low Water Mark for synchronization */
2648 }
2649 /* High Water Mark for synchronization */
2654 }
2677 /* max_bit_rate = symbol_rate * nr_bits * coef */
2678 /* coef = 188/204 */
2679 max_bit_rate =
2681 /* pass through b/c Annex A/c need following settings */
2687 }
2688 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
2692 }
2697 }
2702 }
2707 }
2713 }
2719 }
2720 }
2725 }
2730 }
2736 /* Check insertion of the Reed-Solomon parity bytes */
2741 }
2746 }
2748 /* enable parity symbol forward */
2750 /* MVAL disable during parity bytes */
2767 }
2771 /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */
2772 rcn_rate =
2773 (frac28
2783 /* disable parity symbol forward */
2785 /* MVAL enable during parity bytes */
2802 }
2806 /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */
2807 rcn_rate =
2808 (frac28
2816 }
2818 if (cfg_data->enable_parallel == true) { /* MPEG data output is paralel -> clear ipr_mode[0] */
2822 }
2824 /* Control slective inversion of output bits */
2827 else
2832 else
2837 else
2842 else
2847 else
2865 {
2870 }
2872 symbol_rate_th) {
2876 }
2877 }
2891 }
2892 bit_rate =
2895 dto_rate =
2898 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
2902 }
2903 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
2907 }
2908 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
2912 }
2913 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
2917 }
2922 }
2929 }
2936 }
2941 }
2942 }
2948 }
2950 /* Write appropriate registers with requested configuration */
2955 }
2960 }
2965 }
2967 /* enabling for both parallel and serial now */
2968 /* Write magic word to enable pdr reg write */
2973 }
2974 /* Set MPEG TS pads to outputmode */
2979 }
2984 }
2985 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
2989 }
2994 }
2995 sio_pdr_md_cfg =
2996 MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH <<
3002 }
3003 if (cfg_data->enable_parallel == true) { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */
3004 sio_pdr_md_cfg =
3005 MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH <<
3007 SIO_PDR_MD0_CFG_MODE__B;
3012 }
3017 }
3022 }
3027 }
3032 }
3037 }
3042 }
3047 }
3053 }
3058 }
3063 }
3068 }
3073 }
3078 }
3083 }
3084 }
3085 /* Enable Monitor Bus output over MPEG pads and ctl input */
3090 }
3091 /* Write nomagic word to enable pdr reg write */
3096 }
3098 /* Write magic word to enable pdr reg write */
3103 }
3104 /* Set MPEG TS pads to inputmode */
3109 }
3114 }
3119 }
3124 }
3129 }
3134 }
3139 }
3144 }
3149 }
3154 }
3159 }
3164 }
3165 /* Enable Monitor Bus output over MPEG pads and ctl input */
3170 }
3171 /* Write nomagic word to enable pdr reg write */
3176 }
3177 }
3179 /* save values for restore after re-acquire */
3192 rw_error:
3194 }
3196 /*----------------------------------------------------------------------------*/
3198 #if 0
3199 /**
3200 * \fn int ctrl_get_cfg_mpeg_output()
3201 * \brief Get MPEG output configuration of the device.
3202 * \param devmod Pointer to demodulator instance.
3203 * \param cfg_data Pointer to MPEG output configuaration struct.
3204 * \return int.
3205 *
3206 * Retrieve MPEG output configuartion.
3207 *
3208 */
3209 static int
3210 ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
3211 {
3241 }
3247 }
3248 /* Frcn_rate = rate_reg * Fsys / 2 ^ 25 */
3252 }
3255 rw_error:
3257 }
3258 #endif
3260 /*----------------------------------------------------------------------------*/
3261 /* MPEG Output Configuration Functions - end */
3262 /*----------------------------------------------------------------------------*/
3264 /*----------------------------------------------------------------------------*/
3265 /* miscellaneous configuartions - begin */
3266 /*----------------------------------------------------------------------------*/
3268 /**
3269 * \fn int set_mpegtei_handling()
3270 * \brief Activate MPEG TEI handling settings.
3271 * \param devmod Pointer to demodulator instance.
3272 * \return int.
3273 *
3274 * This routine should be called during a set channel of QAM/VSB
3275 *
3276 */
3278 {
3293 }
3298 }
3303 }
3305 /* reset to default, allow TEI bit to be changed */
3308 FEC_OC_SNC_MODE_CORR_DISABLE__M));
3312 /* do not change TEI bit */
3317 }
3323 }
3328 }
3333 }
3336 rw_error:
3338 }
3340 /*----------------------------------------------------------------------------*/
3341 /**
3342 * \fn int bit_reverse_mpeg_output()
3343 * \brief Set MPEG output bit-endian settings.
3344 * \param devmod Pointer to demodulator instance.
3345 * \return int.
3346 *
3347 * This routine should be called during a set channel of QAM/VSB
3348 *
3349 */
3351 {
3364 }
3366 /* reset to default (normal bit order) */
3376 }
3379 rw_error:
3381 }
3383 /*----------------------------------------------------------------------------*/
3384 /**
3385 * \fn int set_mpeg_output_clock_rate()
3386 * \brief Set MPEG output clock rate.
3387 * \param devmod Pointer to demodulator instance.
3388 * \return int.
3389 *
3390 * This routine should be called during a set channel of QAM/VSB
3391 *
3392 */
3393 #if 0
3395 {
3404 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_PERIOD__A, ext_attr->mpeg_output_clock_rate - 1, 0);
3408 }
3409 }
3412 rw_error:
3414 }
3415 #endif
3417 /*----------------------------------------------------------------------------*/
3418 /**
3419 * \fn int set_mpeg_start_width()
3420 * \brief Set MPEG start width.
3421 * \param devmod Pointer to demodulator instance.
3422 * \return int.
3423 *
3424 * This routine should be called during a set channel of QAM/VSB
3425 *
3426 */
3428 {
3445 }
3453 }
3454 }
3457 rw_error:
3459 }
3461 #if 0
3462 /*----------------------------------------------------------------------------*/
3463 /**
3464 * \fn int ctrl_set_cfg_mpeg_output_misc()
3465 * \brief Set miscellaneous configuartions
3466 * \param devmod Pointer to demodulator instance.
3467 * \param cfg_data pDRXJCfgMisc_t
3468 * \return int.
3469 *
3470 * This routine can be used to set configuartion options that are DRXJ
3471 * specific and/or added to the requirements at a late stage.
3472 *
3473 */
3474 static int
3477 {
3486 /*
3487 Set disable TEI bit handling flag.
3488 TEI must be left untouched by device in case of BER measurements using
3489 external equipment that is unable to ignore the TEI bit in the TS.
3490 Default will false (enable TEI bit handling).
3491 Reverse output bit order. Default is false (msb on MD7 (parallel) or out first (serial)).
3492 Set clock rate. Default is auto that is derived from symbol rate.
3493 The flags and values will also be used to set registers during a set channel.
3494 */
3499 /* Don't care what the active standard is, activate setting immediatly */
3504 }
3509 }
3514 }
3519 }
3522 rw_error:
3524 }
3526 /*----------------------------------------------------------------------------*/
3528 /**
3529 * \fn int ctrl_get_cfg_mpeg_output_misc()
3530 * \brief Get miscellaneous configuartions.
3531 * \param devmod Pointer to demodulator instance.
3532 * \param cfg_data Pointer to DRXJCfgMisc_t.
3533 * \return int.
3534 *
3535 * This routine can be used to retreive the current setting of the configuartion
3536 * options that are DRXJ specific and/or added to the requirements at a
3537 * late stage.
3538 *
3539 */
3540 static int
3543 {
3562 }
3565 }
3568 rw_error:
3570 }
3572 /*----------------------------------------------------------------------------*/
3574 /**
3575 * \fn int ctrl_get_cfg_hw_cfg()
3576 * \brief Get HW configuartions.
3577 * \param devmod Pointer to demodulator instance.
3578 * \param cfg_data Pointer to Bool.
3579 * \return int.
3580 *
3581 * This routine can be used to retreive the current setting of the configuartion
3582 * options that are DRXJ specific and/or added to the requirements at a
3583 * late stage.
3584 *
3585 */
3586 static int
3588 {
3599 }
3604 }
3609 }
3615 rw_error:
3617 }
3618 #endif
3620 /*----------------------------------------------------------------------------*/
3621 /* miscellaneous configuartions - end */
3622 /*----------------------------------------------------------------------------*/
3624 /*----------------------------------------------------------------------------*/
3625 /* UIO Configuration Functions - begin */
3626 /*----------------------------------------------------------------------------*/
3627 /**
3628 * \fn int ctrl_set_uio_cfg()
3629 * \brief Configure modus oprandi UIO.
3630 * \param demod Pointer to demodulator instance.
3631 * \param uio_cfg Pointer to a configuration setting for a certain UIO.
3632 * \return int.
3633 */
3635 {
3644 /* Write magic word to enable pdr reg write */
3645 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3649 }
3651 /*====================================================================*/
3653 /* DRX_UIO1: SMA_TX UIO-1 */
3664 /* pad configuration register is set 0 - input mode */
3669 }
3675 /*====================================================================*/
3677 /* DRX_UIO2: SMA_RX UIO-2 */
3687 /* pad configuration register is set 0 - input mode */
3692 }
3699 /*====================================================================*/
3701 /* DRX_UIO3: GPIO UIO-3 */
3711 /* pad configuration register is set 0 - input mode */
3716 }
3723 /*====================================================================*/
3725 /* DRX_UIO4: IRQN UIO-4 */
3733 /* pad configuration register is set 0 - input mode */
3738 }
3747 /*====================================================================*/
3752 /* Write magic word to disable pdr reg write */
3757 }
3760 rw_error:
3762 }
3764 #if 0
3765 /*============================================================================*/
3766 /**
3767 * \fn int ctrl_getuio_cfg()
3768 * \brief Get modus oprandi UIO.
3769 * \param demod Pointer to demodulator instance.
3770 * \param uio_cfg Pointer to a configuration setting for a certain UIO.
3771 * \return int.
3772 */
3774 {
3804 }
3805 #endif
3807 /**
3808 * \fn int ctrl_uio_write()
3809 * \brief Write to a UIO.
3810 * \param demod Pointer to demodulator instance.
3811 * \param uio_data Pointer to data container for a certain UIO.
3812 * \return int.
3813 */
3814 static int
3816 {
3827 /* Write magic word to enable pdr reg write */
3828 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3832 }
3834 /*====================================================================*/
3836 /* DRX_UIO1: SMA_TX UIO-1 */
3842 }
3844 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3846 /* io_pad_cfg_mode output mode is drive always */
3847 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3849 /* write to io pad configuration register - output mode */
3850 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
3854 }
3856 /* use corresponding bit in io data output registar */
3861 }
3864 else
3867 /* write back to io data output register */
3872 }
3874 /*======================================================================*/
3876 /* DRX_UIO2: SMA_RX UIO-2 */
3883 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3885 /* io_pad_cfg_mode output mode is drive always */
3886 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3888 /* write to io pad configuration register - output mode */
3889 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
3893 }
3895 /* use corresponding bit in io data output registar */
3900 }
3903 else
3906 /* write back to io data output register */
3911 }
3913 /*====================================================================*/
3915 /* DRX_UIO3: ASEL UIO-3 */
3922 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3924 /* io_pad_cfg_mode output mode is drive always */
3925 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3927 /* write to io pad configuration register - output mode */
3932 }
3934 /* use corresponding bit in io data output registar */
3939 }
3942 else
3945 /* write back to io data output register */
3950 }
3952 /*=====================================================================*/
3954 /* DRX_UIO4: IRQN UIO-4 */
3962 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3964 /* io_pad_cfg_mode output mode is drive always */
3965 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3967 /* write to io pad configuration register - output mode */
3972 }
3974 /* use corresponding bit in io data output registar */
3979 }
3982 else
3985 /* write back to io data output register */
3990 }
3992 /*=====================================================================*/
3997 /* Write magic word to disable pdr reg write */
4002 }
4005 rw_error:
4007 }
4009 #if 0
4010 /**
4011 *\fn int ctrl_uio_read
4012 *\brief Read from a UIO.
4013 * \param demod Pointer to demodulator instance.
4014 * \param uio_data Pointer to data container for a certain UIO.
4015 * \return int.
4016 */
4018 {
4029 /* Write magic word to enable pdr reg write */
4030 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
4034 }
4036 /*====================================================================*/
4038 /* DRX_UIO1: SMA_TX UIO-1 */
4046 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
4048 /* io_pad_cfg_mode output mode is drive always */
4049 /* io_pad_cfg_drive is set to power 2 (23 mA) */
4051 /* write to io pad configuration register - input mode */
4052 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
4056 }
4062 }
4067 }
4069 /*======================================================================*/
4071 /* DRX_UIO2: SMA_RX UIO-2 */
4079 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
4081 /* io_pad_cfg_mode output mode is drive always */
4082 /* io_pad_cfg_drive is set to power 2 (23 mA) */
4084 /* write to io pad configuration register - input mode */
4085 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
4089 }
4095 }
4099 else
4103 /*=====================================================================*/
4105 /* DRX_UIO3: GPIO UIO-3 */
4113 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
4115 /* io_pad_cfg_mode output mode is drive always */
4116 /* io_pad_cfg_drive is set to power 2 (23 mA) */
4118 /* write to io pad configuration register - input mode */
4123 }
4125 /* read io input data registar */
4130 }
4135 }
4137 /*=====================================================================*/
4139 /* DRX_UIO4: IRQN UIO-4 */
4147 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
4149 /* io_pad_cfg_mode output mode is drive always */
4150 /* io_pad_cfg_drive is set to power 2 (23 mA) */
4152 /* write to io pad configuration register - input mode */
4157 }
4159 /* read io input data registar */
4164 }
4167 else
4171 /*====================================================================*/
4176 /* Write magic word to disable pdr reg write */
4181 }
4184 rw_error:
4186 }
4187 #endif
4189 /*---------------------------------------------------------------------------*/
4190 /* UIO Configuration Functions - end */
4191 /*---------------------------------------------------------------------------*/
4193 /*----------------------------------------------------------------------------*/
4194 /* I2C Bridge Functions - begin */
4195 /*----------------------------------------------------------------------------*/
4196 /**
4197 * \fn int ctrl_i2c_bridge()
4198 * \brief Open or close the I2C switch to tuner.
4199 * \param demod Pointer to demodulator instance.
4200 * \param bridge_closed Pointer to bool indication if bridge is closed not.
4201 * \return int.
4203 */
4204 static int
4206 {
4210 /* check arguments */
4218 else
4222 }
4224 /*----------------------------------------------------------------------------*/
4225 /* I2C Bridge Functions - end */
4226 /*----------------------------------------------------------------------------*/
4228 /*----------------------------------------------------------------------------*/
4229 /* Smart antenna Functions - begin */
4230 /*----------------------------------------------------------------------------*/
4231 /**
4232 * \fn int smart_ant_init()
4233 * \brief Initialize Smart Antenna.
4234 * \param pointer to struct drx_demod_instance.
4235 * \return int.
4236 *
4237 */
4239 {
4249 /* Write magic word to enable pdr reg write */
4250 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
4254 }
4255 /* init smart antenna */
4260 }
4262 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
4266 }
4268 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
4272 }
4273 }
4275 /* config SMA_TX pin to smart antenna mode */
4280 }
4285 }
4290 }
4292 /* Write magic word to disable pdr reg write */
4297 }
4300 rw_error:
4302 }
4304 #if 0
4305 /**
4306 * \fn int ctrl_set_cfg_smart_ant()
4307 * \brief Set Smart Antenna.
4308 * \param pointer to struct drxj_cfg_smart_ant.
4309 * \return int.
4310 *
4311 */
4312 static int
4314 {
4325 /* check arguments */
4335 }
4337 }
4339 /* Write magic word to enable pdr reg write */
4340 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
4344 }
4348 /* enable Tx if Mode B (input) is supported */
4349 /*
4350 RR16( dev_addr, SIO_SA_TX_COMMAND__A, &data );
4351 WR16( dev_addr, SIO_SA_TX_COMMAND__A, data | SIO_SA_TX_COMMAND_TX_ENABLE__M );
4352 */
4359 }
4360 } while ((data & SIO_SA_TX_STATUS_BUSY__M) && ((jiffies_to_msecs(jiffies) - start_time) < DRXJ_MAX_WAITTIME));
4365 /* write to smart antenna configuration register */
4366 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA0__A, 0x9200 | ((smart_ant->ctrl_data & 0x0001) << 8) | ((smart_ant->ctrl_data & 0x0002) << 10) | ((smart_ant->ctrl_data & 0x0004) << 12), 0);
4370 }
4371 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA1__A, 0x4924 | ((smart_ant->ctrl_data & 0x0008) >> 2) | ((smart_ant->ctrl_data & 0x0010)) | ((smart_ant->ctrl_data & 0x0020) << 2) | ((smart_ant->ctrl_data & 0x0040) << 4) | ((smart_ant->ctrl_data & 0x0080) << 6), 0);
4375 }
4376 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA2__A, 0x2492 | ((smart_ant->ctrl_data & 0x0100) >> 8) | ((smart_ant->ctrl_data & 0x0200) >> 6) | ((smart_ant->ctrl_data & 0x0400) >> 4) | ((smart_ant->ctrl_data & 0x0800) >> 2) | ((smart_ant->ctrl_data & 0x1000)) | ((smart_ant->ctrl_data & 0x2000) << 2), 0);
4380 }
4385 }
4387 /* trigger the sending */
4392 }
4396 /* disable Tx if Mode B (input) is supported */
4397 /*
4398 RR16( dev_addr, SIO_SA_TX_COMMAND__A, &data );
4399 WR16( dev_addr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) );
4400 */
4403 }
4404 /* Write magic word to enable pdr reg write */
4409 }
4412 rw_error:
4414 }
4415 #endif
4418 {
4423 /* Check param */
4427 /* Wait until SCU command interface is ready to receive command */
4432 }
4468 /* do nothing */
4471 /* this number of parameters is not supported */
4473 }
4478 }
4480 /* Wait until SCU has processed command */
4487 }
4494 /* read results */
4496 s16 err;
4524 /* do nothing */
4527 /* this number of parameters is not supported */
4529 }
4531 /* Check if an error was reported by SCU */
4534 /* check a few fixed error codes */
4539 ) {
4541 }
4542 /* here it is assumed that negative means error, and positive no error */
4545 else
4547 }
4551 rw_error:
4553 }
4555 /**
4556 * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock()
4557 * \brief Basic access routine for SCU atomic read or write access
4558 * \param dev_addr pointer to i2c dev address
4559 * \param addr destination/source address
4560 * \param datasize size of data buffer in bytes
4561 * \param data pointer to data buffer
4562 * \return int
4563 * \retval 0 Succes
4564 * \retval -EIO Timeout, I2C error, illegal bank
4565 *
4566 */
4567 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4568 static
4569 int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */
4571 {
4577 /* Parameter check */
4593 }
4596 }
4599 SCU_RAM_COMMAND_STANDARD_TOP |
4600 SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS;
4607 }
4611 /* read data from buffer */
4615 }
4616 }
4620 rw_error:
4623 }
4625 /*============================================================================*/
4627 /**
4628 * \fn int DRXJ_DAP_AtomicReadReg16()
4629 * \brief Atomic read of 16 bits words
4630 */
4631 static
4633 u32 addr,
4635 {
4652 }
4654 /*============================================================================*/
4655 /**
4656 * \fn int drxj_dap_scu_atomic_write_reg16()
4657 * \brief Atomic read of 16 bits words
4658 */
4659 static
4661 u32 addr,
4663 {
4673 }
4675 /* -------------------------------------------------------------------------- */
4676 /**
4677 * \brief Measure result of ADC synchronisation
4678 * \param demod demod instance
4679 * \param count (returned) count
4680 * \return int.
4681 * \retval 0 Success
4682 * \retval -EIO Failure: I2C error
4683 *
4684 */
4686 {
4693 /* Start measurement */
4698 }
4703 }
4705 /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */
4713 }
4720 }
4727 }
4732 rw_error:
4734 }
4736 /**
4737 * \brief Synchronize analog and digital clock domains
4738 * \param demod demod instance
4739 * \return int.
4740 * \retval 0 Success
4741 * \retval -EIO Failure: I2C error or failure to synchronize
4742 *
4743 * An IQM reset will also reset the results of this synchronization.
4744 * After an IQM reset this routine needs to be called again.
4745 *
4746 */
4749 {
4760 }
4763 /* Try sampling on a diffrent edge */
4770 }
4777 }
4783 }
4784 }
4786 /* TODO: implement fallback scenarios */
4791 rw_error:
4793 }
4795 #if 0
4796 /**
4797 * \brief Configure IQM AF registers
4798 * \param demod instance of demodulator.
4799 * \param active
4800 * \return int.
4801 */
4803 {
4808 /* Configure IQM */
4813 }
4815 data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
4816 else
4817 data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
4822 }
4825 rw_error:
4827 }
4829 /* -------------------------------------------------------------------------- */
4830 static int
4831 ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg);
4833 /**
4834 * \brief set configuration of pin-safe mode
4835 * \param demod instance of demodulator.
4836 * \param enable boolean; true: activate pin-safe mode, false: de-activate p.s.m.
4837 * \return int.
4838 */
4839 static int
4841 {
4852 /* Write magic word to enable pdr reg write */
4857 }
4862 /* MPEG pins to input */
4867 }
4872 }
4877 }
4882 }
4887 }
4892 }
4897 }
4902 }
4907 }
4912 }
4917 }
4922 }
4924 /* PD_I2C_SDA2 Bridge off, Port2 Inactive
4925 PD_I2C_SCL2 Bridge off, Port2 Inactive */
4930 }
4935 }
4940 }
4942 /* PD_GPIO Store and set to input
4943 PD_VSYNC Store and set to input
4944 PD_SMA_RX Store and set to input
4945 PD_SMA_TX Store and set to input */
4946 rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, &ext_attr->pdr_safe_restore_val_gpio, 0);
4950 }
4951 rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, &ext_attr->pdr_safe_restore_val_v_sync, 0);
4955 }
4956 rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_rx, 0);
4960 }
4961 rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_tx, 0);
4965 }
4970 }
4975 }
4980 }
4985 }
4987 /* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate!
4988 PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */
4993 }
4995 /* PD_CVBS Analog DAC output, standby mode
4996 PD_SIF Analog DAC output, standby mode */
4997 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
5001 }
5003 /* PD_I2S_CL Input
5004 PD_I2S_DA Input
5005 PD_I2S_WS Input */
5010 }
5015 }
5020 }
5022 /* No need to restore MPEG pins;
5023 is done in SetStandard/SetChannel */
5025 /* PD_I2C_SDA2 Port2 active
5026 PD_I2C_SCL2 Port2 active */
5027 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE, 0);
5031 }
5032 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE, 0);
5036 }
5038 /* PD_GPIO Restore
5039 PD_VSYNC Restore
5040 PD_SMA_RX Restore
5041 PD_SMA_TX Restore */
5042 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, ext_attr->pdr_safe_restore_val_gpio, 0);
5046 }
5047 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, ext_attr->pdr_safe_restore_val_v_sync, 0);
5051 }
5052 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, ext_attr->pdr_safe_restore_val_sma_rx, 0);
5056 }
5057 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, ext_attr->pdr_safe_restore_val_sma_tx, 0);
5061 }
5063 /* PD_RF_AGC, PD_IF_AGC
5064 No need to restore; will be restored in SetStandard/SetChannel */
5066 /* PD_CVBS, PD_SIF
5067 No need to restore; will be restored in SetStandard/SetChannel */
5069 /* PD_I2S_CL, PD_I2S_DA, PD_I2S_WS
5070 Should be restored via DRX_CTRL_SET_AUD */
5071 }
5073 /* Write magic word to disable pdr reg write */
5078 }
5083 rw_error:
5085 }
5087 /* -------------------------------------------------------------------------- */
5089 /**
5090 * \brief get configuration of pin-safe mode
5091 * \param demod instance of demodulator.
5092 * \param enable boolean indicating whether pin-safe mode is active
5093 * \return int.
5094 */
5095 static int
5097 {
5107 }
5108 #endif
5110 /*============================================================================*/
5111 /*== END AUXILIARY FUNCTIONS ==*/
5112 /*============================================================================*/
5114 /*============================================================================*/
5115 /*============================================================================*/
5116 /*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
5117 /*============================================================================*/
5118 /*============================================================================*/
5119 /**
5120 * \fn int init_agc ()
5121 * \brief Initialize AGC for all standards.
5122 * \param demod instance of demodulator.
5123 * \param channel pointer to channel data.
5124 * \return int.
5125 */
5127 {
5171 }
5176 }
5181 }
5186 }
5191 }
5196 }
5201 }
5206 }
5211 }
5216 }
5221 }
5226 }
5231 }
5235 #ifndef DRXJ_VSB_ONLY
5254 }
5259 }
5264 }
5269 }
5274 }
5279 }
5284 }
5289 }
5294 }
5299 }
5306 }
5312 }
5318 }
5320 #endif
5321 #if 0
5340 }
5363 }
5384 }
5386 #endif
5389 }
5391 /* for new AGC interface */
5392 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
5396 }
5406 }
5407 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
5411 }
5421 }
5426 }
5431 }
5436 }
5441 }
5446 }
5451 }
5456 }
5461 }
5466 }
5471 }
5476 }
5481 }
5486 }
5491 }
5496 }
5501 }
5506 }
5511 }
5516 }
5521 }
5535 }
5540 }
5542 /* Set/restore Ki DGAIN factor */
5547 }
5554 }
5557 rw_error:
5559 }
5561 /**
5562 * \fn int set_frequency ()
5563 * \brief Set frequency shift.
5564 * \param demod instance of demodulator.
5565 * \param channel pointer to channel data.
5566 * \param tuner_freq_offset residual frequency from tuner.
5567 * \return int.
5568 */
5569 static int
5572 {
5592 /*
5593 Program frequency shifter
5594 No need to account for mirroring on RF
5595 */
5604 /* After IQM FS sound carrier must appear at 4 Mhz in spect.
5605 Sound carrier is already 3Mhz above centre frequency due
5606 to tuner setting so now add an extra shift of 1MHz... */
5618 }
5623 else
5626 /* adc mirrors */
5630 /* adc doesn't mirror */
5633 }
5636 image_to_select =
5643 /* Program frequency shifter with tuner offset compensation */
5644 /* frequency_shift += tuner_freq_offset; TODO */
5649 }
5654 rw_error:
5656 }
5658 #if 0
5659 /**
5660 * \fn int get_sig_strength()
5661 * \brief Retrieve signal strength for VSB and QAM.
5662 * \param demod Pointer to demod instance
5663 * \param u16-t Pointer to signal strength data; range 0, .. , 100.
5664 * \return int.
5665 * \retval 0 sig_strength contains valid data.
5666 * \retval -EINVAL sig_strength is NULL.
5667 * \retval -EIO Erroneous data, sig_strength contains invalid data.
5668 */
5669 #define DRXJ_AGC_TOP 0x2800
5670 #define DRXJ_AGC_SNS 0x1600
5671 #define DRXJ_RFAGC_MAX 0x3fff
5672 #define DRXJ_RFAGC_MIN 0x800
5675 {
5689 }
5695 }
5710 }
5713 rf_agc_min);
5720 }
5727 }
5729 }
5732 rw_error:
5734 }
5735 #endif
5737 /**
5738 * \fn int get_acc_pkt_err()
5739 * \brief Retrieve signal strength for VSB and QAM.
5740 * \param demod Pointer to demod instance
5741 * \param packet_err Pointer to packet error
5742 * \return int.
5743 * \retval 0 sig_strength contains valid data.
5744 * \retval -EINVAL sig_strength is NULL.
5745 * \retval -EIO Erroneous data, sig_strength contains invalid data.
5746 */
5747 #ifdef DRXJ_SIGNAL_ACCUM_ERR
5749 {
5764 }
5769 }
5776 }
5781 rw_error:
5783 }
5784 #endif
5786 #if 0
5787 /**
5788 * \fn int ResetAccPktErr()
5789 * \brief Reset Accumulating packet error count.
5790 * \param demod Pointer to demod instance
5791 * \return int.
5792 * \retval 0.
5793 * \retval -EIO Erroneous data.
5794 */
5796 {
5803 /* call to reset counter */
5808 }
5811 rw_error:
5813 }
5815 /**
5816 * \fn static short get_str_freq_offset()
5817 * \brief Get symbol rate offset in QAM & 8VSB mode
5818 * \return Error code
5819 */
5821 {
5833 }
5840 symbol_nom_frequency_ratio),
5842 else
5845 symbol_frequency_ratio),
5849 rw_error:
5851 }
5853 /**
5854 * \fn static short get_ctl_freq_offset
5855 * \brief Get the value of ctl_freq in QAM & ATSC mode
5856 * \return Error code
5857 */
5859 {
5878 /* both registers are sign extended */
5884 }
5887 /* negative image */
5890 /* positive image */
5892 }
5894 /* carrier Frequency Shift In Hz */
5898 }
5900 /* *ctl_freq = carrier_frequency_shift * 50.625e6 / (1 << 28); */
5906 rw_error:
5908 }
5909 #endif
5911 /*============================================================================*/
5913 /**
5914 * \fn int set_agc_rf ()
5915 * \brief Configure RF AGC
5916 * \param demod instance of demodulator.
5917 * \param agc_settings AGC configuration structure
5918 * \return int.
5919 */
5920 static int
5922 {
5941 }
5943 /* Configure AGC only if standard is currently active */
5954 /* Enable RF AGC DAC */
5959 }
5965 }
5967 /* Enable SCU RF AGC loop */
5972 }
5978 else
5983 else
5989 }
5991 /* Set speed ( using complementary reduction value ) */
5996 }
5998 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
6002 }
6010 else
6013 /* Set TOP, only if IF-AGC is in AUTO mode */
6019 }
6024 }
6025 }
6027 /* Cut-Off current */
6032 }
6036 /* Enable RF AGC DAC */
6041 }
6047 }
6049 /* Disable SCU RF AGC loop */
6054 }
6058 else
6064 }
6066 /* Write value to output pin */
6071 }
6075 /* Disable RF AGC DAC */
6080 }
6086 }
6088 /* Disable SCU RF AGC loop */
6093 }
6099 }
6104 }
6106 /* Store rf agc settings */
6111 #ifndef DRXJ_VSB_ONLY
6117 #endif
6118 #if 0
6128 #endif
6131 }
6134 rw_error:
6136 }
6138 #if 0
6139 /**
6140 * \fn int get_agc_rf ()
6141 * \brief get configuration of RF AGC
6142 * \param demod instance of demodulator.
6143 * \param agc_settings AGC configuration structure
6144 * \return int.
6145 */
6146 static int
6148 {
6157 /* Return stored AGC settings */
6163 #ifndef DRXJ_VSB_ONLY
6169 #endif
6170 #if 0
6180 #endif
6183 }
6186 /* Get AGC output only if standard is currently active. */
6192 rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, &(agc_settings->output_level), 0);
6196 }
6197 }
6200 rw_error:
6202 }
6203 #endif
6205 /**
6206 * \fn int set_agc_if ()
6207 * \brief Configure If AGC
6208 * \param demod instance of demodulator.
6209 * \param agc_settings AGC configuration structure
6210 * \return int.
6211 */
6212 static int
6214 {
6233 }
6235 /* Configure AGC only if standard is currently active */
6245 /* Enable IF AGC DAC */
6250 }
6256 }
6258 /* Enable SCU IF AGC loop */
6263 }
6270 else
6275 else
6281 }
6283 /* Set speed (using complementary reduction value) */
6288 }
6290 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
6294 }
6302 else
6305 /* Restore TOP */
6311 }
6316 }
6322 }
6327 }
6328 }
6333 /* Enable IF AGC DAC */
6338 }
6344 }
6346 /* Disable SCU IF AGC loop */
6351 }
6356 else
6362 }
6364 /* Write value to output pin */
6369 }
6374 /* Disable If AGC DAC */
6379 }
6385 }
6387 /* Disable SCU IF AGC loop */
6392 }
6399 }
6405 /* always set the top to support configurations without if-loop */
6410 }
6411 }
6413 /* Store if agc settings */
6418 #ifndef DRXJ_VSB_ONLY
6424 #endif
6425 #if 0
6435 #endif
6438 }
6441 rw_error:
6443 }
6445 #if 0
6446 /**
6447 * \fn int get_agc_if ()
6448 * \brief get configuration of If AGC
6449 * \param demod instance of demodulator.
6450 * \param agc_settings AGC configuration structure
6451 * \return int.
6452 */
6453 static int
6455 {
6464 /* Return stored ATV AGC settings */
6470 #ifndef DRXJ_VSB_ONLY
6476 #endif
6488 }
6491 /* Get AGC output only if standard is currently active */
6497 /* read output level */
6498 rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, &(agc_settings->output_level), 0);
6502 }
6503 }
6506 rw_error:
6508 }
6509 #endif
6511 /**
6512 * \fn int set_iqm_af ()
6513 * \brief Configure IQM AF registers
6514 * \param demod instance of demodulator.
6515 * \param active
6516 * \return int.
6517 */
6519 {
6526 /* Configure IQM */
6531 }
6533 data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
6534 else
6535 data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
6540 }
6543 rw_error:
6545 }
6547 /*============================================================================*/
6548 /*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
6549 /*============================================================================*/
6551 /*============================================================================*/
6552 /*============================================================================*/
6553 /*== 8VSB DATAPATH FUNCTIONS ==*/
6554 /*============================================================================*/
6555 /*============================================================================*/
6557 /**
6558 * \fn int power_down_vsb ()
6559 * \brief Powr down QAM related blocks.
6560 * \param demod instance of demodulator.
6561 * \param channel pointer to channel data.
6562 * \return int.
6563 */
6565 {
6571 /* *result */ NULL
6572 };
6577 /*
6578 STOP demodulator
6579 reset of FEC and VSB HW
6580 */
6582 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
6591 }
6593 /* stop all comm_exec */
6598 }
6603 }
6609 }
6614 }
6620 }
6625 }
6630 }
6635 }
6640 }
6641 }
6648 }
6651 rw_error:
6653 }
6655 /**
6656 * \fn int set_vsb_leak_n_gain ()
6657 * \brief Set ATSC demod.
6658 * \param demod instance of demodulator.
6659 * \return int.
6660 */
6662 {
6795 };
6852 };
6855 rc = DRXJ_DAP.write_block_func(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
6859 }
6860 rc = DRXJ_DAP.write_block_func(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
6864 }
6867 rw_error:
6869 }
6871 /**
6872 * \fn int set_vsb()
6873 * \brief Set 8VSB demod.
6874 * \param demod instance of demodulator.
6875 * \return int.
6876 *
6877 */
6879 {
6916 };
6922 /* stop all comm_exec */
6927 }
6932 }
6937 }
6942 }
6947 }
6952 }
6957 }
6959 /* reset demodulator */
6970 }
6976 }
6981 }
6986 }
6992 }
6997 }
7002 }
7008 }
7013 }
7018 }
7023 }
7028 }
7033 }
7038 }
7043 }
7048 }
7050 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
7054 }
7055 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
7059 }
7092 /* Initialize the FEC Subsystem */
7097 }
7098 {
7104 }
7105 /* output data even when not locked */
7106 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
7110 }
7111 }
7113 /* set clip */
7118 }
7123 }
7128 }
7133 }
7134 /* no transparent, no A&C framing; parity is set in mpegoutput */
7135 {
7141 }
7142 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
7146 }
7147 }
7158 }
7164 /* initialize RS packet error measurement parameters */
7165 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
7169 }
7170 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
7174 }
7176 /* init measurement period of MER/SER */
7177 rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
7181 }
7186 }
7191 }
7196 }
7202 }
7203 /* B-Input to ADC, PGA+filter in standby */
7209 }
7210 }
7212 /* turn on IQMAF. It has to be in front of setAgc**() */
7217 }
7222 }
7228 }
7233 }
7238 }
7239 {
7240 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
7241 of only the gain */
7249 }
7250 }
7255 }
7257 /* Mpeg output has to be in front of FEC active */
7262 }
7267 }
7272 }
7273 {
7274 /* TODO: move to set_standard after hardware reset value problem is solved */
7275 /* Configure initial MPEG output */
7292 }
7293 }
7295 /* TBD: what parameters should be set */
7307 }
7313 }
7318 }
7319 rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
7323 }
7328 }
7333 }
7338 }
7343 }
7348 }
7350 /* start demodulator */
7361 }
7367 }
7372 }
7377 }
7380 rw_error:
7382 }
7384 /**
7385 * \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs)
7386 * \brief Get the values of packet error in 8VSB mode
7387 * \return Error code
7388 */
7390 {
7402 }
7408 /* packet error rate = (error packet number) per second */
7409 /* 77.3 us is time for per packet */
7413 }
7419 rw_error:
7421 }
7423 /**
7424 * \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber)
7425 * \brief Get the values of ber in VSB mode
7426 * \return Error code
7427 */
7429 {
7441 }
7455 }
7462 }
7465 rw_error:
7467 }
7469 /**
7470 * \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber)
7471 * \brief Get the values of ber in VSB mode
7472 * \return Error code
7473 */
7475 {
7483 }
7489 rw_error:
7491 }
7493 #if 0
7494 /**
7495 * \fn static short get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ber)
7496 * \brief Get the values of ber in VSB mode
7497 * \return Error code
7498 */
7500 {
7512 }
7523 }
7528 rw_error:
7530 }
7531 #endif
7533 /**
7534 * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
7535 * \brief Get the values of MER
7536 * \return Error code
7537 */
7539 {
7547 }
7552 rw_error:
7554 }
7556 #if 0
7557 /*============================================================================*/
7558 /**
7559 * \fn int ctrl_get_vsb_constel()
7560 * \brief Retreive a VSB constellation point via I2C.
7561 * \param demod Pointer to demodulator instance.
7562 * \param complex_nr Pointer to the structure in which to store the
7563 constellation point.
7564 * \return int.
7565 */
7566 static int
7568 {
7571 /**< device address */
7577 /* read device info */
7580 /* TODO: */
7581 /* Monitor bus grabbing is an open external interface issue */
7582 /* Needs to be checked when external interface PG is updated */
7584 /* Configure MB (Monitor bus) */
7589 }
7590 /* set observe flag & MB mux */
7592 VSB_TOP_COMM_MB_OBS_OBS_ON |
7593 VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2);
7598 }
7600 /* Enable MB grabber in the FEC OC */
7601 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M, 0);
7605 }
7607 /* Disable MB grabber in the FEC OC */
7612 }
7614 /* read data */
7619 }
7626 /* Restore MB (Monitor bus) */
7631 }
7634 rw_error:
7636 }
7637 #endif
7639 /*============================================================================*/
7640 /*== END 8VSB DATAPATH FUNCTIONS ==*/
7641 /*============================================================================*/
7643 /*============================================================================*/
7644 /*============================================================================*/
7645 /*== QAM DATAPATH FUNCTIONS ==*/
7646 /*============================================================================*/
7647 /*============================================================================*/
7649 /**
7650 * \fn int power_down_qam ()
7651 * \brief Powr down QAM related blocks.
7652 * \param demod instance of demodulator.
7653 * \param channel pointer to channel data.
7654 * \return int.
7655 */
7657 {
7662 /* *result */ NULL
7663 };
7669 /*
7670 STOP demodulator
7671 resets IQM, QAM and FEC HW blocks
7672 */
7673 /* stop all comm_exec */
7678 }
7683 }
7686 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
7695 }
7702 }
7707 }
7713 }
7718 }
7723 }
7728 }
7733 }
7734 }
7741 }
7744 rw_error:
7746 }
7748 /*============================================================================*/
7750 /**
7751 * \fn int set_qam_measurement ()
7752 * \brief Setup of the QAM Measuremnt intervals for signal quality
7753 * \param demod instance of demod.
7754 * \param constellation current constellation.
7755 * \return int.
7756 *
7757 * NOTE:
7758 * Take into account that for certain settings the errorcounters can overflow.
7759 * The implementation does not check this.
7760 *
7761 * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
7762 * constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired
7763 * field ?
7764 *
7765 */
7766 #ifndef DRXJ_VSB_ONLY
7767 static int
7770 {
7809 }
7811 /* Parameters for Reed-Solomon Decoder */
7812 /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */
7813 /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */
7814 /* result is within 32 bit arithmetic -> */
7815 /* no need for mult or frac functions */
7817 /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */
7828 }
7835 }
7840 /* limit to max 16 bit value (I2C register width) if needed */
7844 /* write corresponding registers */
7861 }
7865 }
7867 rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
7871 }
7876 }
7881 }
7888 }
7893 }
7898 }
7901 /* Parameters for Viterbi Decoder */
7902 /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */
7903 /* (qamvd_prescale*plen*(qam_constellation+1))) */
7904 /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */
7905 /* result is within 32 bit arithmetic -> */
7906 /* no need for mult or frac functions */
7908 /* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */
7915 /* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */
7916 qam_vd_period =
7921 /* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */
7922 qam_vd_period =
7928 }
7932 }
7934 /* limit to max 16 bit value (I2C register width) if needed */
7938 /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */
7945 }
7950 }
7953 }
7956 rw_error:
7958 }
7960 /*============================================================================*/
7962 /**
7963 * \fn int set_qam16 ()
7964 * \brief QAM16 specific setup
7965 * \param demod instance of demod.
7966 * \return int.
7967 */
7969 {
7979 };
7987 };
7989 rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7993 }
7994 rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7998 }
8004 }
8009 }
8014 }
8019 }
8024 }
8029 }
8035 }
8040 }
8045 }
8051 }
8056 }
8061 }
8066 }
8071 }
8076 }
8081 }
8087 }
8092 }
8097 }
8102 }
8107 }
8112 }
8117 }
8122 }
8127 }
8132 }
8137 }
8142 }
8147 }
8152 }
8157 }
8162 }
8167 }
8172 }
8177 }
8182 }
8188 }
8191 rw_error:
8193 }
8195 /*============================================================================*/
8197 /**
8198 * \fn int set_qam32 ()
8199 * \brief QAM32 specific setup
8200 * \param demod instance of demod.
8201 * \return int.
8202 */
8204 {
8214 };
8222 };
8224 rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
8228 }
8229 rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
8233 }
8239 }
8244 }
8249 }
8254 }
8259 }
8264 }
8270 }
8275 }
8280 }
8286 }
8291 }
8296 }
8301 }
8306 }
8311 }
8316 }
8322 }
8327 }
8332 }
8337 }
8342 }
8347 }
8352 }
8357 }
8362 }
8367 }
8372 }
8377 }
8382 }
8387 }
8392 }
8397 }
8402 }
8407 }
8412 }
8417 }
8423 }
8426 rw_error:
8428 }
8430 /*============================================================================*/
8432 /**
8433 * \fn int set_qam64 ()
8434 * \brief QAM64 specific setup
8435 * \param demod instance of demod.
8436 * \return int.
8437 */
8439 {
8449 };
8457 };
8459 rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
8463 }
8464 rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
8468 }
8474 }
8479 }
8484 }
8489 }
8494 }
8499 }
8505 }
8510 }
8515 }
8521 }
8526 }
8531 }
8536 }
8541 }
8546 }
8551 }
8557 }
8562 }
8567 }
8572 }
8577 }
8582 }
8587 }
8592 }
8597 }
8602 }
8607 }
8612 }
8617 }
8622 }
8627 }
8632 }
8637 }
8642 }
8647 }
8652 }
8658 }
8661 rw_error:
8663 }
8665 /*============================================================================*/
8667 /**
8668 * \fn int set_qam128 ()
8669 * \brief QAM128 specific setup
8670 * \param demod: instance of demod.
8671 * \return int.
8672 */
8674 {
8684 };
8692 };
8694 rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
8698 }
8699 rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
8703 }
8709 }
8714 }
8719 }
8724 }
8729 }
8734 }
8740 }
8745 }
8750 }
8756 }
8761 }
8766 }
8771 }
8776 }
8781 }
8786 }
8792 }
8797 }
8802 }
8807 }
8812 }
8817 }
8822 }
8827 }
8832 }
8837 }
8842 }
8847 }
8852 }
8857 }
8862 }
8867 }
8872 }
8877 }
8882 }
8887 }
8893 }
8896 rw_error:
8898 }
8900 /*============================================================================*/
8902 /**
8903 * \fn int set_qam256 ()
8904 * \brief QAM256 specific setup
8905 * \param demod: instance of demod.
8906 * \return int.
8907 */
8909 {
8919 };
8927 };
8929 rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
8933 }
8934 rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
8938 }
8944 }
8949 }
8954 }
8959 }
8964 }
8969 }
8975 }
8980 }
8985 }
8991 }
8996 }
9001 }
9006 }
9011 }
9016 }
9021 }
9027 }
9032 }
9037 }
9042 }
9047 }
9052 }
9057 }
9062 }
9067 }
9072 }
9077 }
9082 }
9087 }
9092 }
9097 }
9102 }
9107 }
9112 }
9117 }
9122 }
9128 }
9131 rw_error:
9133 }
9135 /*============================================================================*/
9136 #define QAM_SET_OP_ALL 0x1
9137 #define QAM_SET_OP_CONSTELLATION 0x2
9138 #define QAM_SET_OP_SPECTRUM 0X4
9140 /**
9141 * \fn int set_qam ()
9142 * \brief Set QAM demod.
9143 * \param demod: instance of demod.
9144 * \param channel: pointer to channel data.
9145 * \return int.
9146 */
9147 static int
9150 {
9166 /* result */ NULL
9167 };
9197 };
9227 };
9257 };
9287 };
9298 lc_symbol_freq =
9299 QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256;
9311 }
9317 }
9318 iqm_rc_rate =
9320 (frac28
9323 lc_symbol_freq =
9332 }
9348 }
9349 }
9352 /*
9353 STEP 1: reset demodulator
9354 resets IQM, QAM and FEC HW blocks
9355 resets SCU variables
9356 */
9357 /* stop all comm_exec */
9362 }
9367 }
9372 }
9377 }
9382 }
9387 }
9392 }
9395 SCU_RAM_COMMAND_CMD_DEMOD_RESET;
9404 }
9405 }
9408 /*
9409 STEP 2: configure demodulator
9410 -set env
9411 -set params (resets IQM,QAM,FEC HW; initializes some SCU variables )
9412 */
9414 SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
9423 }
9426 SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
9435 }
9436 /* set symbol rate */
9441 }
9447 }
9448 }
9449 /* STEP 3: enable the system in a mode where the ADC provides valid signal
9450 setup constellation independent registers */
9451 /* from qam_cmd.py script (qam_driver_b) */
9452 /* TODO: remove re-writes of HW reset values */
9458 }
9459 }
9467 }
9472 }
9473 }
9481 }
9482 }
9487 }
9492 }
9497 }
9509 }
9514 }
9519 }
9524 }
9529 }
9534 }
9539 }
9545 }
9582 }
9587 }
9600 }
9605 }
9610 }
9615 }
9626 }
9631 }
9636 }
9641 }
9646 }
9651 }
9656 }
9661 }
9666 }
9671 }
9676 }
9681 }
9686 }
9691 }
9696 }
9701 }
9706 }
9711 }
9716 }
9722 }
9727 }
9732 }
9737 }
9742 }
9744 /* No more resets of the IQM, current standard correctly set =>
9745 now AGCs can be configured. */
9746 /* turn on IQMAF. It has to be in front of setAgc**() */
9751 }
9756 }
9762 }
9767 }
9772 }
9773 {
9774 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
9775 of only the gain */
9783 }
9784 }
9789 }
9790 }
9794 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
9798 }
9799 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
9803 }
9807 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
9811 }
9812 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
9816 }
9819 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
9823 }
9824 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
9828 }
9832 }
9834 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
9838 }
9839 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
9843 }
9844 }
9846 /* SETP 4: constellation specific setup */
9853 }
9860 }
9867 }
9874 }
9881 }
9886 }
9893 }
9895 /* Mpeg output has to be in front of FEC active */
9900 }
9905 }
9910 }
9911 {
9912 /* TODO: move to set_standard after hardware reset value problem is solved */
9913 /* Configure initial MPEG output */
9933 }
9934 }
9935 }
9939 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
9941 SCU_RAM_COMMAND_CMD_DEMOD_START;
9950 }
9951 }
9957 }
9962 }
9967 }
9970 rw_error:
9972 }
9974 /*============================================================================*/
9975 static int
9976 ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality);
9978 {
9994 /* Silence the controlling of lc, equ, and the acquisition state machine */
9999 }
10000 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
10004 }
10006 /* freeze the frequency control loop */
10011 }
10016 }
10022 }
10027 }
10032 /* freeze dq/fq updating */
10037 }
10043 }
10048 }
10050 /* lc_cp / _ci / _ca */
10055 }
10060 }
10065 }
10067 /* flip the spec */
10072 }
10076 /* freeze dq/fq updating */
10081 }
10088 }
10093 }
10100 }
10105 }
10106 }
10113 }
10118 }
10119 }
10126 }
10131 }
10137 }
10145 }
10146 }
10151 }
10154 rw_error:
10157 }
10159 #define NO_LOCK 0x0
10160 #define DEMOD_LOCKED 0x1
10161 #define SYNC_FLIPPED 0x2
10162 #define SPEC_MIRRORED 0x4
10163 /**
10164 * \fn int qam64auto ()
10165 * \brief auto do sync pattern switching and mirroring.
10166 * \param demod: instance of demod.
10167 * \param channel: pointer to channel data.
10168 * \param tuner_freq_offset: tuner frequency offset.
10169 * \param lock_status: pointer to lock status.
10170 * \return int.
10171 */
10172 static int
10176 {
10186 /* external attributes for storing aquired channel constellation */
10196 }
10205 }
10208 /* some delay to see if fec_lock possible TODO find the right value */
10211 }
10212 }
10217 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
10222 }
10227 }
10230 }
10235 /* flip sync pattern back */
10240 }
10245 }
10246 /* flip spectrum */
10252 }
10254 /* reset timer TODO: still need 500ms? */
10260 start_time =
10263 }
10264 }
10269 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
10274 }
10280 }
10285 }
10286 /* no need to wait lock */
10287 start_time =
10290 }
10291 }
10295 }
10302 );
10303 /* Returning control to apllication ... */
10306 rw_error:
10308 }
10310 /**
10311 * \fn int qam256auto ()
10312 * \brief auto do sync pattern switching and mirroring.
10313 * \param demod: instance of demod.
10314 * \param channel: pointer to channel data.
10315 * \param tuner_freq_offset: tuner frequency offset.
10316 * \param lock_status: pointer to lock status.
10317 * \return int.
10318 */
10319 static int
10323 {
10332 /* external attributes for storing aquired channel constellation */
10342 }
10350 }
10355 }
10356 }
10362 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
10368 }
10370 /* reset timer TODO: still need 300ms? */
10373 }
10374 }
10380 }
10389 rw_error:
10391 }
10393 /**
10394 * \fn int set_qam_channel ()
10395 * \brief Set QAM channel according to the requested constellation.
10396 * \param demod: instance of demod.
10397 * \param channel: pointer to channel data.
10398 * \return int.
10399 */
10400 static int
10403 {
10409 /* external attributes for storing aquired channel constellation */
10412 /* set QAM channel constellation */
10422 else
10428 }
10436 }
10437 }
10446 }
10447 }
10452 /* try to lock default QAM constellation: QAM64 */
10457 else
10463 }
10468 }
10471 /* QAM254 not locked -> try to lock QAM64 constellation */
10473 DRX_CONSTELLATION_QAM64;
10475 DRX_CONSTELLATION_QAM64;
10478 else
10480 {
10482 rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
10486 }
10487 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
10491 }
10502 }
10503 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena, 0);
10507 }
10508 }
10513 }
10514 }
10523 else
10525 {
10527 rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
10531 }
10532 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
10536 }
10547 }
10548 rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena, 0);
10552 }
10553 }
10558 }
10563 }
10567 }
10570 rw_error:
10571 /* restore starting value */
10575 }
10577 /*============================================================================*/
10579 /**
10580 * \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr)
10581 * \brief Get RS error count in QAM mode (used for post RS BER calculation)
10582 * \return Error code
10583 *
10584 * precondition: measurement period & measurement prescale must be set
10585 *
10586 */
10587 static int
10589 {
10595 /* check arguments */
10599 /* all reported errors are received in the */
10600 /* most recently finished measurment period */
10601 /* no of pre RS bit errors */
10606 }
10607 /* no of symbol errors */
10612 }
10613 /* no of packet errors */
10618 }
10619 /* no of failures to decode */
10624 }
10625 /* no of post RS bit erros */
10630 }
10631 /* TODO: NOTE */
10632 /* These register values are fetched in non-atomic fashion */
10633 /* It is possible that the read values contain unrelated information */
10643 rw_error:
10645 }
10647 /*============================================================================*/
10649 /**
10650 * \fn int ctrl_get_qam_sig_quality()
10651 * \brief Retreive QAM signal quality from device.
10652 * \param devmod Pointer to demodulator instance.
10653 * \param sig_quality Pointer to signal quality data.
10654 * \return int.
10655 * \retval 0 sig_quality contains valid data.
10656 * \retval -EINVAL sig_quality is NULL.
10657 * \retval -EIO Erroneous data, sig_quality contains invalid data.
10659 * Pre-condition: Device must be started and in lock.
10660 */
10661 static int
10662 ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality)
10663 {
10678 /* calculation constants */
10681 /* intermediate results */
10685 /* signal quality info */
10694 /* get device basic information */
10699 /* read the physical registers */
10700 /* Get the RS error data */
10705 }
10706 /* get the register value needed for MER */
10711 }
10712 /* get the register value needed for post RS BER */
10717 }
10719 /* get constants needed for signal quality calculation */
10727 /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */
10746 }
10748 /* ------------------------------ */
10749 /* MER Calculation */
10750 /* ------------------------------ */
10751 /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */
10753 /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */
10756 else
10759 /* ----------------------------------------- */
10760 /* Pre Viterbi Symbol Error Rate Calculation */
10761 /* ----------------------------------------- */
10762 /* pre viterbi SER is good if it is bellow 0.025 */
10764 /* get the register value */
10765 /* no of quadrature symbol errors */
10770 }
10771 /* Extract the Exponent and the Mantisa */
10772 /* of number of quadrature symbol errors */
10774 QAM_VD_NR_QSYM_ERRORS_EXP__B;
10776 QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B;
10780 else
10783 /* --------------------------------------- */
10784 /* pre and post RedSolomon BER Calculation */
10785 /* --------------------------------------- */
10786 /* pre RS BER is good if it is below 3.5e-4 */
10788 /* get the register values */
10792 /* Extract the Exponent and the Mantisa of the */
10793 /* pre Reed-Solomon bit error count */
10795 FEC_RS_NR_BIT_ERRORS_EXP__B;
10797 FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B;
10801 /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */
10804 else
10807 /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */
10808 /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */
10809 /*
10810 => c = (1000000*100*11.17)/1504 =
10811 post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) /
10812 (100 * FEC_OC_SNC_FAIL_PERIOD__A)
10813 *100 and /100 is for more precision.
10814 => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation
10816 Precision errors still possible.
10817 */
10822 else
10825 /* fill signal quality data structure */
10829 else
10834 #ifdef DRXJ_SIGNAL_ACCUM_ERR
10839 }
10840 #else
10842 #endif
10845 rw_error:
10847 }
10849 #if 0
10850 /**
10851 * \fn int ctrl_get_qam_constel()
10852 * \brief Retreive a QAM constellation point via I2C.
10853 * \param demod Pointer to demodulator instance.
10854 * \param complex_nr Pointer to the structure in which to store the
10855 constellation point.
10856 * \return int.
10857 */
10858 static int
10860 {
10865 /**< FEC OCR grabber configuration */
10868 /**< QAM SL MB intial configuration */
10871 /**< device address */
10873 /* read device info */
10876 /* TODO: */
10877 /* Monitor bus grabbing is an open external interface issue */
10878 /* Needs to be checked when external interface PG is updated */
10880 /* Configure MB (Monitor bus) */
10885 }
10886 /* set observe flag & MB mux */
10888 QAM_SL_COMM_MB_MUX_OBS__M));
10890 QAM_SL_COMM_MB_MUX_OBS_CONST_CORR);
10895 }
10897 /* Enable MB grabber in the FEC OC */
10901 /* grabber enable: on */
10904 /* grabber select: observe bus */
10907 /* grabber mode: continuous */
10914 }
10916 /* Disable MB grabber in the FEC OC */
10921 }
10923 /* read data */
10928 }
10932 /* TODO: */
10933 /* interpret data (re & im) according to the Monitor bus mapping ?? */
10935 /* sign extension, 10th bit is sign bit */
10943 /* Restore MB (Monitor bus) */
10948 }
10951 rw_error:
10953 }
10957 /*============================================================================*/
10958 /*== END QAM DATAPATH FUNCTIONS ==*/
10959 /*============================================================================*/
10961 /*============================================================================*/
10962 /*============================================================================*/
10963 /*== ATV DATAPATH FUNCTIONS ==*/
10964 /*============================================================================*/
10965 /*============================================================================*/
10967 /*
10968 Implementation notes.
10970 NTSC/FM AGCs
10972 Four AGCs are used for NTSC:
10973 (1) RF (used to attenuate the input signal in case of to much power)
10974 (2) IF (used to attenuate the input signal in case of to much power)
10975 (3) Video AGC (used to amplify the output signal in case input to low)
10976 (4) SIF AGC (used to amplify the output signal in case input to low)
10978 Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed
10979 that the coupling between Video AGC and the RF and IF AGCs also works in
10980 favor of the SIF AGC.
10982 Three AGCs are used for FM:
10983 (1) RF (used to attenuate the input signal in case of to much power)
10984 (2) IF (used to attenuate the input signal in case of to much power)
10985 (3) SIF AGC (used to amplify the output signal in case input to low)
10987 The SIF AGC is now coupled to the RF/IF AGCs.
10988 The SIF AGC is needed for both SIF ouput and the internal SIF signal to
10989 the AUD block.
10991 RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of
10992 the ATV block. The AGC control algorithms are all implemented in
10993 microcode.
10995 ATV SETTINGS
10997 (Shadow settings will not be used for now, they will be implemented
10998 later on because of the schedule)
11000 Several HW/SCU "settings" can be used for ATV. The standard selection
11001 will reset most of these settings. To avoid that the end user apllication
11002 has to perform these settings each time the ATV or FM standards is
11003 selected the driver will shadow these settings. This enables the end user
11004 to perform the settings only once after a drx_open(). The driver must
11005 write the shadow settings to HW/SCU incase:
11006 ( setstandard FM/ATV) ||
11007 ( settings have changed && FM/ATV standard is active)
11008 The shadow settings will be stored in the device specific data container.
11009 A set of flags will be defined to flag changes in shadow settings.
11010 A routine will be implemented to write all changed shadow settings to
11011 HW/SCU.
11013 The "settings" will consist of: AGC settings, filter settings etc.
11015 Disadvantage of use of shadow settings:
11016 Direct changes in HW/SCU registers will not be reflected in the
11017 shadow settings and these changes will be overwritten during a next
11018 update. This can happen during evaluation. This will not be a problem
11019 for normal customer usage.
11020 */
11021 /* -------------------------------------------------------------------------- */
11023 #if 0
11024 /**
11025 * \brief Get array index for atv coef (ext_attr->atvTopCoefX[index])
11026 * \param standard
11027 * \param pointer to index
11028 * \return int.
11029 *
11030 */
11032 {
11059 }
11062 }
11064 /* -------------------------------------------------------------------------- */
11065 /**
11066 * \fn int atv_update_config ()
11067 * \brief Flush changes in ATV shadow registers to physical registers.
11068 * \param demod instance of demodulator
11069 * \param force_update don't look at standard or change flags, flush all.
11070 * \return int.
11071 *
11072 */
11073 static int
11075 {
11083 /* equalizer coefficients */
11092 }
11097 }
11102 }
11107 }
11112 }
11113 }
11115 /* bypass fast carrier recovery */
11123 }
11127 else
11133 }
11134 }
11136 /* peak filter setting */
11143 }
11144 }
11146 /* noise filter setting */
11153 }
11154 }
11156 /* SIF attenuation */
11177 }
11182 }
11183 }
11185 /* SIF & CVBS enable */
11194 }
11197 else
11202 else
11208 }
11209 }
11214 rw_error:
11216 }
11218 /* -------------------------------------------------------------------------- */
11219 /**
11220 * \fn int ctrl_set_cfg_atv_output()
11221 * \brief Configure ATV ouputs
11222 * \param demod instance of demodulator
11223 * \param output_cfg output configuaration
11224 * \return int.
11225 *
11226 */
11227 static int
11228 ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg)
11229 {
11233 /* Check arguments */
11244 /* Do nothing */
11249 }
11254 }
11255 }
11260 }
11265 }
11271 }
11274 rw_error:
11276 }
11278 /* -------------------------------------------------------------------------- */
11279 /**
11280 * \fn int ctrl_set_cfg_atv_equ_coef()
11281 * \brief Set ATV equalizer coefficients
11282 * \param demod instance of demodulator
11283 * \param coef the equalizer coefficients
11284 * \return int.
11285 *
11286 */
11287 static int
11288 ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_equ_coef *coef)
11289 {
11296 /* current standard needs to be an ATV standard */
11300 /* Check arguments */
11311 }
11317 }
11328 }
11331 rw_error:
11333 }
11335 /* -------------------------------------------------------------------------- */
11336 /**
11337 * \fn int ctrl_get_cfg_atv_equ_coef()
11338 * \brief Get ATV equ coef settings
11339 * \param demod instance of demodulator
11340 * \param coef The ATV equ coefficients
11341 * \return int.
11342 *
11343 * The values are read from the shadow registers maintained by the drxdriver
11344 * If registers are manipulated outside of the drxdriver scope the reported
11345 * settings will not reflect these changes because of the use of shadow
11346 * regitsers.
11347 *
11348 */
11349 static int
11350 ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_equ_coef *coef)
11351 {
11358 /* current standard needs to be an ATV standard */
11362 /* Check arguments */
11370 }
11377 rw_error:
11379 }
11381 /* -------------------------------------------------------------------------- */
11382 /**
11383 * \fn int ctrl_set_cfg_atv_misc()
11384 * \brief Set misc. settings for ATV.
11385 * \param demod instance of demodulator
11386 * \param
11387 * \return int.
11388 *
11389 */
11390 static int
11392 {
11396 /* Check arguments */
11402 }
11403 /* if */
11409 }
11414 }
11420 }
11423 rw_error:
11425 }
11427 /* -------------------------------------------------------------------------- */
11428 /**
11429 * \fn int ctrl_get_cfg_atv_misc()
11430 * \brief Get misc settings of ATV.
11431 * \param demod instance of demodulator
11432 * \param settings misc. ATV settings
11433 * \return int.
11434 *
11435 * The values are read from the shadow registers maintained by the drxdriver
11436 * If registers are manipulated outside of the drxdriver scope the reported
11437 * settings will not reflect these changes because of the use of shadow
11438 * regitsers.
11439 */
11440 static int
11442 {
11445 /* Check arguments */
11455 }
11457 /* -------------------------------------------------------------------------- */
11459 /* -------------------------------------------------------------------------- */
11460 /**
11461 * \fn int ctrl_get_cfg_atv_output()
11462 * \brief
11463 * \param demod instance of demodulator
11464 * \param output_cfg output configuaration
11465 * \return int.
11466 *
11467 */
11468 static int
11469 ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg)
11470 {
11474 /* Check arguments */
11482 }
11485 else
11496 }
11498 }
11501 rw_error:
11503 }
11505 /* -------------------------------------------------------------------------- */
11506 /**
11507 * \fn int ctrl_get_cfg_atv_agc_status()
11508 * \brief
11509 * \param demod instance of demodulator
11510 * \param agc_status agc status
11511 * \return int.
11512 *
11513 */
11514 static int
11517 {
11523 /* Check arguments */
11529 /*
11530 RFgain = (IQM_AF_AGC_RF__A * 26.75)/1000 (uA)
11531 = ((IQM_AF_AGC_RF__A * 27) - (0.25*IQM_AF_AGC_RF__A))/1000
11533 IQM_AF_AGC_RF__A * 27 is 20 bits worst case.
11534 */
11539 }
11542 /* rounding */
11546 /*
11547 IFgain = (IQM_AF_AGC_IF__A * 26.75)/1000 (uA)
11548 = ((IQM_AF_AGC_IF__A * 27) - (0.25*IQM_AF_AGC_IF__A))/1000
11550 IQM_AF_AGC_IF__A * 27 is 20 bits worst case.
11551 */
11556 }
11559 /* rounding */
11563 /*
11564 videoGain = (ATV_TOP_SFR_VID_GAIN__A/16 -150)* 0.05 (dB)
11565 = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (dB)
11566 = 10*(ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (in 0.1 dB)
11567 = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/2 (in 0.1 dB)
11568 = (ATV_TOP_SFR_VID_GAIN__A/32) - 75 (in 0.1 dB)
11569 */
11575 }
11576 /* dividing by 32 inclusive rounding */
11579 data++;
11583 /*
11584 audioGain = (SCU_RAM_ATV_SIF_GAIN__A -8)* 0.05 (dB)
11585 = (SCU_RAM_ATV_SIF_GAIN__A -8)/20 (dB)
11586 = 10*(SCU_RAM_ATV_SIF_GAIN__A -8)/20 (in 0.1 dB)
11587 = (SCU_RAM_ATV_SIF_GAIN__A -8)/2 (in 0.1 dB)
11588 = (SCU_RAM_ATV_SIF_GAIN__A/2) - 4 (in 0.1 dB)
11589 */
11595 }
11597 /* dividing by 2 inclusive rounding */
11599 data++;
11603 /* Loop gain's */
11608 }
11617 rw_error:
11619 }
11621 /* -------------------------------------------------------------------------- */
11623 /**
11624 * \fn int power_up_atv ()
11625 * \brief Power up ATV.
11626 * \param demod instance of demodulator
11627 * \param standard either NTSC or FM (sub strandard for ATV )
11628 * \return int.
11629 *
11630 * * Starts ATV and IQM
11631 * * AUdio already started during standard init for ATV.
11632 */
11634 {
11638 /* ATV NTSC */
11643 }
11644 /* turn on IQM_AF */
11649 }
11654 }
11660 }
11662 /* Audio, already done during set standard */
11665 rw_error:
11667 }
11668 #endif
11670 /* -------------------------------------------------------------------------- */
11672 /**
11673 * \fn int power_down_atv ()
11674 * \brief Power down ATV.
11675 * \param demod instance of demodulator
11676 * \param standard either NTSC or FM (sub strandard for ATV )
11677 * \return int.
11678 *
11679 * Stops and thus resets ATV and IQM block
11680 * SIF and CVBS ADC are powered down
11681 * Calls audio power down
11682 */
11683 static int
11685 {
11691 /* *result */ NULL
11692 };
11696 /* ATV NTSC */
11698 /* Stop ATV SCU (will reset ATV and IQM hardware */
11700 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
11709 }
11710 /* Disable ATV outputs (ATV reset enables CVBS, undo this) */
11711 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
11715 }
11721 }
11727 }
11732 }
11738 }
11743 }
11748 }
11753 }
11758 }
11759 }
11764 }
11767 rw_error:
11769 }
11771 /* -------------------------------------------------------------------------- */
11772 /**
11773 * \fn int set_atv_standard ()
11774 * \brief Set up ATV demodulator.
11775 * \param demod instance of demodulator
11776 * \param standard either NTSC or FM (sub strandard for ATV )
11777 * \return int.
11778 *
11779 * Init all channel independent registers.
11780 * Assuming that IQM, ATV and AUD blocks have been reset and are in STOP mode
11781 *
11782 */
11783 #if 0
11785 static int
11787 {
11788 /* TODO: enable alternative for tap settings via external file
11790 something like:
11791 #ifdef DRXJ_ATV_COEF_FILE
11792 #include DRXJ_ATV_COEF_FILE
11793 #else
11794 ... code defining fixed coef's ...
11795 #endif
11797 Cutsomer must create file "customer_coefs.c.inc" containing
11798 modified copy off the constants below, and define the compiler
11799 switch DRXJ_ATV_COEF_FILE="customer_coefs.c.inc".
11801 Still to check if this will work; DRXJ_16TO8 macro may cause
11802 trouble ?
11803 */
11833 };
11863 };
11893 };
11923 };
11953 };
11983 };
12013 };
12043 };
12050 /* *result */ NULL
12051 };
12064 }
12069 }
12074 }
12079 }
12084 }
12089 }
12090 /* Reset ATV SCU */
12092 SCU_RAM_COMMAND_CMD_DEMOD_RESET;
12101 }
12107 }
12109 /* TODO remove AUTO/OFF patches after ucode fix. */
12112 /* NTSC */
12119 }
12124 }
12125 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), ((u8 *)ntsc_taps_re), 0);
12129 }
12130 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), ((u8 *)ntsc_taps_im), 0);
12134 }
12140 }
12141 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_MN | ATV_TOP_CR_CONT_CR_D_MN | ATV_TOP_CR_CONT_CR_I_MN), 0);
12145 }
12150 }
12151 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | ATV_TOP_STD_VID_POL_MN), 0);
12155 }
12160 }
12162 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0);
12166 }
12171 }
12176 }
12177 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0);
12181 }
12186 /* FM */
12193 }
12198 }
12199 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), ((u8 *)fm_taps_re), 0);
12203 }
12204 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), ((u8 *)fm_taps_im), 0);
12208 }
12209 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | ATV_TOP_STD_VID_POL_FM), 0);
12213 }
12218 }
12223 }
12225 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM), 0);
12229 }
12234 }
12239 /* PAL/SECAM B/G */
12251 }
12252 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), ((u8 *)bg_taps_re), 0);
12256 }
12257 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), ((u8 *)bg_taps_im), 0);
12261 }
12266 }
12271 }
12272 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_BG | ATV_TOP_CR_CONT_CR_D_BG | ATV_TOP_CR_CONT_CR_I_BG), 0);
12276 }
12281 }
12282 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | ATV_TOP_STD_VID_POL_BG), 0);
12286 }
12287 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0);
12291 }
12296 }
12301 }
12302 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0);
12306 }
12312 /* PAL/SECAM D/K */
12324 }
12325 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0);
12329 }
12330 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0);
12334 }
12339 }
12344 }
12345 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_DK | ATV_TOP_CR_CONT_CR_D_DK | ATV_TOP_CR_CONT_CR_I_DK), 0);
12349 }
12354 }
12355 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | ATV_TOP_STD_VID_POL_DK), 0);
12359 }
12360 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0);
12364 }
12369 }
12374 }
12375 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK, 0);
12379 }
12385 /* PAL/SECAM I */
12397 }
12398 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0);
12402 }
12403 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0);
12407 }
12412 }
12417 }
12418 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_I | ATV_TOP_CR_CONT_CR_D_I | ATV_TOP_CR_CONT_CR_I_I), 0);
12422 }
12427 }
12428 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | ATV_TOP_STD_VID_POL_I), 0);
12432 }
12433 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0);
12437 }
12442 }
12447 }
12448 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I, 0);
12452 }
12458 /* PAL/SECAM L with negative modulation */
12470 }
12475 }
12476 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0);
12480 }
12481 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0);
12485 }
12491 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_L | ATV_TOP_CR_CONT_CR_D_L | ATV_TOP_CR_CONT_CR_I_L), 0);
12495 }
12500 }
12501 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | ATV_TOP_STD_VID_POL_L), 0);
12505 }
12506 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0);
12510 }
12515 }
12520 }
12521 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0);
12525 }
12532 /* PAL/SECAM L with positive modulation */
12539 }
12549 }
12550 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0);
12554 }
12555 rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0);
12559 }
12565 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_LP | ATV_TOP_CR_CONT_CR_D_LP | ATV_TOP_CR_CONT_CR_I_LP), 0);
12569 }
12574 }
12575 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | ATV_TOP_STD_VID_POL_LP), 0);
12579 }
12580 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0);
12584 }
12589 }
12594 }
12595 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0);
12599 }
12607 }
12609 /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */
12615 }
12616 }
12622 }
12627 }
12632 }
12637 }
12642 }
12647 }
12654 }
12659 }
12664 }
12666 rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON, 0);
12670 }
12676 }
12681 }
12682 /* default: SIF in standby */
12687 }
12692 }
12698 }
12703 }
12708 }
12713 }
12718 }
12723 }
12728 }
12734 }
12739 }
12744 }
12749 }
12754 }
12759 }
12764 }
12769 }
12774 }
12776 /* Override reset values with current shadow settings */
12781 }
12783 /* Configure/restore AGC settings */
12788 }
12793 }
12798 }
12803 }
12805 /* Set SCU ATV substandard,assuming this doesn't require running ATV block */
12807 SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
12816 }
12818 /* turn the analog work around on/off (must after set_env b/c it is set in mc) */
12824 }
12830 }
12835 }
12836 }
12839 rw_error:
12841 }
12843 /* -------------------------------------------------------------------------- */
12845 /**
12846 * \fn int set_atv_channel ()
12847 * \brief Set ATV channel.
12848 * \param demod: instance of demod.
12849 * \return int.
12850 *
12851 * Not much needs to be done here, only start the SCU for NTSC/FM.
12852 * Mirrored channels are not expected in the RF domain, so IQM FS setting
12853 * doesn't need to be remembered.
12854 * The channel->mirror parameter is therefor ignored.
12855 *
12856 */
12857 static int
12859 s32 tuner_freq_offset,
12861 {
12866 /* result */ NULL
12867 };
12876 /*
12877 Program frequency shifter
12878 No need to account for mirroring on RF
12879 */
12882 else
12889 }
12894 }
12896 /* Start ATV SCU */
12898 SCU_RAM_COMMAND_CMD_DEMOD_START;
12907 }
12909 /* if ( (ext_attr->standard == DRX_STANDARD_FM) && (ext_attr->flagSetAUDdone == true) )
12910 {
12911 ext_attr->detectedRDS = (bool)false;
12912 }*/
12915 rw_error:
12917 }
12919 /* -------------------------------------------------------------------------- */
12921 /**
12922 * \fn int get_atv_channel ()
12923 * \brief Set ATV channel.
12924 * \param demod: instance of demod.
12925 * \param channel: pointer to channel data.
12926 * \param standard: NTSC or FM.
12927 * \return int.
12928 *
12929 * Covers NTSC, PAL/SECAM - B/G, D/K, I, L, LP and FM.
12930 * Computes the frequency offset in te RF domain and adds it to
12931 * channel->frequency. Determines the value for channel->bandwidth.
12932 *
12933 */
12934 static int
12937 {
12942 /* Bandwidth */
12951 {
12954 /* get measured frequency offset */
12959 }
12960 /* Signed 8 bit register => sign extension needed */
12963 offset +=
12966 }
12968 {
12971 /* get measured frequency offset */
12976 }
12977 /* Signed 8 bit register => sign extension needed */
12980 offset -=
12982 }
12985 /* TODO: compute offset using AUD_DSP_RD_FM_DC_LEVEL_A__A and
12986 AUD_DSP_RD_FM_DC_LEVEL_B__A. For now leave frequency as is.
12987 */
12988 /* No bandwidth know for FM */
12993 }
12998 rw_error:
13000 }
13002 /* -------------------------------------------------------------------------- */
13003 /**
13004 * \fn int get_atv_sig_strength()
13005 * \brief Retrieve signal strength for ATV & FM.
13006 * \param devmod Pointer to demodulator instance.
13007 * \param sig_quality Pointer to signal strength data; range 0, .. , 100.
13008 * \return int.
13009 * \retval 0 sig_strength contains valid data.
13010 * \retval -EIO Erroneous data, sig_strength equals 0.
13011 *
13012 * Taking into account:
13013 * * digital gain
13014 * * IF gain (not implemented yet, waiting for IF gain control by ucode)
13015 * * RF gain
13016 *
13017 * All weights (digital, if, rf) must add up to 100.
13018 *
13019 * TODO: ? dynamically adapt weights in case RF and/or IF agc of drxj
13020 * is not used ?
13021 */
13022 static int
13024 {
13029 /* All weights must add up to 100 (%)
13030 TODO: change weights when IF ctrl is available */
13061 rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &digital_curr_gain, 0);
13065 }
13070 rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &digital_curr_gain, 0);
13074 }
13081 }
13086 }
13091 }
13093 /* clipping */
13107 /* TODO: use SCU_RAM_ATV_RAGC_HR__A to shift max and min in case
13108 of clipping at ADC */
13110 /* Compute signal strength (in %) per "gain domain" */
13112 /* Digital gain */
13113 /* TODO: ADC clipping not handled */
13117 /* TODO: IF gain not implemented yet in microcode, check after impl. */
13121 /* Rf gain */
13122 /* TODO: ADC clipping not handled */
13126 /* Compute a weighted signal strength (in %) */
13132 rw_error:
13134 }
13136 /* -------------------------------------------------------------------------- */
13137 /**
13138 * \fn int atv_sig_quality()
13139 * \brief Retrieve signal quality indication for ATV.
13140 * \param devmod Pointer to demodulator instance.
13141 * \param sig_quality Pointer to signal quality structure.
13142 * \return int.
13143 * \retval 0 sig_quality contains valid data.
13144 * \retval -EIO Erroneous data, sig_quality indicator equals 0.
13145 *
13146 *
13147 */
13148 static int
13150 {
13157 /* defined values for fields not used */
13165 /*
13166 Mapping:
13167 0x000..0x080: strong signal => 80% .. 100%
13168 0x080..0x700: weak signal => 30% .. 80%
13169 0x700..0x7ff: no signal => 0% .. 30%
13170 */
13176 }
13183 else
13187 rw_error:
13189 }
13191 /*============================================================================*/
13192 /*== END ATV DATAPATH FUNCTIONS ==*/
13193 /*============================================================================*/
13195 /*===========================================================================*/
13196 /*===========================================================================*/
13197 /*== AUDIO DATAPATH FUNCTIONS ==*/
13198 /*===========================================================================*/
13199 /*===========================================================================*/
13201 /*
13202 * \brief Power up AUD.
13203 * \param demod instance of demodulator
13204 * \return int.
13205 *
13206 */
13208 {
13219 }
13220 /* setup TR interface: R/W mode, fifosize=8 */
13225 }
13230 }
13237 }
13238 }
13241 rw_error:
13243 }
13244 #endif
13246 /*============================================================================*/
13248 /**
13249 * \brief Power up AUD.
13250 * \param demod instance of demodulator
13251 * \return int.
13252 *
13253 */
13255 {
13267 }
13272 rw_error:
13274 }
13276 #if 0
13277 /*============================================================================*/
13278 /**
13279 * \brief Get Modus data from audio RAM
13280 * \param demod instance of demodulator
13281 * \param pointer to modus
13282 * \return int.
13283 *
13284 */
13286 {
13301 /* power up */
13307 }
13309 }
13311 /* Modus register is combined in to RAM location */
13316 }
13321 }
13329 rw_error:
13332 }
13334 /*============================================================================*/
13335 /**
13336 * \brief Get audio RDS dat
13337 * \param demod instance of demodulator
13338 * \param pointer to struct drx_cfg_aud_rds * \return int.
13339 *
13340 */
13341 static int
13343 {
13359 /* power up */
13365 }
13367 }
13375 }
13378 AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID) {
13379 /* invalid data */
13381 }
13384 /* no new data */
13386 }
13388 /* RDS is detected, as long as FM radio is selected assume
13389 RDS will be available */
13392 /* new data */
13393 /* read the data */
13399 }
13401 }
13407 }
13412 }
13415 rw_error:
13417 }
13419 /*============================================================================*/
13420 /**
13421 * \brief Get the current audio carrier detection status
13422 * \param demod instance of demodulator
13423 * \param pointer to aud_ctrl_get_status
13424 * \return int.
13425 *
13426 */
13427 static int
13428 aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_aud_status *status)
13429 {
13441 /* power up */
13447 }
13449 }
13451 /* initialize the variables */
13458 /* read stereo sound mode indication */
13463 }
13465 /* carrier a detected */
13469 /* carrier b detected */
13472 /* nicam detected */
13474 AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED) {
13477 else
13479 }
13481 /* audio mode bilingual or SAP detected */
13485 /* stereo detected */
13490 rw_error:
13492 }
13494 /*============================================================================*/
13495 /**
13496 * \brief Get the current audio status parameters
13497 * \param demod instance of demodulator
13498 * \param pointer to aud_ctrl_get_status
13499 * \return int.
13500 *
13501 */
13502 static int
13504 {
13517 /* carrier detection */
13522 }
13524 /* rds data */
13530 }
13533 /* fm_ident */
13538 }
13543 rw_error:
13545 }
13547 /*============================================================================*/
13548 /**
13549 * \brief Get the current volume settings
13550 * \param demod instance of demodulator
13551 * \param pointer to struct drx_cfg_aud_volume * \return int.
13552 *
13553 */
13554 static int
13556 {
13572 /* power up */
13578 }
13580 }
13582 /* volume */
13588 }
13595 AUD_DSP_WR_VOLUME_VOL_MAIN__B) -
13596 AUD_VOLUME_ZERO_DB;
13601 }
13603 /* automatic volume control */
13608 }
13629 }
13630 }
13632 /* max attenuation */
13646 }
13648 /* max gain */
13662 }
13664 /* reference level */
13666 AUD_DSP_WR_AVC_AVC_REF_LEV__B);
13668 /* read qpeak registers and calculate strength of left and right carrier */
13669 /* quasi peaks formula: QP(dB) = 20 * log( AUD_DSP_RD_QPEAKx / Q(0dB) */
13670 /* Q(0dB) represents QP value of 0dB (hex value 0x4000) */
13671 /* left carrier */
13673 /* QP vaues */
13674 /* left carrier */
13679 }
13683 /* right carrier */
13688 }
13693 rw_error:
13695 }
13697 /*============================================================================*/
13698 /**
13699 * \brief Set the current volume settings
13700 * \param demod instance of demodulator
13701 * \param pointer to struct drx_cfg_aud_volume * \return int.
13702 *
13703 */
13704 static int
13706 {
13720 /* power up */
13726 }
13728 }
13730 /* volume */
13731 /* volume range from -60 to 12 (expressed in dB) */
13740 }
13742 /* clear the volume mask */
13746 else
13753 }
13755 /* automatic volume control */
13760 }
13762 /* clear masks that require writing */
13772 /* avc decay */
13788 }
13789 }
13791 /* max attenuation */
13805 }
13807 /* max gain */
13821 }
13823 /* avc reference level */
13834 }
13836 /* all done, store config in data structure */
13840 rw_error:
13842 }
13844 /*============================================================================*/
13845 /**
13846 * \brief Get the I2S settings
13847 * \param demod instance of demodulator
13848 * \param pointer to struct drx_cfg_i2s_output * \return int.
13849 *
13850 */
13851 static int
13852 aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s_output *output)
13853 {
13866 /* power up */
13872 }
13874 }
13880 }
13885 }
13887 /* I2S mode */
13897 }
13899 /* I2S format */
13909 }
13911 /* I2S word length */
13921 }
13923 /* I2S polarity */
13933 }
13935 /* I2S output enabled */
13936 if ((w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M) == AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE)
13938 else
13947 }
13950 rw_error:
13952 }
13954 /*============================================================================*/
13955 /**
13956 * \brief Set the I2S settings
13957 * \param demod instance of demodulator
13958 * \param pointer to struct drx_cfg_i2s_output * \return int.
13959 *
13960 */
13961 static int
13962 aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s_output *output)
13963 {
13979 /* power up */
13985 }
13987 }
13993 }
13995 /* I2S mode */
14007 }
14009 /* I2S format */
14021 }
14023 /* I2S word length */
14035 }
14037 /* I2S polarity */
14048 }
14050 /* I2S output enabled */
14054 else
14057 /*
14058 I2S frequency
14060 w_i2s_freq = 6144 * 48000 * nrbits / ( 32 * frequency )
14062 16bit: 6144 * 48000 / ( 2 * freq ) = ( 6144 * 48000 / freq ) / 2
14063 32bit: 6144 * 48000 / freq = ( 6144 * 48000 / freq )
14064 */
14068 }
14080 }
14085 }
14087 /* configure I2S output pads for master or slave mode */
14092 }
14096 SIO_PDR_I2S_DA_CFG_DRIVE__MASTER;
14098 SIO_PDR_I2S_CL_CFG_DRIVE__MASTER;
14100 SIO_PDR_I2S_WS_CFG_DRIVE__MASTER;
14103 SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE;
14105 SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE;
14107 SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE;
14108 }
14114 }
14119 }
14124 }
14130 }
14132 /* all done, store config in data structure */
14136 rw_error:
14138 }
14140 /*============================================================================*/
14141 /**
14142 * \brief Get the Automatic Standard Select (ASS)
14143 * and Automatic Sound Change (ASC)
14144 * \param demod instance of demodulator
14145 * \param pointer to pDRXAudAutoSound_t
14146 * \return int.
14147 *
14148 */
14149 static int
14152 {
14162 /* power up */
14168 }
14170 }
14176 }
14179 AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M)) {
14183 DRX_AUD_AUTO_SOUND_OFF;
14187 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON;
14191 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF;
14195 }
14198 rw_error:
14200 }
14202 /*============================================================================*/
14203 /**
14204 * \brief Set the Automatic Standard Select (ASS)
14205 * and Automatic Sound Change (ASC)
14206 * \param demod instance of demodulator
14207 * \param pointer to pDRXAudAutoSound_t
14208 * \return int.
14209 *
14210 */
14211 static int
14214 {
14227 /* power up */
14233 }
14235 }
14241 }
14244 /* clear ASS & ASC bits */
14263 }
14270 }
14271 }
14272 /* copy to data structure */
14276 rw_error:
14278 }
14280 /*============================================================================*/
14281 /**
14282 * \brief Get the Automatic Standard Select thresholds
14283 * \param demod instance of demodulator
14284 * \param pointer to pDRXAudASSThres_t
14285 * \return int.
14286 *
14287 */
14288 static int
14289 aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ass_thres *thres)
14290 {
14304 /* power up */
14310 }
14312 }
14318 }
14323 }
14328 }
14335 rw_error:
14337 }
14339 /*============================================================================*/
14340 /**
14341 * \brief Get the Automatic Standard Select thresholds
14342 * \param demod instance of demodulator
14343 * \param pointer to pDRXAudASSThres_t
14344 * \return int.
14345 *
14346 */
14347 static int
14348 aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ass_thres *thres)
14349 {
14359 /* power up */
14365 }
14367 }
14373 }
14378 }
14383 }
14385 /* update DRXK data structure with hardware values */
14389 rw_error:
14391 }
14393 /*============================================================================*/
14394 /**
14395 * \brief Get Audio Carrier settings
14396 * \param demod instance of demodulator
14397 * \param pointer to struct drx_aud_carrier ** \return int.
14398 *
14399 */
14400 static int
14401 aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_carriers *carriers)
14402 {
14428 /* power up */
14434 }
14436 }
14442 }
14444 /* Behaviour of primary audio channel */
14455 }
14457 /* Behaviour of secondary audio channel */
14468 }
14470 /* frequency adjustment for primary & secondary audio channel */
14475 }
14480 }
14485 }
14490 }
14495 /* Multiply by 20250 * 1>>24 ~= 2 / 1657 */
14499 /* DC level of the incoming FM signal on the primary
14500 & seconday sound channel */
14505 }
14510 }
14512 /* offset (kHz) = (dcLvl / 322) */
14516 /* Carrier detetcion threshold for primary & secondary channel */
14521 }
14526 }
14532 rw_error:
14534 }
14536 /*============================================================================*/
14537 /**
14538 * \brief Set Audio Carrier settings
14539 * \param demod instance of demodulator
14540 * \param pointer to struct drx_aud_carrier ** \return int.
14541 *
14542 */
14543 static int
14544 aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_carriers *carriers)
14545 {
14564 /* power up */
14570 }
14572 }
14578 }
14582 /* Behaviour of primary audio channel */
14593 }
14595 /* Behaviour of secondary audio channel */
14607 }
14609 /* now update the modus register */
14615 }
14616 }
14618 /* frequency adjustment for primary & secondary audio channel */
14631 }
14636 }
14641 }
14646 }
14648 /* Carrier detetcion threshold for primary & secondary channel */
14653 }
14658 }
14660 /* update DRXK data structure */
14664 rw_error:
14666 }
14668 /*============================================================================*/
14669 /**
14670 * \brief Get I2S Source, I2S matrix and FM matrix
14671 * \param demod instance of demodulator
14672 * \param pointer to pDRXAudmixer_t
14673 * \return int.
14674 *
14675 */
14676 static int
14678 {
14691 /* power up */
14697 }
14699 }
14701 /* Source Selctor */
14706 }
14723 }
14725 /* Matrix */
14741 }
14743 /* FM Matrix */
14748 }
14767 }
14770 rw_error:
14772 }
14774 /*============================================================================*/
14775 /**
14776 * \brief Set I2S Source, I2S matrix and FM matrix
14777 * \param demod instance of demodulator
14778 * \param pointer to DRXAudmixer_t
14779 * \return int.
14780 *
14781 */
14782 static int
14784 {
14797 /* power up */
14803 }
14805 }
14807 /* Source Selctor */
14812 }
14830 }
14832 /* Matrix */
14849 }
14850 /* write the result */
14855 }
14857 /* FM Matrix */
14862 }
14882 }
14884 /* Only write if ASS is off */
14890 }
14891 }
14893 /* update the data structure with hardware state */
14897 rw_error:
14899 }
14901 /*============================================================================*/
14902 /**
14903 * \brief Set AV Sync settings
14904 * \param demod instance of demodulator
14905 * \param pointer to DRXICfgAVSync_t
14906 * \return int.
14907 *
14908 */
14909 static int
14911 {
14923 /* power up */
14929 }
14931 }
14933 /* audio/video synchronisation */
14938 }
14944 else
14960 /* OK */
14964 }
14970 }
14972 rw_error:
14974 }
14976 /*============================================================================*/
14977 /**
14978 * \brief Get AV Sync settings
14979 * \param demod instance of demodulator
14980 * \param pointer to DRXICfgAVSync_t
14981 * \return int.
14982 *
14983 */
14984 static int
14986 {
14998 /* power up */
15004 }
15006 }
15008 /* audio/video synchronisation */
15013 }
15016 AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE) {
15019 }
15033 }
15036 rw_error:
15038 }
15040 /*============================================================================*/
15041 /**
15042 * \brief Get deviation mode
15043 * \param demod instance of demodulator
15044 * \param pointer to enum drx_cfg_aud_deviation * \return int.
15045 *
15046 */
15047 static int
15049 {
15060 }
15071 }
15074 rw_error:
15076 }
15078 /*============================================================================*/
15079 /**
15080 * \brief Get deviation mode
15081 * \param demod instance of demodulator
15082 * \param pointer to enum drx_cfg_aud_deviation * \return int.
15083 *
15084 */
15085 static int
15087 {
15104 }
15119 }
15121 /* now update the modus register */
15127 }
15128 }
15129 /* store in drxk data struct */
15133 rw_error:
15135 }
15137 /*============================================================================*/
15138 /**
15139 * \brief Get Prescaler settings
15140 * \param demod instance of demodulator
15141 * \param pointer to struct drx_cfg_aud_prescale * \return int.
15142 *
15143 */
15144 static int
15145 aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_prescale *presc)
15146 {
15159 /* power up */
15165 }
15167 }
15169 /* read register data */
15174 }
15179 }
15181 /* calculate max FM deviation */
15188 }
15190 /* calculate NICAM gain from pre-scaler */
15191 /*
15192 nicam_gain = 20 * ( log10( preScaler / 16) )
15193 = ( 100log10( preScaler ) - 100log10( 16 ) ) / 5
15195 because log1_times100() cannot return negative numbers
15196 = ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) / 5
15198 for 0.1dB resolution:
15200 nicam_gain = 200 * ( log10( preScaler / 16) )
15201 = 2 * ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) )
15202 = ( 100log10( 10 * preScaler^2 ) - 100log10( 10 * 16^2 ) )
15204 */
15208 else
15209 presc->nicam_gain = (s16)(((s32)(log1_times100(10 * r_nicam_prescaler * r_nicam_prescaler)) - (s32)(log1_times100(10 * 16 * 16))));
15212 rw_error:
15214 }
15216 /*============================================================================*/
15217 /**
15218 * \brief Set Prescaler settings
15219 * \param demod instance of demodulator
15220 * \param pointer to struct drx_cfg_aud_prescale * \return int.
15221 *
15222 */
15223 static int
15224 aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_prescale *presc)
15225 {
15230 u16 nicam_prescaler;
15238 /* power up */
15244 }
15246 }
15248 /* setting of max FM deviation */
15254 /* NICAM Prescaler */
15256 /* calculation
15258 prescaler = 16 * 10^( gd_b / 20 )
15260 minval of gd_b = -20*log( 16 ) = -24.1dB
15262 negative numbers not allowed for d_b2lin_times100, so
15264 prescaler = 16 * 10^( gd_b / 20 )
15265 = 10^( (gd_b / 20) + log10(16) )
15266 = 10^( (gd_b + 20log10(16)) / 20 )
15268 in 0.1dB
15270 = 10^( G0.1dB + 200log10(16)) / 200 )
15272 */
15276 /* clip result */
15280 /* shift before writing to register */
15284 }
15285 /* end of setting NICAM Prescaler */
15291 }
15296 }
15301 rw_error:
15303 }
15305 /*============================================================================*/
15306 /**
15307 * \brief Beep
15308 * \param demod instance of demodulator
15309 * \param pointer to struct drx_aud_beep * \return int.
15310 *
15311 */
15313 {
15327 /* power up */
15333 }
15335 }
15358 }
15361 rw_error:
15363 }
15365 /*============================================================================*/
15366 /**
15367 * \brief Set an audio standard
15368 * \param demod instance of demodulator
15369 * \param pointer to enum drx_aud_standard * \return int.
15370 *
15371 */
15372 static int
15374 {
15393 /* power up */
15399 }
15401 }
15403 /* reset RDS data availability flag */
15406 /* we need to mute from here to avoid noise during standard switching */
15411 /* restore data structure from DRX ExtAttr, call volume first to mute */
15416 }
15421 }
15426 }
15431 }
15436 }
15441 }
15446 }
15448 /* get prescaler from presets */
15453 }
15459 }
15510 }
15513 /* we need the current standard here */
15518 if ((current_standard == DRX_STANDARD_PAL_SECAM_L) || (current_standard == DRX_STANDARD_PAL_SECAM_LP))
15520 else
15526 else
15529 }
15533 /* just get hardcoded deemphasis and activate here */
15536 else
15542 else
15550 }
15551 }
15557 }
15559 /**************************************************************************/
15560 /* NOT calling aud_ctrl_set_cfg_volume to avoid interfering standard */
15561 /* detection, need to keep things very minimal here, but keep audio */
15562 /* buffers intact */
15563 /**************************************************************************/
15567 AUD_DSP_WR_VOLUME_VOL_MAIN__B);
15572 }
15573 }
15575 /* write standard selected */
15579 rw_error:
15581 }
15583 /*============================================================================*/
15584 /**
15585 * \brief Get the current audio standard
15586 * \param demod instance of demodulator
15587 * \param pointer to enum drx_aud_standard * \return int.
15588 *
15589 */
15590 static int
15592 {
15604 /* power up */
15610 }
15612 }
15620 }
15622 /* return OK if the detection is not ready yet */
15626 }
15628 /* detection done, return correct standard */
15630 /* no standard detected */
15634 /* standard is KOREA(A2) */
15638 /* standard is EIA-J (Japan) */
15642 /* standard is BTSC-stereo */
15646 /* standard is BTSC-mono (SAP) */
15650 /* standard is FM radio */
15654 /* standard is BG FM */
15658 /* standard is DK-1 FM */
15662 /* standard is DK-2 FM */
15666 /* standard is DK-3 FM */
15670 /* standard is BG-NICAM FM */
15674 /* standard is L-NICAM AM */
15678 /* standard is I-NICAM FM */
15682 /* standard is DK-NICAM FM */
15688 }
15691 rw_error:
15694 }
15696 /*============================================================================*/
15697 /**
15698 * \brief Retreive lock status in case of FM standard
15699 * \param demod instance of demodulator
15700 * \param pointer to lock status
15701 * \return int.
15702 *
15703 */
15704 static int
15706 {
15710 /* Check detection of audio carriers */
15715 }
15717 /* locked if either primary or secondary carrier is detected */
15720 else
15725 rw_error:
15727 }
15729 /*============================================================================*/
15730 /**
15731 * \brief retreive signal quality in case of FM standard
15732 * \param demod instance of demodulator
15733 * \param pointer to signal quality
15734 * \return int.
15735 *
15736 * Only the quality indicator field is will be supplied.
15737 * This will either be 0% or 100%, nothing in between.
15738 *
15739 */
15740 static int
15742 {
15750 }
15753 else
15758 rw_error:
15760 }
15762 /*===========================================================================*/
15763 /*== END AUDIO DATAPATH FUNCTIONS ==*/
15764 /*===========================================================================*/
15766 /*============================================================================*/
15767 /*============================================================================*/
15768 /*== OOB DATAPATH FUNCTIONS ==*/
15769 /*============================================================================*/
15770 /*============================================================================*/
15771 /**
15772 * \fn int get_oob_lock_status ()
15773 * \brief Get OOB lock status.
15774 * \param dev_addr I2C address
15775 \ oob_lock OOB lock status.
15776 * \return int.
15777 *
15778 * Gets OOB lock status
15779 *
15780 */
15781 static int
15784 {
15788 u16 oob_lock_state;
15793 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
15802 }
15805 /* 0x00 NOT LOCKED */
15808 /* 0x40 DEMOD LOCKED */
15811 /* 0x80 DEMOD + OOB LOCKED (system lock) */
15819 /* 0xC0 NEVER LOCKED (system will never be able to lock to the signal) */
15821 }
15823 /* *oob_lock = scu_cmd.result[1]; */
15826 rw_error:
15828 }
15830 /**
15831 * \fn int get_oob_symbol_rate_offset ()
15832 * \brief Get OOB Symbol rate offset. Unit is [ppm]
15833 * \param dev_addr I2C address
15834 * \ Symbol Rate Offset OOB parameter.
15835 * \return int.
15836 *
15837 * Gets OOB frequency offset
15838 *
15839 */
15840 static int
15842 {
15843 /* offset = -{(timing_offset/2^19)*(symbol_rate/12,656250MHz)}*10^6 [ppm] */
15844 /* offset = -{(timing_offset/2^19)*(symbol_rate/12656250)}*10^6 [ppm] */
15845 /* after reconfiguration: */
15846 /* offset = -{(timing_offset*symbol_rate)/(2^19*12656250)}*10^6 [ppm] */
15847 /* shift symbol rate left by 5 without lossing information */
15848 /* offset = -{(timing_offset*(symbol_rate * 2^-5))/(2^14*12656250)}*10^6 [ppm]*/
15849 /* shift 10^6 left by 6 without loosing information */
15850 /* offset = -{(timing_offset*(symbol_rate * 2^-5))/(2^8*12656250)}*15625 [ppm]*/
15851 /* trim 12656250/15625 = 810 */
15852 /* offset = -{(timing_offset*(symbol_rate * 2^-5))/(2^8*810)} [ppm] */
15853 /* offset = -[(symbol_rate * 2^-5)*(timing_offset)/(2^8)]/810 [ppm] */
15863 /* read data rate */
15868 }
15886 }
15892 }
15893 /* convert data to positive and keep information about sign */
15897 else
15910 else
15916 rw_error:
15918 }
15920 /**
15921 * \fn int get_oob_freq_offset ()
15922 * \brief Get OOB lock status.
15923 * \param dev_addr I2C address
15924 * \ freq_offset OOB frequency offset.
15925 * \return int.
15926 *
15927 * Gets OOB frequency offset
15928 *
15929 */
15930 static int
15932 {
15948 /* check arguments */
15957 /* read sign (spectrum inversion) */
15962 }
15964 /* read frequency offset */
15969 }
15970 /* find COARSE frequency offset */
15971 /* coarse_freq_offset = ( 25312500Hz*FRQ_OFFSET >> 21 ); */
15975 }
15980 /* get value in KHz */
15982 /* read data rate */
15983 rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbol_rate_reg, 0);
15987 }
16005 }
16007 /* find FINE frequency offset */
16008 /* fine_freq_offset = ( (CORRECTION_VALUE*symbol_rate) >> 18 ); */
16013 }
16014 /* at least 5 MSB are 0 so first divide with 2^5 without information loss */
16021 }
16022 /* Left to divide with 8192 (2^13) */
16024 /* and to divide with 1000 to get KHz */
16029 else
16033 rw_error:
16035 }
16037 /**
16038 * \fn int get_oob_frequency ()
16039 * \brief Get OOB frequency (Unit:KHz).
16040 * \param dev_addr I2C address
16041 * \ frequency OOB frequency parameters.
16042 * \return int.
16043 *
16044 * Gets OOB frequency
16045 *
16046 */
16047 static int
16049 {
16060 rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data, 0);
16064 }
16072 }
16077 rw_error:
16079 }
16081 /**
16082 * \fn int get_oobmer ()
16083 * \brief Get OOB MER.
16084 * \param dev_addr I2C address
16085 \ MER OOB parameter in dB.
16086 * \return int.
16087 *
16088 * Gets OOB MER. Table for MER is in Programming guide.
16089 *
16090 */
16092 {
16097 /* READ MER */
16102 }
16223 }
16225 rw_error:
16227 }
16228 #endif
16230 /**
16231 * \fn int set_orx_nsu_aox()
16232 * \brief Configure OrxNsuAox for OOB
16233 * \param demod instance of demodulator.
16234 * \param active
16235 * \return int.
16236 */
16238 {
16243 /* Configure NSU_AOX */
16248 }
16250 data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));
16251 else
16252 data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);
16257 }
16260 rw_error:
16262 }
16264 /**
16265 * \fn int ctrl_set_oob()
16266 * \brief Set OOB channel to be used.
16267 * \param demod instance of demodulator
16268 * \param oob_param OOB parameters for channel setting.
16269 * \frequency should be in KHz
16270 * \return int.
16271 *
16272 * Accepts only. Returns error otherwise.
16273 * Demapper value is written after scu_command START
16274 * because START command causes COMM_EXEC transition
16275 * from 0 to 1 which causes all registers to be
16276 * overwritten with initial value
16277 *
16278 */
16280 /* Nyquist filter impulse response */
16281 #define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */
16282 #define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */
16283 #define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */
16285 /* Coefficients for the nyquist fitler (total: 27 taps) */
16286 #define NYQFILTERLEN 27
16288 #if 0
16290 {
16305 IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */
16306 };
16309 {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */
16310 {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */
16311 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
16312 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
16313 };
16314 u16 mode_index;
16320 /* Check parameters */
16322 /* power off oob module */
16332 }
16337 }
16342 }
16346 }
16353 {
16360 trk_filter_value =
16365 }
16367 /*********/
16368 /* Stop */
16369 /*********/
16374 }
16384 }
16385 /*********/
16386 /* Reset */
16387 /*********/
16397 }
16398 /***********/
16399 /* SET_ENV */
16400 /***********/
16401 /* set frequency, spectrum inversion and data rate */
16405 /* 1-data rate;2-frequency */
16409 /* signal is transmitted inverted */
16411 /* and tuner is not mirroring the signal */
16413 /* or */
16414 /* signal is transmitted noninverted */
16416 /* and tuner is mirroring the signal */
16418 )
16420 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
16421 else
16423 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC;
16427 /* signal is transmitted inverted */
16429 /* and tuner is not mirroring the signal */
16431 /* or */
16432 /* signal is transmitted noninverted */
16434 /* and tuner is mirroring the signal */
16436 )
16438 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
16439 else
16441 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC;
16446 /* signal is transmitted inverted */
16448 /* and tuner is not mirroring the signal */
16450 /* or */
16451 /* signal is transmitted noninverted */
16453 /* and tuner is mirroring the signal */
16455 )
16457 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
16458 else
16460 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC;
16462 }
16473 }
16480 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
16484 }
16485 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
16489 }
16500 }
16505 }
16510 }
16512 /* ddc */
16517 }
16519 /* nsu */
16524 }
16526 /* initialization for target mode */
16527 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
16531 }
16532 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
16536 }
16538 /* Reset bits for timing and freq. recovery */
16543 }
16548 }
16553 }
16558 }
16560 /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */
16565 }
16570 }
16575 }
16580 }
16585 }
16587 /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */
16592 }
16597 }
16602 }
16607 }
16612 }
16614 /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */
16619 }
16624 }
16629 }
16634 }
16639 }
16641 /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */
16646 }
16651 }
16656 }
16661 }
16666 }
16668 /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */
16673 }
16678 }
16683 }
16688 }
16693 }
16695 /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */
16700 }
16705 }
16710 }
16715 }
16720 }
16722 /* PRE-Filter coefficients (PFI) */
16723 rc = DRXJ_DAP.write_block_func(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
16727 }
16732 }
16734 /* NYQUIST-Filter coefficients (NYQ) */
16740 }
16741 rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
16745 }
16746 }
16751 }
16756 }
16757 /*********/
16758 /* Start */
16759 /*********/
16769 }
16775 }
16780 }
16785 rw_error:
16787 }
16789 /**
16790 * \fn int ctrl_get_oob()
16791 * \brief Set modulation standard to be used.
16792 * \param demod instance of demodulator
16793 * \param oob_status OOB status parameters.
16794 * \return int.
16795 */
16796 static int
16798 {
16807 /* check arguments */
16818 }
16823 }
16828 }
16833 }
16838 }
16844 }
16849 }
16854 }
16859 }
16862 rw_error:
16864 }
16866 /**
16867 * \fn int ctrl_set_cfg_oob_pre_saw()
16868 * \brief Configure PreSAW treshold value
16869 * \param cfg_data Pointer to configuration parameter
16870 * \return Error code
16871 */
16872 static int
16874 {
16889 }
16892 rw_error:
16894 }
16896 /**
16897 * \fn int ctrl_get_cfg_oob_pre_saw()
16898 * \brief Configure PreSAW treshold value
16899 * \param cfg_data Pointer to configuration parameter
16900 * \return Error code
16901 */
16902 static int
16904 {
16915 }
16917 /**
16918 * \fn int ctrl_set_cfg_oob_lo_power()
16919 * \brief Configure LO Power value
16920 * \param cfg_data Pointer to enum drxj_cfg_oob_lo_power ** \return Error code
16921 */
16922 static int
16923 ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo_power *cfg_data)
16924 {
16939 }
16942 rw_error:
16944 }
16946 /**
16947 * \fn int ctrl_get_cfg_oob_lo_power()
16948 * \brief Configure LO Power value
16949 * \param cfg_data Pointer to enum drxj_cfg_oob_lo_power ** \return Error code
16950 */
16951 static int
16952 ctrl_get_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo_power *cfg_data)
16953 {
16964 }
16965 #endif
16966 /*============================================================================*/
16967 /*== END OOB DATAPATH FUNCTIONS ==*/
16968 /*============================================================================*/
16970 /*=============================================================================
16971 ===== MC command related functions ==========================================
16972 ===========================================================================*/
16974 /*=============================================================================
16975 ===== ctrl_set_channel() ==========================================================
16976 ===========================================================================*/
16977 /**
16978 * \fn int ctrl_set_channel()
16979 * \brief Select a new transmission channel.
16980 * \param demod instance of demod.
16981 * \param channel Pointer to channel data.
16982 * \return int.
16983 *
16984 * In case the tuner module is not used and in case of NTSC/FM the pogrammer
16985 * must tune the tuner to the centre frequency of the NTSC/FM channel.
16986 *
16987 */
16988 static int
16990 {
16998 #ifndef DRXJ_VSB_ONLY
17003 #endif
17004 /*== check arguments ======================================================*/
17013 /* check valid standards */
17016 #ifndef DRXJ_VSB_ONLY
17021 #if 0
17029 #endif
17034 }
17036 /* check bandwidth QAM annex B, NTSC and 8VSB */
17049 }
17050 }
17051 #if 0
17056 /* ok */
17062 }
17063 }
17064 /* check bandwidth PAL/SECAM */
17079 }
17080 }
17081 #endif
17083 /* For QAM annex A and annex C:
17084 -check symbolrate and constellation
17085 -derive bandwidth from symbolrate (input bandwidth is ignored)
17086 */
17087 #ifndef DRXJ_VSB_ONLY
17096 /* config SMA_TX pin to SAW switch mode */
17101 }
17106 }
17118 bandwidth++;
17127 }
17131 }
17132 }
17134 /* For QAM annex B:
17135 -check constellation
17136 */
17145 }
17170 }
17171 }
17174 /* SAW SW, user UIO is used for switchable SAW */
17190 }
17196 }
17197 }
17203 }
17208 /*== Setup demod for specific standard ====================================*/
17213 else
17219 }
17224 }
17226 #if 0
17236 else
17242 }
17244 #endif
17245 #ifndef DRXJ_VSB_ONLY
17253 }
17255 #endif
17259 }
17261 /* flag the packet error counter reset */
17265 rw_error:
17267 }
17269 #if 0
17270 /*=============================================================================
17271 ===== ctrl_get_channel() ==========================================================
17272 ===========================================================================*/
17273 /**
17274 * \fn int ctrl_get_channel()
17275 * \brief Retreive parameters of current transmission channel.
17276 * \param demod Pointer to demod instance.
17277 * \param channel Pointer to channel data.
17278 * \return int.
17279 */
17280 static int
17282 {
17293 #ifndef DRXJ_VSB_ONLY
17296 #endif
17298 /* check arguments */
17307 /* initialize channel fields */
17321 /* channel->interleaver = DRX_INTERLEAVER_UNKNOWN;*/
17326 /* check lock status */
17331 }
17337 }
17346 /* get the channel frequency */
17351 }
17353 /* get the channel constellation */
17356 #ifndef DRXJ_VSB_ONLY
17360 {
17361 /* get the channel frequency */
17366 }
17372 /* annex A & C */
17379 bandwidth_temp =
17384 bandwidth++;
17388 DRX_BANDWIDTH_6MHZ;
17392 DRX_BANDWIDTH_7MHZ;
17395 DRX_BANDWIDTH_8MHZ;
17396 }
17399 {
17404 SCU_RAM_COMMAND_STANDARD_QAM |
17405 SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM;
17414 }
17419 }
17424 DRX_CONSTELLATION_QAM256;
17428 DRX_CONSTELLATION_QAM128;
17432 DRX_CONSTELLATION_QAM64;
17436 DRX_CONSTELLATION_QAM32;
17440 DRX_CONSTELLATION_QAM16;
17444 DRX_CONSTELLATION_UNKNOWN;
17446 }
17447 }
17449 #endif
17461 }
17470 }
17471 /* if ( lock_status == DRX_LOCKED ) */
17473 rw_error:
17475 }
17476 #endif
17478 /*=============================================================================
17479 ===== SigQuality() ==========================================================
17480 ===========================================================================*/
17482 static u16
17484 {
17495 else
17499 }
17502 }
17504 /**
17505 * \fn int ctrl_sig_quality()
17506 * \brief Retreive signal quality form device.
17507 * \param devmod Pointer to demodulator instance.
17508 * \param sig_quality Pointer to signal quality data.
17509 * \return int.
17510 * \retval 0 sig_quality contains valid data.
17511 * \retval -EINVAL sig_quality is NULL.
17512 * \retval -EIO Erroneous data, sig_quality contains invalid data.
17514 */
17515 static int
17517 {
17527 /* Check arguments */
17534 /* get basic information */
17540 }
17543 #ifdef DRXJ_SIGNAL_ACCUM_ERR
17548 }
17549 #else
17554 }
17555 #endif
17561 /* PostViterbi is compute in steps of 10^(-6) */
17566 }
17571 }
17576 }
17577 }
17585 max_mer);
17587 #ifndef DRXJ_VSB_ONLY
17595 }
17616 }
17617 }
17636 }
17639 max_mer);
17641 #endif
17642 #if 0
17653 }
17660 }
17662 #endif
17665 }
17668 rw_error:
17670 }
17672 /*============================================================================*/
17674 /**
17675 * \fn int ctrl_lock_status()
17676 * \brief Retreive lock status .
17677 * \param dev_addr Pointer to demodulator device address.
17678 * \param lock_stat Pointer to lock status structure.
17679 * \return int.
17680 *
17681 */
17682 static int
17684 {
17692 /* *result */ NULL
17693 };
17698 /* check arguments */
17708 /* define the SCU command code */
17712 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
17715 #ifndef DRXJ_VSB_ONLY
17720 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
17722 #endif
17723 #if 0
17731 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
17735 #endif
17739 }
17741 /* define the SCU command paramters and execute the command */
17750 }
17752 /* set the lock status */
17754 /* 0x0000 NOT LOCKED */
17759 SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) {
17760 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
17763 /* 0xC000 NEVER LOCKED */
17764 /* (system will never be able to lock to the signal) */
17766 }
17769 rw_error:
17771 }
17773 /*============================================================================*/
17775 #if 0
17776 /**
17777 * \fn int ctrl_constel()
17778 * \brief Retreive a constellation point via I2C.
17779 * \param demod Pointer to demodulator instance.
17780 * \param complex_nr Pointer to the structure in which to store the
17781 constellation point.
17782 * \return int.
17783 */
17784 static int
17786 {
17789 /**< active standard */
17791 /* check arguments */
17795 /* read device info */
17798 /* Read constellation point */
17805 }
17807 #ifndef DRXJ_VSB_ONLY
17815 }
17817 #endif
17821 }
17824 rw_error:
17826 }
17827 #endif
17829 /*============================================================================*/
17831 /**
17832 * \fn int ctrl_set_standard()
17833 * \brief Set modulation standard to be used.
17834 * \param standard Modulation standard.
17835 * \return int.
17836 *
17837 * Setup stuff for the desired demodulation standard.
17838 * Disable and power down the previous selected demodulation standard
17839 *
17840 */
17841 static int
17843 {
17848 /* check arguments */
17855 /*
17856 Stop and power down previous standard
17857 */
17859 #ifndef DRXJ_VSB_ONLY
17867 }
17869 #endif
17875 }
17877 #if 0
17889 }
17891 #endif
17893 /* Do nothing */
17898 }
17900 /*
17901 Initialize channel independent registers
17902 Power up new standard
17903 */
17907 #ifndef DRXJ_VSB_ONLY
17912 u16 dummy;
17917 }
17920 #endif
17926 }
17928 #if 0
17940 }
17945 }
17947 #endif
17952 }
17955 rw_error:
17956 /* Don't know what the standard is now ... try again */
17959 }
17961 #if 0
17962 /*============================================================================*/
17964 /**
17965 * \fn int ctrl_get_standard()
17966 * \brief Get modulation standard currently used to demodulate.
17967 * \param standard Modulation standard.
17968 * \return int.
17969 *
17970 * Returns 8VSB, NTSC, QAM only.
17971 *
17972 */
17973 static int
17975 {
17980 /* check arguments */
17986 u16 dummy;
17991 }
17995 rw_error:
17997 }
17999 /*============================================================================*/
18001 /**
18002 * \fn int ctrl_get_cfg_symbol_clock_offset()
18003 * \brief Get frequency offsets of STR.
18004 * \param pointer to s32.
18005 * \return int.
18006 *
18007 */
18008 static int
18010 {
18015 /* check arguments */
18024 #ifndef DRXJ_VSB_ONLY
18028 #endif
18033 }
18039 }
18042 rw_error:
18044 }
18045 #endif
18047 /*============================================================================*/
18050 {
18051 /* Initialize default AFE configuartion for QAM */
18053 /* IF AGC off, PGA active */
18054 #ifndef DRXJ_VSB_ONLY
18058 #endif
18063 /* IF AGC on, PGA not active */
18064 #ifndef DRXJ_VSB_ONLY
18072 #endif
18080 }
18081 /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */
18082 /* mc has not used them */
18083 #ifndef DRXJ_VSB_ONLY
18094 #endif
18095 /* Initialize default AFE configuartion for VSB */
18107 #if 0
18108 /* Initialize default AFE configuartion for ATV */
18121 #endif
18122 }
18124 /**
18125 * \fn int ctrl_power_mode()
18126 * \brief Set the power mode of the device to the specified power mode
18127 * \param demod Pointer to demodulator instance.
18128 * \param mode Pointer to new power mode.
18129 * \return int.
18130 * \retval 0 Success
18131 * \retval -EIO I2C error or other failure
18132 * \retval -EINVAL Invalid mode argument.
18133 *
18134 *
18135 */
18136 static int
18138 {
18149 /* Check arguments */
18153 /* If already in requested power mode, do nothing */
18172 /* Unknow sleep mode */
18175 }
18177 /* Check if device needs to be powered up */
18183 }
18184 }
18187 /* Restore analog & pin configuartion */
18189 /* Initialize default AFE configuartion for VSB */
18192 /* Power down to requested mode */
18193 /* Backup some register settings */
18194 /* Set pins with possible pull-ups connected to them in input mode */
18195 /* Analog power down */
18196 /* ADC power down */
18197 /* Power down device */
18198 /* stop all comm_exec */
18199 /*
18200 Stop and power down previous standard
18201 */
18211 }
18218 }
18231 }
18234 /* Do nothing */
18239 }
18246 }
18251 }
18253 /* Initialize HI, wakeup key especially before put IC to sleep */
18258 }
18265 }
18266 }
18268 }
18273 rw_error:
18275 }
18277 #if 0
18278 /*============================================================================*/
18280 /**
18281 * \fn int ctrl_probe_device()
18282 * \brief Probe device, check if it is present
18283 * \param demod Pointer to demodulator instance.
18284 * \return int.
18285 * \retval 0 a drx39xxj device has been detected.
18286 * \retval -EIO no drx39xxj device detected.
18287 *
18288 * This funtion can be caled before open() and after close().
18289 *
18290 */
18293 {
18309 /* Remeber original power mode */
18317 }
18320 /* Wake-up device, feedback from device */
18325 }
18326 }
18327 /* Initialize HI, wakeup key especially */
18332 }
18334 /* Check device id */
18339 }
18352 /* ok , do nothing */
18357 }
18359 /* Device was not opened, return to orginal powermode,
18360 feedback from device */
18365 }
18367 /* dummy read to make this function fail in case device
18368 suddenly disappears after a succesful drx_open */
18370 u16 dummy;
18375 }
18377 }
18381 rw_error:
18384 }
18385 #endif
18387 /*============================================================================*/
18388 /*== CTRL Set/Get Config related functions ===================================*/
18389 /*============================================================================*/
18391 #if 0
18392 /*===== SigStrength() =========================================================*/
18393 /**
18394 * \fn int ctrl_sig_strength()
18395 * \brief Retrieve signal strength.
18396 * \param devmod Pointer to demodulator instance.
18397 * \param sig_quality Pointer to signal strength data; range 0, .. , 100.
18398 * \return int.
18399 * \retval 0 sig_strength contains valid data.
18400 * \retval -EINVAL sig_strength is NULL.
18401 * \retval -EIO Erroneous data, sig_strength contains invalid data.
18403 */
18404 static int
18406 {
18411 /* Check arguments */
18419 /* Signal strength indication for each standard */
18422 #ifndef DRXJ_VSB_ONLY
18426 #endif
18431 }
18444 }
18449 }
18451 /* TODO */
18452 /* find out if signal strength is calculated in the same way for all standards */
18454 rw_error:
18456 }
18458 /*============================================================================*/
18459 /**
18460 * \fn int ctrl_get_cfg_oob_misc()
18461 * \brief Get current state information of OOB.
18462 * \param pointer to struct drxj_cfg_oob_misc.
18463 * \return int.
18464 *
18465 */
18466 static int
18468 {
18477 /* check arguments */
18483 /* TODO */
18484 /* check if the same registers are used for all standards (QAM/VSB/ATV) */
18489 }
18494 }
18499 }
18510 }
18523 }
18527 rw_error:
18529 }
18531 /**
18532 * \fn int ctrl_get_cfg_vsb_misc()
18533 * \brief Get current state information of OOB.
18534 * \param pointer to struct drxj_cfg_oob_misc.
18535 * \return int.
18536 *
18537 */
18538 static int
18540 {
18544 /* check arguments */
18554 }
18557 rw_error:
18559 }
18561 /*============================================================================*/
18563 /**
18564 * \fn int ctrl_set_cfg_agc_if()
18565 * \brief Set IF AGC.
18566 * \param demod demod instance
18567 * \param agc_settings If agc configuration
18568 * \return int.
18569 *
18570 * Check arguments
18571 * Dispatch handling to standard specific function.
18572 *
18573 */
18574 static int
18576 {
18577 /* check arguments */
18588 }
18590 /* Distpatch */
18593 #ifndef DRXJ_VSB_ONLY
18597 #endif
18598 #if 0
18606 #endif
18611 }
18614 }
18616 /*============================================================================*/
18618 /**
18619 * \fn int ctrl_get_cfg_agc_if()
18620 * \brief Retrieve IF AGC settings.
18621 * \param demod demod instance
18622 * \param agc_settings If agc configuration
18623 * \return int.
18624 *
18625 * Check arguments
18626 * Dispatch handling to standard specific function.
18627 *
18628 */
18629 static int
18631 {
18632 /* check arguments */
18636 /* Distpatch */
18639 #ifndef DRXJ_VSB_ONLY
18643 #endif
18644 #if 0
18652 #endif
18657 }
18660 }
18662 /*============================================================================*/
18664 /**
18665 * \fn int ctrl_set_cfg_agc_rf()
18666 * \brief Set RF AGC.
18667 * \param demod demod instance
18668 * \param agc_settings rf agc configuration
18669 * \return int.
18670 *
18671 * Check arguments
18672 * Dispatch handling to standard specific function.
18673 *
18674 */
18675 static int
18677 {
18678 /* check arguments */
18689 }
18691 /* Distpatch */
18694 #ifndef DRXJ_VSB_ONLY
18698 #endif
18710 }
18713 }
18715 /*============================================================================*/
18717 /**
18718 * \fn int ctrl_get_cfg_agc_rf()
18719 * \brief Retrieve RF AGC settings.
18720 * \param demod demod instance
18721 * \param agc_settings Rf agc configuration
18722 * \return int.
18723 *
18724 * Check arguments
18725 * Dispatch handling to standard specific function.
18726 *
18727 */
18728 static int
18730 {
18731 /* check arguments */
18735 /* Distpatch */
18738 #ifndef DRXJ_VSB_ONLY
18742 #endif
18754 }
18757 }
18759 /*============================================================================*/
18761 /**
18762 * \fn int ctrl_get_cfg_agc_internal()
18763 * \brief Retrieve internal AGC value.
18764 * \param demod demod instance
18765 * \param u16
18766 * \return int.
18767 *
18768 * Check arguments
18769 * Dispatch handling to standard specific function.
18770 *
18771 */
18772 static int
18774 {
18784 /* check arguments */
18794 }
18798 }
18800 /* Distpatch */
18805 #ifndef DRXJ_VSB_ONLY
18821 }
18823 #endif
18826 }
18832 }
18837 }
18842 }
18843 /* IQM_CF_PWR_CORRECTION_dB = 3;
18844 P5dB =10*log10(IQM_CF_POW)+12-6*9-IQM_CF_PWR_CORRECTION_dB; */
18845 /* P4dB = P5dB -20*log10(IQM_CF_AMP)-6*10
18846 -IQM_CF_Gain_dB-18+6*(27-IQM_CF_SCALE_SH*2-10)
18847 +6*7+10*log10(1+0.115/4); */
18848 /* PadcdB = P4dB +3 -6 +60; dBmV */
18854 rw_error:
18856 }
18858 /*============================================================================*/
18859 #endif
18861 /**
18862 * \fn int ctrl_set_cfg_pre_saw()
18863 * \brief Set Pre-saw reference.
18864 * \param demod demod instance
18865 * \param u16 *
18866 * \return int.
18867 *
18868 * Check arguments
18869 * Dispatch handling to standard specific function.
18870 *
18871 */
18872 static int
18874 {
18882 /* check arguments */
18884 ) {
18886 }
18888 /* Only if standard is currently active */
18898 }
18899 }
18901 /* Store pre-saw settings */
18906 #ifndef DRXJ_VSB_ONLY
18912 #endif
18913 #if 0
18923 #endif
18926 }
18929 rw_error:
18931 }
18933 /*============================================================================*/
18935 /**
18936 * \fn int ctrl_set_cfg_afe_gain()
18937 * \brief Set AFE Gain.
18938 * \param demod demod instance
18939 * \param u16 *
18940 * \return int.
18941 *
18942 * Check arguments
18943 * Dispatch handling to standard specific function.
18944 *
18945 */
18946 static int
18948 {
18954 /* check arguments */
18963 #ifndef DRXJ_VSB_ONLY
18967 #endif
18968 /* Do nothing */
18972 }
18974 /* TODO PGA gain is also written by microcode (at least by QAM and VSB)
18975 So I (PJ) think interface requires choice between auto, user mode */
18981 else
18984 /* Only if standard is currently active */
18990 }
18991 }
18993 /* Store AFE Gain settings */
18998 #ifndef DRXJ_VSB_ONLY
19004 #endif
19007 }
19010 rw_error:
19012 }
19014 /*============================================================================*/
19016 #if 0
19017 /**
19018 * \fn int ctrl_get_cfg_pre_saw()
19019 * \brief Get Pre-saw reference setting.
19020 * \param demod demod instance
19021 * \param u16 *
19022 * \return int.
19023 *
19024 * Check arguments
19025 * Dispatch handling to standard specific function.
19026 *
19027 */
19028 static int
19030 {
19033 /* check arguments */
19043 #ifndef DRXJ_VSB_ONLY
19049 #endif
19066 }
19069 }
19071 /*============================================================================*/
19073 /**
19074 * \fn int ctrl_get_cfg_afe_gain()
19075 * \brief Get AFE Gain.
19076 * \param demod demod instance
19077 * \param u16 *
19078 * \return int.
19079 *
19080 * Check arguments
19081 * Dispatch handling to standard specific function.
19082 *
19083 */
19084 static int
19086 {
19089 /* check arguments */
19099 #ifndef DRXJ_VSB_ONLY
19105 #endif
19108 }
19111 }
19113 /*============================================================================*/
19115 /**
19116 * \fn int ctrl_get_fec_meas_seq_count()
19117 * \brief Get FEC measurement sequnce number.
19118 * \param demod demod instance
19119 * \param u16 *
19120 * \return int.
19121 *
19122 * Check arguments
19123 * Dispatch handling to standard specific function.
19124 *
19125 */
19126 static int
19128 {
19130 /* check arguments */
19134 rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, fec_meas_seq_count, 0);
19138 }
19141 rw_error:
19143 }
19145 /*============================================================================*/
19147 /**
19148 * \fn int ctrl_get_accum_cr_rs_cw_err()
19149 * \brief Get accumulative corrected RS codeword number.
19150 * \param demod demod instance
19151 * \param u32 *
19152 * \return int.
19153 *
19154 * Check arguments
19155 * Dispatch handling to standard specific function.
19156 *
19157 */
19158 static int
19160 {
19165 rc = DRXJ_DAP.read_reg32func(demod->my_i2c_dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accum_cr_rs_cw_err, 0);
19169 }
19172 rw_error:
19174 }
19176 /**
19177 * \fn int ctrl_set_cfg()
19178 * \brief Set 'some' configuration of the device.
19179 * \param devmod Pointer to demodulator instance.
19180 * \param config Pointer to configuration parameters (type and data).
19181 * \return int.
19183 */
19185 {
19192 u16 dummy;
19197 }
19203 cfg_data);
19219 cfg_data));
19222 #if 0
19228 cfg_data));
19235 cfg_data);
19239 cfg_data);
19240 #endif
19245 #ifndef DRXJ_EXCLUDE_AUDIO
19249 cfg_data);
19253 cfg_data);
19263 cfg_data);
19267 cfg_data);
19271 cfg_data);
19278 cfg_data);
19280 #endif
19283 }
19286 rw_error:
19288 }
19290 /*============================================================================*/
19292 /**
19293 * \fn int ctrl_get_cfg()
19294 * \brief Get 'some' configuration of the device.
19295 * \param devmod Pointer to demodulator instance.
19296 * \param config Pointer to configuration parameters (type and data).
19297 * \return int.
19298 */
19301 {
19308 u16 dummy;
19313 }
19320 cfg_data);
19345 #if 0
19354 cfg_data));
19358 cfg_data);
19365 cfg_data);
19369 cfg_data);
19370 #endif
19378 #ifndef DRXJ_EXCLUDE_AUDIO
19382 cfg_data);
19386 cfg_data);
19394 cfg_data);
19398 cfg_data);
19402 cfg_data);
19406 cfg_data);
19410 cfg_data);
19417 cfg_data);
19418 #endif
19422 }
19425 rw_error:
19427 }
19428 #endif
19430 /*=============================================================================
19431 ===== EXPORTED FUNCTIONS ====================================================*/
19437 /**
19438 * \fn drxj_open()
19439 * \brief Open the demod instance, configure device, configure drxdriver
19440 * \return Status_t Return status.
19441 *
19442 * drxj_open() can be called with a NULL ucode image => no ucode upload.
19443 * This means that drxj_open() must NOT contain SCU commands or, in general,
19444 * rely on SCU or AUD ucode to be present.
19445 *
19446 */
19449 {
19465 }
19467 /* Check arguments */
19479 }
19482 /* has to be in front of setIqmAf and setOrxNsuAox */
19487 }
19489 /* Soft reset of sys- and osc-clockdomain */
19490 rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_SOFT_RST__A, (SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
19494 }
19499 }
19502 /* TODO first make sure that everything keeps working before enabling this */
19503 /* PowerDownAnalogBlocks() */
19504 rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
19508 }
19514 }
19519 }
19525 }
19527 /* disable mpegoutput pins */
19533 }
19534 /* Stop AUD Inform SetAudio it will need to do all setting */
19539 }
19540 /* Stop SCU */
19545 }
19547 /* Upload microcode */
19549 /* Dirty trick to use common ucode upload & verify,
19550 pretend device is already open */
19557 }
19563 }
19568 rc);
19570 }
19571 }
19573 }
19575 /* Run SCU for a little while to initialize microcode version numbers */
19580 }
19582 /* Initialize scan timeout */
19593 }
19595 /* Stamp driver version number in SCU data RAM in BCD code
19596 Done to enable field application engineers to retreive drxdriver version
19597 via I2C from SCU RAM
19598 */
19614 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
19618 }
19619 rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
19623 }
19625 /* refresh the audio data structure with default */
19630 rw_error:
19633 }
19635 /*============================================================================*/
19636 /**
19637 * \fn drxj_close()
19638 * \brief Close the demod instance, power down the device
19639 * \return Status_t Return status.
19640 *
19641 */
19643 {
19654 }
19656 /* power up */
19661 }
19667 }
19673 }
19678 rw_error:
19682 }
19684 /*
19685 * Microcode related functions
19686 */
19688 /**
19689 * drx_u_code_compute_crc - Compute CRC of block of microcode data.
19690 * @block_data: Pointer to microcode data.
19691 * @nr_words: Size of microcode block (number of 16 bits words).
19692 *
19693 * returns The computed CRC residue.
19694 */
19696 {
19709 }
19710 i++;
19712 }
19714 }
19716 /**
19717 * drx_check_firmware - checks if the loaded firmware is valid
19718 *
19719 * @demod: demod structure
19720 * @mc_data: pointer to the start of the firmware
19721 * @size: firmware size
19722 */
19725 {
19732 /*
19733 * Scan microcode blocks first for version info
19734 * and firmware check
19735 */
19737 /* Clear version block */
19747 /* Process block header */
19763 u16 auxtype;
19770 /* Aux block. Check type */
19790 }
19795 }
19797 eof:
19800 }
19802 /**
19803 * drx_ctrl_u_code - Handle microcode upload or verify.
19804 * @dev_addr: Address of device.
19805 * @mc_info: Pointer to information about microcode data.
19806 * @action: Either UCODE_UPLOAD or UCODE_VERIFY
19807 *
19808 * This function returns:
19809 * 0:
19810 * - In case of UCODE_UPLOAD: code is successfully uploaded.
19811 * - In case of UCODE_VERIFY: image on device is equal to
19812 * image provided to this control function.
19813 * -EIO:
19814 * - In case of UCODE_UPLOAD: I2C error.
19815 * - In case of UCODE_VERIFY: I2C error or image on device
19816 * is not equal to image provided to this control function.
19817 * -EINVAL:
19818 * - Invalid arguments.
19819 * - Provided image is corrupt
19820 */
19824 {
19835 /* Check arguments */
19846 }
19853 }
19857 }
19863 /* Check data */
19873 }
19882 }
19884 /* Process microcode blocks */
19889 /* Process block header */
19903 /* Check block header on:
19904 - data larger than 64Kb
19905 - if CRC enabled check CRC
19906 */
19910 ) {
19911 /* Wrong data ! */
19915 }
19922 /* Perform the desired action */
19927 mc_block_nr_bytes,
19933 }
19946 else
19951 curr_addr,
19958 }
19961 bytes_to_comp);
19967 }
19972 }
19974 }
19979 }
19981 }
19985 release:
19990 }
19992 /*
19993 * The Linux DVB Driver for Micronas DRX39xx family (drx3933j)
19994 *
19995 * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
19996 */
19999 {
20007 else
20014 }
20018 }
20021 {
20033 }
20057 | FE_HAS_CARRIER
20062 }
20065 }
20068 {
20079 }
20083 }
20087 {
20098 }
20100 /* 1-100% scaled to 0-65535 */
20103 }
20106 {
20117 }
20121 }
20124 {
20135 }
20139 }
20142 {
20143 #ifdef DJH_DEBUG
20145 #endif
20168 /* frame mode */ DRX_FRAMEMODE_UNKNOWN
20169 };
20172 /* Bring the demod out of sleep */
20176 u32 int_freq;
20181 /* Set tuner to desired frequency and standard */
20184 /* Use the tuner's IF */
20188 }
20192 }
20211 }
20215 }
20218 /* Set the standard (will be powered up if necessary */
20222 result);
20224 }
20227 }
20229 /* set channel parameters */
20235 /* program channel */
20240 }
20241 /* Just for giggles, let's shut off the LNA again.... */
20248 }
20249 #ifdef DJH_DEBUG
20251 fe_status_t status;
20256 }
20257 #endif
20260 }
20263 {
20264 /* power-down the demodulator */
20266 }
20269 {
20275 #ifdef DJH_DEBUG
20278 #endif
20282 else
20286 /* We're already in the desired state */
20288 }
20293 result);
20297 }
20299 }
20302 {
20303 /* Bring the demod out of sleep */
20307 }
20311 {
20314 }
20317 {
20328 }
20333 {
20344 /* allocate memory for the internal state */
20370 /* setup the state */
20374 /* setup the demod data */
20391 }
20393 /* Turn off the LNA */
20396 /* Configure user-I/O #3: enable read/write */
20401 }
20409 }
20411 /* create dvb_frontend */
20418 error:
20426 }
20437 },
20450 };