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net: ethernet: mediatek: fix fails from TX housekeeping due to incorrect port setup
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
blob7fc2ff0c5bf0b9cda00b881fe7578128569e234c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/if_vlan.h>
22 #include <linux/reset.h>
23 #include <linux/tcp.h>
24
25 #include "mtk_eth_soc.h"
26
27 static int mtk_msg_level = -1;
28 module_param_named(msg_level, mtk_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34 /* strings used by ethtool */
35 static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38 } mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51 };
52
53 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54 {
55 __raw_writel(val, eth->base + reg);
56 }
57
58 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59 {
60 return __raw_readl(eth->base + reg);
61 }
62
63 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64 {
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77 }
78
79 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
81 {
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96 }
97
98 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
99 {
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116 }
117
118 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120 {
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124 }
125
126 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127 {
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131 }
132
133 static void mtk_phy_link_adjust(struct net_device *dev)
134 {
135 struct mtk_mac *mac = netdev_priv(dev);
136 u16 lcl_adv = 0, rmt_adv = 0;
137 u8 flowctrl;
138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
141 MAC_MCR_BACKPR_EN;
142
143 switch (mac->phy_dev->speed) {
144 case SPEED_1000:
145 mcr |= MAC_MCR_SPEED_1000;
146 break;
147 case SPEED_100:
148 mcr |= MAC_MCR_SPEED_100;
149 break;
150 };
151
152 if (mac->phy_dev->link)
153 mcr |= MAC_MCR_FORCE_LINK;
154
155 if (mac->phy_dev->duplex) {
156 mcr |= MAC_MCR_FORCE_DPX;
157
158 if (mac->phy_dev->pause)
159 rmt_adv = LPA_PAUSE_CAP;
160 if (mac->phy_dev->asym_pause)
161 rmt_adv |= LPA_PAUSE_ASYM;
162
163 if (mac->phy_dev->advertising & ADVERTISED_Pause)
164 lcl_adv |= ADVERTISE_PAUSE_CAP;
165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
166 lcl_adv |= ADVERTISE_PAUSE_ASYM;
167
168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
169
170 if (flowctrl & FLOW_CTRL_TX)
171 mcr |= MAC_MCR_FORCE_TX_FC;
172 if (flowctrl & FLOW_CTRL_RX)
173 mcr |= MAC_MCR_FORCE_RX_FC;
174
175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
178 }
179
180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
181
182 if (mac->phy_dev->link)
183 netif_carrier_on(dev);
184 else
185 netif_carrier_off(dev);
186 }
187
188 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
189 struct device_node *phy_node)
190 {
191 const __be32 *_addr = NULL;
192 struct phy_device *phydev;
193 int phy_mode, addr;
194
195 _addr = of_get_property(phy_node, "reg", NULL);
196
197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
198 pr_err("%s: invalid phy address\n", phy_node->name);
199 return -EINVAL;
200 }
201 addr = be32_to_cpu(*_addr);
202 phy_mode = of_get_phy_mode(phy_node);
203 if (phy_mode < 0) {
204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
205 return -EINVAL;
206 }
207
208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
209 mtk_phy_link_adjust, 0, phy_mode);
210 if (!phydev) {
211 dev_err(eth->dev, "could not connect to PHY\n");
212 return -ENODEV;
213 }
214
215 dev_info(eth->dev,
216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
217 mac->id, phydev_name(phydev), phydev->phy_id,
218 phydev->drv->name);
219
220 mac->phy_dev = phydev;
221
222 return 0;
223 }
224
225 static int mtk_phy_connect(struct mtk_mac *mac)
226 {
227 struct mtk_eth *eth = mac->hw;
228 struct device_node *np;
229 u32 val, ge_mode;
230
231 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
232 if (!np && of_phy_is_fixed_link(mac->of_node))
233 if (!of_phy_register_fixed_link(mac->of_node))
234 np = of_node_get(mac->of_node);
235 if (!np)
236 return -ENODEV;
237
238 switch (of_get_phy_mode(np)) {
239 case PHY_INTERFACE_MODE_RGMII_TXID:
240 case PHY_INTERFACE_MODE_RGMII_RXID:
241 case PHY_INTERFACE_MODE_RGMII_ID:
242 case PHY_INTERFACE_MODE_RGMII:
243 ge_mode = 0;
244 break;
245 case PHY_INTERFACE_MODE_MII:
246 ge_mode = 1;
247 break;
248 case PHY_INTERFACE_MODE_REVMII:
249 ge_mode = 2;
250 break;
251 case PHY_INTERFACE_MODE_RMII:
252 if (!mac->id)
253 goto err_phy;
254 ge_mode = 3;
255 break;
256 default:
257 goto err_phy;
258 }
259
260 /* put the gmac into the right mode */
261 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
262 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
263 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
264 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
265
266 mtk_phy_connect_node(eth, mac, np);
267 mac->phy_dev->autoneg = AUTONEG_ENABLE;
268 mac->phy_dev->speed = 0;
269 mac->phy_dev->duplex = 0;
270
271 if (of_phy_is_fixed_link(mac->of_node))
272 mac->phy_dev->supported |=
273 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
274
275 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
276 SUPPORTED_Asym_Pause;
277 mac->phy_dev->advertising = mac->phy_dev->supported |
278 ADVERTISED_Autoneg;
279 phy_start_aneg(mac->phy_dev);
280
281 of_node_put(np);
282
283 return 0;
284
285 err_phy:
286 of_node_put(np);
287 dev_err(eth->dev, "invalid phy_mode\n");
288 return -EINVAL;
289 }
290
291 static int mtk_mdio_init(struct mtk_eth *eth)
292 {
293 struct device_node *mii_np;
294 int err;
295
296 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
297 if (!mii_np) {
298 dev_err(eth->dev, "no %s child node found", "mdio-bus");
299 return -ENODEV;
300 }
301
302 if (!of_device_is_available(mii_np)) {
303 err = 0;
304 goto err_put_node;
305 }
306
307 eth->mii_bus = mdiobus_alloc();
308 if (!eth->mii_bus) {
309 err = -ENOMEM;
310 goto err_put_node;
311 }
312
313 eth->mii_bus->name = "mdio";
314 eth->mii_bus->read = mtk_mdio_read;
315 eth->mii_bus->write = mtk_mdio_write;
316 eth->mii_bus->priv = eth;
317 eth->mii_bus->parent = eth->dev;
318
319 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
320 err = of_mdiobus_register(eth->mii_bus, mii_np);
321 if (err)
322 goto err_free_bus;
323
324 return 0;
325
326 err_free_bus:
327 mdiobus_free(eth->mii_bus);
328
329 err_put_node:
330 of_node_put(mii_np);
331 eth->mii_bus = NULL;
332 return err;
333 }
334
335 static void mtk_mdio_cleanup(struct mtk_eth *eth)
336 {
337 if (!eth->mii_bus)
338 return;
339
340 mdiobus_unregister(eth->mii_bus);
341 of_node_put(eth->mii_bus->dev.of_node);
342 mdiobus_free(eth->mii_bus);
343 }
344
345 static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
346 {
347 unsigned long flags;
348 u32 val;
349
350 spin_lock_irqsave(&eth->irq_lock, flags);
351 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
352 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
353 spin_unlock_irqrestore(&eth->irq_lock, flags);
354 }
355
356 static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
357 {
358 unsigned long flags;
359 u32 val;
360
361 spin_lock_irqsave(&eth->irq_lock, flags);
362 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
363 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
364 spin_unlock_irqrestore(&eth->irq_lock, flags);
365 }
366
367 static int mtk_set_mac_address(struct net_device *dev, void *p)
368 {
369 int ret = eth_mac_addr(dev, p);
370 struct mtk_mac *mac = netdev_priv(dev);
371 const char *macaddr = dev->dev_addr;
372 unsigned long flags;
373
374 if (ret)
375 return ret;
376
377 spin_lock_irqsave(&mac->hw->page_lock, flags);
378 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
379 MTK_GDMA_MAC_ADRH(mac->id));
380 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
381 (macaddr[4] << 8) | macaddr[5],
382 MTK_GDMA_MAC_ADRL(mac->id));
383 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
384
385 return 0;
386 }
387
388 void mtk_stats_update_mac(struct mtk_mac *mac)
389 {
390 struct mtk_hw_stats *hw_stats = mac->hw_stats;
391 unsigned int base = MTK_GDM1_TX_GBCNT;
392 u64 stats;
393
394 base += hw_stats->reg_offset;
395
396 u64_stats_update_begin(&hw_stats->syncp);
397
398 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
399 stats = mtk_r32(mac->hw, base + 0x04);
400 if (stats)
401 hw_stats->rx_bytes += (stats << 32);
402 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
403 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
404 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
405 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
406 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
407 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
408 hw_stats->rx_flow_control_packets +=
409 mtk_r32(mac->hw, base + 0x24);
410 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
411 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
412 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
413 stats = mtk_r32(mac->hw, base + 0x34);
414 if (stats)
415 hw_stats->tx_bytes += (stats << 32);
416 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
417 u64_stats_update_end(&hw_stats->syncp);
418 }
419
420 static void mtk_stats_update(struct mtk_eth *eth)
421 {
422 int i;
423
424 for (i = 0; i < MTK_MAC_COUNT; i++) {
425 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
426 continue;
427 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
428 mtk_stats_update_mac(eth->mac[i]);
429 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
430 }
431 }
432 }
433
434 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
435 struct rtnl_link_stats64 *storage)
436 {
437 struct mtk_mac *mac = netdev_priv(dev);
438 struct mtk_hw_stats *hw_stats = mac->hw_stats;
439 unsigned int start;
440
441 if (netif_running(dev) && netif_device_present(dev)) {
442 if (spin_trylock(&hw_stats->stats_lock)) {
443 mtk_stats_update_mac(mac);
444 spin_unlock(&hw_stats->stats_lock);
445 }
446 }
447
448 do {
449 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
450 storage->rx_packets = hw_stats->rx_packets;
451 storage->tx_packets = hw_stats->tx_packets;
452 storage->rx_bytes = hw_stats->rx_bytes;
453 storage->tx_bytes = hw_stats->tx_bytes;
454 storage->collisions = hw_stats->tx_collisions;
455 storage->rx_length_errors = hw_stats->rx_short_errors +
456 hw_stats->rx_long_errors;
457 storage->rx_over_errors = hw_stats->rx_overflow;
458 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
459 storage->rx_errors = hw_stats->rx_checksum_errors;
460 storage->tx_aborted_errors = hw_stats->tx_skip;
461 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
462
463 storage->tx_errors = dev->stats.tx_errors;
464 storage->rx_dropped = dev->stats.rx_dropped;
465 storage->tx_dropped = dev->stats.tx_dropped;
466
467 return storage;
468 }
469
470 static inline int mtk_max_frag_size(int mtu)
471 {
472 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
473 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
474 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
475
476 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
477 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
478 }
479
480 static inline int mtk_max_buf_size(int frag_size)
481 {
482 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
483 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
484
485 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
486
487 return buf_size;
488 }
489
490 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
491 struct mtk_rx_dma *dma_rxd)
492 {
493 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
494 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
495 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
496 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
497 }
498
499 /* the qdma core needs scratch memory to be setup */
500 static int mtk_init_fq_dma(struct mtk_eth *eth)
501 {
502 dma_addr_t phy_ring_tail;
503 int cnt = MTK_DMA_SIZE;
504 dma_addr_t dma_addr;
505 int i;
506
507 eth->scratch_ring = dma_alloc_coherent(eth->dev,
508 cnt * sizeof(struct mtk_tx_dma),
509 &eth->phy_scratch_ring,
510 GFP_ATOMIC | __GFP_ZERO);
511 if (unlikely(!eth->scratch_ring))
512 return -ENOMEM;
513
514 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
515 GFP_KERNEL);
516 if (unlikely(!eth->scratch_head))
517 return -ENOMEM;
518
519 dma_addr = dma_map_single(eth->dev,
520 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
521 DMA_FROM_DEVICE);
522 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
523 return -ENOMEM;
524
525 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
526 phy_ring_tail = eth->phy_scratch_ring +
527 (sizeof(struct mtk_tx_dma) * (cnt - 1));
528
529 for (i = 0; i < cnt; i++) {
530 eth->scratch_ring[i].txd1 =
531 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
532 if (i < cnt - 1)
533 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
534 ((i + 1) * sizeof(struct mtk_tx_dma)));
535 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
536 }
537
538 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
539 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
540 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
541 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
542
543 return 0;
544 }
545
546 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
547 {
548 void *ret = ring->dma;
549
550 return ret + (desc - ring->phys);
551 }
552
553 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
554 struct mtk_tx_dma *txd)
555 {
556 int idx = txd - ring->dma;
557
558 return &ring->buf[idx];
559 }
560
561 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
562 {
563 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
564 dma_unmap_single(eth->dev,
565 dma_unmap_addr(tx_buf, dma_addr0),
566 dma_unmap_len(tx_buf, dma_len0),
567 DMA_TO_DEVICE);
568 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
569 dma_unmap_page(eth->dev,
570 dma_unmap_addr(tx_buf, dma_addr0),
571 dma_unmap_len(tx_buf, dma_len0),
572 DMA_TO_DEVICE);
573 }
574 tx_buf->flags = 0;
575 if (tx_buf->skb &&
576 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
577 dev_kfree_skb_any(tx_buf->skb);
578 tx_buf->skb = NULL;
579 }
580
581 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
582 int tx_num, struct mtk_tx_ring *ring, bool gso)
583 {
584 struct mtk_mac *mac = netdev_priv(dev);
585 struct mtk_eth *eth = mac->hw;
586 struct mtk_tx_dma *itxd, *txd;
587 struct mtk_tx_buf *tx_buf;
588 dma_addr_t mapped_addr;
589 unsigned int nr_frags;
590 int i, n_desc = 1;
591 u32 txd4 = 0, fport;
592
593 itxd = ring->next_free;
594 if (itxd == ring->last_free)
595 return -ENOMEM;
596
597 /* set the forward port */
598 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
599 txd4 |= fport;
600
601 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
602 memset(tx_buf, 0, sizeof(*tx_buf));
603
604 if (gso)
605 txd4 |= TX_DMA_TSO;
606
607 /* TX Checksum offload */
608 if (skb->ip_summed == CHECKSUM_PARTIAL)
609 txd4 |= TX_DMA_CHKSUM;
610
611 /* VLAN header offload */
612 if (skb_vlan_tag_present(skb))
613 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
614
615 mapped_addr = dma_map_single(eth->dev, skb->data,
616 skb_headlen(skb), DMA_TO_DEVICE);
617 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
618 return -ENOMEM;
619
620 WRITE_ONCE(itxd->txd1, mapped_addr);
621 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
622 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
623 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
624
625 /* TX SG offload */
626 txd = itxd;
627 nr_frags = skb_shinfo(skb)->nr_frags;
628 for (i = 0; i < nr_frags; i++) {
629 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
630 unsigned int offset = 0;
631 int frag_size = skb_frag_size(frag);
632
633 while (frag_size) {
634 bool last_frag = false;
635 unsigned int frag_map_size;
636
637 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
638 if (txd == ring->last_free)
639 goto err_dma;
640
641 n_desc++;
642 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
643 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
644 frag_map_size,
645 DMA_TO_DEVICE);
646 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
647 goto err_dma;
648
649 if (i == nr_frags - 1 &&
650 (frag_size - frag_map_size) == 0)
651 last_frag = true;
652
653 WRITE_ONCE(txd->txd1, mapped_addr);
654 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
655 TX_DMA_PLEN0(frag_map_size) |
656 last_frag * TX_DMA_LS0));
657 WRITE_ONCE(txd->txd4, fport);
658
659 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
660 tx_buf = mtk_desc_to_tx_buf(ring, txd);
661 memset(tx_buf, 0, sizeof(*tx_buf));
662
663 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
664 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
665 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
666 frag_size -= frag_map_size;
667 offset += frag_map_size;
668 }
669 }
670
671 /* store skb to cleanup */
672 tx_buf->skb = skb;
673
674 WRITE_ONCE(itxd->txd4, txd4);
675 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
676 (!nr_frags * TX_DMA_LS0)));
677
678 netdev_sent_queue(dev, skb->len);
679 skb_tx_timestamp(skb);
680
681 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
682 atomic_sub(n_desc, &ring->free_count);
683
684 /* make sure that all changes to the dma ring are flushed before we
685 * continue
686 */
687 wmb();
688
689 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
690 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
691
692 return 0;
693
694 err_dma:
695 do {
696 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
697
698 /* unmap dma */
699 mtk_tx_unmap(eth, tx_buf);
700
701 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
702 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
703 } while (itxd != txd);
704
705 return -ENOMEM;
706 }
707
708 static inline int mtk_cal_txd_req(struct sk_buff *skb)
709 {
710 int i, nfrags;
711 struct skb_frag_struct *frag;
712
713 nfrags = 1;
714 if (skb_is_gso(skb)) {
715 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
716 frag = &skb_shinfo(skb)->frags[i];
717 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
718 }
719 } else {
720 nfrags += skb_shinfo(skb)->nr_frags;
721 }
722
723 return nfrags;
724 }
725
726 static int mtk_queue_stopped(struct mtk_eth *eth)
727 {
728 int i;
729
730 for (i = 0; i < MTK_MAC_COUNT; i++) {
731 if (!eth->netdev[i])
732 continue;
733 if (netif_queue_stopped(eth->netdev[i]))
734 return 1;
735 }
736
737 return 0;
738 }
739
740 static void mtk_wake_queue(struct mtk_eth *eth)
741 {
742 int i;
743
744 for (i = 0; i < MTK_MAC_COUNT; i++) {
745 if (!eth->netdev[i])
746 continue;
747 netif_wake_queue(eth->netdev[i]);
748 }
749 }
750
751 static void mtk_stop_queue(struct mtk_eth *eth)
752 {
753 int i;
754
755 for (i = 0; i < MTK_MAC_COUNT; i++) {
756 if (!eth->netdev[i])
757 continue;
758 netif_stop_queue(eth->netdev[i]);
759 }
760 }
761
762 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
763 {
764 struct mtk_mac *mac = netdev_priv(dev);
765 struct mtk_eth *eth = mac->hw;
766 struct mtk_tx_ring *ring = &eth->tx_ring;
767 struct net_device_stats *stats = &dev->stats;
768 unsigned long flags;
769 bool gso = false;
770 int tx_num;
771
772 /* normally we can rely on the stack not calling this more than once,
773 * however we have 2 queues running on the same ring so we need to lock
774 * the ring access
775 */
776 spin_lock_irqsave(&eth->page_lock, flags);
777
778 tx_num = mtk_cal_txd_req(skb);
779 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
780 mtk_stop_queue(eth);
781 netif_err(eth, tx_queued, dev,
782 "Tx Ring full when queue awake!\n");
783 spin_unlock_irqrestore(&eth->page_lock, flags);
784 return NETDEV_TX_BUSY;
785 }
786
787 /* TSO: fill MSS info in tcp checksum field */
788 if (skb_is_gso(skb)) {
789 if (skb_cow_head(skb, 0)) {
790 netif_warn(eth, tx_err, dev,
791 "GSO expand head fail.\n");
792 goto drop;
793 }
794
795 if (skb_shinfo(skb)->gso_type &
796 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
797 gso = true;
798 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
799 }
800 }
801
802 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
803 goto drop;
804
805 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
806 mtk_stop_queue(eth);
807
808 spin_unlock_irqrestore(&eth->page_lock, flags);
809
810 return NETDEV_TX_OK;
811
812 drop:
813 spin_unlock_irqrestore(&eth->page_lock, flags);
814 stats->tx_dropped++;
815 dev_kfree_skb(skb);
816 return NETDEV_TX_OK;
817 }
818
819 static int mtk_poll_rx(struct napi_struct *napi, int budget,
820 struct mtk_eth *eth)
821 {
822 struct mtk_rx_ring *ring = &eth->rx_ring;
823 int idx = ring->calc_idx;
824 struct sk_buff *skb;
825 u8 *data, *new_data;
826 struct mtk_rx_dma *rxd, trxd;
827 int done = 0;
828
829 while (done < budget) {
830 struct net_device *netdev;
831 unsigned int pktlen;
832 dma_addr_t dma_addr;
833 int mac = 0;
834
835 idx = NEXT_RX_DESP_IDX(idx);
836 rxd = &ring->dma[idx];
837 data = ring->data[idx];
838
839 mtk_rx_get_desc(&trxd, rxd);
840 if (!(trxd.rxd2 & RX_DMA_DONE))
841 break;
842
843 /* find out which mac the packet come from. values start at 1 */
844 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
845 RX_DMA_FPORT_MASK;
846 mac--;
847
848 netdev = eth->netdev[mac];
849
850 /* alloc new buffer */
851 new_data = napi_alloc_frag(ring->frag_size);
852 if (unlikely(!new_data)) {
853 netdev->stats.rx_dropped++;
854 goto release_desc;
855 }
856 dma_addr = dma_map_single(eth->dev,
857 new_data + NET_SKB_PAD,
858 ring->buf_size,
859 DMA_FROM_DEVICE);
860 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
861 skb_free_frag(new_data);
862 netdev->stats.rx_dropped++;
863 goto release_desc;
864 }
865
866 /* receive data */
867 skb = build_skb(data, ring->frag_size);
868 if (unlikely(!skb)) {
869 put_page(virt_to_head_page(new_data));
870 netdev->stats.rx_dropped++;
871 goto release_desc;
872 }
873 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
874
875 dma_unmap_single(eth->dev, trxd.rxd1,
876 ring->buf_size, DMA_FROM_DEVICE);
877 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
878 skb->dev = netdev;
879 skb_put(skb, pktlen);
880 if (trxd.rxd4 & RX_DMA_L4_VALID)
881 skb->ip_summed = CHECKSUM_UNNECESSARY;
882 else
883 skb_checksum_none_assert(skb);
884 skb->protocol = eth_type_trans(skb, netdev);
885
886 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
887 RX_DMA_VID(trxd.rxd3))
888 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
889 RX_DMA_VID(trxd.rxd3));
890 napi_gro_receive(napi, skb);
891
892 ring->data[idx] = new_data;
893 rxd->rxd1 = (unsigned int)dma_addr;
894
895 release_desc:
896 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
897
898 ring->calc_idx = idx;
899 /* make sure that all changes to the dma ring are flushed before
900 * we continue
901 */
902 wmb();
903 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
904 done++;
905 }
906
907 if (done < budget)
908 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
909
910 return done;
911 }
912
913 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
914 {
915 struct mtk_tx_ring *ring = &eth->tx_ring;
916 struct mtk_tx_dma *desc;
917 struct sk_buff *skb;
918 struct mtk_tx_buf *tx_buf;
919 unsigned int done[MTK_MAX_DEVS];
920 unsigned int bytes[MTK_MAX_DEVS];
921 u32 cpu, dma;
922 static int condition;
923 int total = 0, i;
924
925 memset(done, 0, sizeof(done));
926 memset(bytes, 0, sizeof(bytes));
927
928 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
929 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
930
931 desc = mtk_qdma_phys_to_virt(ring, cpu);
932
933 while ((cpu != dma) && budget) {
934 u32 next_cpu = desc->txd2;
935 int mac;
936
937 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
938 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
939 break;
940
941 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
942 TX_DMA_FPORT_MASK;
943 mac--;
944
945 tx_buf = mtk_desc_to_tx_buf(ring, desc);
946 skb = tx_buf->skb;
947 if (!skb) {
948 condition = 1;
949 break;
950 }
951
952 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
953 bytes[mac] += skb->len;
954 done[mac]++;
955 budget--;
956 }
957 mtk_tx_unmap(eth, tx_buf);
958
959 ring->last_free = desc;
960 atomic_inc(&ring->free_count);
961
962 cpu = next_cpu;
963 }
964
965 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
966
967 for (i = 0; i < MTK_MAC_COUNT; i++) {
968 if (!eth->netdev[i] || !done[i])
969 continue;
970 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
971 total += done[i];
972 }
973
974 if (mtk_queue_stopped(eth) &&
975 (atomic_read(&ring->free_count) > ring->thresh))
976 mtk_wake_queue(eth);
977
978 return total;
979 }
980
981 static void mtk_handle_status_irq(struct mtk_eth *eth)
982 {
983 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
984
985 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
986 mtk_stats_update(eth);
987 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
988 MTK_INT_STATUS2);
989 }
990 }
991
992 static int mtk_napi_tx(struct napi_struct *napi, int budget)
993 {
994 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
995 u32 status, mask;
996 int tx_done = 0;
997
998 mtk_handle_status_irq(eth);
999 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1000 tx_done = mtk_poll_tx(eth, budget);
1001
1002 if (unlikely(netif_msg_intr(eth))) {
1003 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1004 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1005 dev_info(eth->dev,
1006 "done tx %d, intr 0x%08x/0x%x\n",
1007 tx_done, status, mask);
1008 }
1009
1010 if (tx_done == budget)
1011 return budget;
1012
1013 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1014 if (status & MTK_TX_DONE_INT)
1015 return budget;
1016
1017 napi_complete(napi);
1018 mtk_irq_enable(eth, MTK_TX_DONE_INT);
1019
1020 return tx_done;
1021 }
1022
1023 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1024 {
1025 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1026 u32 status, mask;
1027 int rx_done = 0;
1028
1029 mtk_handle_status_irq(eth);
1030 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
1031 rx_done = mtk_poll_rx(napi, budget, eth);
1032
1033 if (unlikely(netif_msg_intr(eth))) {
1034 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1035 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1036 dev_info(eth->dev,
1037 "done rx %d, intr 0x%08x/0x%x\n",
1038 rx_done, status, mask);
1039 }
1040
1041 if (rx_done == budget)
1042 return budget;
1043
1044 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1045 if (status & MTK_RX_DONE_INT)
1046 return budget;
1047
1048 napi_complete(napi);
1049 mtk_irq_enable(eth, MTK_RX_DONE_INT);
1050
1051 return rx_done;
1052 }
1053
1054 static int mtk_tx_alloc(struct mtk_eth *eth)
1055 {
1056 struct mtk_tx_ring *ring = &eth->tx_ring;
1057 int i, sz = sizeof(*ring->dma);
1058
1059 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1060 GFP_KERNEL);
1061 if (!ring->buf)
1062 goto no_tx_mem;
1063
1064 ring->dma = dma_alloc_coherent(eth->dev,
1065 MTK_DMA_SIZE * sz,
1066 &ring->phys,
1067 GFP_ATOMIC | __GFP_ZERO);
1068 if (!ring->dma)
1069 goto no_tx_mem;
1070
1071 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1072 for (i = 0; i < MTK_DMA_SIZE; i++) {
1073 int next = (i + 1) % MTK_DMA_SIZE;
1074 u32 next_ptr = ring->phys + next * sz;
1075
1076 ring->dma[i].txd2 = next_ptr;
1077 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1078 }
1079
1080 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1081 ring->next_free = &ring->dma[0];
1082 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1083 ring->thresh = MAX_SKB_FRAGS;
1084
1085 /* make sure that all changes to the dma ring are flushed before we
1086 * continue
1087 */
1088 wmb();
1089
1090 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1091 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1092 mtk_w32(eth,
1093 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1094 MTK_QTX_CRX_PTR);
1095 mtk_w32(eth,
1096 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1097 MTK_QTX_DRX_PTR);
1098
1099 return 0;
1100
1101 no_tx_mem:
1102 return -ENOMEM;
1103 }
1104
1105 static void mtk_tx_clean(struct mtk_eth *eth)
1106 {
1107 struct mtk_tx_ring *ring = &eth->tx_ring;
1108 int i;
1109
1110 if (ring->buf) {
1111 for (i = 0; i < MTK_DMA_SIZE; i++)
1112 mtk_tx_unmap(eth, &ring->buf[i]);
1113 kfree(ring->buf);
1114 ring->buf = NULL;
1115 }
1116
1117 if (ring->dma) {
1118 dma_free_coherent(eth->dev,
1119 MTK_DMA_SIZE * sizeof(*ring->dma),
1120 ring->dma,
1121 ring->phys);
1122 ring->dma = NULL;
1123 }
1124 }
1125
1126 static int mtk_rx_alloc(struct mtk_eth *eth)
1127 {
1128 struct mtk_rx_ring *ring = &eth->rx_ring;
1129 int i;
1130
1131 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1132 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1133 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1134 GFP_KERNEL);
1135 if (!ring->data)
1136 return -ENOMEM;
1137
1138 for (i = 0; i < MTK_DMA_SIZE; i++) {
1139 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1140 if (!ring->data[i])
1141 return -ENOMEM;
1142 }
1143
1144 ring->dma = dma_alloc_coherent(eth->dev,
1145 MTK_DMA_SIZE * sizeof(*ring->dma),
1146 &ring->phys,
1147 GFP_ATOMIC | __GFP_ZERO);
1148 if (!ring->dma)
1149 return -ENOMEM;
1150
1151 for (i = 0; i < MTK_DMA_SIZE; i++) {
1152 dma_addr_t dma_addr = dma_map_single(eth->dev,
1153 ring->data[i] + NET_SKB_PAD,
1154 ring->buf_size,
1155 DMA_FROM_DEVICE);
1156 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1157 return -ENOMEM;
1158 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1159
1160 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1161 }
1162 ring->calc_idx = MTK_DMA_SIZE - 1;
1163 /* make sure that all changes to the dma ring are flushed before we
1164 * continue
1165 */
1166 wmb();
1167
1168 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1169 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1170 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1171 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1172 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1173
1174 return 0;
1175 }
1176
1177 static void mtk_rx_clean(struct mtk_eth *eth)
1178 {
1179 struct mtk_rx_ring *ring = &eth->rx_ring;
1180 int i;
1181
1182 if (ring->data && ring->dma) {
1183 for (i = 0; i < MTK_DMA_SIZE; i++) {
1184 if (!ring->data[i])
1185 continue;
1186 if (!ring->dma[i].rxd1)
1187 continue;
1188 dma_unmap_single(eth->dev,
1189 ring->dma[i].rxd1,
1190 ring->buf_size,
1191 DMA_FROM_DEVICE);
1192 skb_free_frag(ring->data[i]);
1193 }
1194 kfree(ring->data);
1195 ring->data = NULL;
1196 }
1197
1198 if (ring->dma) {
1199 dma_free_coherent(eth->dev,
1200 MTK_DMA_SIZE * sizeof(*ring->dma),
1201 ring->dma,
1202 ring->phys);
1203 ring->dma = NULL;
1204 }
1205 }
1206
1207 /* wait for DMA to finish whatever it is doing before we start using it again */
1208 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1209 {
1210 unsigned long t_start = jiffies;
1211
1212 while (1) {
1213 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1214 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1215 return 0;
1216 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1217 break;
1218 }
1219
1220 dev_err(eth->dev, "DMA init timeout\n");
1221 return -1;
1222 }
1223
1224 static int mtk_dma_init(struct mtk_eth *eth)
1225 {
1226 int err;
1227
1228 if (mtk_dma_busy_wait(eth))
1229 return -EBUSY;
1230
1231 /* QDMA needs scratch memory for internal reordering of the
1232 * descriptors
1233 */
1234 err = mtk_init_fq_dma(eth);
1235 if (err)
1236 return err;
1237
1238 err = mtk_tx_alloc(eth);
1239 if (err)
1240 return err;
1241
1242 err = mtk_rx_alloc(eth);
1243 if (err)
1244 return err;
1245
1246 /* Enable random early drop and set drop threshold automatically */
1247 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1248 MTK_QDMA_FC_THRES);
1249 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1250
1251 return 0;
1252 }
1253
1254 static void mtk_dma_free(struct mtk_eth *eth)
1255 {
1256 int i;
1257
1258 for (i = 0; i < MTK_MAC_COUNT; i++)
1259 if (eth->netdev[i])
1260 netdev_reset_queue(eth->netdev[i]);
1261 if (eth->scratch_ring) {
1262 dma_free_coherent(eth->dev,
1263 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1264 eth->scratch_ring,
1265 eth->phy_scratch_ring);
1266 eth->scratch_ring = NULL;
1267 eth->phy_scratch_ring = 0;
1268 }
1269 mtk_tx_clean(eth);
1270 mtk_rx_clean(eth);
1271 kfree(eth->scratch_head);
1272 }
1273
1274 static void mtk_tx_timeout(struct net_device *dev)
1275 {
1276 struct mtk_mac *mac = netdev_priv(dev);
1277 struct mtk_eth *eth = mac->hw;
1278
1279 eth->netdev[mac->id]->stats.tx_errors++;
1280 netif_err(eth, tx_err, dev,
1281 "transmit timed out\n");
1282 schedule_work(&eth->pending_work);
1283 }
1284
1285 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1286 {
1287 struct mtk_eth *eth = _eth;
1288
1289 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1290 __napi_schedule(&eth->rx_napi);
1291 mtk_irq_disable(eth, MTK_RX_DONE_INT);
1292 }
1293
1294 return IRQ_HANDLED;
1295 }
1296
1297 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1298 {
1299 struct mtk_eth *eth = _eth;
1300
1301 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1302 __napi_schedule(&eth->tx_napi);
1303 mtk_irq_disable(eth, MTK_TX_DONE_INT);
1304 }
1305
1306 return IRQ_HANDLED;
1307 }
1308
1309 #ifdef CONFIG_NET_POLL_CONTROLLER
1310 static void mtk_poll_controller(struct net_device *dev)
1311 {
1312 struct mtk_mac *mac = netdev_priv(dev);
1313 struct mtk_eth *eth = mac->hw;
1314 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1315
1316 mtk_irq_disable(eth, int_mask);
1317 mtk_handle_irq_rx(eth->irq[2], dev);
1318 mtk_irq_enable(eth, int_mask);
1319 }
1320 #endif
1321
1322 static int mtk_start_dma(struct mtk_eth *eth)
1323 {
1324 int err;
1325
1326 err = mtk_dma_init(eth);
1327 if (err) {
1328 mtk_dma_free(eth);
1329 return err;
1330 }
1331
1332 mtk_w32(eth,
1333 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1334 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
1335 MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
1336 MTK_QDMA_GLO_CFG);
1337
1338 return 0;
1339 }
1340
1341 static int mtk_open(struct net_device *dev)
1342 {
1343 struct mtk_mac *mac = netdev_priv(dev);
1344 struct mtk_eth *eth = mac->hw;
1345
1346 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1347 if (!atomic_read(&eth->dma_refcnt)) {
1348 int err = mtk_start_dma(eth);
1349
1350 if (err)
1351 return err;
1352
1353 napi_enable(&eth->tx_napi);
1354 napi_enable(&eth->rx_napi);
1355 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1356 }
1357 atomic_inc(&eth->dma_refcnt);
1358
1359 phy_start(mac->phy_dev);
1360 netif_start_queue(dev);
1361
1362 return 0;
1363 }
1364
1365 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1366 {
1367 unsigned long flags;
1368 u32 val;
1369 int i;
1370
1371 /* stop the dma engine */
1372 spin_lock_irqsave(&eth->page_lock, flags);
1373 val = mtk_r32(eth, glo_cfg);
1374 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1375 glo_cfg);
1376 spin_unlock_irqrestore(&eth->page_lock, flags);
1377
1378 /* wait for dma stop */
1379 for (i = 0; i < 10; i++) {
1380 val = mtk_r32(eth, glo_cfg);
1381 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1382 msleep(20);
1383 continue;
1384 }
1385 break;
1386 }
1387 }
1388
1389 static int mtk_stop(struct net_device *dev)
1390 {
1391 struct mtk_mac *mac = netdev_priv(dev);
1392 struct mtk_eth *eth = mac->hw;
1393
1394 netif_tx_disable(dev);
1395 phy_stop(mac->phy_dev);
1396
1397 /* only shutdown DMA if this is the last user */
1398 if (!atomic_dec_and_test(&eth->dma_refcnt))
1399 return 0;
1400
1401 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1402 napi_disable(&eth->tx_napi);
1403 napi_disable(&eth->rx_napi);
1404
1405 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1406
1407 mtk_dma_free(eth);
1408
1409 return 0;
1410 }
1411
1412 static int __init mtk_hw_init(struct mtk_eth *eth)
1413 {
1414 int err, i;
1415
1416 /* reset the frame engine */
1417 reset_control_assert(eth->rstc);
1418 usleep_range(10, 20);
1419 reset_control_deassert(eth->rstc);
1420 usleep_range(10, 20);
1421
1422 /* Set GE2 driving and slew rate */
1423 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1424
1425 /* set GE2 TDSEL */
1426 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1427
1428 /* set GE2 TUNE */
1429 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1430
1431 /* GE1, Force 1000M/FD, FC ON */
1432 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1433
1434 /* GE2, Force 1000M/FD, FC ON */
1435 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1436
1437 /* Enable RX VLan Offloading */
1438 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1439
1440 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
1441 dev_name(eth->dev), eth);
1442 if (err)
1443 return err;
1444 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
1445 dev_name(eth->dev), eth);
1446 if (err)
1447 return err;
1448
1449 err = mtk_mdio_init(eth);
1450 if (err)
1451 return err;
1452
1453 /* disable delay and normal interrupt */
1454 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1455 mtk_irq_disable(eth, ~0);
1456 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1457 mtk_w32(eth, 0, MTK_RST_GL);
1458
1459 /* FE int grouping */
1460 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1461 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1462 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1463 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1464 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1465
1466 for (i = 0; i < 2; i++) {
1467 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1468
1469 /* setup the forward port to send frame to QDMA */
1470 val &= ~0xffff;
1471 val |= 0x5555;
1472
1473 /* Enable RX checksum */
1474 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1475
1476 /* setup the mac dma */
1477 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1478 }
1479
1480 return 0;
1481 }
1482
1483 static int __init mtk_init(struct net_device *dev)
1484 {
1485 struct mtk_mac *mac = netdev_priv(dev);
1486 struct mtk_eth *eth = mac->hw;
1487 const char *mac_addr;
1488
1489 mac_addr = of_get_mac_address(mac->of_node);
1490 if (mac_addr)
1491 ether_addr_copy(dev->dev_addr, mac_addr);
1492
1493 /* If the mac address is invalid, use random mac address */
1494 if (!is_valid_ether_addr(dev->dev_addr)) {
1495 random_ether_addr(dev->dev_addr);
1496 dev_err(eth->dev, "generated random MAC address %pM\n",
1497 dev->dev_addr);
1498 dev->addr_assign_type = NET_ADDR_RANDOM;
1499 }
1500
1501 return mtk_phy_connect(mac);
1502 }
1503
1504 static void mtk_uninit(struct net_device *dev)
1505 {
1506 struct mtk_mac *mac = netdev_priv(dev);
1507 struct mtk_eth *eth = mac->hw;
1508
1509 phy_disconnect(mac->phy_dev);
1510 mtk_mdio_cleanup(eth);
1511 mtk_irq_disable(eth, ~0);
1512 free_irq(eth->irq[1], dev);
1513 free_irq(eth->irq[2], dev);
1514 }
1515
1516 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1517 {
1518 struct mtk_mac *mac = netdev_priv(dev);
1519
1520 switch (cmd) {
1521 case SIOCGMIIPHY:
1522 case SIOCGMIIREG:
1523 case SIOCSMIIREG:
1524 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1525 default:
1526 break;
1527 }
1528
1529 return -EOPNOTSUPP;
1530 }
1531
1532 static void mtk_pending_work(struct work_struct *work)
1533 {
1534 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
1535 int err, i;
1536 unsigned long restart = 0;
1537
1538 rtnl_lock();
1539
1540 /* stop all devices to make sure that dma is properly shut down */
1541 for (i = 0; i < MTK_MAC_COUNT; i++) {
1542 if (!eth->netdev[i])
1543 continue;
1544 mtk_stop(eth->netdev[i]);
1545 __set_bit(i, &restart);
1546 }
1547
1548 /* restart DMA and enable IRQs */
1549 for (i = 0; i < MTK_MAC_COUNT; i++) {
1550 if (!test_bit(i, &restart))
1551 continue;
1552 err = mtk_open(eth->netdev[i]);
1553 if (err) {
1554 netif_alert(eth, ifup, eth->netdev[i],
1555 "Driver up/down cycle failed, closing device.\n");
1556 dev_close(eth->netdev[i]);
1557 }
1558 }
1559 rtnl_unlock();
1560 }
1561
1562 static int mtk_cleanup(struct mtk_eth *eth)
1563 {
1564 int i;
1565
1566 for (i = 0; i < MTK_MAC_COUNT; i++) {
1567 if (!eth->netdev[i])
1568 continue;
1569
1570 unregister_netdev(eth->netdev[i]);
1571 free_netdev(eth->netdev[i]);
1572 }
1573 cancel_work_sync(&eth->pending_work);
1574
1575 return 0;
1576 }
1577
1578 static int mtk_get_settings(struct net_device *dev,
1579 struct ethtool_cmd *cmd)
1580 {
1581 struct mtk_mac *mac = netdev_priv(dev);
1582 int err;
1583
1584 err = phy_read_status(mac->phy_dev);
1585 if (err)
1586 return -ENODEV;
1587
1588 return phy_ethtool_gset(mac->phy_dev, cmd);
1589 }
1590
1591 static int mtk_set_settings(struct net_device *dev,
1592 struct ethtool_cmd *cmd)
1593 {
1594 struct mtk_mac *mac = netdev_priv(dev);
1595
1596 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1597 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1598 cmd->phy_address);
1599 if (!mac->phy_dev)
1600 return -ENODEV;
1601 }
1602
1603 return phy_ethtool_sset(mac->phy_dev, cmd);
1604 }
1605
1606 static void mtk_get_drvinfo(struct net_device *dev,
1607 struct ethtool_drvinfo *info)
1608 {
1609 struct mtk_mac *mac = netdev_priv(dev);
1610
1611 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1612 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1613 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1614 }
1615
1616 static u32 mtk_get_msglevel(struct net_device *dev)
1617 {
1618 struct mtk_mac *mac = netdev_priv(dev);
1619
1620 return mac->hw->msg_enable;
1621 }
1622
1623 static void mtk_set_msglevel(struct net_device *dev, u32 value)
1624 {
1625 struct mtk_mac *mac = netdev_priv(dev);
1626
1627 mac->hw->msg_enable = value;
1628 }
1629
1630 static int mtk_nway_reset(struct net_device *dev)
1631 {
1632 struct mtk_mac *mac = netdev_priv(dev);
1633
1634 return genphy_restart_aneg(mac->phy_dev);
1635 }
1636
1637 static u32 mtk_get_link(struct net_device *dev)
1638 {
1639 struct mtk_mac *mac = netdev_priv(dev);
1640 int err;
1641
1642 err = genphy_update_link(mac->phy_dev);
1643 if (err)
1644 return ethtool_op_get_link(dev);
1645
1646 return mac->phy_dev->link;
1647 }
1648
1649 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1650 {
1651 int i;
1652
1653 switch (stringset) {
1654 case ETH_SS_STATS:
1655 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1656 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1657 data += ETH_GSTRING_LEN;
1658 }
1659 break;
1660 }
1661 }
1662
1663 static int mtk_get_sset_count(struct net_device *dev, int sset)
1664 {
1665 switch (sset) {
1666 case ETH_SS_STATS:
1667 return ARRAY_SIZE(mtk_ethtool_stats);
1668 default:
1669 return -EOPNOTSUPP;
1670 }
1671 }
1672
1673 static void mtk_get_ethtool_stats(struct net_device *dev,
1674 struct ethtool_stats *stats, u64 *data)
1675 {
1676 struct mtk_mac *mac = netdev_priv(dev);
1677 struct mtk_hw_stats *hwstats = mac->hw_stats;
1678 u64 *data_src, *data_dst;
1679 unsigned int start;
1680 int i;
1681
1682 if (netif_running(dev) && netif_device_present(dev)) {
1683 if (spin_trylock(&hwstats->stats_lock)) {
1684 mtk_stats_update_mac(mac);
1685 spin_unlock(&hwstats->stats_lock);
1686 }
1687 }
1688
1689 do {
1690 data_src = (u64*)hwstats;
1691 data_dst = data;
1692 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1693
1694 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1695 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1696 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1697 }
1698
1699 static struct ethtool_ops mtk_ethtool_ops = {
1700 .get_settings = mtk_get_settings,
1701 .set_settings = mtk_set_settings,
1702 .get_drvinfo = mtk_get_drvinfo,
1703 .get_msglevel = mtk_get_msglevel,
1704 .set_msglevel = mtk_set_msglevel,
1705 .nway_reset = mtk_nway_reset,
1706 .get_link = mtk_get_link,
1707 .get_strings = mtk_get_strings,
1708 .get_sset_count = mtk_get_sset_count,
1709 .get_ethtool_stats = mtk_get_ethtool_stats,
1710 };
1711
1712 static const struct net_device_ops mtk_netdev_ops = {
1713 .ndo_init = mtk_init,
1714 .ndo_uninit = mtk_uninit,
1715 .ndo_open = mtk_open,
1716 .ndo_stop = mtk_stop,
1717 .ndo_start_xmit = mtk_start_xmit,
1718 .ndo_set_mac_address = mtk_set_mac_address,
1719 .ndo_validate_addr = eth_validate_addr,
1720 .ndo_do_ioctl = mtk_do_ioctl,
1721 .ndo_change_mtu = eth_change_mtu,
1722 .ndo_tx_timeout = mtk_tx_timeout,
1723 .ndo_get_stats64 = mtk_get_stats64,
1724 #ifdef CONFIG_NET_POLL_CONTROLLER
1725 .ndo_poll_controller = mtk_poll_controller,
1726 #endif
1727 };
1728
1729 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1730 {
1731 struct mtk_mac *mac;
1732 const __be32 *_id = of_get_property(np, "reg", NULL);
1733 int id, err;
1734
1735 if (!_id) {
1736 dev_err(eth->dev, "missing mac id\n");
1737 return -EINVAL;
1738 }
1739
1740 id = be32_to_cpup(_id);
1741 if (id >= MTK_MAC_COUNT) {
1742 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1743 return -EINVAL;
1744 }
1745
1746 if (eth->netdev[id]) {
1747 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1748 return -EINVAL;
1749 }
1750
1751 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1752 if (!eth->netdev[id]) {
1753 dev_err(eth->dev, "alloc_etherdev failed\n");
1754 return -ENOMEM;
1755 }
1756 mac = netdev_priv(eth->netdev[id]);
1757 eth->mac[id] = mac;
1758 mac->id = id;
1759 mac->hw = eth;
1760 mac->of_node = np;
1761
1762 mac->hw_stats = devm_kzalloc(eth->dev,
1763 sizeof(*mac->hw_stats),
1764 GFP_KERNEL);
1765 if (!mac->hw_stats) {
1766 dev_err(eth->dev, "failed to allocate counter memory\n");
1767 err = -ENOMEM;
1768 goto free_netdev;
1769 }
1770 spin_lock_init(&mac->hw_stats->stats_lock);
1771 u64_stats_init(&mac->hw_stats->syncp);
1772 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1773
1774 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
1775 eth->netdev[id]->watchdog_timeo = 5 * HZ;
1776 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1777 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1778 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1779 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1780 eth->netdev[id]->features |= MTK_HW_FEATURES;
1781 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1782
1783 err = register_netdev(eth->netdev[id]);
1784 if (err) {
1785 dev_err(eth->dev, "error bringing up device\n");
1786 goto free_netdev;
1787 }
1788 eth->netdev[id]->irq = eth->irq[0];
1789 netif_info(eth, probe, eth->netdev[id],
1790 "mediatek frame engine at 0x%08lx, irq %d\n",
1791 eth->netdev[id]->base_addr, eth->irq[0]);
1792
1793 return 0;
1794
1795 free_netdev:
1796 free_netdev(eth->netdev[id]);
1797 return err;
1798 }
1799
1800 static int mtk_probe(struct platform_device *pdev)
1801 {
1802 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1803 struct device_node *mac_np;
1804 const struct of_device_id *match;
1805 struct mtk_soc_data *soc;
1806 struct mtk_eth *eth;
1807 int err;
1808 int i;
1809
1810 match = of_match_device(of_mtk_match, &pdev->dev);
1811 soc = (struct mtk_soc_data *)match->data;
1812
1813 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1814 if (!eth)
1815 return -ENOMEM;
1816
1817 eth->base = devm_ioremap_resource(&pdev->dev, res);
1818 if (IS_ERR(eth->base))
1819 return PTR_ERR(eth->base);
1820
1821 spin_lock_init(&eth->page_lock);
1822 spin_lock_init(&eth->irq_lock);
1823
1824 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1825 "mediatek,ethsys");
1826 if (IS_ERR(eth->ethsys)) {
1827 dev_err(&pdev->dev, "no ethsys regmap found\n");
1828 return PTR_ERR(eth->ethsys);
1829 }
1830
1831 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1832 "mediatek,pctl");
1833 if (IS_ERR(eth->pctl)) {
1834 dev_err(&pdev->dev, "no pctl regmap found\n");
1835 return PTR_ERR(eth->pctl);
1836 }
1837
1838 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1839 if (IS_ERR(eth->rstc)) {
1840 dev_err(&pdev->dev, "no eth reset found\n");
1841 return PTR_ERR(eth->rstc);
1842 }
1843
1844 for (i = 0; i < 3; i++) {
1845 eth->irq[i] = platform_get_irq(pdev, i);
1846 if (eth->irq[i] < 0) {
1847 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
1848 return -ENXIO;
1849 }
1850 }
1851
1852 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1853 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1854 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1855 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1856 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1857 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1858 return -ENODEV;
1859
1860 clk_prepare_enable(eth->clk_ethif);
1861 clk_prepare_enable(eth->clk_esw);
1862 clk_prepare_enable(eth->clk_gp1);
1863 clk_prepare_enable(eth->clk_gp2);
1864
1865 eth->dev = &pdev->dev;
1866 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
1867 INIT_WORK(&eth->pending_work, mtk_pending_work);
1868
1869 err = mtk_hw_init(eth);
1870 if (err)
1871 return err;
1872
1873 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1874 if (!of_device_is_compatible(mac_np,
1875 "mediatek,eth-mac"))
1876 continue;
1877
1878 if (!of_device_is_available(mac_np))
1879 continue;
1880
1881 err = mtk_add_mac(eth, mac_np);
1882 if (err)
1883 goto err_free_dev;
1884 }
1885
1886 /* we run 2 devices on the same DMA ring so we need a dummy device
1887 * for NAPI to work
1888 */
1889 init_dummy_netdev(&eth->dummy_dev);
1890 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
1891 MTK_NAPI_WEIGHT);
1892 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
1893 MTK_NAPI_WEIGHT);
1894
1895 platform_set_drvdata(pdev, eth);
1896
1897 return 0;
1898
1899 err_free_dev:
1900 mtk_cleanup(eth);
1901 return err;
1902 }
1903
1904 static int mtk_remove(struct platform_device *pdev)
1905 {
1906 struct mtk_eth *eth = platform_get_drvdata(pdev);
1907
1908 clk_disable_unprepare(eth->clk_ethif);
1909 clk_disable_unprepare(eth->clk_esw);
1910 clk_disable_unprepare(eth->clk_gp1);
1911 clk_disable_unprepare(eth->clk_gp2);
1912
1913 netif_napi_del(&eth->tx_napi);
1914 netif_napi_del(&eth->rx_napi);
1915 mtk_cleanup(eth);
1916 platform_set_drvdata(pdev, NULL);
1917
1918 return 0;
1919 }
1920
1921 const struct of_device_id of_mtk_match[] = {
1922 { .compatible = "mediatek,mt7623-eth" },
1923 {},
1924 };
1925
1926 static struct platform_driver mtk_driver = {
1927 .probe = mtk_probe,
1928 .remove = mtk_remove,
1929 .driver = {
1930 .name = "mtk_soc_eth",
1931 .of_match_table = of_mtk_match,
1932 },
1933 };
1934
1935 module_platform_driver(mtk_driver);
1936
1937 MODULE_LICENSE("GPL");
1938 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1939 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
(deprecated) Btrfs devel tree