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gianfar: Cleanup dead code and minor formatting
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / freescale / gianfar.c
blob434b31bd88e6fbe435f30bd3ace29bbc0ca35678
1 /* drivers/net/ethernet/freescale/gianfar.c
2 *
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
11 *
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65 #define DEBUG
66
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
80 #include <linux/mm.h>
81 #include <linux/of_mdio.h>
82 #include <linux/of_platform.h>
83 #include <linux/ip.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
86 #include <linux/in.h>
87 #include <linux/net_tstamp.h>
88
89 #include <asm/io.h>
90 #include <asm/reg.h>
91 #include <asm/irq.h>
92 #include <asm/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
99 #include <linux/of.h>
100 #include <linux/of_net.h>
101
102 #include "gianfar.h"
103
104 #define TX_TIMEOUT (1*HZ)
105
106 const char gfar_driver_version[] = "1.3";
107
108 static int gfar_enet_open(struct net_device *dev);
109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
110 static void gfar_reset_task(struct work_struct *work);
111 static void gfar_timeout(struct net_device *dev);
112 static int gfar_close(struct net_device *dev);
113 struct sk_buff *gfar_new_skb(struct net_device *dev);
114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
115 struct sk_buff *skb);
116 static int gfar_set_mac_address(struct net_device *dev);
117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
118 static irqreturn_t gfar_error(int irq, void *dev_id);
119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
121 static void adjust_link(struct net_device *dev);
122 static void init_registers(struct net_device *dev);
123 static int init_phy(struct net_device *dev);
124 static int gfar_probe(struct platform_device *ofdev);
125 static int gfar_remove(struct platform_device *ofdev);
126 static void free_skb_resources(struct gfar_private *priv);
127 static void gfar_set_multi(struct net_device *dev);
128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
129 static void gfar_configure_serdes(struct net_device *dev);
130 static int gfar_poll(struct napi_struct *napi, int budget);
131 #ifdef CONFIG_NET_POLL_CONTROLLER
132 static void gfar_netpoll(struct net_device *dev);
133 #endif
134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
136 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 int amount_pull, struct napi_struct *napi);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
143 const u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
145
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
149
150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
151 dma_addr_t buf)
152 {
153 u32 lstatus;
154
155 bdp->bufPtr = buf;
156
157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
159 lstatus |= BD_LFLAG(RXBD_WRAP);
160
161 eieio();
162
163 bdp->lstatus = lstatus;
164 }
165
166 static int gfar_init_bds(struct net_device *ndev)
167 {
168 struct gfar_private *priv = netdev_priv(ndev);
169 struct gfar_priv_tx_q *tx_queue = NULL;
170 struct gfar_priv_rx_q *rx_queue = NULL;
171 struct txbd8 *txbdp;
172 struct rxbd8 *rxbdp;
173 int i, j;
174
175 for (i = 0; i < priv->num_tx_queues; i++) {
176 tx_queue = priv->tx_queue[i];
177 /* Initialize some variables in our dev structure */
178 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
179 tx_queue->dirty_tx = tx_queue->tx_bd_base;
180 tx_queue->cur_tx = tx_queue->tx_bd_base;
181 tx_queue->skb_curtx = 0;
182 tx_queue->skb_dirtytx = 0;
183
184 /* Initialize Transmit Descriptor Ring */
185 txbdp = tx_queue->tx_bd_base;
186 for (j = 0; j < tx_queue->tx_ring_size; j++) {
187 txbdp->lstatus = 0;
188 txbdp->bufPtr = 0;
189 txbdp++;
190 }
191
192 /* Set the last descriptor in the ring to indicate wrap */
193 txbdp--;
194 txbdp->status |= TXBD_WRAP;
195 }
196
197 for (i = 0; i < priv->num_rx_queues; i++) {
198 rx_queue = priv->rx_queue[i];
199 rx_queue->cur_rx = rx_queue->rx_bd_base;
200 rx_queue->skb_currx = 0;
201 rxbdp = rx_queue->rx_bd_base;
202
203 for (j = 0; j < rx_queue->rx_ring_size; j++) {
204 struct sk_buff *skb = rx_queue->rx_skbuff[j];
205
206 if (skb) {
207 gfar_init_rxbdp(rx_queue, rxbdp,
208 rxbdp->bufPtr);
209 } else {
210 skb = gfar_new_skb(ndev);
211 if (!skb) {
212 netdev_err(ndev, "Can't allocate RX buffers\n");
213 return -ENOMEM;
214 }
215 rx_queue->rx_skbuff[j] = skb;
216
217 gfar_new_rxbdp(rx_queue, rxbdp, skb);
218 }
219
220 rxbdp++;
221 }
222
223 }
224
225 return 0;
226 }
227
228 static int gfar_alloc_skb_resources(struct net_device *ndev)
229 {
230 void *vaddr;
231 dma_addr_t addr;
232 int i, j, k;
233 struct gfar_private *priv = netdev_priv(ndev);
234 struct device *dev = priv->dev;
235 struct gfar_priv_tx_q *tx_queue = NULL;
236 struct gfar_priv_rx_q *rx_queue = NULL;
237
238 priv->total_tx_ring_size = 0;
239 for (i = 0; i < priv->num_tx_queues; i++)
240 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
241
242 priv->total_rx_ring_size = 0;
243 for (i = 0; i < priv->num_rx_queues; i++)
244 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
245
246 /* Allocate memory for the buffer descriptors */
247 vaddr = dma_alloc_coherent(dev,
248 (priv->total_tx_ring_size *
249 sizeof(struct txbd8)) +
250 (priv->total_rx_ring_size *
251 sizeof(struct rxbd8)),
252 &addr, GFP_KERNEL);
253 if (!vaddr)
254 return -ENOMEM;
255
256 for (i = 0; i < priv->num_tx_queues; i++) {
257 tx_queue = priv->tx_queue[i];
258 tx_queue->tx_bd_base = vaddr;
259 tx_queue->tx_bd_dma_base = addr;
260 tx_queue->dev = ndev;
261 /* enet DMA only understands physical addresses */
262 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
263 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
264 }
265
266 /* Start the rx descriptor ring where the tx ring leaves off */
267 for (i = 0; i < priv->num_rx_queues; i++) {
268 rx_queue = priv->rx_queue[i];
269 rx_queue->rx_bd_base = vaddr;
270 rx_queue->rx_bd_dma_base = addr;
271 rx_queue->dev = ndev;
272 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
273 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
274 }
275
276 /* Setup the skbuff rings */
277 for (i = 0; i < priv->num_tx_queues; i++) {
278 tx_queue = priv->tx_queue[i];
279 tx_queue->tx_skbuff =
280 kmalloc_array(tx_queue->tx_ring_size,
281 sizeof(*tx_queue->tx_skbuff),
282 GFP_KERNEL);
283 if (!tx_queue->tx_skbuff)
284 goto cleanup;
285
286 for (k = 0; k < tx_queue->tx_ring_size; k++)
287 tx_queue->tx_skbuff[k] = NULL;
288 }
289
290 for (i = 0; i < priv->num_rx_queues; i++) {
291 rx_queue = priv->rx_queue[i];
292 rx_queue->rx_skbuff =
293 kmalloc_array(rx_queue->rx_ring_size,
294 sizeof(*rx_queue->rx_skbuff),
295 GFP_KERNEL);
296 if (!rx_queue->rx_skbuff)
297 goto cleanup;
298
299 for (j = 0; j < rx_queue->rx_ring_size; j++)
300 rx_queue->rx_skbuff[j] = NULL;
301 }
302
303 if (gfar_init_bds(ndev))
304 goto cleanup;
305
306 return 0;
307
308 cleanup:
309 free_skb_resources(priv);
310 return -ENOMEM;
311 }
312
313 static void gfar_init_tx_rx_base(struct gfar_private *priv)
314 {
315 struct gfar __iomem *regs = priv->gfargrp[0].regs;
316 u32 __iomem *baddr;
317 int i;
318
319 baddr = &regs->tbase0;
320 for (i = 0; i < priv->num_tx_queues; i++) {
321 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
322 baddr += 2;
323 }
324
325 baddr = &regs->rbase0;
326 for (i = 0; i < priv->num_rx_queues; i++) {
327 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
328 baddr += 2;
329 }
330 }
331
332 static void gfar_init_mac(struct net_device *ndev)
333 {
334 struct gfar_private *priv = netdev_priv(ndev);
335 struct gfar __iomem *regs = priv->gfargrp[0].regs;
336 u32 rctrl = 0;
337 u32 tctrl = 0;
338 u32 attrs = 0;
339
340 /* write the tx/rx base registers */
341 gfar_init_tx_rx_base(priv);
342
343 /* Configure the coalescing support */
344 gfar_configure_coalescing_all(priv);
345
346 /* set this when rx hw offload (TOE) functions are being used */
347 priv->uses_rxfcb = 0;
348
349 if (priv->rx_filer_enable) {
350 rctrl |= RCTRL_FILREN;
351 /* Program the RIR0 reg with the required distribution */
352 gfar_write(&regs->rir0, DEFAULT_RIR0);
353 }
354
355 /* Restore PROMISC mode */
356 if (ndev->flags & IFF_PROMISC)
357 rctrl |= RCTRL_PROM;
358
359 if (ndev->features & NETIF_F_RXCSUM) {
360 rctrl |= RCTRL_CHECKSUMMING;
361 priv->uses_rxfcb = 1;
362 }
363
364 if (priv->extended_hash) {
365 rctrl |= RCTRL_EXTHASH;
366
367 gfar_clear_exact_match(ndev);
368 rctrl |= RCTRL_EMEN;
369 }
370
371 if (priv->padding) {
372 rctrl &= ~RCTRL_PAL_MASK;
373 rctrl |= RCTRL_PADDING(priv->padding);
374 }
375
376 /* Insert receive time stamps into padding alignment bytes */
377 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
378 rctrl &= ~RCTRL_PAL_MASK;
379 rctrl |= RCTRL_PADDING(8);
380 priv->padding = 8;
381 }
382
383 /* Enable HW time stamping if requested from user space */
384 if (priv->hwts_rx_en) {
385 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
386 priv->uses_rxfcb = 1;
387 }
388
389 if (ndev->features & NETIF_F_HW_VLAN_RX) {
390 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
391 priv->uses_rxfcb = 1;
392 }
393
394 /* Init rctrl based on our settings */
395 gfar_write(&regs->rctrl, rctrl);
396
397 if (ndev->features & NETIF_F_IP_CSUM)
398 tctrl |= TCTRL_INIT_CSUM;
399
400 if (priv->prio_sched_en)
401 tctrl |= TCTRL_TXSCHED_PRIO;
402 else {
403 tctrl |= TCTRL_TXSCHED_WRRS;
404 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
405 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
406 }
407
408 gfar_write(&regs->tctrl, tctrl);
409
410 /* Set the extraction length and index */
411 attrs = ATTRELI_EL(priv->rx_stash_size) |
412 ATTRELI_EI(priv->rx_stash_index);
413
414 gfar_write(&regs->attreli, attrs);
415
416 /* Start with defaults, and add stashing or locking
417 * depending on the approprate variables
418 */
419 attrs = ATTR_INIT_SETTINGS;
420
421 if (priv->bd_stash_en)
422 attrs |= ATTR_BDSTASH;
423
424 if (priv->rx_stash_size != 0)
425 attrs |= ATTR_BUFSTASH;
426
427 gfar_write(&regs->attr, attrs);
428
429 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
430 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
431 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
432 }
433
434 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
435 {
436 struct gfar_private *priv = netdev_priv(dev);
437 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
438 unsigned long tx_packets = 0, tx_bytes = 0;
439 int i;
440
441 for (i = 0; i < priv->num_rx_queues; i++) {
442 rx_packets += priv->rx_queue[i]->stats.rx_packets;
443 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
444 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
445 }
446
447 dev->stats.rx_packets = rx_packets;
448 dev->stats.rx_bytes = rx_bytes;
449 dev->stats.rx_dropped = rx_dropped;
450
451 for (i = 0; i < priv->num_tx_queues; i++) {
452 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
453 tx_packets += priv->tx_queue[i]->stats.tx_packets;
454 }
455
456 dev->stats.tx_bytes = tx_bytes;
457 dev->stats.tx_packets = tx_packets;
458
459 return &dev->stats;
460 }
461
462 static const struct net_device_ops gfar_netdev_ops = {
463 .ndo_open = gfar_enet_open,
464 .ndo_start_xmit = gfar_start_xmit,
465 .ndo_stop = gfar_close,
466 .ndo_change_mtu = gfar_change_mtu,
467 .ndo_set_features = gfar_set_features,
468 .ndo_set_rx_mode = gfar_set_multi,
469 .ndo_tx_timeout = gfar_timeout,
470 .ndo_do_ioctl = gfar_ioctl,
471 .ndo_get_stats = gfar_get_stats,
472 .ndo_set_mac_address = eth_mac_addr,
473 .ndo_validate_addr = eth_validate_addr,
474 #ifdef CONFIG_NET_POLL_CONTROLLER
475 .ndo_poll_controller = gfar_netpoll,
476 #endif
477 };
478
479 void lock_rx_qs(struct gfar_private *priv)
480 {
481 int i;
482
483 for (i = 0; i < priv->num_rx_queues; i++)
484 spin_lock(&priv->rx_queue[i]->rxlock);
485 }
486
487 void lock_tx_qs(struct gfar_private *priv)
488 {
489 int i;
490
491 for (i = 0; i < priv->num_tx_queues; i++)
492 spin_lock(&priv->tx_queue[i]->txlock);
493 }
494
495 void unlock_rx_qs(struct gfar_private *priv)
496 {
497 int i;
498
499 for (i = 0; i < priv->num_rx_queues; i++)
500 spin_unlock(&priv->rx_queue[i]->rxlock);
501 }
502
503 void unlock_tx_qs(struct gfar_private *priv)
504 {
505 int i;
506
507 for (i = 0; i < priv->num_tx_queues; i++)
508 spin_unlock(&priv->tx_queue[i]->txlock);
509 }
510
511 static void free_tx_pointers(struct gfar_private *priv)
512 {
513 int i;
514
515 for (i = 0; i < priv->num_tx_queues; i++)
516 kfree(priv->tx_queue[i]);
517 }
518
519 static void free_rx_pointers(struct gfar_private *priv)
520 {
521 int i;
522
523 for (i = 0; i < priv->num_rx_queues; i++)
524 kfree(priv->rx_queue[i]);
525 }
526
527 static void unmap_group_regs(struct gfar_private *priv)
528 {
529 int i;
530
531 for (i = 0; i < MAXGROUPS; i++)
532 if (priv->gfargrp[i].regs)
533 iounmap(priv->gfargrp[i].regs);
534 }
535
536 static void free_gfar_dev(struct gfar_private *priv)
537 {
538 int i, j;
539
540 for (i = 0; i < priv->num_grps; i++)
541 for (j = 0; j < GFAR_NUM_IRQS; j++) {
542 kfree(priv->gfargrp[i].irqinfo[j]);
543 priv->gfargrp[i].irqinfo[j] = NULL;
544 }
545
546 free_netdev(priv->ndev);
547 }
548
549 static void disable_napi(struct gfar_private *priv)
550 {
551 int i;
552
553 for (i = 0; i < priv->num_grps; i++)
554 napi_disable(&priv->gfargrp[i].napi);
555 }
556
557 static void enable_napi(struct gfar_private *priv)
558 {
559 int i;
560
561 for (i = 0; i < priv->num_grps; i++)
562 napi_enable(&priv->gfargrp[i].napi);
563 }
564
565 static int gfar_parse_group(struct device_node *np,
566 struct gfar_private *priv, const char *model)
567 {
568 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
569 u32 *queue_mask;
570 int i;
571
572 for (i = 0; i < GFAR_NUM_IRQS; i++) {
573 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
574 GFP_KERNEL);
575 if (!grp->irqinfo[i])
576 return -ENOMEM;
577 }
578
579 grp->regs = of_iomap(np, 0);
580 if (!grp->regs)
581 return -ENOMEM;
582
583 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
584
585 /* If we aren't the FEC we have multiple interrupts */
586 if (model && strcasecmp(model, "FEC")) {
587 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
588 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
589 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
590 gfar_irq(grp, RX)->irq == NO_IRQ ||
591 gfar_irq(grp, ER)->irq == NO_IRQ)
592 return -EINVAL;
593 }
594
595 grp->grp_id = priv->num_grps;
596 grp->priv = priv;
597 spin_lock_init(&grp->grplock);
598 if (priv->mode == MQ_MG_MODE) {
599 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
600 grp->rx_bit_map = queue_mask ?
601 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
602 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
603 grp->tx_bit_map = queue_mask ?
604 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
605 } else {
606 grp->rx_bit_map = 0xFF;
607 grp->tx_bit_map = 0xFF;
608 }
609 priv->num_grps++;
610
611 return 0;
612 }
613
614 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
615 {
616 const char *model;
617 const char *ctype;
618 const void *mac_addr;
619 int err = 0, i;
620 struct net_device *dev = NULL;
621 struct gfar_private *priv = NULL;
622 struct device_node *np = ofdev->dev.of_node;
623 struct device_node *child = NULL;
624 const u32 *stash;
625 const u32 *stash_len;
626 const u32 *stash_idx;
627 unsigned int num_tx_qs, num_rx_qs;
628 u32 *tx_queues, *rx_queues;
629
630 if (!np || !of_device_is_available(np))
631 return -ENODEV;
632
633 /* parse the num of tx and rx queues */
634 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
635 num_tx_qs = tx_queues ? *tx_queues : 1;
636
637 if (num_tx_qs > MAX_TX_QS) {
638 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
639 num_tx_qs, MAX_TX_QS);
640 pr_err("Cannot do alloc_etherdev, aborting\n");
641 return -EINVAL;
642 }
643
644 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
645 num_rx_qs = rx_queues ? *rx_queues : 1;
646
647 if (num_rx_qs > MAX_RX_QS) {
648 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
649 num_rx_qs, MAX_RX_QS);
650 pr_err("Cannot do alloc_etherdev, aborting\n");
651 return -EINVAL;
652 }
653
654 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
655 dev = *pdev;
656 if (NULL == dev)
657 return -ENOMEM;
658
659 priv = netdev_priv(dev);
660 priv->ndev = dev;
661
662 priv->num_tx_queues = num_tx_qs;
663 netif_set_real_num_rx_queues(dev, num_rx_qs);
664 priv->num_rx_queues = num_rx_qs;
665 priv->num_grps = 0x0;
666
667 /* Init Rx queue filer rule set linked list */
668 INIT_LIST_HEAD(&priv->rx_list.list);
669 priv->rx_list.count = 0;
670 mutex_init(&priv->rx_queue_access);
671
672 model = of_get_property(np, "model", NULL);
673
674 for (i = 0; i < MAXGROUPS; i++)
675 priv->gfargrp[i].regs = NULL;
676
677 /* Parse and initialize group specific information */
678 if (of_device_is_compatible(np, "fsl,etsec2")) {
679 priv->mode = MQ_MG_MODE;
680 for_each_child_of_node(np, child) {
681 err = gfar_parse_group(child, priv, model);
682 if (err)
683 goto err_grp_init;
684 }
685 } else {
686 priv->mode = SQ_SG_MODE;
687 err = gfar_parse_group(np, priv, model);
688 if (err)
689 goto err_grp_init;
690 }
691
692 for (i = 0; i < priv->num_tx_queues; i++)
693 priv->tx_queue[i] = NULL;
694 for (i = 0; i < priv->num_rx_queues; i++)
695 priv->rx_queue[i] = NULL;
696
697 for (i = 0; i < priv->num_tx_queues; i++) {
698 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
699 GFP_KERNEL);
700 if (!priv->tx_queue[i]) {
701 err = -ENOMEM;
702 goto tx_alloc_failed;
703 }
704 priv->tx_queue[i]->tx_skbuff = NULL;
705 priv->tx_queue[i]->qindex = i;
706 priv->tx_queue[i]->dev = dev;
707 spin_lock_init(&(priv->tx_queue[i]->txlock));
708 }
709
710 for (i = 0; i < priv->num_rx_queues; i++) {
711 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
712 GFP_KERNEL);
713 if (!priv->rx_queue[i]) {
714 err = -ENOMEM;
715 goto rx_alloc_failed;
716 }
717 priv->rx_queue[i]->rx_skbuff = NULL;
718 priv->rx_queue[i]->qindex = i;
719 priv->rx_queue[i]->dev = dev;
720 spin_lock_init(&(priv->rx_queue[i]->rxlock));
721 }
722
723
724 stash = of_get_property(np, "bd-stash", NULL);
725
726 if (stash) {
727 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
728 priv->bd_stash_en = 1;
729 }
730
731 stash_len = of_get_property(np, "rx-stash-len", NULL);
732
733 if (stash_len)
734 priv->rx_stash_size = *stash_len;
735
736 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
737
738 if (stash_idx)
739 priv->rx_stash_index = *stash_idx;
740
741 if (stash_len || stash_idx)
742 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
743
744 mac_addr = of_get_mac_address(np);
745
746 if (mac_addr)
747 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
748
749 if (model && !strcasecmp(model, "TSEC"))
750 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
751 FSL_GIANFAR_DEV_HAS_COALESCE |
752 FSL_GIANFAR_DEV_HAS_RMON |
753 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
754
755 if (model && !strcasecmp(model, "eTSEC"))
756 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
757 FSL_GIANFAR_DEV_HAS_COALESCE |
758 FSL_GIANFAR_DEV_HAS_RMON |
759 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
760 FSL_GIANFAR_DEV_HAS_PADDING |
761 FSL_GIANFAR_DEV_HAS_CSUM |
762 FSL_GIANFAR_DEV_HAS_VLAN |
763 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
764 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
765 FSL_GIANFAR_DEV_HAS_TIMER;
766
767 ctype = of_get_property(np, "phy-connection-type", NULL);
768
769 /* We only care about rgmii-id. The rest are autodetected */
770 if (ctype && !strcmp(ctype, "rgmii-id"))
771 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
772 else
773 priv->interface = PHY_INTERFACE_MODE_MII;
774
775 if (of_get_property(np, "fsl,magic-packet", NULL))
776 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
777
778 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
779
780 /* Find the TBI PHY. If it's not there, we don't support SGMII */
781 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
782
783 return 0;
784
785 rx_alloc_failed:
786 free_rx_pointers(priv);
787 tx_alloc_failed:
788 free_tx_pointers(priv);
789 err_grp_init:
790 unmap_group_regs(priv);
791 free_gfar_dev(priv);
792 return err;
793 }
794
795 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
796 struct ifreq *ifr, int cmd)
797 {
798 struct hwtstamp_config config;
799 struct gfar_private *priv = netdev_priv(netdev);
800
801 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
802 return -EFAULT;
803
804 /* reserved for future extensions */
805 if (config.flags)
806 return -EINVAL;
807
808 switch (config.tx_type) {
809 case HWTSTAMP_TX_OFF:
810 priv->hwts_tx_en = 0;
811 break;
812 case HWTSTAMP_TX_ON:
813 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
814 return -ERANGE;
815 priv->hwts_tx_en = 1;
816 break;
817 default:
818 return -ERANGE;
819 }
820
821 switch (config.rx_filter) {
822 case HWTSTAMP_FILTER_NONE:
823 if (priv->hwts_rx_en) {
824 stop_gfar(netdev);
825 priv->hwts_rx_en = 0;
826 startup_gfar(netdev);
827 }
828 break;
829 default:
830 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
831 return -ERANGE;
832 if (!priv->hwts_rx_en) {
833 stop_gfar(netdev);
834 priv->hwts_rx_en = 1;
835 startup_gfar(netdev);
836 }
837 config.rx_filter = HWTSTAMP_FILTER_ALL;
838 break;
839 }
840
841 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
842 -EFAULT : 0;
843 }
844
845 /* Ioctl MII Interface */
846 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
847 {
848 struct gfar_private *priv = netdev_priv(dev);
849
850 if (!netif_running(dev))
851 return -EINVAL;
852
853 if (cmd == SIOCSHWTSTAMP)
854 return gfar_hwtstamp_ioctl(dev, rq, cmd);
855
856 if (!priv->phydev)
857 return -ENODEV;
858
859 return phy_mii_ioctl(priv->phydev, rq, cmd);
860 }
861
862 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
863 {
864 unsigned int new_bit_map = 0x0;
865 int mask = 0x1 << (max_qs - 1), i;
866
867 for (i = 0; i < max_qs; i++) {
868 if (bit_map & mask)
869 new_bit_map = new_bit_map + (1 << i);
870 mask = mask >> 0x1;
871 }
872 return new_bit_map;
873 }
874
875 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
876 u32 class)
877 {
878 u32 rqfpr = FPR_FILER_MASK;
879 u32 rqfcr = 0x0;
880
881 rqfar--;
882 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
883 priv->ftp_rqfpr[rqfar] = rqfpr;
884 priv->ftp_rqfcr[rqfar] = rqfcr;
885 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
886
887 rqfar--;
888 rqfcr = RQFCR_CMP_NOMATCH;
889 priv->ftp_rqfpr[rqfar] = rqfpr;
890 priv->ftp_rqfcr[rqfar] = rqfcr;
891 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
892
893 rqfar--;
894 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
895 rqfpr = class;
896 priv->ftp_rqfcr[rqfar] = rqfcr;
897 priv->ftp_rqfpr[rqfar] = rqfpr;
898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
899
900 rqfar--;
901 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
902 rqfpr = class;
903 priv->ftp_rqfcr[rqfar] = rqfcr;
904 priv->ftp_rqfpr[rqfar] = rqfpr;
905 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
906
907 return rqfar;
908 }
909
910 static void gfar_init_filer_table(struct gfar_private *priv)
911 {
912 int i = 0x0;
913 u32 rqfar = MAX_FILER_IDX;
914 u32 rqfcr = 0x0;
915 u32 rqfpr = FPR_FILER_MASK;
916
917 /* Default rule */
918 rqfcr = RQFCR_CMP_MATCH;
919 priv->ftp_rqfcr[rqfar] = rqfcr;
920 priv->ftp_rqfpr[rqfar] = rqfpr;
921 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
922
923 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
924 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
925 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
926 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
927 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
928 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
929
930 /* cur_filer_idx indicated the first non-masked rule */
931 priv->cur_filer_idx = rqfar;
932
933 /* Rest are masked rules */
934 rqfcr = RQFCR_CMP_NOMATCH;
935 for (i = 0; i < rqfar; i++) {
936 priv->ftp_rqfcr[i] = rqfcr;
937 priv->ftp_rqfpr[i] = rqfpr;
938 gfar_write_filer(priv, i, rqfcr, rqfpr);
939 }
940 }
941
942 static void gfar_detect_errata(struct gfar_private *priv)
943 {
944 struct device *dev = &priv->ofdev->dev;
945 unsigned int pvr = mfspr(SPRN_PVR);
946 unsigned int svr = mfspr(SPRN_SVR);
947 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
948 unsigned int rev = svr & 0xffff;
949
950 /* MPC8313 Rev 2.0 and higher; All MPC837x */
951 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
952 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
953 priv->errata |= GFAR_ERRATA_74;
954
955 /* MPC8313 and MPC837x all rev */
956 if ((pvr == 0x80850010 && mod == 0x80b0) ||
957 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
958 priv->errata |= GFAR_ERRATA_76;
959
960 /* MPC8313 and MPC837x all rev */
961 if ((pvr == 0x80850010 && mod == 0x80b0) ||
962 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
963 priv->errata |= GFAR_ERRATA_A002;
964
965 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
966 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
967 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
968 priv->errata |= GFAR_ERRATA_12;
969
970 if (priv->errata)
971 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
972 priv->errata);
973 }
974
975 /* Set up the ethernet device structure, private data,
976 * and anything else we need before we start
977 */
978 static int gfar_probe(struct platform_device *ofdev)
979 {
980 u32 tempval;
981 struct net_device *dev = NULL;
982 struct gfar_private *priv = NULL;
983 struct gfar __iomem *regs = NULL;
984 int err = 0, i, grp_idx = 0;
985 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
986 u32 isrg = 0;
987 u32 __iomem *baddr;
988
989 err = gfar_of_init(ofdev, &dev);
990
991 if (err)
992 return err;
993
994 priv = netdev_priv(dev);
995 priv->ndev = dev;
996 priv->ofdev = ofdev;
997 priv->dev = &ofdev->dev;
998 SET_NETDEV_DEV(dev, &ofdev->dev);
999
1000 spin_lock_init(&priv->bflock);
1001 INIT_WORK(&priv->reset_task, gfar_reset_task);
1002
1003 dev_set_drvdata(&ofdev->dev, priv);
1004 regs = priv->gfargrp[0].regs;
1005
1006 gfar_detect_errata(priv);
1007
1008 /* Stop the DMA engine now, in case it was running before
1009 * (The firmware could have used it, and left it running).
1010 */
1011 gfar_halt(dev);
1012
1013 /* Reset MAC layer */
1014 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1015
1016 /* We need to delay at least 3 TX clocks */
1017 udelay(2);
1018
1019 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1020 gfar_write(&regs->maccfg1, tempval);
1021
1022 /* Initialize MACCFG2. */
1023 tempval = MACCFG2_INIT_SETTINGS;
1024 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1025 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1026 gfar_write(&regs->maccfg2, tempval);
1027
1028 /* Initialize ECNTRL */
1029 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1030
1031 /* Set the dev->base_addr to the gfar reg region */
1032 dev->base_addr = (unsigned long) regs;
1033
1034 /* Fill in the dev structure */
1035 dev->watchdog_timeo = TX_TIMEOUT;
1036 dev->mtu = 1500;
1037 dev->netdev_ops = &gfar_netdev_ops;
1038 dev->ethtool_ops = &gfar_ethtool_ops;
1039
1040 /* Register for napi ...We are registering NAPI for each grp */
1041 for (i = 0; i < priv->num_grps; i++)
1042 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1043 GFAR_DEV_WEIGHT);
1044
1045 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1046 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1047 NETIF_F_RXCSUM;
1048 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1049 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1050 }
1051
1052 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1053 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1054 dev->features |= NETIF_F_HW_VLAN_RX;
1055 }
1056
1057 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1058 priv->extended_hash = 1;
1059 priv->hash_width = 9;
1060
1061 priv->hash_regs[0] = &regs->igaddr0;
1062 priv->hash_regs[1] = &regs->igaddr1;
1063 priv->hash_regs[2] = &regs->igaddr2;
1064 priv->hash_regs[3] = &regs->igaddr3;
1065 priv->hash_regs[4] = &regs->igaddr4;
1066 priv->hash_regs[5] = &regs->igaddr5;
1067 priv->hash_regs[6] = &regs->igaddr6;
1068 priv->hash_regs[7] = &regs->igaddr7;
1069 priv->hash_regs[8] = &regs->gaddr0;
1070 priv->hash_regs[9] = &regs->gaddr1;
1071 priv->hash_regs[10] = &regs->gaddr2;
1072 priv->hash_regs[11] = &regs->gaddr3;
1073 priv->hash_regs[12] = &regs->gaddr4;
1074 priv->hash_regs[13] = &regs->gaddr5;
1075 priv->hash_regs[14] = &regs->gaddr6;
1076 priv->hash_regs[15] = &regs->gaddr7;
1077
1078 } else {
1079 priv->extended_hash = 0;
1080 priv->hash_width = 8;
1081
1082 priv->hash_regs[0] = &regs->gaddr0;
1083 priv->hash_regs[1] = &regs->gaddr1;
1084 priv->hash_regs[2] = &regs->gaddr2;
1085 priv->hash_regs[3] = &regs->gaddr3;
1086 priv->hash_regs[4] = &regs->gaddr4;
1087 priv->hash_regs[5] = &regs->gaddr5;
1088 priv->hash_regs[6] = &regs->gaddr6;
1089 priv->hash_regs[7] = &regs->gaddr7;
1090 }
1091
1092 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1093 priv->padding = DEFAULT_PADDING;
1094 else
1095 priv->padding = 0;
1096
1097 if (dev->features & NETIF_F_IP_CSUM ||
1098 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1099 dev->needed_headroom = GMAC_FCB_LEN;
1100
1101 /* Program the isrg regs only if number of grps > 1 */
1102 if (priv->num_grps > 1) {
1103 baddr = &regs->isrg0;
1104 for (i = 0; i < priv->num_grps; i++) {
1105 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1106 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1107 gfar_write(baddr, isrg);
1108 baddr++;
1109 isrg = 0x0;
1110 }
1111 }
1112
1113 /* Need to reverse the bit maps as bit_map's MSB is q0
1114 * but, for_each_set_bit parses from right to left, which
1115 * basically reverses the queue numbers
1116 */
1117 for (i = 0; i< priv->num_grps; i++) {
1118 priv->gfargrp[i].tx_bit_map =
1119 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1120 priv->gfargrp[i].rx_bit_map =
1121 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1122 }
1123
1124 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1125 * also assign queues to groups
1126 */
1127 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1128 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1129
1130 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1131 priv->num_rx_queues) {
1132 priv->gfargrp[grp_idx].num_rx_queues++;
1133 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1134 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1135 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1136 }
1137 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1138
1139 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1140 priv->num_tx_queues) {
1141 priv->gfargrp[grp_idx].num_tx_queues++;
1142 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1143 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1144 tqueue = tqueue | (TQUEUE_EN0 >> i);
1145 }
1146 priv->gfargrp[grp_idx].rstat = rstat;
1147 priv->gfargrp[grp_idx].tstat = tstat;
1148 rstat = tstat =0;
1149 }
1150
1151 gfar_write(&regs->rqueue, rqueue);
1152 gfar_write(&regs->tqueue, tqueue);
1153
1154 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1155
1156 /* Initializing some of the rx/tx queue level parameters */
1157 for (i = 0; i < priv->num_tx_queues; i++) {
1158 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1159 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1160 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1161 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1162 }
1163
1164 for (i = 0; i < priv->num_rx_queues; i++) {
1165 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1166 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1167 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1168 }
1169
1170 /* always enable rx filer */
1171 priv->rx_filer_enable = 1;
1172 /* Enable most messages by default */
1173 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1174 /* use pritority h/w tx queue scheduling for single queue devices */
1175 if (priv->num_tx_queues == 1)
1176 priv->prio_sched_en = 1;
1177
1178 /* Carrier starts down, phylib will bring it up */
1179 netif_carrier_off(dev);
1180
1181 err = register_netdev(dev);
1182
1183 if (err) {
1184 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1185 goto register_fail;
1186 }
1187
1188 device_init_wakeup(&dev->dev,
1189 priv->device_flags &
1190 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1191
1192 /* fill out IRQ number and name fields */
1193 for (i = 0; i < priv->num_grps; i++) {
1194 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1195 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1196 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1197 dev->name, "_g", '0' + i, "_tx");
1198 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1199 dev->name, "_g", '0' + i, "_rx");
1200 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1201 dev->name, "_g", '0' + i, "_er");
1202 } else
1203 strcpy(gfar_irq(grp, TX)->name, dev->name);
1204 }
1205
1206 /* Initialize the filer table */
1207 gfar_init_filer_table(priv);
1208
1209 /* Create all the sysfs files */
1210 gfar_init_sysfs(dev);
1211
1212 /* Print out the device info */
1213 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1214
1215 /* Even more device info helps when determining which kernel
1216 * provided which set of benchmarks.
1217 */
1218 netdev_info(dev, "Running with NAPI enabled\n");
1219 for (i = 0; i < priv->num_rx_queues; i++)
1220 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1221 i, priv->rx_queue[i]->rx_ring_size);
1222 for (i = 0; i < priv->num_tx_queues; i++)
1223 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1224 i, priv->tx_queue[i]->tx_ring_size);
1225
1226 return 0;
1227
1228 register_fail:
1229 unmap_group_regs(priv);
1230 free_tx_pointers(priv);
1231 free_rx_pointers(priv);
1232 if (priv->phy_node)
1233 of_node_put(priv->phy_node);
1234 if (priv->tbi_node)
1235 of_node_put(priv->tbi_node);
1236 free_gfar_dev(priv);
1237 return err;
1238 }
1239
1240 static int gfar_remove(struct platform_device *ofdev)
1241 {
1242 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1243
1244 if (priv->phy_node)
1245 of_node_put(priv->phy_node);
1246 if (priv->tbi_node)
1247 of_node_put(priv->tbi_node);
1248
1249 dev_set_drvdata(&ofdev->dev, NULL);
1250
1251 unregister_netdev(priv->ndev);
1252 unmap_group_regs(priv);
1253 free_gfar_dev(priv);
1254
1255 return 0;
1256 }
1257
1258 #ifdef CONFIG_PM
1259
1260 static int gfar_suspend(struct device *dev)
1261 {
1262 struct gfar_private *priv = dev_get_drvdata(dev);
1263 struct net_device *ndev = priv->ndev;
1264 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1265 unsigned long flags;
1266 u32 tempval;
1267
1268 int magic_packet = priv->wol_en &&
1269 (priv->device_flags &
1270 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1271
1272 netif_device_detach(ndev);
1273
1274 if (netif_running(ndev)) {
1275
1276 local_irq_save(flags);
1277 lock_tx_qs(priv);
1278 lock_rx_qs(priv);
1279
1280 gfar_halt_nodisable(ndev);
1281
1282 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1283 tempval = gfar_read(&regs->maccfg1);
1284
1285 tempval &= ~MACCFG1_TX_EN;
1286
1287 if (!magic_packet)
1288 tempval &= ~MACCFG1_RX_EN;
1289
1290 gfar_write(&regs->maccfg1, tempval);
1291
1292 unlock_rx_qs(priv);
1293 unlock_tx_qs(priv);
1294 local_irq_restore(flags);
1295
1296 disable_napi(priv);
1297
1298 if (magic_packet) {
1299 /* Enable interrupt on Magic Packet */
1300 gfar_write(&regs->imask, IMASK_MAG);
1301
1302 /* Enable Magic Packet mode */
1303 tempval = gfar_read(&regs->maccfg2);
1304 tempval |= MACCFG2_MPEN;
1305 gfar_write(&regs->maccfg2, tempval);
1306 } else {
1307 phy_stop(priv->phydev);
1308 }
1309 }
1310
1311 return 0;
1312 }
1313
1314 static int gfar_resume(struct device *dev)
1315 {
1316 struct gfar_private *priv = dev_get_drvdata(dev);
1317 struct net_device *ndev = priv->ndev;
1318 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1319 unsigned long flags;
1320 u32 tempval;
1321 int magic_packet = priv->wol_en &&
1322 (priv->device_flags &
1323 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1324
1325 if (!netif_running(ndev)) {
1326 netif_device_attach(ndev);
1327 return 0;
1328 }
1329
1330 if (!magic_packet && priv->phydev)
1331 phy_start(priv->phydev);
1332
1333 /* Disable Magic Packet mode, in case something
1334 * else woke us up.
1335 */
1336 local_irq_save(flags);
1337 lock_tx_qs(priv);
1338 lock_rx_qs(priv);
1339
1340 tempval = gfar_read(&regs->maccfg2);
1341 tempval &= ~MACCFG2_MPEN;
1342 gfar_write(&regs->maccfg2, tempval);
1343
1344 gfar_start(ndev);
1345
1346 unlock_rx_qs(priv);
1347 unlock_tx_qs(priv);
1348 local_irq_restore(flags);
1349
1350 netif_device_attach(ndev);
1351
1352 enable_napi(priv);
1353
1354 return 0;
1355 }
1356
1357 static int gfar_restore(struct device *dev)
1358 {
1359 struct gfar_private *priv = dev_get_drvdata(dev);
1360 struct net_device *ndev = priv->ndev;
1361
1362 if (!netif_running(ndev)) {
1363 netif_device_attach(ndev);
1364
1365 return 0;
1366 }
1367
1368 if (gfar_init_bds(ndev)) {
1369 free_skb_resources(priv);
1370 return -ENOMEM;
1371 }
1372
1373 init_registers(ndev);
1374 gfar_set_mac_address(ndev);
1375 gfar_init_mac(ndev);
1376 gfar_start(ndev);
1377
1378 priv->oldlink = 0;
1379 priv->oldspeed = 0;
1380 priv->oldduplex = -1;
1381
1382 if (priv->phydev)
1383 phy_start(priv->phydev);
1384
1385 netif_device_attach(ndev);
1386 enable_napi(priv);
1387
1388 return 0;
1389 }
1390
1391 static struct dev_pm_ops gfar_pm_ops = {
1392 .suspend = gfar_suspend,
1393 .resume = gfar_resume,
1394 .freeze = gfar_suspend,
1395 .thaw = gfar_resume,
1396 .restore = gfar_restore,
1397 };
1398
1399 #define GFAR_PM_OPS (&gfar_pm_ops)
1400
1401 #else
1402
1403 #define GFAR_PM_OPS NULL
1404
1405 #endif
1406
1407 /* Reads the controller's registers to determine what interface
1408 * connects it to the PHY.
1409 */
1410 static phy_interface_t gfar_get_interface(struct net_device *dev)
1411 {
1412 struct gfar_private *priv = netdev_priv(dev);
1413 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1414 u32 ecntrl;
1415
1416 ecntrl = gfar_read(&regs->ecntrl);
1417
1418 if (ecntrl & ECNTRL_SGMII_MODE)
1419 return PHY_INTERFACE_MODE_SGMII;
1420
1421 if (ecntrl & ECNTRL_TBI_MODE) {
1422 if (ecntrl & ECNTRL_REDUCED_MODE)
1423 return PHY_INTERFACE_MODE_RTBI;
1424 else
1425 return PHY_INTERFACE_MODE_TBI;
1426 }
1427
1428 if (ecntrl & ECNTRL_REDUCED_MODE) {
1429 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1430 return PHY_INTERFACE_MODE_RMII;
1431 }
1432 else {
1433 phy_interface_t interface = priv->interface;
1434
1435 /* This isn't autodetected right now, so it must
1436 * be set by the device tree or platform code.
1437 */
1438 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1439 return PHY_INTERFACE_MODE_RGMII_ID;
1440
1441 return PHY_INTERFACE_MODE_RGMII;
1442 }
1443 }
1444
1445 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1446 return PHY_INTERFACE_MODE_GMII;
1447
1448 return PHY_INTERFACE_MODE_MII;
1449 }
1450
1451
1452 /* Initializes driver's PHY state, and attaches to the PHY.
1453 * Returns 0 on success.
1454 */
1455 static int init_phy(struct net_device *dev)
1456 {
1457 struct gfar_private *priv = netdev_priv(dev);
1458 uint gigabit_support =
1459 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1460 SUPPORTED_1000baseT_Full : 0;
1461 phy_interface_t interface;
1462
1463 priv->oldlink = 0;
1464 priv->oldspeed = 0;
1465 priv->oldduplex = -1;
1466
1467 interface = gfar_get_interface(dev);
1468
1469 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1470 interface);
1471 if (!priv->phydev)
1472 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1473 interface);
1474 if (!priv->phydev) {
1475 dev_err(&dev->dev, "could not attach to PHY\n");
1476 return -ENODEV;
1477 }
1478
1479 if (interface == PHY_INTERFACE_MODE_SGMII)
1480 gfar_configure_serdes(dev);
1481
1482 /* Remove any features not supported by the controller */
1483 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1484 priv->phydev->advertising = priv->phydev->supported;
1485
1486 return 0;
1487 }
1488
1489 /* Initialize TBI PHY interface for communicating with the
1490 * SERDES lynx PHY on the chip. We communicate with this PHY
1491 * through the MDIO bus on each controller, treating it as a
1492 * "normal" PHY at the address found in the TBIPA register. We assume
1493 * that the TBIPA register is valid. Either the MDIO bus code will set
1494 * it to a value that doesn't conflict with other PHYs on the bus, or the
1495 * value doesn't matter, as there are no other PHYs on the bus.
1496 */
1497 static void gfar_configure_serdes(struct net_device *dev)
1498 {
1499 struct gfar_private *priv = netdev_priv(dev);
1500 struct phy_device *tbiphy;
1501
1502 if (!priv->tbi_node) {
1503 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1504 "device tree specify a tbi-handle\n");
1505 return;
1506 }
1507
1508 tbiphy = of_phy_find_device(priv->tbi_node);
1509 if (!tbiphy) {
1510 dev_err(&dev->dev, "error: Could not get TBI device\n");
1511 return;
1512 }
1513
1514 /* If the link is already up, we must already be ok, and don't need to
1515 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1516 * everything for us? Resetting it takes the link down and requires
1517 * several seconds for it to come back.
1518 */
1519 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1520 return;
1521
1522 /* Single clk mode, mii mode off(for serdes communication) */
1523 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1524
1525 phy_write(tbiphy, MII_ADVERTISE,
1526 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1527 ADVERTISE_1000XPSE_ASYM);
1528
1529 phy_write(tbiphy, MII_BMCR,
1530 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1531 BMCR_SPEED1000);
1532 }
1533
1534 static void init_registers(struct net_device *dev)
1535 {
1536 struct gfar_private *priv = netdev_priv(dev);
1537 struct gfar __iomem *regs = NULL;
1538 int i;
1539
1540 for (i = 0; i < priv->num_grps; i++) {
1541 regs = priv->gfargrp[i].regs;
1542 /* Clear IEVENT */
1543 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1544
1545 /* Initialize IMASK */
1546 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1547 }
1548
1549 regs = priv->gfargrp[0].regs;
1550 /* Init hash registers to zero */
1551 gfar_write(&regs->igaddr0, 0);
1552 gfar_write(&regs->igaddr1, 0);
1553 gfar_write(&regs->igaddr2, 0);
1554 gfar_write(&regs->igaddr3, 0);
1555 gfar_write(&regs->igaddr4, 0);
1556 gfar_write(&regs->igaddr5, 0);
1557 gfar_write(&regs->igaddr6, 0);
1558 gfar_write(&regs->igaddr7, 0);
1559
1560 gfar_write(&regs->gaddr0, 0);
1561 gfar_write(&regs->gaddr1, 0);
1562 gfar_write(&regs->gaddr2, 0);
1563 gfar_write(&regs->gaddr3, 0);
1564 gfar_write(&regs->gaddr4, 0);
1565 gfar_write(&regs->gaddr5, 0);
1566 gfar_write(&regs->gaddr6, 0);
1567 gfar_write(&regs->gaddr7, 0);
1568
1569 /* Zero out the rmon mib registers if it has them */
1570 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1571 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1572
1573 /* Mask off the CAM interrupts */
1574 gfar_write(&regs->rmon.cam1, 0xffffffff);
1575 gfar_write(&regs->rmon.cam2, 0xffffffff);
1576 }
1577
1578 /* Initialize the max receive buffer length */
1579 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1580
1581 /* Initialize the Minimum Frame Length Register */
1582 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1583 }
1584
1585 static int __gfar_is_rx_idle(struct gfar_private *priv)
1586 {
1587 u32 res;
1588
1589 /* Normaly TSEC should not hang on GRS commands, so we should
1590 * actually wait for IEVENT_GRSC flag.
1591 */
1592 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1593 return 0;
1594
1595 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1596 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1597 * and the Rx can be safely reset.
1598 */
1599 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1600 res &= 0x7f807f80;
1601 if ((res & 0xffff) == (res >> 16))
1602 return 1;
1603
1604 return 0;
1605 }
1606
1607 /* Halt the receive and transmit queues */
1608 static void gfar_halt_nodisable(struct net_device *dev)
1609 {
1610 struct gfar_private *priv = netdev_priv(dev);
1611 struct gfar __iomem *regs = NULL;
1612 u32 tempval;
1613 int i;
1614
1615 for (i = 0; i < priv->num_grps; i++) {
1616 regs = priv->gfargrp[i].regs;
1617 /* Mask all interrupts */
1618 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1619
1620 /* Clear all interrupts */
1621 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1622 }
1623
1624 regs = priv->gfargrp[0].regs;
1625 /* Stop the DMA, and wait for it to stop */
1626 tempval = gfar_read(&regs->dmactrl);
1627 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1628 (DMACTRL_GRS | DMACTRL_GTS)) {
1629 int ret;
1630
1631 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1632 gfar_write(&regs->dmactrl, tempval);
1633
1634 do {
1635 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1636 (IEVENT_GRSC | IEVENT_GTSC)) ==
1637 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1638 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1639 ret = __gfar_is_rx_idle(priv);
1640 } while (!ret);
1641 }
1642 }
1643
1644 /* Halt the receive and transmit queues */
1645 void gfar_halt(struct net_device *dev)
1646 {
1647 struct gfar_private *priv = netdev_priv(dev);
1648 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1649 u32 tempval;
1650
1651 gfar_halt_nodisable(dev);
1652
1653 /* Disable Rx and Tx */
1654 tempval = gfar_read(&regs->maccfg1);
1655 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1656 gfar_write(&regs->maccfg1, tempval);
1657 }
1658
1659 static void free_grp_irqs(struct gfar_priv_grp *grp)
1660 {
1661 free_irq(gfar_irq(grp, TX)->irq, grp);
1662 free_irq(gfar_irq(grp, RX)->irq, grp);
1663 free_irq(gfar_irq(grp, ER)->irq, grp);
1664 }
1665
1666 void stop_gfar(struct net_device *dev)
1667 {
1668 struct gfar_private *priv = netdev_priv(dev);
1669 unsigned long flags;
1670 int i;
1671
1672 phy_stop(priv->phydev);
1673
1674
1675 /* Lock it down */
1676 local_irq_save(flags);
1677 lock_tx_qs(priv);
1678 lock_rx_qs(priv);
1679
1680 gfar_halt(dev);
1681
1682 unlock_rx_qs(priv);
1683 unlock_tx_qs(priv);
1684 local_irq_restore(flags);
1685
1686 /* Free the IRQs */
1687 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1688 for (i = 0; i < priv->num_grps; i++)
1689 free_grp_irqs(&priv->gfargrp[i]);
1690 } else {
1691 for (i = 0; i < priv->num_grps; i++)
1692 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1693 &priv->gfargrp[i]);
1694 }
1695
1696 free_skb_resources(priv);
1697 }
1698
1699 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1700 {
1701 struct txbd8 *txbdp;
1702 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1703 int i, j;
1704
1705 txbdp = tx_queue->tx_bd_base;
1706
1707 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1708 if (!tx_queue->tx_skbuff[i])
1709 continue;
1710
1711 dma_unmap_single(priv->dev, txbdp->bufPtr,
1712 txbdp->length, DMA_TO_DEVICE);
1713 txbdp->lstatus = 0;
1714 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1715 j++) {
1716 txbdp++;
1717 dma_unmap_page(priv->dev, txbdp->bufPtr,
1718 txbdp->length, DMA_TO_DEVICE);
1719 }
1720 txbdp++;
1721 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1722 tx_queue->tx_skbuff[i] = NULL;
1723 }
1724 kfree(tx_queue->tx_skbuff);
1725 tx_queue->tx_skbuff = NULL;
1726 }
1727
1728 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1729 {
1730 struct rxbd8 *rxbdp;
1731 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1732 int i;
1733
1734 rxbdp = rx_queue->rx_bd_base;
1735
1736 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1737 if (rx_queue->rx_skbuff[i]) {
1738 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1739 priv->rx_buffer_size,
1740 DMA_FROM_DEVICE);
1741 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1742 rx_queue->rx_skbuff[i] = NULL;
1743 }
1744 rxbdp->lstatus = 0;
1745 rxbdp->bufPtr = 0;
1746 rxbdp++;
1747 }
1748 kfree(rx_queue->rx_skbuff);
1749 rx_queue->rx_skbuff = NULL;
1750 }
1751
1752 /* If there are any tx skbs or rx skbs still around, free them.
1753 * Then free tx_skbuff and rx_skbuff
1754 */
1755 static void free_skb_resources(struct gfar_private *priv)
1756 {
1757 struct gfar_priv_tx_q *tx_queue = NULL;
1758 struct gfar_priv_rx_q *rx_queue = NULL;
1759 int i;
1760
1761 /* Go through all the buffer descriptors and free their data buffers */
1762 for (i = 0; i < priv->num_tx_queues; i++) {
1763 struct netdev_queue *txq;
1764
1765 tx_queue = priv->tx_queue[i];
1766 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1767 if (tx_queue->tx_skbuff)
1768 free_skb_tx_queue(tx_queue);
1769 netdev_tx_reset_queue(txq);
1770 }
1771
1772 for (i = 0; i < priv->num_rx_queues; i++) {
1773 rx_queue = priv->rx_queue[i];
1774 if (rx_queue->rx_skbuff)
1775 free_skb_rx_queue(rx_queue);
1776 }
1777
1778 dma_free_coherent(priv->dev,
1779 sizeof(struct txbd8) * priv->total_tx_ring_size +
1780 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1781 priv->tx_queue[0]->tx_bd_base,
1782 priv->tx_queue[0]->tx_bd_dma_base);
1783 }
1784
1785 void gfar_start(struct net_device *dev)
1786 {
1787 struct gfar_private *priv = netdev_priv(dev);
1788 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1789 u32 tempval;
1790 int i = 0;
1791
1792 /* Enable Rx and Tx in MACCFG1 */
1793 tempval = gfar_read(&regs->maccfg1);
1794 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1795 gfar_write(&regs->maccfg1, tempval);
1796
1797 /* Initialize DMACTRL to have WWR and WOP */
1798 tempval = gfar_read(&regs->dmactrl);
1799 tempval |= DMACTRL_INIT_SETTINGS;
1800 gfar_write(&regs->dmactrl, tempval);
1801
1802 /* Make sure we aren't stopped */
1803 tempval = gfar_read(&regs->dmactrl);
1804 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1805 gfar_write(&regs->dmactrl, tempval);
1806
1807 for (i = 0; i < priv->num_grps; i++) {
1808 regs = priv->gfargrp[i].regs;
1809 /* Clear THLT/RHLT, so that the DMA starts polling now */
1810 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1811 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1812 /* Unmask the interrupts we look for */
1813 gfar_write(&regs->imask, IMASK_DEFAULT);
1814 }
1815
1816 dev->trans_start = jiffies; /* prevent tx timeout */
1817 }
1818
1819 static void gfar_configure_coalescing(struct gfar_private *priv,
1820 unsigned long tx_mask, unsigned long rx_mask)
1821 {
1822 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1823 u32 __iomem *baddr;
1824
1825 if (priv->mode == MQ_MG_MODE) {
1826 int i = 0;
1827
1828 baddr = &regs->txic0;
1829 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1830 gfar_write(baddr + i, 0);
1831 if (likely(priv->tx_queue[i]->txcoalescing))
1832 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1833 }
1834
1835 baddr = &regs->rxic0;
1836 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1837 gfar_write(baddr + i, 0);
1838 if (likely(priv->rx_queue[i]->rxcoalescing))
1839 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1840 }
1841 } else {
1842 /* Backward compatible case -- even if we enable
1843 * multiple queues, there's only single reg to program
1844 */
1845 gfar_write(&regs->txic, 0);
1846 if (likely(priv->tx_queue[0]->txcoalescing))
1847 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1848
1849 gfar_write(&regs->rxic, 0);
1850 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1851 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1852 }
1853 }
1854
1855 void gfar_configure_coalescing_all(struct gfar_private *priv)
1856 {
1857 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1858 }
1859
1860 static int register_grp_irqs(struct gfar_priv_grp *grp)
1861 {
1862 struct gfar_private *priv = grp->priv;
1863 struct net_device *dev = priv->ndev;
1864 int err;
1865
1866 /* If the device has multiple interrupts, register for
1867 * them. Otherwise, only register for the one
1868 */
1869 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1870 /* Install our interrupt handlers for Error,
1871 * Transmit, and Receive
1872 */
1873 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1874 gfar_irq(grp, ER)->name, grp);
1875 if (err < 0) {
1876 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1877 gfar_irq(grp, ER)->irq);
1878
1879 goto err_irq_fail;
1880 }
1881 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1882 gfar_irq(grp, TX)->name, grp);
1883 if (err < 0) {
1884 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1885 gfar_irq(grp, TX)->irq);
1886 goto tx_irq_fail;
1887 }
1888 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1889 gfar_irq(grp, RX)->name, grp);
1890 if (err < 0) {
1891 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1892 gfar_irq(grp, RX)->irq);
1893 goto rx_irq_fail;
1894 }
1895 } else {
1896 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1897 gfar_irq(grp, TX)->name, grp);
1898 if (err < 0) {
1899 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1900 gfar_irq(grp, TX)->irq);
1901 goto err_irq_fail;
1902 }
1903 }
1904
1905 return 0;
1906
1907 rx_irq_fail:
1908 free_irq(gfar_irq(grp, TX)->irq, grp);
1909 tx_irq_fail:
1910 free_irq(gfar_irq(grp, ER)->irq, grp);
1911 err_irq_fail:
1912 return err;
1913
1914 }
1915
1916 /* Bring the controller up and running */
1917 int startup_gfar(struct net_device *ndev)
1918 {
1919 struct gfar_private *priv = netdev_priv(ndev);
1920 struct gfar __iomem *regs = NULL;
1921 int err, i, j;
1922
1923 for (i = 0; i < priv->num_grps; i++) {
1924 regs= priv->gfargrp[i].regs;
1925 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1926 }
1927
1928 regs= priv->gfargrp[0].regs;
1929 err = gfar_alloc_skb_resources(ndev);
1930 if (err)
1931 return err;
1932
1933 gfar_init_mac(ndev);
1934
1935 for (i = 0; i < priv->num_grps; i++) {
1936 err = register_grp_irqs(&priv->gfargrp[i]);
1937 if (err) {
1938 for (j = 0; j < i; j++)
1939 free_grp_irqs(&priv->gfargrp[j]);
1940 goto irq_fail;
1941 }
1942 }
1943
1944 /* Start the controller */
1945 gfar_start(ndev);
1946
1947 phy_start(priv->phydev);
1948
1949 gfar_configure_coalescing_all(priv);
1950
1951 return 0;
1952
1953 irq_fail:
1954 free_skb_resources(priv);
1955 return err;
1956 }
1957
1958 /* Called when something needs to use the ethernet device
1959 * Returns 0 for success.
1960 */
1961 static int gfar_enet_open(struct net_device *dev)
1962 {
1963 struct gfar_private *priv = netdev_priv(dev);
1964 int err;
1965
1966 enable_napi(priv);
1967
1968 /* Initialize a bunch of registers */
1969 init_registers(dev);
1970
1971 gfar_set_mac_address(dev);
1972
1973 err = init_phy(dev);
1974
1975 if (err) {
1976 disable_napi(priv);
1977 return err;
1978 }
1979
1980 err = startup_gfar(dev);
1981 if (err) {
1982 disable_napi(priv);
1983 return err;
1984 }
1985
1986 netif_tx_start_all_queues(dev);
1987
1988 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1989
1990 return err;
1991 }
1992
1993 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1994 {
1995 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1996
1997 memset(fcb, 0, GMAC_FCB_LEN);
1998
1999 return fcb;
2000 }
2001
2002 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2003 int fcb_length)
2004 {
2005 /* If we're here, it's a IP packet with a TCP or UDP
2006 * payload. We set it to checksum, using a pseudo-header
2007 * we provide
2008 */
2009 u8 flags = TXFCB_DEFAULT;
2010
2011 /* Tell the controller what the protocol is
2012 * And provide the already calculated phcs
2013 */
2014 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2015 flags |= TXFCB_UDP;
2016 fcb->phcs = udp_hdr(skb)->check;
2017 } else
2018 fcb->phcs = tcp_hdr(skb)->check;
2019
2020 /* l3os is the distance between the start of the
2021 * frame (skb->data) and the start of the IP hdr.
2022 * l4os is the distance between the start of the
2023 * l3 hdr and the l4 hdr
2024 */
2025 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2026 fcb->l4os = skb_network_header_len(skb);
2027
2028 fcb->flags = flags;
2029 }
2030
2031 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2032 {
2033 fcb->flags |= TXFCB_VLN;
2034 fcb->vlctl = vlan_tx_tag_get(skb);
2035 }
2036
2037 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2038 struct txbd8 *base, int ring_size)
2039 {
2040 struct txbd8 *new_bd = bdp + stride;
2041
2042 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2043 }
2044
2045 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2046 int ring_size)
2047 {
2048 return skip_txbd(bdp, 1, base, ring_size);
2049 }
2050
2051 /* This is called by the kernel when a frame is ready for transmission.
2052 * It is pointed to by the dev->hard_start_xmit function pointer
2053 */
2054 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2055 {
2056 struct gfar_private *priv = netdev_priv(dev);
2057 struct gfar_priv_tx_q *tx_queue = NULL;
2058 struct netdev_queue *txq;
2059 struct gfar __iomem *regs = NULL;
2060 struct txfcb *fcb = NULL;
2061 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2062 u32 lstatus;
2063 int i, rq = 0, do_tstamp = 0;
2064 u32 bufaddr;
2065 unsigned long flags;
2066 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2067
2068 /* TOE=1 frames larger than 2500 bytes may see excess delays
2069 * before start of transmission.
2070 */
2071 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2072 skb->ip_summed == CHECKSUM_PARTIAL &&
2073 skb->len > 2500)) {
2074 int ret;
2075
2076 ret = skb_checksum_help(skb);
2077 if (ret)
2078 return ret;
2079 }
2080
2081 rq = skb->queue_mapping;
2082 tx_queue = priv->tx_queue[rq];
2083 txq = netdev_get_tx_queue(dev, rq);
2084 base = tx_queue->tx_bd_base;
2085 regs = tx_queue->grp->regs;
2086
2087 /* check if time stamp should be generated */
2088 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2089 priv->hwts_tx_en)) {
2090 do_tstamp = 1;
2091 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2092 }
2093
2094 /* make space for additional header when fcb is needed */
2095 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2096 vlan_tx_tag_present(skb) ||
2097 unlikely(do_tstamp)) &&
2098 (skb_headroom(skb) < fcb_length)) {
2099 struct sk_buff *skb_new;
2100
2101 skb_new = skb_realloc_headroom(skb, fcb_length);
2102 if (!skb_new) {
2103 dev->stats.tx_errors++;
2104 kfree_skb(skb);
2105 return NETDEV_TX_OK;
2106 }
2107
2108 if (skb->sk)
2109 skb_set_owner_w(skb_new, skb->sk);
2110 consume_skb(skb);
2111 skb = skb_new;
2112 }
2113
2114 /* total number of fragments in the SKB */
2115 nr_frags = skb_shinfo(skb)->nr_frags;
2116
2117 /* calculate the required number of TxBDs for this skb */
2118 if (unlikely(do_tstamp))
2119 nr_txbds = nr_frags + 2;
2120 else
2121 nr_txbds = nr_frags + 1;
2122
2123 /* check if there is space to queue this packet */
2124 if (nr_txbds > tx_queue->num_txbdfree) {
2125 /* no space, stop the queue */
2126 netif_tx_stop_queue(txq);
2127 dev->stats.tx_fifo_errors++;
2128 return NETDEV_TX_BUSY;
2129 }
2130
2131 /* Update transmit stats */
2132 tx_queue->stats.tx_bytes += skb->len;
2133 tx_queue->stats.tx_packets++;
2134
2135 txbdp = txbdp_start = tx_queue->cur_tx;
2136 lstatus = txbdp->lstatus;
2137
2138 /* Time stamp insertion requires one additional TxBD */
2139 if (unlikely(do_tstamp))
2140 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2141 tx_queue->tx_ring_size);
2142
2143 if (nr_frags == 0) {
2144 if (unlikely(do_tstamp))
2145 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2146 TXBD_INTERRUPT);
2147 else
2148 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2149 } else {
2150 /* Place the fragment addresses and lengths into the TxBDs */
2151 for (i = 0; i < nr_frags; i++) {
2152 /* Point at the next BD, wrapping as needed */
2153 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2154
2155 length = skb_shinfo(skb)->frags[i].size;
2156
2157 lstatus = txbdp->lstatus | length |
2158 BD_LFLAG(TXBD_READY);
2159
2160 /* Handle the last BD specially */
2161 if (i == nr_frags - 1)
2162 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2163
2164 bufaddr = skb_frag_dma_map(priv->dev,
2165 &skb_shinfo(skb)->frags[i],
2166 0,
2167 length,
2168 DMA_TO_DEVICE);
2169
2170 /* set the TxBD length and buffer pointer */
2171 txbdp->bufPtr = bufaddr;
2172 txbdp->lstatus = lstatus;
2173 }
2174
2175 lstatus = txbdp_start->lstatus;
2176 }
2177
2178 /* Add TxPAL between FCB and frame if required */
2179 if (unlikely(do_tstamp)) {
2180 skb_push(skb, GMAC_TXPAL_LEN);
2181 memset(skb->data, 0, GMAC_TXPAL_LEN);
2182 }
2183
2184 /* Set up checksumming */
2185 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2186 fcb = gfar_add_fcb(skb);
2187 /* as specified by errata */
2188 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2189 ((unsigned long)fcb % 0x20) > 0x18)) {
2190 __skb_pull(skb, GMAC_FCB_LEN);
2191 skb_checksum_help(skb);
2192 } else {
2193 lstatus |= BD_LFLAG(TXBD_TOE);
2194 gfar_tx_checksum(skb, fcb, fcb_length);
2195 }
2196 }
2197
2198 if (vlan_tx_tag_present(skb)) {
2199 if (unlikely(NULL == fcb)) {
2200 fcb = gfar_add_fcb(skb);
2201 lstatus |= BD_LFLAG(TXBD_TOE);
2202 }
2203
2204 gfar_tx_vlan(skb, fcb);
2205 }
2206
2207 /* Setup tx hardware time stamping if requested */
2208 if (unlikely(do_tstamp)) {
2209 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2210 if (fcb == NULL)
2211 fcb = gfar_add_fcb(skb);
2212 fcb->ptp = 1;
2213 lstatus |= BD_LFLAG(TXBD_TOE);
2214 }
2215
2216 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2217 skb_headlen(skb), DMA_TO_DEVICE);
2218
2219 /* If time stamping is requested one additional TxBD must be set up. The
2220 * first TxBD points to the FCB and must have a data length of
2221 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2222 * the full frame length.
2223 */
2224 if (unlikely(do_tstamp)) {
2225 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2226 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2227 (skb_headlen(skb) - fcb_length);
2228 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2229 } else {
2230 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2231 }
2232
2233 netdev_tx_sent_queue(txq, skb->len);
2234
2235 /* We can work in parallel with gfar_clean_tx_ring(), except
2236 * when modifying num_txbdfree. Note that we didn't grab the lock
2237 * when we were reading the num_txbdfree and checking for available
2238 * space, that's because outside of this function it can only grow,
2239 * and once we've got needed space, it cannot suddenly disappear.
2240 *
2241 * The lock also protects us from gfar_error(), which can modify
2242 * regs->tstat and thus retrigger the transfers, which is why we
2243 * also must grab the lock before setting ready bit for the first
2244 * to be transmitted BD.
2245 */
2246 spin_lock_irqsave(&tx_queue->txlock, flags);
2247
2248 /* The powerpc-specific eieio() is used, as wmb() has too strong
2249 * semantics (it requires synchronization between cacheable and
2250 * uncacheable mappings, which eieio doesn't provide and which we
2251 * don't need), thus requiring a more expensive sync instruction. At
2252 * some point, the set of architecture-independent barrier functions
2253 * should be expanded to include weaker barriers.
2254 */
2255 eieio();
2256
2257 txbdp_start->lstatus = lstatus;
2258
2259 eieio(); /* force lstatus write before tx_skbuff */
2260
2261 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2262
2263 /* Update the current skb pointer to the next entry we will use
2264 * (wrapping if necessary)
2265 */
2266 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2267 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2268
2269 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2270
2271 /* reduce TxBD free count */
2272 tx_queue->num_txbdfree -= (nr_txbds);
2273
2274 /* If the next BD still needs to be cleaned up, then the bds
2275 * are full. We need to tell the kernel to stop sending us stuff.
2276 */
2277 if (!tx_queue->num_txbdfree) {
2278 netif_tx_stop_queue(txq);
2279
2280 dev->stats.tx_fifo_errors++;
2281 }
2282
2283 /* Tell the DMA to go go go */
2284 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2285
2286 /* Unlock priv */
2287 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2288
2289 return NETDEV_TX_OK;
2290 }
2291
2292 /* Stops the kernel queue, and halts the controller */
2293 static int gfar_close(struct net_device *dev)
2294 {
2295 struct gfar_private *priv = netdev_priv(dev);
2296
2297 disable_napi(priv);
2298
2299 cancel_work_sync(&priv->reset_task);
2300 stop_gfar(dev);
2301
2302 /* Disconnect from the PHY */
2303 phy_disconnect(priv->phydev);
2304 priv->phydev = NULL;
2305
2306 netif_tx_stop_all_queues(dev);
2307
2308 return 0;
2309 }
2310
2311 /* Changes the mac address if the controller is not running. */
2312 static int gfar_set_mac_address(struct net_device *dev)
2313 {
2314 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2315
2316 return 0;
2317 }
2318
2319 /* Check if rx parser should be activated */
2320 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2321 {
2322 struct gfar __iomem *regs;
2323 u32 tempval;
2324
2325 regs = priv->gfargrp[0].regs;
2326
2327 tempval = gfar_read(&regs->rctrl);
2328 /* If parse is no longer required, then disable parser */
2329 if (tempval & RCTRL_REQ_PARSER) {
2330 tempval |= RCTRL_PRSDEP_INIT;
2331 priv->uses_rxfcb = 1;
2332 } else {
2333 tempval &= ~RCTRL_PRSDEP_INIT;
2334 priv->uses_rxfcb = 0;
2335 }
2336 gfar_write(&regs->rctrl, tempval);
2337 }
2338
2339 /* Enables and disables VLAN insertion/extraction */
2340 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2341 {
2342 struct gfar_private *priv = netdev_priv(dev);
2343 struct gfar __iomem *regs = NULL;
2344 unsigned long flags;
2345 u32 tempval;
2346
2347 regs = priv->gfargrp[0].regs;
2348 local_irq_save(flags);
2349 lock_rx_qs(priv);
2350
2351 if (features & NETIF_F_HW_VLAN_TX) {
2352 /* Enable VLAN tag insertion */
2353 tempval = gfar_read(&regs->tctrl);
2354 tempval |= TCTRL_VLINS;
2355 gfar_write(&regs->tctrl, tempval);
2356 } else {
2357 /* Disable VLAN tag insertion */
2358 tempval = gfar_read(&regs->tctrl);
2359 tempval &= ~TCTRL_VLINS;
2360 gfar_write(&regs->tctrl, tempval);
2361 }
2362
2363 if (features & NETIF_F_HW_VLAN_RX) {
2364 /* Enable VLAN tag extraction */
2365 tempval = gfar_read(&regs->rctrl);
2366 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2367 gfar_write(&regs->rctrl, tempval);
2368 priv->uses_rxfcb = 1;
2369 } else {
2370 /* Disable VLAN tag extraction */
2371 tempval = gfar_read(&regs->rctrl);
2372 tempval &= ~RCTRL_VLEX;
2373 gfar_write(&regs->rctrl, tempval);
2374
2375 gfar_check_rx_parser_mode(priv);
2376 }
2377
2378 gfar_change_mtu(dev, dev->mtu);
2379
2380 unlock_rx_qs(priv);
2381 local_irq_restore(flags);
2382 }
2383
2384 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2385 {
2386 int tempsize, tempval;
2387 struct gfar_private *priv = netdev_priv(dev);
2388 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2389 int oldsize = priv->rx_buffer_size;
2390 int frame_size = new_mtu + ETH_HLEN;
2391
2392 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2393 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2394 return -EINVAL;
2395 }
2396
2397 if (priv->uses_rxfcb)
2398 frame_size += GMAC_FCB_LEN;
2399
2400 frame_size += priv->padding;
2401
2402 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2403 INCREMENTAL_BUFFER_SIZE;
2404
2405 /* Only stop and start the controller if it isn't already
2406 * stopped, and we changed something
2407 */
2408 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2409 stop_gfar(dev);
2410
2411 priv->rx_buffer_size = tempsize;
2412
2413 dev->mtu = new_mtu;
2414
2415 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2416 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2417
2418 /* If the mtu is larger than the max size for standard
2419 * ethernet frames (ie, a jumbo frame), then set maccfg2
2420 * to allow huge frames, and to check the length
2421 */
2422 tempval = gfar_read(&regs->maccfg2);
2423
2424 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2425 gfar_has_errata(priv, GFAR_ERRATA_74))
2426 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2427 else
2428 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2429
2430 gfar_write(&regs->maccfg2, tempval);
2431
2432 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2433 startup_gfar(dev);
2434
2435 return 0;
2436 }
2437
2438 /* gfar_reset_task gets scheduled when a packet has not been
2439 * transmitted after a set amount of time.
2440 * For now, assume that clearing out all the structures, and
2441 * starting over will fix the problem.
2442 */
2443 static void gfar_reset_task(struct work_struct *work)
2444 {
2445 struct gfar_private *priv = container_of(work, struct gfar_private,
2446 reset_task);
2447 struct net_device *dev = priv->ndev;
2448
2449 if (dev->flags & IFF_UP) {
2450 netif_tx_stop_all_queues(dev);
2451 stop_gfar(dev);
2452 startup_gfar(dev);
2453 netif_tx_start_all_queues(dev);
2454 }
2455
2456 netif_tx_schedule_all(dev);
2457 }
2458
2459 static void gfar_timeout(struct net_device *dev)
2460 {
2461 struct gfar_private *priv = netdev_priv(dev);
2462
2463 dev->stats.tx_errors++;
2464 schedule_work(&priv->reset_task);
2465 }
2466
2467 static void gfar_align_skb(struct sk_buff *skb)
2468 {
2469 /* We need the data buffer to be aligned properly. We will reserve
2470 * as many bytes as needed to align the data properly
2471 */
2472 skb_reserve(skb, RXBUF_ALIGNMENT -
2473 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2474 }
2475
2476 /* Interrupt Handler for Transmit complete */
2477 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2478 {
2479 struct net_device *dev = tx_queue->dev;
2480 struct netdev_queue *txq;
2481 struct gfar_private *priv = netdev_priv(dev);
2482 struct txbd8 *bdp, *next = NULL;
2483 struct txbd8 *lbdp = NULL;
2484 struct txbd8 *base = tx_queue->tx_bd_base;
2485 struct sk_buff *skb;
2486 int skb_dirtytx;
2487 int tx_ring_size = tx_queue->tx_ring_size;
2488 int frags = 0, nr_txbds = 0;
2489 int i;
2490 int howmany = 0;
2491 int tqi = tx_queue->qindex;
2492 unsigned int bytes_sent = 0;
2493 u32 lstatus;
2494 size_t buflen;
2495
2496 txq = netdev_get_tx_queue(dev, tqi);
2497 bdp = tx_queue->dirty_tx;
2498 skb_dirtytx = tx_queue->skb_dirtytx;
2499
2500 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2501 unsigned long flags;
2502
2503 frags = skb_shinfo(skb)->nr_frags;
2504
2505 /* When time stamping, one additional TxBD must be freed.
2506 * Also, we need to dma_unmap_single() the TxPAL.
2507 */
2508 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2509 nr_txbds = frags + 2;
2510 else
2511 nr_txbds = frags + 1;
2512
2513 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2514
2515 lstatus = lbdp->lstatus;
2516
2517 /* Only clean completed frames */
2518 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2519 (lstatus & BD_LENGTH_MASK))
2520 break;
2521
2522 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2523 next = next_txbd(bdp, base, tx_ring_size);
2524 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2525 } else
2526 buflen = bdp->length;
2527
2528 dma_unmap_single(priv->dev, bdp->bufPtr,
2529 buflen, DMA_TO_DEVICE);
2530
2531 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2532 struct skb_shared_hwtstamps shhwtstamps;
2533 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2534
2535 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2536 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2537 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2538 skb_tstamp_tx(skb, &shhwtstamps);
2539 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2540 bdp = next;
2541 }
2542
2543 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2544 bdp = next_txbd(bdp, base, tx_ring_size);
2545
2546 for (i = 0; i < frags; i++) {
2547 dma_unmap_page(priv->dev, bdp->bufPtr,
2548 bdp->length, DMA_TO_DEVICE);
2549 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2550 bdp = next_txbd(bdp, base, tx_ring_size);
2551 }
2552
2553 bytes_sent += skb->len;
2554
2555 dev_kfree_skb_any(skb);
2556
2557 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2558
2559 skb_dirtytx = (skb_dirtytx + 1) &
2560 TX_RING_MOD_MASK(tx_ring_size);
2561
2562 howmany++;
2563 spin_lock_irqsave(&tx_queue->txlock, flags);
2564 tx_queue->num_txbdfree += nr_txbds;
2565 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2566 }
2567
2568 /* If we freed a buffer, we can restart transmission, if necessary */
2569 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2570 netif_wake_subqueue(dev, tqi);
2571
2572 /* Update dirty indicators */
2573 tx_queue->skb_dirtytx = skb_dirtytx;
2574 tx_queue->dirty_tx = bdp;
2575
2576 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2577 }
2578
2579 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2580 {
2581 unsigned long flags;
2582
2583 spin_lock_irqsave(&gfargrp->grplock, flags);
2584 if (napi_schedule_prep(&gfargrp->napi)) {
2585 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2586 __napi_schedule(&gfargrp->napi);
2587 } else {
2588 /* Clear IEVENT, so interrupts aren't called again
2589 * because of the packets that have already arrived.
2590 */
2591 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2592 }
2593 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2594
2595 }
2596
2597 /* Interrupt Handler for Transmit complete */
2598 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2599 {
2600 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2601 return IRQ_HANDLED;
2602 }
2603
2604 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2605 struct sk_buff *skb)
2606 {
2607 struct net_device *dev = rx_queue->dev;
2608 struct gfar_private *priv = netdev_priv(dev);
2609 dma_addr_t buf;
2610
2611 buf = dma_map_single(priv->dev, skb->data,
2612 priv->rx_buffer_size, DMA_FROM_DEVICE);
2613 gfar_init_rxbdp(rx_queue, bdp, buf);
2614 }
2615
2616 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2617 {
2618 struct gfar_private *priv = netdev_priv(dev);
2619 struct sk_buff *skb;
2620
2621 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2622 if (!skb)
2623 return NULL;
2624
2625 gfar_align_skb(skb);
2626
2627 return skb;
2628 }
2629
2630 struct sk_buff *gfar_new_skb(struct net_device *dev)
2631 {
2632 return gfar_alloc_skb(dev);
2633 }
2634
2635 static inline void count_errors(unsigned short status, struct net_device *dev)
2636 {
2637 struct gfar_private *priv = netdev_priv(dev);
2638 struct net_device_stats *stats = &dev->stats;
2639 struct gfar_extra_stats *estats = &priv->extra_stats;
2640
2641 /* If the packet was truncated, none of the other errors matter */
2642 if (status & RXBD_TRUNCATED) {
2643 stats->rx_length_errors++;
2644
2645 atomic64_inc(&estats->rx_trunc);
2646
2647 return;
2648 }
2649 /* Count the errors, if there were any */
2650 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2651 stats->rx_length_errors++;
2652
2653 if (status & RXBD_LARGE)
2654 atomic64_inc(&estats->rx_large);
2655 else
2656 atomic64_inc(&estats->rx_short);
2657 }
2658 if (status & RXBD_NONOCTET) {
2659 stats->rx_frame_errors++;
2660 atomic64_inc(&estats->rx_nonoctet);
2661 }
2662 if (status & RXBD_CRCERR) {
2663 atomic64_inc(&estats->rx_crcerr);
2664 stats->rx_crc_errors++;
2665 }
2666 if (status & RXBD_OVERRUN) {
2667 atomic64_inc(&estats->rx_overrun);
2668 stats->rx_crc_errors++;
2669 }
2670 }
2671
2672 irqreturn_t gfar_receive(int irq, void *grp_id)
2673 {
2674 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2675 return IRQ_HANDLED;
2676 }
2677
2678 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2679 {
2680 /* If valid headers were found, and valid sums
2681 * were verified, then we tell the kernel that no
2682 * checksumming is necessary. Otherwise, it is [FIXME]
2683 */
2684 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2685 skb->ip_summed = CHECKSUM_UNNECESSARY;
2686 else
2687 skb_checksum_none_assert(skb);
2688 }
2689
2690
2691 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2692 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2693 int amount_pull, struct napi_struct *napi)
2694 {
2695 struct gfar_private *priv = netdev_priv(dev);
2696 struct rxfcb *fcb = NULL;
2697
2698 gro_result_t ret;
2699
2700 /* fcb is at the beginning if exists */
2701 fcb = (struct rxfcb *)skb->data;
2702
2703 /* Remove the FCB from the skb
2704 * Remove the padded bytes, if there are any
2705 */
2706 if (amount_pull) {
2707 skb_record_rx_queue(skb, fcb->rq);
2708 skb_pull(skb, amount_pull);
2709 }
2710
2711 /* Get receive timestamp from the skb */
2712 if (priv->hwts_rx_en) {
2713 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2714 u64 *ns = (u64 *) skb->data;
2715
2716 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2717 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2718 }
2719
2720 if (priv->padding)
2721 skb_pull(skb, priv->padding);
2722
2723 if (dev->features & NETIF_F_RXCSUM)
2724 gfar_rx_checksum(skb, fcb);
2725
2726 /* Tell the skb what kind of packet this is */
2727 skb->protocol = eth_type_trans(skb, dev);
2728
2729 /* There's need to check for NETIF_F_HW_VLAN_RX here.
2730 * Even if vlan rx accel is disabled, on some chips
2731 * RXFCB_VLN is pseudo randomly set.
2732 */
2733 if (dev->features & NETIF_F_HW_VLAN_RX &&
2734 fcb->flags & RXFCB_VLN)
2735 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2736
2737 /* Send the packet up the stack */
2738 ret = napi_gro_receive(napi, skb);
2739
2740 if (unlikely(GRO_DROP == ret))
2741 atomic64_inc(&priv->extra_stats.kernel_dropped);
2742 }
2743
2744 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2745 * until the budget/quota has been reached. Returns the number
2746 * of frames handled
2747 */
2748 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2749 {
2750 struct net_device *dev = rx_queue->dev;
2751 struct rxbd8 *bdp, *base;
2752 struct sk_buff *skb;
2753 int pkt_len;
2754 int amount_pull;
2755 int howmany = 0;
2756 struct gfar_private *priv = netdev_priv(dev);
2757
2758 /* Get the first full descriptor */
2759 bdp = rx_queue->cur_rx;
2760 base = rx_queue->rx_bd_base;
2761
2762 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2763
2764 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2765 struct sk_buff *newskb;
2766
2767 rmb();
2768
2769 /* Add another skb for the future */
2770 newskb = gfar_new_skb(dev);
2771
2772 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2773
2774 dma_unmap_single(priv->dev, bdp->bufPtr,
2775 priv->rx_buffer_size, DMA_FROM_DEVICE);
2776
2777 if (unlikely(!(bdp->status & RXBD_ERR) &&
2778 bdp->length > priv->rx_buffer_size))
2779 bdp->status = RXBD_LARGE;
2780
2781 /* We drop the frame if we failed to allocate a new buffer */
2782 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2783 bdp->status & RXBD_ERR)) {
2784 count_errors(bdp->status, dev);
2785
2786 if (unlikely(!newskb))
2787 newskb = skb;
2788 else if (skb)
2789 dev_kfree_skb(skb);
2790 } else {
2791 /* Increment the number of packets */
2792 rx_queue->stats.rx_packets++;
2793 howmany++;
2794
2795 if (likely(skb)) {
2796 pkt_len = bdp->length - ETH_FCS_LEN;
2797 /* Remove the FCS from the packet length */
2798 skb_put(skb, pkt_len);
2799 rx_queue->stats.rx_bytes += pkt_len;
2800 skb_record_rx_queue(skb, rx_queue->qindex);
2801 gfar_process_frame(dev, skb, amount_pull,
2802 &rx_queue->grp->napi);
2803
2804 } else {
2805 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2806 rx_queue->stats.rx_dropped++;
2807 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2808 }
2809
2810 }
2811
2812 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2813
2814 /* Setup the new bdp */
2815 gfar_new_rxbdp(rx_queue, bdp, newskb);
2816
2817 /* Update to the next pointer */
2818 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2819
2820 /* update to point at the next skb */
2821 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2822 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2823 }
2824
2825 /* Update the current rxbd pointer to be the next one */
2826 rx_queue->cur_rx = bdp;
2827
2828 return howmany;
2829 }
2830
2831 static int gfar_poll(struct napi_struct *napi, int budget)
2832 {
2833 struct gfar_priv_grp *gfargrp =
2834 container_of(napi, struct gfar_priv_grp, napi);
2835 struct gfar_private *priv = gfargrp->priv;
2836 struct gfar __iomem *regs = gfargrp->regs;
2837 struct gfar_priv_tx_q *tx_queue = NULL;
2838 struct gfar_priv_rx_q *rx_queue = NULL;
2839 int work_done = 0, work_done_per_q = 0;
2840 int i, budget_per_q = 0;
2841 int has_tx_work;
2842 unsigned long rstat_rxf;
2843 int num_act_queues;
2844
2845 /* Clear IEVENT, so interrupts aren't called again
2846 * because of the packets that have already arrived
2847 */
2848 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2849
2850 rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2851
2852 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2853 if (num_act_queues)
2854 budget_per_q = budget/num_act_queues;
2855
2856 while (1) {
2857 has_tx_work = 0;
2858 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2859 tx_queue = priv->tx_queue[i];
2860 /* run Tx cleanup to completion */
2861 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2862 gfar_clean_tx_ring(tx_queue);
2863 has_tx_work = 1;
2864 }
2865 }
2866
2867 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2868 /* skip queue if not active */
2869 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2870 continue;
2871
2872 rx_queue = priv->rx_queue[i];
2873 work_done_per_q =
2874 gfar_clean_rx_ring(rx_queue, budget_per_q);
2875 work_done += work_done_per_q;
2876
2877 /* finished processing this queue */
2878 if (work_done_per_q < budget_per_q) {
2879 /* clear active queue hw indication */
2880 gfar_write(&regs->rstat,
2881 RSTAT_CLEAR_RXF0 >> i);
2882 rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i);
2883 num_act_queues--;
2884
2885 if (!num_act_queues)
2886 break;
2887 /* recompute budget per Rx queue */
2888 budget_per_q =
2889 (budget - work_done) / num_act_queues;
2890 }
2891 }
2892
2893 if (work_done >= budget)
2894 break;
2895
2896 if (!num_act_queues && !has_tx_work) {
2897
2898 napi_complete(napi);
2899
2900 /* Clear the halt bit in RSTAT */
2901 gfar_write(&regs->rstat, gfargrp->rstat);
2902
2903 gfar_write(&regs->imask, IMASK_DEFAULT);
2904
2905 /* If we are coalescing interrupts, update the timer
2906 * Otherwise, clear it
2907 */
2908 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2909 gfargrp->tx_bit_map);
2910 break;
2911 }
2912 }
2913
2914 return work_done;
2915 }
2916
2917 #ifdef CONFIG_NET_POLL_CONTROLLER
2918 /* Polling 'interrupt' - used by things like netconsole to send skbs
2919 * without having to re-enable interrupts. It's not called while
2920 * the interrupt routine is executing.
2921 */
2922 static void gfar_netpoll(struct net_device *dev)
2923 {
2924 struct gfar_private *priv = netdev_priv(dev);
2925 int i;
2926
2927 /* If the device has multiple interrupts, run tx/rx */
2928 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2929 for (i = 0; i < priv->num_grps; i++) {
2930 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2931
2932 disable_irq(gfar_irq(grp, TX)->irq);
2933 disable_irq(gfar_irq(grp, RX)->irq);
2934 disable_irq(gfar_irq(grp, ER)->irq);
2935 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2936 enable_irq(gfar_irq(grp, ER)->irq);
2937 enable_irq(gfar_irq(grp, RX)->irq);
2938 enable_irq(gfar_irq(grp, TX)->irq);
2939 }
2940 } else {
2941 for (i = 0; i < priv->num_grps; i++) {
2942 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2943
2944 disable_irq(gfar_irq(grp, TX)->irq);
2945 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2946 enable_irq(gfar_irq(grp, TX)->irq);
2947 }
2948 }
2949 }
2950 #endif
2951
2952 /* The interrupt handler for devices with one interrupt */
2953 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2954 {
2955 struct gfar_priv_grp *gfargrp = grp_id;
2956
2957 /* Save ievent for future reference */
2958 u32 events = gfar_read(&gfargrp->regs->ievent);
2959
2960 /* Check for reception */
2961 if (events & IEVENT_RX_MASK)
2962 gfar_receive(irq, grp_id);
2963
2964 /* Check for transmit completion */
2965 if (events & IEVENT_TX_MASK)
2966 gfar_transmit(irq, grp_id);
2967
2968 /* Check for errors */
2969 if (events & IEVENT_ERR_MASK)
2970 gfar_error(irq, grp_id);
2971
2972 return IRQ_HANDLED;
2973 }
2974
2975 /* Called every time the controller might need to be made
2976 * aware of new link state. The PHY code conveys this
2977 * information through variables in the phydev structure, and this
2978 * function converts those variables into the appropriate
2979 * register values, and can bring down the device if needed.
2980 */
2981 static void adjust_link(struct net_device *dev)
2982 {
2983 struct gfar_private *priv = netdev_priv(dev);
2984 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2985 unsigned long flags;
2986 struct phy_device *phydev = priv->phydev;
2987 int new_state = 0;
2988
2989 local_irq_save(flags);
2990 lock_tx_qs(priv);
2991
2992 if (phydev->link) {
2993 u32 tempval = gfar_read(&regs->maccfg2);
2994 u32 ecntrl = gfar_read(&regs->ecntrl);
2995
2996 /* Now we make sure that we can be in full duplex mode.
2997 * If not, we operate in half-duplex mode.
2998 */
2999 if (phydev->duplex != priv->oldduplex) {
3000 new_state = 1;
3001 if (!(phydev->duplex))
3002 tempval &= ~(MACCFG2_FULL_DUPLEX);
3003 else
3004 tempval |= MACCFG2_FULL_DUPLEX;
3005
3006 priv->oldduplex = phydev->duplex;
3007 }
3008
3009 if (phydev->speed != priv->oldspeed) {
3010 new_state = 1;
3011 switch (phydev->speed) {
3012 case 1000:
3013 tempval =
3014 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3015
3016 ecntrl &= ~(ECNTRL_R100);
3017 break;
3018 case 100:
3019 case 10:
3020 tempval =
3021 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3022
3023 /* Reduced mode distinguishes
3024 * between 10 and 100
3025 */
3026 if (phydev->speed == SPEED_100)
3027 ecntrl |= ECNTRL_R100;
3028 else
3029 ecntrl &= ~(ECNTRL_R100);
3030 break;
3031 default:
3032 netif_warn(priv, link, dev,
3033 "Ack! Speed (%d) is not 10/100/1000!\n",
3034 phydev->speed);
3035 break;
3036 }
3037
3038 priv->oldspeed = phydev->speed;
3039 }
3040
3041 gfar_write(&regs->maccfg2, tempval);
3042 gfar_write(&regs->ecntrl, ecntrl);
3043
3044 if (!priv->oldlink) {
3045 new_state = 1;
3046 priv->oldlink = 1;
3047 }
3048 } else if (priv->oldlink) {
3049 new_state = 1;
3050 priv->oldlink = 0;
3051 priv->oldspeed = 0;
3052 priv->oldduplex = -1;
3053 }
3054
3055 if (new_state && netif_msg_link(priv))
3056 phy_print_status(phydev);
3057 unlock_tx_qs(priv);
3058 local_irq_restore(flags);
3059 }
3060
3061 /* Update the hash table based on the current list of multicast
3062 * addresses we subscribe to. Also, change the promiscuity of
3063 * the device based on the flags (this function is called
3064 * whenever dev->flags is changed
3065 */
3066 static void gfar_set_multi(struct net_device *dev)
3067 {
3068 struct netdev_hw_addr *ha;
3069 struct gfar_private *priv = netdev_priv(dev);
3070 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3071 u32 tempval;
3072
3073 if (dev->flags & IFF_PROMISC) {
3074 /* Set RCTRL to PROM */
3075 tempval = gfar_read(&regs->rctrl);
3076 tempval |= RCTRL_PROM;
3077 gfar_write(&regs->rctrl, tempval);
3078 } else {
3079 /* Set RCTRL to not PROM */
3080 tempval = gfar_read(&regs->rctrl);
3081 tempval &= ~(RCTRL_PROM);
3082 gfar_write(&regs->rctrl, tempval);
3083 }
3084
3085 if (dev->flags & IFF_ALLMULTI) {
3086 /* Set the hash to rx all multicast frames */
3087 gfar_write(&regs->igaddr0, 0xffffffff);
3088 gfar_write(&regs->igaddr1, 0xffffffff);
3089 gfar_write(&regs->igaddr2, 0xffffffff);
3090 gfar_write(&regs->igaddr3, 0xffffffff);
3091 gfar_write(&regs->igaddr4, 0xffffffff);
3092 gfar_write(&regs->igaddr5, 0xffffffff);
3093 gfar_write(&regs->igaddr6, 0xffffffff);
3094 gfar_write(&regs->igaddr7, 0xffffffff);
3095 gfar_write(&regs->gaddr0, 0xffffffff);
3096 gfar_write(&regs->gaddr1, 0xffffffff);
3097 gfar_write(&regs->gaddr2, 0xffffffff);
3098 gfar_write(&regs->gaddr3, 0xffffffff);
3099 gfar_write(&regs->gaddr4, 0xffffffff);
3100 gfar_write(&regs->gaddr5, 0xffffffff);
3101 gfar_write(&regs->gaddr6, 0xffffffff);
3102 gfar_write(&regs->gaddr7, 0xffffffff);
3103 } else {
3104 int em_num;
3105 int idx;
3106
3107 /* zero out the hash */
3108 gfar_write(&regs->igaddr0, 0x0);
3109 gfar_write(&regs->igaddr1, 0x0);
3110 gfar_write(&regs->igaddr2, 0x0);
3111 gfar_write(&regs->igaddr3, 0x0);
3112 gfar_write(&regs->igaddr4, 0x0);
3113 gfar_write(&regs->igaddr5, 0x0);
3114 gfar_write(&regs->igaddr6, 0x0);
3115 gfar_write(&regs->igaddr7, 0x0);
3116 gfar_write(&regs->gaddr0, 0x0);
3117 gfar_write(&regs->gaddr1, 0x0);
3118 gfar_write(&regs->gaddr2, 0x0);
3119 gfar_write(&regs->gaddr3, 0x0);
3120 gfar_write(&regs->gaddr4, 0x0);
3121 gfar_write(&regs->gaddr5, 0x0);
3122 gfar_write(&regs->gaddr6, 0x0);
3123 gfar_write(&regs->gaddr7, 0x0);
3124
3125 /* If we have extended hash tables, we need to
3126 * clear the exact match registers to prepare for
3127 * setting them
3128 */
3129 if (priv->extended_hash) {
3130 em_num = GFAR_EM_NUM + 1;
3131 gfar_clear_exact_match(dev);
3132 idx = 1;
3133 } else {
3134 idx = 0;
3135 em_num = 0;
3136 }
3137
3138 if (netdev_mc_empty(dev))
3139 return;
3140
3141 /* Parse the list, and set the appropriate bits */
3142 netdev_for_each_mc_addr(ha, dev) {
3143 if (idx < em_num) {
3144 gfar_set_mac_for_addr(dev, idx, ha->addr);
3145 idx++;
3146 } else
3147 gfar_set_hash_for_addr(dev, ha->addr);
3148 }
3149 }
3150 }
3151
3152
3153 /* Clears each of the exact match registers to zero, so they
3154 * don't interfere with normal reception
3155 */
3156 static void gfar_clear_exact_match(struct net_device *dev)
3157 {
3158 int idx;
3159 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3160
3161 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3162 gfar_set_mac_for_addr(dev, idx, zero_arr);
3163 }
3164
3165 /* Set the appropriate hash bit for the given addr */
3166 /* The algorithm works like so:
3167 * 1) Take the Destination Address (ie the multicast address), and
3168 * do a CRC on it (little endian), and reverse the bits of the
3169 * result.
3170 * 2) Use the 8 most significant bits as a hash into a 256-entry
3171 * table. The table is controlled through 8 32-bit registers:
3172 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3173 * gaddr7. This means that the 3 most significant bits in the
3174 * hash index which gaddr register to use, and the 5 other bits
3175 * indicate which bit (assuming an IBM numbering scheme, which
3176 * for PowerPC (tm) is usually the case) in the register holds
3177 * the entry.
3178 */
3179 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3180 {
3181 u32 tempval;
3182 struct gfar_private *priv = netdev_priv(dev);
3183 u32 result = ether_crc(ETH_ALEN, addr);
3184 int width = priv->hash_width;
3185 u8 whichbit = (result >> (32 - width)) & 0x1f;
3186 u8 whichreg = result >> (32 - width + 5);
3187 u32 value = (1 << (31-whichbit));
3188
3189 tempval = gfar_read(priv->hash_regs[whichreg]);
3190 tempval |= value;
3191 gfar_write(priv->hash_regs[whichreg], tempval);
3192 }
3193
3194
3195 /* There are multiple MAC Address register pairs on some controllers
3196 * This function sets the numth pair to a given address
3197 */
3198 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3199 const u8 *addr)
3200 {
3201 struct gfar_private *priv = netdev_priv(dev);
3202 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3203 int idx;
3204 char tmpbuf[ETH_ALEN];
3205 u32 tempval;
3206 u32 __iomem *macptr = &regs->macstnaddr1;
3207
3208 macptr += num*2;
3209
3210 /* Now copy it into the mac registers backwards, cuz
3211 * little endian is silly
3212 */
3213 for (idx = 0; idx < ETH_ALEN; idx++)
3214 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3215
3216 gfar_write(macptr, *((u32 *) (tmpbuf)));
3217
3218 tempval = *((u32 *) (tmpbuf + 4));
3219
3220 gfar_write(macptr+1, tempval);
3221 }
3222
3223 /* GFAR error interrupt handler */
3224 static irqreturn_t gfar_error(int irq, void *grp_id)
3225 {
3226 struct gfar_priv_grp *gfargrp = grp_id;
3227 struct gfar __iomem *regs = gfargrp->regs;
3228 struct gfar_private *priv= gfargrp->priv;
3229 struct net_device *dev = priv->ndev;
3230
3231 /* Save ievent for future reference */
3232 u32 events = gfar_read(&regs->ievent);
3233
3234 /* Clear IEVENT */
3235 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3236
3237 /* Magic Packet is not an error. */
3238 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3239 (events & IEVENT_MAG))
3240 events &= ~IEVENT_MAG;
3241
3242 /* Hmm... */
3243 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3244 netdev_dbg(dev,
3245 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3246 events, gfar_read(&regs->imask));
3247
3248 /* Update the error counters */
3249 if (events & IEVENT_TXE) {
3250 dev->stats.tx_errors++;
3251
3252 if (events & IEVENT_LC)
3253 dev->stats.tx_window_errors++;
3254 if (events & IEVENT_CRL)
3255 dev->stats.tx_aborted_errors++;
3256 if (events & IEVENT_XFUN) {
3257 unsigned long flags;
3258
3259 netif_dbg(priv, tx_err, dev,
3260 "TX FIFO underrun, packet dropped\n");
3261 dev->stats.tx_dropped++;
3262 atomic64_inc(&priv->extra_stats.tx_underrun);
3263
3264 local_irq_save(flags);
3265 lock_tx_qs(priv);
3266
3267 /* Reactivate the Tx Queues */
3268 gfar_write(&regs->tstat, gfargrp->tstat);
3269
3270 unlock_tx_qs(priv);
3271 local_irq_restore(flags);
3272 }
3273 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3274 }
3275 if (events & IEVENT_BSY) {
3276 dev->stats.rx_errors++;
3277 atomic64_inc(&priv->extra_stats.rx_bsy);
3278
3279 gfar_receive(irq, grp_id);
3280
3281 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3282 gfar_read(&regs->rstat));
3283 }
3284 if (events & IEVENT_BABR) {
3285 dev->stats.rx_errors++;
3286 atomic64_inc(&priv->extra_stats.rx_babr);
3287
3288 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3289 }
3290 if (events & IEVENT_EBERR) {
3291 atomic64_inc(&priv->extra_stats.eberr);
3292 netif_dbg(priv, rx_err, dev, "bus error\n");
3293 }
3294 if (events & IEVENT_RXC)
3295 netif_dbg(priv, rx_status, dev, "control frame\n");
3296
3297 if (events & IEVENT_BABT) {
3298 atomic64_inc(&priv->extra_stats.tx_babt);
3299 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3300 }
3301 return IRQ_HANDLED;
3302 }
3303
3304 static struct of_device_id gfar_match[] =
3305 {
3306 {
3307 .type = "network",
3308 .compatible = "gianfar",
3309 },
3310 {
3311 .compatible = "fsl,etsec2",
3312 },
3313 {},
3314 };
3315 MODULE_DEVICE_TABLE(of, gfar_match);
3316
3317 /* Structure for a device driver */
3318 static struct platform_driver gfar_driver = {
3319 .driver = {
3320 .name = "fsl-gianfar",
3321 .owner = THIS_MODULE,
3322 .pm = GFAR_PM_OPS,
3323 .of_match_table = gfar_match,
3324 },
3325 .probe = gfar_probe,
3326 .remove = gfar_remove,
3327 };
3328
3329 module_platform_driver(gfar_driver);
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