drivers/clk/uniphier/clk-uniphier.h

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef __CLK_UNIPHIER_H__
  17 #define __CLK_UNIPHIER_H__
  18
  19 struct clk_hw;
  20 struct device;
  21 struct regmap;
  22
  23 #define UNIPHIER_CLK_MUX_MAX_PARENTS    8
  24
  25 enum uniphier_clk_type {
  26         UNIPHIER_CLK_TYPE_FIXED_FACTOR,
  27         UNIPHIER_CLK_TYPE_FIXED_RATE,
  28         UNIPHIER_CLK_TYPE_GATE,
  29         UNIPHIER_CLK_TYPE_MUX,
  30 };
  31
  32 struct uniphier_clk_fixed_factor_data {
  33         const char *parent_name;
  34         unsigned int mult;
  35         unsigned int div;
  36 };
  37
  38 struct uniphier_clk_fixed_rate_data {
  39         unsigned long fixed_rate;
  40 };
  41
  42 struct uniphier_clk_gate_data {
  43         const char *parent_name;
  44         unsigned int reg;
  45         unsigned int bit;
  46 };
  47
  48 struct uniphier_clk_mux_data {
  49         const char *parent_names[UNIPHIER_CLK_MUX_MAX_PARENTS];
  50         unsigned int num_parents;
  51         unsigned int reg;
  52         unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
  53         unsigned int vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
  54 };
  55
  56 struct uniphier_clk_data {
  57         const char *name;
  58         enum uniphier_clk_type type;
  59         int idx;
  60         union {
  61                 struct uniphier_clk_fixed_factor_data factor;
  62                 struct uniphier_clk_fixed_rate_data rate;
  63                 struct uniphier_clk_gate_data gate;
  64                 struct uniphier_clk_mux_data mux;
  65         } data;
  66 };
  67
  68 #define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div)  \
  69         {                                                       \
  70                 .name = (_name),                                \
  71                 .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,         \
  72                 .idx = (_idx),                                  \
  73                 .data.factor = {                                \
  74                         .parent_name = (_parent),               \
  75                         .mult = (_mult),                        \
  76                         .div = (_div),                          \
  77                 },                                              \
  78         }
  79
  80
  81 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit)     \
  82         {                                                       \
  83                 .name = (_name),                                \
  84                 .type = UNIPHIER_CLK_TYPE_GATE,                 \
  85                 .idx = (_idx),                                  \
  86                 .data.gate = {                                  \
  87                         .parent_name = (_parent),               \
  88                         .reg = (_reg),                          \
  89                         .bit = (_bit),                          \
  90                 },                                              \
  91         }
  92
  93
  94 struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
  95                                                   const char *name,
  96                         const struct uniphier_clk_fixed_factor_data *data);
  97 struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
  98                                                 const char *name,
  99                         const struct uniphier_clk_fixed_rate_data *data);
 100 struct clk_hw *uniphier_clk_register_gate(struct device *dev,
 101                                           struct regmap *regmap,
 102                                           const char *name,
 103                                 const struct uniphier_clk_gate_data *data);
 104 struct clk_hw *uniphier_clk_register_mux(struct device *dev,
 105                                          struct regmap *regmap,
 106                                          const char *name,
 107                                 const struct uniphier_clk_mux_data *data);
 108
 109 extern const struct uniphier_clk_data uniphier_sld3_sys_clk_data[];
 110 extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
 111 extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
 112 extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
 113 extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];
 114 extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
 115 extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
 116 extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
 117 extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
 118 extern const struct uniphier_clk_data uniphier_pro5_mio_clk_data[];
 119 extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
 120 extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
 121
 122 #endif /* __CLK_UNIPHIER_H__ */