drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72 #include <ttm/ttm_execbuf_util.h>
  73
  74 #include "radeon_family.h"
  75 #include "radeon_mode.h"
  76 #include "radeon_reg.h"
  77
  78 /*
  79  * Modules parameters.
  80  */
  81 extern int radeon_no_wb;
  82 extern int radeon_modeset;
  83 extern int radeon_dynclks;
  84 extern int radeon_r4xx_atom;
  85 extern int radeon_agpmode;
  86 extern int radeon_vram_limit;
  87 extern int radeon_gart_size;
  88 extern int radeon_benchmarking;
  89 extern int radeon_testing;
  90 extern int radeon_connector_table;
  91 extern int radeon_tv;
  92 extern int radeon_audio;
  93 extern int radeon_disp_priority;
  94 extern int radeon_hw_i2c;
  95 extern int radeon_pcie_gen2;
  96 extern int radeon_msi;
  97
  98 /*
  99  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 100  * symbol;
 101  */
 102 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
 103 #define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
 104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 105 #define RADEON_IB_POOL_SIZE             16
 106 #define RADEON_DEBUGFS_MAX_COMPONENTS   32
 107 #define RADEONFB_CONN_LIMIT             4
 108 #define RADEON_BIOS_NUM_SCRATCH         8
 109
 110 /* max number of rings */
 111 #define RADEON_NUM_RINGS 3
 112
 113 /* internal ring indices */
 114 /* r1xx+ has gfx CP ring */
 115 #define RADEON_RING_TYPE_GFX_INDEX  0
 116
 117 /* cayman has 2 compute CP rings */
 118 #define CAYMAN_RING_TYPE_CP1_INDEX 1
 119 #define CAYMAN_RING_TYPE_CP2_INDEX 2
 120
 121 /* hardcode those limit for now */
 122 #define RADEON_VA_RESERVED_SIZE         (8 << 20)
 123 #define RADEON_IB_VM_MAX_SIZE           (64 << 10)
 124
 125 /*
 126  * Errata workarounds.
 127  */
 128 enum radeon_pll_errata {
 129         CHIP_ERRATA_R300_CG             = 0x00000001,
 130         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 131         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 132 };
 133
 134
 135 struct radeon_device;
 136
 137
 138 /*
 139  * BIOS.
 140  */
 141 #define ATRM_BIOS_PAGE 4096
 142
 143 #if defined(CONFIG_VGA_SWITCHEROO)
 144 bool radeon_atrm_supported(struct pci_dev *pdev);
 145 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
 146 #else
 147 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
 148 {
 149         return false;
 150 }
 151
 152 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
 153         return -EINVAL;
 154 }
 155 #endif
 156 bool radeon_get_bios(struct radeon_device *rdev);
 157
 158
 159 /*
 160  * Mutex which allows recursive locking from the same process.
 161  */
 162 struct radeon_mutex {
 163         struct mutex            mutex;
 164         struct task_struct      *owner;
 165         int                     level;
 166 };
 167
 168 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
 169 {
 170         mutex_init(&mutex->mutex);
 171         mutex->owner = NULL;
 172         mutex->level = 0;
 173 }
 174
 175 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
 176 {
 177         if (mutex_trylock(&mutex->mutex)) {
 178                 /* The mutex was unlocked before, so it's ours now */
 179                 mutex->owner = current;
 180         } else if (mutex->owner != current) {
 181                 /* Another process locked the mutex, take it */
 182                 mutex_lock(&mutex->mutex);
 183                 mutex->owner = current;
 184         }
 185         /* Otherwise the mutex was already locked by this process */
 186
 187         mutex->level++;
 188 }
 189
 190 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
 191 {
 192         if (--mutex->level > 0)
 193                 return;
 194
 195         mutex->owner = NULL;
 196         mutex_unlock(&mutex->mutex);
 197 }
 198
 199
 200 /*
 201  * Dummy page
 202  */
 203 struct radeon_dummy_page {
 204         struct page     *page;
 205         dma_addr_t      addr;
 206 };
 207 int radeon_dummy_page_init(struct radeon_device *rdev);
 208 void radeon_dummy_page_fini(struct radeon_device *rdev);
 209
 210
 211 /*
 212  * Clocks
 213  */
 214 struct radeon_clock {
 215         struct radeon_pll p1pll;
 216         struct radeon_pll p2pll;
 217         struct radeon_pll dcpll;
 218         struct radeon_pll spll;
 219         struct radeon_pll mpll;
 220         /* 10 Khz units */
 221         uint32_t default_mclk;
 222         uint32_t default_sclk;
 223         uint32_t default_dispclk;
 224         uint32_t dp_extclk;
 225         uint32_t max_pixel_clock;
 226 };
 227
 228 /*
 229  * Power management
 230  */
 231 int radeon_pm_init(struct radeon_device *rdev);
 232 void radeon_pm_fini(struct radeon_device *rdev);
 233 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 234 void radeon_pm_suspend(struct radeon_device *rdev);
 235 void radeon_pm_resume(struct radeon_device *rdev);
 236 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 237 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 238 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 239 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
 240 void rs690_pm_info(struct radeon_device *rdev);
 241 extern int rv6xx_get_temp(struct radeon_device *rdev);
 242 extern int rv770_get_temp(struct radeon_device *rdev);
 243 extern int evergreen_get_temp(struct radeon_device *rdev);
 244 extern int sumo_get_temp(struct radeon_device *rdev);
 245 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 246                                     unsigned *bankh, unsigned *mtaspect,
 247                                     unsigned *tile_split);
 248
 249 /*
 250  * Fences.
 251  */
 252 struct radeon_fence_driver {
 253         uint32_t                        scratch_reg;
 254         uint64_t                        gpu_addr;
 255         volatile uint32_t               *cpu_addr;
 256         atomic_t                        seq;
 257         uint32_t                        last_seq;
 258         unsigned long                   last_jiffies;
 259         unsigned long                   last_timeout;
 260         wait_queue_head_t               queue;
 261         struct list_head                created;
 262         struct list_head                emitted;
 263         struct list_head                signaled;
 264         bool                            initialized;
 265 };
 266
 267 struct radeon_fence {
 268         struct radeon_device            *rdev;
 269         struct kref                     kref;
 270         struct list_head                list;
 271         /* protected by radeon_fence.lock */
 272         uint32_t                        seq;
 273         bool                            emitted;
 274         bool                            signaled;
 275         /* RB, DMA, etc. */
 276         int                             ring;
 277         struct radeon_semaphore         *semaphore;
 278 };
 279
 280 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
 281 int radeon_fence_driver_init(struct radeon_device *rdev);
 282 void radeon_fence_driver_fini(struct radeon_device *rdev);
 283 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 284 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 285 void radeon_fence_process(struct radeon_device *rdev, int ring);
 286 bool radeon_fence_signaled(struct radeon_fence *fence);
 287 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 288 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
 289 int radeon_fence_wait_last(struct radeon_device *rdev, int ring);
 290 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 291 void radeon_fence_unref(struct radeon_fence **fence);
 292 int radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
 293
 294 /*
 295  * Tiling registers
 296  */
 297 struct radeon_surface_reg {
 298         struct radeon_bo *bo;
 299 };
 300
 301 #define RADEON_GEM_MAX_SURFACES 8
 302
 303 /*
 304  * TTM.
 305  */
 306 struct radeon_mman {
 307         struct ttm_bo_global_ref        bo_global_ref;
 308         struct drm_global_reference     mem_global_ref;
 309         struct ttm_bo_device            bdev;
 310         bool                            mem_global_referenced;
 311         bool                            initialized;
 312 };
 313
 314 /* bo virtual address in a specific vm */
 315 struct radeon_bo_va {
 316         /* bo list is protected by bo being reserved */
 317         struct list_head                bo_list;
 318         /* vm list is protected by vm mutex */
 319         struct list_head                vm_list;
 320         /* constant after initialization */
 321         struct radeon_vm                *vm;
 322         struct radeon_bo                *bo;
 323         uint64_t                        soffset;
 324         uint64_t                        eoffset;
 325         uint32_t                        flags;
 326         bool                            valid;
 327 };
 328
 329 struct radeon_bo {
 330         /* Protected by gem.mutex */
 331         struct list_head                list;
 332         /* Protected by tbo.reserved */
 333         u32                             placements[3];
 334         struct ttm_placement            placement;
 335         struct ttm_buffer_object        tbo;
 336         struct ttm_bo_kmap_obj          kmap;
 337         unsigned                        pin_count;
 338         void                            *kptr;
 339         u32                             tiling_flags;
 340         u32                             pitch;
 341         int                             surface_reg;
 342         /* list of all virtual address to which this bo
 343          * is associated to
 344          */
 345         struct list_head                va;
 346         /* Constant after initialization */
 347         struct radeon_device            *rdev;
 348         struct drm_gem_object           gem_base;
 349 };
 350 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 351
 352 struct radeon_bo_list {
 353         struct ttm_validate_buffer tv;
 354         struct radeon_bo        *bo;
 355         uint64_t                gpu_offset;
 356         unsigned                rdomain;
 357         unsigned                wdomain;
 358         u32                     tiling_flags;
 359 };
 360
 361 /* sub-allocation manager, it has to be protected by another lock.
 362  * By conception this is an helper for other part of the driver
 363  * like the indirect buffer or semaphore, which both have their
 364  * locking.
 365  *
 366  * Principe is simple, we keep a list of sub allocation in offset
 367  * order (first entry has offset == 0, last entry has the highest
 368  * offset).
 369  *
 370  * When allocating new object we first check if there is room at
 371  * the end total_size - (last_object_offset + last_object_size) >=
 372  * alloc_size. If so we allocate new object there.
 373  *
 374  * When there is not enough room at the end, we start waiting for
 375  * each sub object until we reach object_offset+object_size >=
 376  * alloc_size, this object then become the sub object we return.
 377  *
 378  * Alignment can't be bigger than page size.
 379  *
 380  * Hole are not considered for allocation to keep things simple.
 381  * Assumption is that there won't be hole (all object on same
 382  * alignment).
 383  */
 384 struct radeon_sa_manager {
 385         struct radeon_bo        *bo;
 386         struct list_head        sa_bo;
 387         unsigned                size;
 388         uint64_t                gpu_addr;
 389         void                    *cpu_ptr;
 390         uint32_t                domain;
 391 };
 392
 393 struct radeon_sa_bo;
 394
 395 /* sub-allocation buffer */
 396 struct radeon_sa_bo {
 397         struct list_head                list;
 398         struct radeon_sa_manager        *manager;
 399         unsigned                        offset;
 400         unsigned                        size;
 401 };
 402
 403 /*
 404  * GEM objects.
 405  */
 406 struct radeon_gem {
 407         struct mutex            mutex;
 408         struct list_head        objects;
 409 };
 410
 411 int radeon_gem_init(struct radeon_device *rdev);
 412 void radeon_gem_fini(struct radeon_device *rdev);
 413 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 414                                 int alignment, int initial_domain,
 415                                 bool discardable, bool kernel,
 416                                 struct drm_gem_object **obj);
 417 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 418                           uint64_t *gpu_addr);
 419 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 420
 421 int radeon_mode_dumb_create(struct drm_file *file_priv,
 422                             struct drm_device *dev,
 423                             struct drm_mode_create_dumb *args);
 424 int radeon_mode_dumb_mmap(struct drm_file *filp,
 425                           struct drm_device *dev,
 426                           uint32_t handle, uint64_t *offset_p);
 427 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
 428                              struct drm_device *dev,
 429                              uint32_t handle);
 430
 431 /*
 432  * Semaphores.
 433  */
 434 struct radeon_ring;
 435
 436 #define RADEON_SEMAPHORE_BO_SIZE        256
 437
 438 struct radeon_semaphore_driver {
 439         rwlock_t                        lock;
 440         struct list_head                bo;
 441 };
 442
 443 struct radeon_semaphore_bo;
 444
 445 /* everything here is constant */
 446 struct radeon_semaphore {
 447         struct list_head                list;
 448         uint64_t                        gpu_addr;
 449         uint32_t                        *cpu_ptr;
 450         struct radeon_semaphore_bo      *bo;
 451 };
 452
 453 struct radeon_semaphore_bo {
 454         struct list_head                list;
 455         struct radeon_ib                *ib;
 456         struct list_head                free;
 457         struct radeon_semaphore         semaphores[RADEON_SEMAPHORE_BO_SIZE/8];
 458         unsigned                        nused;
 459 };
 460
 461 void radeon_semaphore_driver_fini(struct radeon_device *rdev);
 462 int radeon_semaphore_create(struct radeon_device *rdev,
 463                             struct radeon_semaphore **semaphore);
 464 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
 465                                   struct radeon_semaphore *semaphore);
 466 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
 467                                 struct radeon_semaphore *semaphore);
 468 void radeon_semaphore_free(struct radeon_device *rdev,
 469                            struct radeon_semaphore *semaphore);
 470
 471 /*
 472  * GART structures, functions & helpers
 473  */
 474 struct radeon_mc;
 475
 476 #define RADEON_GPU_PAGE_SIZE 4096
 477 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 478 #define RADEON_GPU_PAGE_SHIFT 12
 479 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 480
 481 struct radeon_gart {
 482         dma_addr_t                      table_addr;
 483         struct radeon_bo                *robj;
 484         void                            *ptr;
 485         unsigned                        num_gpu_pages;
 486         unsigned                        num_cpu_pages;
 487         unsigned                        table_size;
 488         struct page                     **pages;
 489         dma_addr_t                      *pages_addr;
 490         bool                            ready;
 491 };
 492
 493 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 494 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 495 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 496 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 497 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 498 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 499 int radeon_gart_init(struct radeon_device *rdev);
 500 void radeon_gart_fini(struct radeon_device *rdev);
 501 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 502                         int pages);
 503 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 504                      int pages, struct page **pagelist,
 505                      dma_addr_t *dma_addr);
 506 void radeon_gart_restore(struct radeon_device *rdev);
 507
 508
 509 /*
 510  * GPU MC structures, functions & helpers
 511  */
 512 struct radeon_mc {
 513         resource_size_t         aper_size;
 514         resource_size_t         aper_base;
 515         resource_size_t         agp_base;
 516         /* for some chips with <= 32MB we need to lie
 517          * about vram size near mc fb location */
 518         u64                     mc_vram_size;
 519         u64                     visible_vram_size;
 520         u64                     gtt_size;
 521         u64                     gtt_start;
 522         u64                     gtt_end;
 523         u64                     vram_start;
 524         u64                     vram_end;
 525         unsigned                vram_width;
 526         u64                     real_vram_size;
 527         int                     vram_mtrr;
 528         bool                    vram_is_ddr;
 529         bool                    igp_sideport_enabled;
 530         u64                     gtt_base_align;
 531 };
 532
 533 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 534 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 535
 536 /*
 537  * GPU scratch registers structures, functions & helpers
 538  */
 539 struct radeon_scratch {
 540         unsigned                num_reg;
 541         uint32_t                reg_base;
 542         bool                    free[32];
 543         uint32_t                reg[32];
 544 };
 545
 546 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 547 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 548
 549
 550 /*
 551  * IRQS.
 552  */
 553
 554 struct radeon_unpin_work {
 555         struct work_struct work;
 556         struct radeon_device *rdev;
 557         int crtc_id;
 558         struct radeon_fence *fence;
 559         struct drm_pending_vblank_event *event;
 560         struct radeon_bo *old_rbo;
 561         u64 new_crtc_base;
 562 };
 563
 564 struct r500_irq_stat_regs {
 565         u32 disp_int;
 566 };
 567
 568 struct r600_irq_stat_regs {
 569         u32 disp_int;
 570         u32 disp_int_cont;
 571         u32 disp_int_cont2;
 572         u32 d1grph_int;
 573         u32 d2grph_int;
 574 };
 575
 576 struct evergreen_irq_stat_regs {
 577         u32 disp_int;
 578         u32 disp_int_cont;
 579         u32 disp_int_cont2;
 580         u32 disp_int_cont3;
 581         u32 disp_int_cont4;
 582         u32 disp_int_cont5;
 583         u32 d1grph_int;
 584         u32 d2grph_int;
 585         u32 d3grph_int;
 586         u32 d4grph_int;
 587         u32 d5grph_int;
 588         u32 d6grph_int;
 589 };
 590
 591 union radeon_irq_stat_regs {
 592         struct r500_irq_stat_regs r500;
 593         struct r600_irq_stat_regs r600;
 594         struct evergreen_irq_stat_regs evergreen;
 595 };
 596
 597 #define RADEON_MAX_HPD_PINS 6
 598 #define RADEON_MAX_CRTCS 6
 599 #define RADEON_MAX_HDMI_BLOCKS 2
 600
 601 struct radeon_irq {
 602         bool            installed;
 603         bool            sw_int[RADEON_NUM_RINGS];
 604         bool            crtc_vblank_int[RADEON_MAX_CRTCS];
 605         bool            pflip[RADEON_MAX_CRTCS];
 606         wait_queue_head_t       vblank_queue;
 607         bool            hpd[RADEON_MAX_HPD_PINS];
 608         bool            gui_idle;
 609         bool            gui_idle_acked;
 610         wait_queue_head_t       idle_queue;
 611         bool            hdmi[RADEON_MAX_HDMI_BLOCKS];
 612         spinlock_t sw_lock;
 613         int sw_refcount[RADEON_NUM_RINGS];
 614         union radeon_irq_stat_regs stat_regs;
 615         spinlock_t pflip_lock[RADEON_MAX_CRTCS];
 616         int pflip_refcount[RADEON_MAX_CRTCS];
 617 };
 618
 619 int radeon_irq_kms_init(struct radeon_device *rdev);
 620 void radeon_irq_kms_fini(struct radeon_device *rdev);
 621 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
 622 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
 623 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 624 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 625
 626 /*
 627  * CP & rings.
 628  */
 629
 630 struct radeon_ib {
 631         struct radeon_sa_bo     sa_bo;
 632         unsigned                idx;
 633         uint32_t                length_dw;
 634         uint64_t                gpu_addr;
 635         uint32_t                *ptr;
 636         struct radeon_fence     *fence;
 637         unsigned                vm_id;
 638 };
 639
 640 /*
 641  * locking -
 642  * mutex protects scheduled_ibs, ready, alloc_bm
 643  */
 644 struct radeon_ib_pool {
 645         struct radeon_mutex             mutex;
 646         struct radeon_sa_manager        sa_manager;
 647         struct radeon_ib                ibs[RADEON_IB_POOL_SIZE];
 648         bool                            ready;
 649         unsigned                        head_id;
 650 };
 651
 652 struct radeon_ring {
 653         struct radeon_bo        *ring_obj;
 654         volatile uint32_t       *ring;
 655         unsigned                rptr;
 656         unsigned                rptr_offs;
 657         unsigned                rptr_reg;
 658         unsigned                wptr;
 659         unsigned                wptr_old;
 660         unsigned                wptr_reg;
 661         unsigned                ring_size;
 662         unsigned                ring_free_dw;
 663         int                     count_dw;
 664         uint64_t                gpu_addr;
 665         uint32_t                align_mask;
 666         uint32_t                ptr_mask;
 667         struct mutex            mutex;
 668         bool                    ready;
 669         u32                     ptr_reg_shift;
 670         u32                     ptr_reg_mask;
 671         u32                     nop;
 672 };
 673
 674 /*
 675  * VM
 676  */
 677 struct radeon_vm {
 678         struct list_head                list;
 679         struct list_head                va;
 680         int                             id;
 681         unsigned                        last_pfn;
 682         u64                             pt_gpu_addr;
 683         u64                             *pt;
 684         struct radeon_sa_bo             sa_bo;
 685         struct mutex                    mutex;
 686         /* last fence for cs using this vm */
 687         struct radeon_fence             *fence;
 688 };
 689
 690 struct radeon_vm_funcs {
 691         int (*init)(struct radeon_device *rdev);
 692         void (*fini)(struct radeon_device *rdev);
 693         /* cs mutex must be lock for schedule_ib */
 694         int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
 695         void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
 696         void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
 697         uint32_t (*page_flags)(struct radeon_device *rdev,
 698                                struct radeon_vm *vm,
 699                                uint32_t flags);
 700         void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
 701                         unsigned pfn, uint64_t addr, uint32_t flags);
 702 };
 703
 704 struct radeon_vm_manager {
 705         struct list_head                lru_vm;
 706         uint32_t                        use_bitmap;
 707         struct radeon_sa_manager        sa_manager;
 708         uint32_t                        max_pfn;
 709         /* fields constant after init */
 710         const struct radeon_vm_funcs    *funcs;
 711         /* number of VMIDs */
 712         unsigned                        nvm;
 713         /* vram base address for page table entry  */
 714         u64                             vram_base_offset;
 715         /* is vm enabled? */
 716         bool                            enabled;
 717 };
 718
 719 /*
 720  * file private structure
 721  */
 722 struct radeon_fpriv {
 723         struct radeon_vm                vm;
 724 };
 725
 726 /*
 727  * R6xx+ IH ring
 728  */
 729 struct r600_ih {
 730         struct radeon_bo        *ring_obj;
 731         volatile uint32_t       *ring;
 732         unsigned                rptr;
 733         unsigned                rptr_offs;
 734         unsigned                wptr;
 735         unsigned                wptr_old;
 736         unsigned                ring_size;
 737         uint64_t                gpu_addr;
 738         uint32_t                ptr_mask;
 739         spinlock_t              lock;
 740         bool                    enabled;
 741 };
 742
 743 struct r600_blit_cp_primitives {
 744         void (*set_render_target)(struct radeon_device *rdev, int format,
 745                                   int w, int h, u64 gpu_addr);
 746         void (*cp_set_surface_sync)(struct radeon_device *rdev,
 747                                     u32 sync_type, u32 size,
 748                                     u64 mc_addr);
 749         void (*set_shaders)(struct radeon_device *rdev);
 750         void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
 751         void (*set_tex_resource)(struct radeon_device *rdev,
 752                                  int format, int w, int h, int pitch,
 753                                  u64 gpu_addr, u32 size);
 754         void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
 755                              int x2, int y2);
 756         void (*draw_auto)(struct radeon_device *rdev);
 757         void (*set_default_state)(struct radeon_device *rdev);
 758 };
 759
 760 struct r600_blit {
 761         struct mutex            mutex;
 762         struct radeon_bo        *shader_obj;
 763         struct r600_blit_cp_primitives primitives;
 764         int max_dim;
 765         int ring_size_common;
 766         int ring_size_per_loop;
 767         u64 shader_gpu_addr;
 768         u32 vs_offset, ps_offset;
 769         u32 state_offset;
 770         u32 state_len;
 771         u32 vb_used, vb_total;
 772         struct radeon_ib *vb_ib;
 773 };
 774
 775 void r600_blit_suspend(struct radeon_device *rdev);
 776
 777 int radeon_ib_get(struct radeon_device *rdev, int ring,
 778                   struct radeon_ib **ib, unsigned size);
 779 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 780 bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib);
 781 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 782 int radeon_ib_pool_init(struct radeon_device *rdev);
 783 void radeon_ib_pool_fini(struct radeon_device *rdev);
 784 int radeon_ib_pool_start(struct radeon_device *rdev);
 785 int radeon_ib_pool_suspend(struct radeon_device *rdev);
 786 /* Ring access between begin & end cannot sleep */
 787 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
 788 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
 789 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 790 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 791 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 792 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 793 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
 794 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 795 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
 796                      unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
 797                      u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
 798 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
 799
 800
 801 /*
 802  * CS.
 803  */
 804 struct radeon_cs_reloc {
 805         struct drm_gem_object           *gobj;
 806         struct radeon_bo                *robj;
 807         struct radeon_bo_list           lobj;
 808         uint32_t                        handle;
 809         uint32_t                        flags;
 810 };
 811
 812 struct radeon_cs_chunk {
 813         uint32_t                chunk_id;
 814         uint32_t                length_dw;
 815         int                     kpage_idx[2];
 816         uint32_t                *kpage[2];
 817         uint32_t                *kdata;
 818         void __user             *user_ptr;
 819         int                     last_copied_page;
 820         int                     last_page_index;
 821 };
 822
 823 struct radeon_cs_parser {
 824         struct device           *dev;
 825         struct radeon_device    *rdev;
 826         struct drm_file         *filp;
 827         /* chunks */
 828         unsigned                nchunks;
 829         struct radeon_cs_chunk  *chunks;
 830         uint64_t                *chunks_array;
 831         /* IB */
 832         unsigned                idx;
 833         /* relocations */
 834         unsigned                nrelocs;
 835         struct radeon_cs_reloc  *relocs;
 836         struct radeon_cs_reloc  **relocs_ptr;
 837         struct list_head        validated;
 838         /* indices of various chunks */
 839         int                     chunk_ib_idx;
 840         int                     chunk_relocs_idx;
 841         int                     chunk_flags_idx;
 842         struct radeon_ib        *ib;
 843         void                    *track;
 844         unsigned                family;
 845         int                     parser_error;
 846         u32                     cs_flags;
 847         u32                     ring;
 848         s32                     priority;
 849 };
 850
 851 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 852 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 853 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
 854
 855 struct radeon_cs_packet {
 856         unsigned        idx;
 857         unsigned        type;
 858         unsigned        reg;
 859         unsigned        opcode;
 860         int             count;
 861         unsigned        one_reg_wr;
 862 };
 863
 864 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 865                                       struct radeon_cs_packet *pkt,
 866                                       unsigned idx, unsigned reg);
 867 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 868                                       struct radeon_cs_packet *pkt);
 869
 870
 871 /*
 872  * AGP
 873  */
 874 int radeon_agp_init(struct radeon_device *rdev);
 875 void radeon_agp_resume(struct radeon_device *rdev);
 876 void radeon_agp_suspend(struct radeon_device *rdev);
 877 void radeon_agp_fini(struct radeon_device *rdev);
 878
 879
 880 /*
 881  * Writeback
 882  */
 883 struct radeon_wb {
 884         struct radeon_bo        *wb_obj;
 885         volatile uint32_t       *wb;
 886         uint64_t                gpu_addr;
 887         bool                    enabled;
 888         bool                    use_event;
 889 };
 890
 891 #define RADEON_WB_SCRATCH_OFFSET 0
 892 #define RADEON_WB_CP_RPTR_OFFSET 1024
 893 #define RADEON_WB_CP1_RPTR_OFFSET 1280
 894 #define RADEON_WB_CP2_RPTR_OFFSET 1536
 895 #define R600_WB_IH_WPTR_OFFSET   2048
 896 #define R600_WB_EVENT_OFFSET     3072
 897
 898 /**
 899  * struct radeon_pm - power management datas
 900  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 901  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 902  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 903  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 904  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 905  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 906  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 907  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 908  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 909  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
 910  * @needed_bandwidth:   current bandwidth needs
 911  *
 912  * It keeps track of various data needed to take powermanagement decision.
 913  * Bandwidth need is used to determine minimun clock of the GPU and memory.
 914  * Equation between gpu/memory clock and available bandwidth is hw dependent
 915  * (type of memory, bus size, efficiency, ...)
 916  */
 917
 918 enum radeon_pm_method {
 919         PM_METHOD_PROFILE,
 920         PM_METHOD_DYNPM,
 921 };
 922
 923 enum radeon_dynpm_state {
 924         DYNPM_STATE_DISABLED,
 925         DYNPM_STATE_MINIMUM,
 926         DYNPM_STATE_PAUSED,
 927         DYNPM_STATE_ACTIVE,
 928         DYNPM_STATE_SUSPENDED,
 929 };
 930 enum radeon_dynpm_action {
 931         DYNPM_ACTION_NONE,
 932         DYNPM_ACTION_MINIMUM,
 933         DYNPM_ACTION_DOWNCLOCK,
 934         DYNPM_ACTION_UPCLOCK,
 935         DYNPM_ACTION_DEFAULT
 936 };
 937
 938 enum radeon_voltage_type {
 939         VOLTAGE_NONE = 0,
 940         VOLTAGE_GPIO,
 941         VOLTAGE_VDDC,
 942         VOLTAGE_SW
 943 };
 944
 945 enum radeon_pm_state_type {
 946         POWER_STATE_TYPE_DEFAULT,
 947         POWER_STATE_TYPE_POWERSAVE,
 948         POWER_STATE_TYPE_BATTERY,
 949         POWER_STATE_TYPE_BALANCED,
 950         POWER_STATE_TYPE_PERFORMANCE,
 951 };
 952
 953 enum radeon_pm_profile_type {
 954         PM_PROFILE_DEFAULT,
 955         PM_PROFILE_AUTO,
 956         PM_PROFILE_LOW,
 957         PM_PROFILE_MID,
 958         PM_PROFILE_HIGH,
 959 };
 960
 961 #define PM_PROFILE_DEFAULT_IDX 0
 962 #define PM_PROFILE_LOW_SH_IDX  1
 963 #define PM_PROFILE_MID_SH_IDX  2
 964 #define PM_PROFILE_HIGH_SH_IDX 3
 965 #define PM_PROFILE_LOW_MH_IDX  4
 966 #define PM_PROFILE_MID_MH_IDX  5
 967 #define PM_PROFILE_HIGH_MH_IDX 6
 968 #define PM_PROFILE_MAX         7
 969
 970 struct radeon_pm_profile {
 971         int dpms_off_ps_idx;
 972         int dpms_on_ps_idx;
 973         int dpms_off_cm_idx;
 974         int dpms_on_cm_idx;
 975 };
 976
 977 enum radeon_int_thermal_type {
 978         THERMAL_TYPE_NONE,
 979         THERMAL_TYPE_RV6XX,
 980         THERMAL_TYPE_RV770,
 981         THERMAL_TYPE_EVERGREEN,
 982         THERMAL_TYPE_SUMO,
 983         THERMAL_TYPE_NI,
 984 };
 985
 986 struct radeon_voltage {
 987         enum radeon_voltage_type type;
 988         /* gpio voltage */
 989         struct radeon_gpio_rec gpio;
 990         u32 delay; /* delay in usec from voltage drop to sclk change */
 991         bool active_high; /* voltage drop is active when bit is high */
 992         /* VDDC voltage */
 993         u8 vddc_id; /* index into vddc voltage table */
 994         u8 vddci_id; /* index into vddci voltage table */
 995         bool vddci_enabled;
 996         /* r6xx+ sw */
 997         u16 voltage;
 998         /* evergreen+ vddci */
 999         u16 vddci;
1000 };
1001
1002 /* clock mode flags */
1003 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
1004
1005 struct radeon_pm_clock_info {
1006         /* memory clock */
1007         u32 mclk;
1008         /* engine clock */
1009         u32 sclk;
1010         /* voltage info */
1011         struct radeon_voltage voltage;
1012         /* standardized clock flags */
1013         u32 flags;
1014 };
1015
1016 /* state flags */
1017 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1018
1019 struct radeon_power_state {
1020         enum radeon_pm_state_type type;
1021         struct radeon_pm_clock_info *clock_info;
1022         /* number of valid clock modes in this power state */
1023         int num_clock_modes;
1024         struct radeon_pm_clock_info *default_clock_mode;
1025         /* standardized state flags */
1026         u32 flags;
1027         u32 misc; /* vbios specific flags */
1028         u32 misc2; /* vbios specific flags */
1029         int pcie_lanes; /* pcie lanes */
1030 };
1031
1032 /*
1033  * Some modes are overclocked by very low value, accept them
1034  */
1035 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1036
1037 struct radeon_pm {
1038         struct mutex            mutex;
1039         u32                     active_crtcs;
1040         int                     active_crtc_count;
1041         int                     req_vblank;
1042         bool                    vblank_sync;
1043         bool                    gui_idle;
1044         fixed20_12              max_bandwidth;
1045         fixed20_12              igp_sideport_mclk;
1046         fixed20_12              igp_system_mclk;
1047         fixed20_12              igp_ht_link_clk;
1048         fixed20_12              igp_ht_link_width;
1049         fixed20_12              k8_bandwidth;
1050         fixed20_12              sideport_bandwidth;
1051         fixed20_12              ht_bandwidth;
1052         fixed20_12              core_bandwidth;
1053         fixed20_12              sclk;
1054         fixed20_12              mclk;
1055         fixed20_12              needed_bandwidth;
1056         struct radeon_power_state *power_state;
1057         /* number of valid power states */
1058         int                     num_power_states;
1059         int                     current_power_state_index;
1060         int                     current_clock_mode_index;
1061         int                     requested_power_state_index;
1062         int                     requested_clock_mode_index;
1063         int                     default_power_state_index;
1064         u32                     current_sclk;
1065         u32                     current_mclk;
1066         u16                     current_vddc;
1067         u16                     current_vddci;
1068         u32                     default_sclk;
1069         u32                     default_mclk;
1070         u16                     default_vddc;
1071         u16                     default_vddci;
1072         struct radeon_i2c_chan *i2c_bus;
1073         /* selected pm method */
1074         enum radeon_pm_method     pm_method;
1075         /* dynpm power management */
1076         struct delayed_work     dynpm_idle_work;
1077         enum radeon_dynpm_state dynpm_state;
1078         enum radeon_dynpm_action        dynpm_planned_action;
1079         unsigned long           dynpm_action_timeout;
1080         bool                    dynpm_can_upclock;
1081         bool                    dynpm_can_downclock;
1082         /* profile-based power management */
1083         enum radeon_pm_profile_type profile;
1084         int                     profile_index;
1085         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1086         /* internal thermal controller on rv6xx+ */
1087         enum radeon_int_thermal_type int_thermal_type;
1088         struct device           *int_hwmon_dev;
1089 };
1090
1091 int radeon_pm_get_type_index(struct radeon_device *rdev,
1092                              enum radeon_pm_state_type ps_type,
1093                              int instance);
1094
1095 /*
1096  * Benchmarking
1097  */
1098 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1099
1100
1101 /*
1102  * Testing
1103  */
1104 void radeon_test_moves(struct radeon_device *rdev);
1105 void radeon_test_ring_sync(struct radeon_device *rdev,
1106                            struct radeon_ring *cpA,
1107                            struct radeon_ring *cpB);
1108 void radeon_test_syncing(struct radeon_device *rdev);
1109
1110
1111 /*
1112  * Debugfs
1113  */
1114 struct radeon_debugfs {
1115         struct drm_info_list    *files;
1116         unsigned                num_files;
1117 };
1118
1119 int radeon_debugfs_add_files(struct radeon_device *rdev,
1120                              struct drm_info_list *files,
1121                              unsigned nfiles);
1122 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1123
1124
1125 /*
1126  * ASIC specific functions.
1127  */
1128 struct radeon_asic {
1129         int (*init)(struct radeon_device *rdev);
1130         void (*fini)(struct radeon_device *rdev);
1131         int (*resume)(struct radeon_device *rdev);
1132         int (*suspend)(struct radeon_device *rdev);
1133         void (*vga_set_state)(struct radeon_device *rdev, bool state);
1134         bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1135         int (*asic_reset)(struct radeon_device *rdev);
1136
1137         struct {
1138                 void (*tlb_flush)(struct radeon_device *rdev);
1139                 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1140         } gart;
1141
1142         struct {
1143                 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1144                 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1145                 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1146                 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1147                                        struct radeon_semaphore *semaphore, bool emit_wait);
1148                 int (*cs_parse)(struct radeon_cs_parser *p);
1149                 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1150                 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1151                 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1152         } ring[RADEON_NUM_RINGS];
1153
1154         struct {
1155                 int (*set)(struct radeon_device *rdev);
1156                 int (*process)(struct radeon_device *rdev);
1157         } irq;
1158
1159         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1160
1161         struct {
1162                 int (*blit)(struct radeon_device *rdev,
1163                             uint64_t src_offset,
1164                             uint64_t dst_offset,
1165                             unsigned num_gpu_pages,
1166                             struct radeon_fence *fence);
1167                 u32 blit_ring_index;
1168                 int (*dma)(struct radeon_device *rdev,
1169                            uint64_t src_offset,
1170                            uint64_t dst_offset,
1171                            unsigned num_gpu_pages,
1172                            struct radeon_fence *fence);
1173                 u32 dma_ring_index;
1174                 /* method used for bo copy */
1175                 int (*copy)(struct radeon_device *rdev,
1176                             uint64_t src_offset,
1177                             uint64_t dst_offset,
1178                             unsigned num_gpu_pages,
1179                             struct radeon_fence *fence);
1180                 /* ring used for bo copies */
1181                 u32 copy_ring_index;
1182         } copy;
1183
1184         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1185         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1186         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1187         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1188         int (*get_pcie_lanes)(struct radeon_device *rdev);
1189         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1190         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1191         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
1192                                uint32_t tiling_flags, uint32_t pitch,
1193                                uint32_t offset, uint32_t obj_size);
1194         void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
1195         void (*bandwidth_update)(struct radeon_device *rdev);
1196
1197         struct {
1198                 void (*init)(struct radeon_device *rdev);
1199                 void (*fini)(struct radeon_device *rdev);
1200                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1201                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1202         } hpd;
1203
1204         /* ioctl hw specific callback. Some hw might want to perform special
1205          * operation on specific ioctl. For instance on wait idle some hw
1206          * might want to perform and HDP flush through MMIO as it seems that
1207          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1208          * through ring.
1209          */
1210         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1211         /* check if 3D engine is idle */
1212         bool (*gui_idle)(struct radeon_device *rdev);
1213         /* power management */
1214         struct {
1215                 void (*misc)(struct radeon_device *rdev);
1216                 void (*prepare)(struct radeon_device *rdev);
1217                 void (*finish)(struct radeon_device *rdev);
1218                 void (*init_profile)(struct radeon_device *rdev);
1219                 void (*get_dynpm_state)(struct radeon_device *rdev);
1220         } pm;
1221         /* pageflipping */
1222         struct {
1223                 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1224                 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1225                 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1226         } pflip;
1227         /* wait for vblank */
1228         void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1229         /* wait for mc_idle */
1230         int (*mc_wait_for_idle)(struct radeon_device *rdev);
1231 };
1232
1233 /*
1234  * Asic structures
1235  */
1236 struct r100_gpu_lockup {
1237         unsigned long   last_jiffies;
1238         u32             last_cp_rptr;
1239 };
1240
1241 struct r100_asic {
1242         const unsigned          *reg_safe_bm;
1243         unsigned                reg_safe_bm_size;
1244         u32                     hdp_cntl;
1245         struct r100_gpu_lockup  lockup;
1246 };
1247
1248 struct r300_asic {
1249         const unsigned          *reg_safe_bm;
1250         unsigned                reg_safe_bm_size;
1251         u32                     resync_scratch;
1252         u32                     hdp_cntl;
1253         struct r100_gpu_lockup  lockup;
1254 };
1255
1256 struct r600_asic {
1257         unsigned                max_pipes;
1258         unsigned                max_tile_pipes;
1259         unsigned                max_simds;
1260         unsigned                max_backends;
1261         unsigned                max_gprs;
1262         unsigned                max_threads;
1263         unsigned                max_stack_entries;
1264         unsigned                max_hw_contexts;
1265         unsigned                max_gs_threads;
1266         unsigned                sx_max_export_size;
1267         unsigned                sx_max_export_pos_size;
1268         unsigned                sx_max_export_smx_size;
1269         unsigned                sq_num_cf_insts;
1270         unsigned                tiling_nbanks;
1271         unsigned                tiling_npipes;
1272         unsigned                tiling_group_size;
1273         unsigned                tile_config;
1274         unsigned                backend_map;
1275         struct r100_gpu_lockup  lockup;
1276 };
1277
1278 struct rv770_asic {
1279         unsigned                max_pipes;
1280         unsigned                max_tile_pipes;
1281         unsigned                max_simds;
1282         unsigned                max_backends;
1283         unsigned                max_gprs;
1284         unsigned                max_threads;
1285         unsigned                max_stack_entries;
1286         unsigned                max_hw_contexts;
1287         unsigned                max_gs_threads;
1288         unsigned                sx_max_export_size;
1289         unsigned                sx_max_export_pos_size;
1290         unsigned                sx_max_export_smx_size;
1291         unsigned                sq_num_cf_insts;
1292         unsigned                sx_num_of_sets;
1293         unsigned                sc_prim_fifo_size;
1294         unsigned                sc_hiz_tile_fifo_size;
1295         unsigned                sc_earlyz_tile_fifo_fize;
1296         unsigned                tiling_nbanks;
1297         unsigned                tiling_npipes;
1298         unsigned                tiling_group_size;
1299         unsigned                tile_config;
1300         unsigned                backend_map;
1301         struct r100_gpu_lockup  lockup;
1302 };
1303
1304 struct evergreen_asic {
1305         unsigned num_ses;
1306         unsigned max_pipes;
1307         unsigned max_tile_pipes;
1308         unsigned max_simds;
1309         unsigned max_backends;
1310         unsigned max_gprs;
1311         unsigned max_threads;
1312         unsigned max_stack_entries;
1313         unsigned max_hw_contexts;
1314         unsigned max_gs_threads;
1315         unsigned sx_max_export_size;
1316         unsigned sx_max_export_pos_size;
1317         unsigned sx_max_export_smx_size;
1318         unsigned sq_num_cf_insts;
1319         unsigned sx_num_of_sets;
1320         unsigned sc_prim_fifo_size;
1321         unsigned sc_hiz_tile_fifo_size;
1322         unsigned sc_earlyz_tile_fifo_size;
1323         unsigned tiling_nbanks;
1324         unsigned tiling_npipes;
1325         unsigned tiling_group_size;
1326         unsigned tile_config;
1327         unsigned backend_map;
1328         struct r100_gpu_lockup  lockup;
1329 };
1330
1331 struct cayman_asic {
1332         unsigned max_shader_engines;
1333         unsigned max_pipes_per_simd;
1334         unsigned max_tile_pipes;
1335         unsigned max_simds_per_se;
1336         unsigned max_backends_per_se;
1337         unsigned max_texture_channel_caches;
1338         unsigned max_gprs;
1339         unsigned max_threads;
1340         unsigned max_gs_threads;
1341         unsigned max_stack_entries;
1342         unsigned sx_num_of_sets;
1343         unsigned sx_max_export_size;
1344         unsigned sx_max_export_pos_size;
1345         unsigned sx_max_export_smx_size;
1346         unsigned max_hw_contexts;
1347         unsigned sq_num_cf_insts;
1348         unsigned sc_prim_fifo_size;
1349         unsigned sc_hiz_tile_fifo_size;
1350         unsigned sc_earlyz_tile_fifo_size;
1351
1352         unsigned num_shader_engines;
1353         unsigned num_shader_pipes_per_simd;
1354         unsigned num_tile_pipes;
1355         unsigned num_simds_per_se;
1356         unsigned num_backends_per_se;
1357         unsigned backend_disable_mask_per_asic;
1358         unsigned backend_map;
1359         unsigned num_texture_channel_caches;
1360         unsigned mem_max_burst_length_bytes;
1361         unsigned mem_row_size_in_kb;
1362         unsigned shader_engine_tile_size;
1363         unsigned num_gpus;
1364         unsigned multi_gpu_tile_size;
1365
1366         unsigned tile_config;
1367         struct r100_gpu_lockup  lockup;
1368 };
1369
1370 union radeon_asic_config {
1371         struct r300_asic        r300;
1372         struct r100_asic        r100;
1373         struct r600_asic        r600;
1374         struct rv770_asic       rv770;
1375         struct evergreen_asic   evergreen;
1376         struct cayman_asic      cayman;
1377 };
1378
1379 /*
1380  * asic initizalization from radeon_asic.c
1381  */
1382 void radeon_agp_disable(struct radeon_device *rdev);
1383 int radeon_asic_init(struct radeon_device *rdev);
1384
1385
1386 /*
1387  * IOCTL.
1388  */
1389 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1390                           struct drm_file *filp);
1391 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1392                             struct drm_file *filp);
1393 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1394                          struct drm_file *file_priv);
1395 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1396                            struct drm_file *file_priv);
1397 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1398                             struct drm_file *file_priv);
1399 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1400                            struct drm_file *file_priv);
1401 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1402                                 struct drm_file *filp);
1403 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1404                           struct drm_file *filp);
1405 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1406                           struct drm_file *filp);
1407 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1408                               struct drm_file *filp);
1409 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1410                           struct drm_file *filp);
1411 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1412 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1413                                 struct drm_file *filp);
1414 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1415                                 struct drm_file *filp);
1416
1417 /* VRAM scratch page for HDP bug, default vram page */
1418 struct r600_vram_scratch {
1419         struct radeon_bo                *robj;
1420         volatile uint32_t               *ptr;
1421         u64                             gpu_addr;
1422 };
1423
1424
1425 /*
1426  * Core structure, functions and helpers.
1427  */
1428 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1429 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1430
1431 struct radeon_device {
1432         struct device                   *dev;
1433         struct drm_device               *ddev;
1434         struct pci_dev                  *pdev;
1435         /* ASIC */
1436         union radeon_asic_config        config;
1437         enum radeon_family              family;
1438         unsigned long                   flags;
1439         int                             usec_timeout;
1440         enum radeon_pll_errata          pll_errata;
1441         int                             num_gb_pipes;
1442         int                             num_z_pipes;
1443         int                             disp_priority;
1444         /* BIOS */
1445         uint8_t                         *bios;
1446         bool                            is_atom_bios;
1447         uint16_t                        bios_header_start;
1448         struct radeon_bo                *stollen_vga_memory;
1449         /* Register mmio */
1450         resource_size_t                 rmmio_base;
1451         resource_size_t                 rmmio_size;
1452         void __iomem                    *rmmio;
1453         radeon_rreg_t                   mc_rreg;
1454         radeon_wreg_t                   mc_wreg;
1455         radeon_rreg_t                   pll_rreg;
1456         radeon_wreg_t                   pll_wreg;
1457         uint32_t                        pcie_reg_mask;
1458         radeon_rreg_t                   pciep_rreg;
1459         radeon_wreg_t                   pciep_wreg;
1460         /* io port */
1461         void __iomem                    *rio_mem;
1462         resource_size_t                 rio_mem_size;
1463         struct radeon_clock             clock;
1464         struct radeon_mc                mc;
1465         struct radeon_gart              gart;
1466         struct radeon_mode_info         mode_info;
1467         struct radeon_scratch           scratch;
1468         struct radeon_mman              mman;
1469         rwlock_t                        fence_lock;
1470         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
1471         struct radeon_semaphore_driver  semaphore_drv;
1472         struct radeon_ring              ring[RADEON_NUM_RINGS];
1473         struct radeon_ib_pool           ib_pool;
1474         struct radeon_irq               irq;
1475         struct radeon_asic              *asic;
1476         struct radeon_gem               gem;
1477         struct radeon_pm                pm;
1478         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1479         struct radeon_mutex             cs_mutex;
1480         struct radeon_wb                wb;
1481         struct radeon_dummy_page        dummy_page;
1482         bool                            gpu_lockup;
1483         bool                            shutdown;
1484         bool                            suspend;
1485         bool                            need_dma32;
1486         bool                            accel_working;
1487         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1488         const struct firmware *me_fw;   /* all family ME firmware */
1489         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
1490         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
1491         const struct firmware *mc_fw;   /* NI MC firmware */
1492         struct r600_blit r600_blit;
1493         struct r600_vram_scratch vram_scratch;
1494         int msi_enabled; /* msi enabled */
1495         struct r600_ih ih; /* r6/700 interrupt ring */
1496         struct work_struct hotplug_work;
1497         int num_crtc; /* number of crtcs */
1498         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1499         struct mutex vram_mutex;
1500
1501         /* audio stuff */
1502         bool                    audio_enabled;
1503         struct timer_list       audio_timer;
1504         int                     audio_channels;
1505         int                     audio_rate;
1506         int                     audio_bits_per_sample;
1507         uint8_t                 audio_status_bits;
1508         uint8_t                 audio_category_code;
1509
1510         struct notifier_block acpi_nb;
1511         /* only one userspace can use Hyperz features or CMASK at a time */
1512         struct drm_file *hyperz_filp;
1513         struct drm_file *cmask_filp;
1514         /* i2c buses */
1515         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1516         /* debugfs */
1517         struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1518         unsigned                debugfs_count;
1519         /* virtual memory */
1520         struct radeon_vm_manager        vm_manager;
1521 };
1522
1523 int radeon_device_init(struct radeon_device *rdev,
1524                        struct drm_device *ddev,
1525                        struct pci_dev *pdev,
1526                        uint32_t flags);
1527 void radeon_device_fini(struct radeon_device *rdev);
1528 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1529
1530 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1531 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1532 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1533 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1534
1535 /*
1536  * Cast helper
1537  */
1538 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1539
1540 /*
1541  * Registers read & write functions.
1542  */
1543 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1544 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1545 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1546 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1547 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1548 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1549 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1550 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1551 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1552 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1553 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1554 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1555 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1556 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1557 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1558 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1559 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1560 #define WREG32_P(reg, val, mask)                                \
1561         do {                                                    \
1562                 uint32_t tmp_ = RREG32(reg);                    \
1563                 tmp_ &= (mask);                                 \
1564                 tmp_ |= ((val) & ~(mask));                      \
1565                 WREG32(reg, tmp_);                              \
1566         } while (0)
1567 #define WREG32_PLL_P(reg, val, mask)                            \
1568         do {                                                    \
1569                 uint32_t tmp_ = RREG32_PLL(reg);                \
1570                 tmp_ &= (mask);                                 \
1571                 tmp_ |= ((val) & ~(mask));                      \
1572                 WREG32_PLL(reg, tmp_);                          \
1573         } while (0)
1574 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1575 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1576 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1577
1578 /*
1579  * Indirect registers accessor
1580  */
1581 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1582 {
1583         uint32_t r;
1584
1585         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1586         r = RREG32(RADEON_PCIE_DATA);
1587         return r;
1588 }
1589
1590 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1591 {
1592         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1593         WREG32(RADEON_PCIE_DATA, (v));
1594 }
1595
1596 void r100_pll_errata_after_index(struct radeon_device *rdev);
1597
1598
1599 /*
1600  * ASICs helpers.
1601  */
1602 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1603                             (rdev->pdev->device == 0x5969))
1604 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1605                 (rdev->family == CHIP_RV200) || \
1606                 (rdev->family == CHIP_RS100) || \
1607                 (rdev->family == CHIP_RS200) || \
1608                 (rdev->family == CHIP_RV250) || \
1609                 (rdev->family == CHIP_RV280) || \
1610                 (rdev->family == CHIP_RS300))
1611 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1612                 (rdev->family == CHIP_RV350) ||                 \
1613                 (rdev->family == CHIP_R350)  ||                 \
1614                 (rdev->family == CHIP_RV380) ||                 \
1615                 (rdev->family == CHIP_R420)  ||                 \
1616                 (rdev->family == CHIP_R423)  ||                 \
1617                 (rdev->family == CHIP_RV410) ||                 \
1618                 (rdev->family == CHIP_RS400) ||                 \
1619                 (rdev->family == CHIP_RS480))
1620 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1621                 (rdev->ddev->pdev->device == 0x9443) || \
1622                 (rdev->ddev->pdev->device == 0x944B) || \
1623                 (rdev->ddev->pdev->device == 0x9506) || \
1624                 (rdev->ddev->pdev->device == 0x9509) || \
1625                 (rdev->ddev->pdev->device == 0x950F) || \
1626                 (rdev->ddev->pdev->device == 0x689C) || \
1627                 (rdev->ddev->pdev->device == 0x689D))
1628 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1629 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
1630                             (rdev->family == CHIP_RS690)  ||    \
1631                             (rdev->family == CHIP_RS740)  ||    \
1632                             (rdev->family >= CHIP_R600))
1633 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1634 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1635 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1636 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1637                              (rdev->flags & RADEON_IS_IGP))
1638 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1639
1640 /*
1641  * BIOS helpers.
1642  */
1643 #define RBIOS8(i) (rdev->bios[i])
1644 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1645 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1646
1647 int radeon_combios_init(struct radeon_device *rdev);
1648 void radeon_combios_fini(struct radeon_device *rdev);
1649 int radeon_atombios_init(struct radeon_device *rdev);
1650 void radeon_atombios_fini(struct radeon_device *rdev);
1651
1652
1653 /*
1654  * RING helpers.
1655  */
1656 #if DRM_DEBUG_CODE == 0
1657 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1658 {
1659         ring->ring[ring->wptr++] = v;
1660         ring->wptr &= ring->ptr_mask;
1661         ring->count_dw--;
1662         ring->ring_free_dw--;
1663 }
1664 #else
1665 /* With debugging this is just too big to inline */
1666 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1667 #endif
1668
1669 /*
1670  * ASICs macro.
1671  */
1672 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1673 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1674 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1675 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1676 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1677 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1678 #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
1679 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1680 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1681 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1682 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1683 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1684 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1685 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1686 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1687 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1688 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1689 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1690 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1691 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1692 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1693 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1694 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1695 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1696 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1697 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1698 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1699 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1700 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1701 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1702 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1703 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1704 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1705 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1706 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1707 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1708 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1709 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1710 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1711 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1712 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1713 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1714 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1715 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1716 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1717 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1718 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1719 #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1720 #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1721 #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->wait_for_vblank((rdev), (crtc))
1722 #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1723
1724 /* Common functions */
1725 /* AGP */
1726 extern int radeon_gpu_reset(struct radeon_device *rdev);
1727 extern void radeon_agp_disable(struct radeon_device *rdev);
1728 extern int radeon_modeset_init(struct radeon_device *rdev);
1729 extern void radeon_modeset_fini(struct radeon_device *rdev);
1730 extern bool radeon_card_posted(struct radeon_device *rdev);
1731 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1732 extern void radeon_update_display_priority(struct radeon_device *rdev);
1733 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1734 extern void radeon_scratch_init(struct radeon_device *rdev);
1735 extern void radeon_wb_fini(struct radeon_device *rdev);
1736 extern int radeon_wb_init(struct radeon_device *rdev);
1737 extern void radeon_wb_disable(struct radeon_device *rdev);
1738 extern void radeon_surface_init(struct radeon_device *rdev);
1739 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1740 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1741 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1742 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1743 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1744 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1745 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1746 extern int radeon_resume_kms(struct drm_device *dev);
1747 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1748 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1749
1750 /*
1751  * vm
1752  */
1753 int radeon_vm_manager_init(struct radeon_device *rdev);
1754 void radeon_vm_manager_fini(struct radeon_device *rdev);
1755 int radeon_vm_manager_start(struct radeon_device *rdev);
1756 int radeon_vm_manager_suspend(struct radeon_device *rdev);
1757 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1758 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1759 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1760 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1761 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1762                             struct radeon_vm *vm,
1763                             struct radeon_bo *bo,
1764                             struct ttm_mem_reg *mem);
1765 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1766                              struct radeon_bo *bo);
1767 int radeon_vm_bo_add(struct radeon_device *rdev,
1768                      struct radeon_vm *vm,
1769                      struct radeon_bo *bo,
1770                      uint64_t offset,
1771                      uint32_t flags);
1772 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1773                      struct radeon_vm *vm,
1774                      struct radeon_bo *bo);
1775
1776
1777 /*
1778  * R600 vram scratch functions
1779  */
1780 int r600_vram_scratch_init(struct radeon_device *rdev);
1781 void r600_vram_scratch_fini(struct radeon_device *rdev);
1782
1783 /*
1784  * r600 cs checking helper
1785  */
1786 unsigned r600_mip_minify(unsigned size, unsigned level);
1787 bool r600_fmt_is_valid_color(u32 format);
1788 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1789 int r600_fmt_get_blocksize(u32 format);
1790 int r600_fmt_get_nblocksx(u32 format, u32 w);
1791 int r600_fmt_get_nblocksy(u32 format, u32 h);
1792
1793 /*
1794  * r600 functions used by radeon_encoder.c
1795  */
1796 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1797 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1798 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1799
1800 extern int ni_init_microcode(struct radeon_device *rdev);
1801 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1802
1803 /* radeon_acpi.c */
1804 #if defined(CONFIG_ACPI)
1805 extern int radeon_acpi_init(struct radeon_device *rdev);
1806 #else
1807 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1808 #endif
1809
1810 #include "radeon_object.h"
1811
1812 #endif