2 * I2C Link Layer for PN544 HCI based Driver
4 * Copyright (C) 2012 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/crc-ccitt.h>
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/gpio.h>
25 #include <linux/miscdevice.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/nfc.h>
29 #include <linux/firmware.h>
30 #include <linux/unaligned/access_ok.h>
31 #include <linux/platform_data/pn544.h>
33 #include <net/nfc/hci.h>
34 #include <net/nfc/llc.h>
35 #include <net/nfc/nfc.h>
39 #define PN544_I2C_FRAME_HEADROOM 1
40 #define PN544_I2C_FRAME_TAILROOM 2
42 /* framing in HCI mode */
43 #define PN544_HCI_I2C_LLC_LEN 1
44 #define PN544_HCI_I2C_LLC_CRC 2
45 #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \
46 PN544_HCI_I2C_LLC_CRC)
47 #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC)
48 #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29
49 #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \
50 PN544_HCI_I2C_LLC_MAX_PAYLOAD)
52 static struct i2c_device_id pn544_hci_i2c_id_table
[] = {
57 MODULE_DEVICE_TABLE(i2c
, pn544_hci_i2c_id_table
);
59 #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
62 * Exposed through the 4 most significant bytes
63 * from the HCI SW_VERSION first byte, a.k.a.
66 #define PN544_HW_VARIANT_C2 0xa
67 #define PN544_HW_VARIANT_C3 0xb
69 #define PN544_FW_CMD_RESET 0x01
70 #define PN544_FW_CMD_WRITE 0x08
71 #define PN544_FW_CMD_CHECK 0x06
72 #define PN544_FW_CMD_SECURE_WRITE 0x0C
73 #define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D
75 struct pn544_i2c_fw_frame_write
{
83 struct pn544_i2c_fw_frame_check
{
91 struct pn544_i2c_fw_frame_response
{
96 struct pn544_i2c_fw_blob
{
102 struct pn544_i2c_fw_secure_frame
{
108 struct pn544_i2c_fw_secure_blob
{
113 #define PN544_FW_CMD_RESULT_TIMEOUT 0x01
114 #define PN544_FW_CMD_RESULT_BAD_CRC 0x02
115 #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08
116 #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B
117 #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11
118 #define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13
119 #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18
120 #define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19
121 #define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D
122 #define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20
123 #define PN544_FW_CMD_RESULT_CHUNK_OK 0x21
124 #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74
125 #define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0
126 #define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6
128 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
130 #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7
131 #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE
132 #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8
133 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\
134 PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\
135 PN544_FW_WRITE_BUFFER_MAX_LEN)
136 #define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3
137 #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\
138 PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN)
139 #define PN544_FW_SECURE_FRAME_HEADER_LEN 3
140 #define PN544_FW_SECURE_BLOB_HEADER_LEN 8
142 #define FW_WORK_STATE_IDLE 1
143 #define FW_WORK_STATE_START 2
144 #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3
145 #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4
146 #define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5
148 struct pn544_i2c_phy
{
149 struct i2c_client
*i2c_dev
;
150 struct nfc_hci_dev
*hdev
;
152 unsigned int gpio_en
;
153 unsigned int gpio_irq
;
154 unsigned int gpio_fw
;
155 unsigned int en_polarity
;
159 struct work_struct fw_work
;
161 char firmware_name
[NFC_FIRMWARE_NAME_MAXSIZE
+ 1];
162 const struct firmware
*fw
;
163 u32 fw_blob_dest_addr
;
165 const u8
*fw_blob_data
;
175 * < 0 if hardware error occured (e.g. i2c err)
176 * and prevents normal operation.
180 #define I2C_DUMP_SKB(info, skb) \
182 pr_debug("%s:\n", info); \
183 print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \
184 16, 1, (skb)->data, (skb)->len, 0); \
187 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy
*phy
)
189 int polarity
, retry
, ret
;
190 char rset_cmd
[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 };
191 int count
= sizeof(rset_cmd
);
193 nfc_info(&phy
->i2c_dev
->dev
, "Detecting nfc_en polarity\n");
195 /* Disable fw download */
196 gpio_set_value(phy
->gpio_fw
, 0);
198 for (polarity
= 0; polarity
< 2; polarity
++) {
199 phy
->en_polarity
= polarity
;
203 gpio_set_value(phy
->gpio_en
, !phy
->en_polarity
);
204 usleep_range(10000, 15000);
207 gpio_set_value(phy
->gpio_en
, phy
->en_polarity
);
208 usleep_range(10000, 15000);
211 dev_dbg(&phy
->i2c_dev
->dev
, "Sending reset cmd\n");
212 ret
= i2c_master_send(phy
->i2c_dev
, rset_cmd
, count
);
214 nfc_info(&phy
->i2c_dev
->dev
,
215 "nfc_en polarity : active %s\n",
216 (polarity
== 0 ? "low" : "high"));
222 nfc_err(&phy
->i2c_dev
->dev
,
223 "Could not detect nfc_en polarity, fallback to active high\n");
226 gpio_set_value(phy
->gpio_en
, !phy
->en_polarity
);
229 static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy
*phy
, int run_mode
)
231 gpio_set_value(phy
->gpio_fw
, run_mode
== PN544_FW_MODE
? 1 : 0);
232 gpio_set_value(phy
->gpio_en
, phy
->en_polarity
);
233 usleep_range(10000, 15000);
235 phy
->run_mode
= run_mode
;
238 static int pn544_hci_i2c_enable(void *phy_id
)
240 struct pn544_i2c_phy
*phy
= phy_id
;
242 pr_info("%s\n", __func__
);
244 pn544_hci_i2c_enable_mode(phy
, PN544_HCI_MODE
);
251 static void pn544_hci_i2c_disable(void *phy_id
)
253 struct pn544_i2c_phy
*phy
= phy_id
;
255 gpio_set_value(phy
->gpio_fw
, 0);
256 gpio_set_value(phy
->gpio_en
, !phy
->en_polarity
);
257 usleep_range(10000, 15000);
259 gpio_set_value(phy
->gpio_en
, phy
->en_polarity
);
260 usleep_range(10000, 15000);
262 gpio_set_value(phy
->gpio_en
, !phy
->en_polarity
);
263 usleep_range(10000, 15000);
268 static void pn544_hci_i2c_add_len_crc(struct sk_buff
*skb
)
274 *skb_push(skb
, 1) = len
;
276 crc
= crc_ccitt(0xffff, skb
->data
, skb
->len
);
278 *skb_put(skb
, 1) = crc
& 0xff;
279 *skb_put(skb
, 1) = crc
>> 8;
282 static void pn544_hci_i2c_remove_len_crc(struct sk_buff
*skb
)
284 skb_pull(skb
, PN544_I2C_FRAME_HEADROOM
);
285 skb_trim(skb
, PN544_I2C_FRAME_TAILROOM
);
289 * Writing a frame must not return the number of written bytes.
290 * It must return either zero for success, or <0 for error.
291 * In addition, it must not alter the skb
293 static int pn544_hci_i2c_write(void *phy_id
, struct sk_buff
*skb
)
296 struct pn544_i2c_phy
*phy
= phy_id
;
297 struct i2c_client
*client
= phy
->i2c_dev
;
299 if (phy
->hard_fault
!= 0)
300 return phy
->hard_fault
;
302 usleep_range(3000, 6000);
304 pn544_hci_i2c_add_len_crc(skb
);
306 I2C_DUMP_SKB("i2c frame written", skb
);
308 r
= i2c_master_send(client
, skb
->data
, skb
->len
);
310 if (r
== -EREMOTEIO
) { /* Retry, chip was in standby */
311 usleep_range(6000, 10000);
312 r
= i2c_master_send(client
, skb
->data
, skb
->len
);
322 pn544_hci_i2c_remove_len_crc(skb
);
327 static int check_crc(u8
*buf
, int buflen
)
333 crc
= crc_ccitt(0xffff, buf
, len
- 2);
336 if (buf
[len
- 2] != (crc
& 0xff) || buf
[len
- 1] != (crc
>> 8)) {
337 pr_err("CRC error 0x%x != 0x%x 0x%x\n",
338 crc
, buf
[len
- 1], buf
[len
- 2]);
339 pr_info("%s: BAD CRC\n", __func__
);
340 print_hex_dump(KERN_DEBUG
, "crc: ", DUMP_PREFIX_NONE
,
341 16, 2, buf
, buflen
, false);
348 * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees
349 * that i2c bus will be flushed and that next read will start on a new frame.
350 * returned skb contains only LLC header and payload.
352 * -EREMOTEIO : i2c read error (fatal)
353 * -EBADMSG : frame was incorrect and discarded
354 * -ENOMEM : cannot allocate skb, frame dropped
356 static int pn544_hci_i2c_read(struct pn544_i2c_phy
*phy
, struct sk_buff
**skb
)
360 u8 tmp
[PN544_HCI_I2C_LLC_MAX_SIZE
- 1];
361 struct i2c_client
*client
= phy
->i2c_dev
;
363 r
= i2c_master_recv(client
, &len
, 1);
365 nfc_err(&client
->dev
, "cannot read len byte\n");
369 if ((len
< (PN544_HCI_I2C_LLC_MIN_SIZE
- 1)) ||
370 (len
> (PN544_HCI_I2C_LLC_MAX_SIZE
- 1))) {
371 nfc_err(&client
->dev
, "invalid len byte\n");
376 *skb
= alloc_skb(1 + len
, GFP_KERNEL
);
382 *skb_put(*skb
, 1) = len
;
384 r
= i2c_master_recv(client
, skb_put(*skb
, len
), len
);
390 I2C_DUMP_SKB("i2c frame read", *skb
);
392 r
= check_crc((*skb
)->data
, (*skb
)->len
);
400 skb_trim(*skb
, (*skb
)->len
- 2);
402 usleep_range(3000, 6000);
407 if (i2c_master_recv(client
, tmp
, sizeof(tmp
)) < 0)
410 usleep_range(3000, 6000);
415 static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy
*phy
)
418 struct pn544_i2c_fw_frame_response response
;
419 struct i2c_client
*client
= phy
->i2c_dev
;
421 r
= i2c_master_recv(client
, (char *) &response
, sizeof(response
));
422 if (r
!= sizeof(response
)) {
423 nfc_err(&client
->dev
, "cannot read fw status\n");
427 usleep_range(3000, 6000);
429 switch (response
.status
) {
432 case PN544_FW_CMD_RESULT_CHUNK_OK
:
433 return response
.status
;
434 case PN544_FW_CMD_RESULT_TIMEOUT
:
436 case PN544_FW_CMD_RESULT_BAD_CRC
:
438 case PN544_FW_CMD_RESULT_ACCESS_DENIED
:
440 case PN544_FW_CMD_RESULT_PROTOCOL_ERROR
:
442 case PN544_FW_CMD_RESULT_INVALID_PARAMETER
:
444 case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND
:
446 case PN544_FW_CMD_RESULT_INVALID_LENGTH
:
448 case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR
:
450 case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR
:
452 case PN544_FW_CMD_RESULT_MEMORY_ERROR
:
454 case PN544_FW_CMD_RESULT_COMMAND_REJECTED
:
456 case PN544_FW_CMD_RESULT_WRITE_FAILED
:
457 case PN544_FW_CMD_RESULT_CHUNK_ERROR
:
465 * Reads an shdlc frame from the chip. This is not as straightforward as it
466 * seems. There are cases where we could loose the frame start synchronization.
467 * The frame format is len-data-crc, and corruption can occur anywhere while
468 * transiting on i2c bus, such that we could read an invalid len.
469 * In order to recover synchronization with the next frame, we must be sure
470 * to read the real amount of data without using the len byte. We do this by
471 * assuming the following:
472 * - the chip will always present only one single complete frame on the bus
473 * before triggering the interrupt
474 * - the chip will not present a new frame until we have completely read
475 * the previous one (or until we have handled the interrupt).
476 * The tricky case is when we read a corrupted len that is less than the real
477 * len. We must detect this here in order to determine that we need to flush
478 * the bus. This is the reason why we check the crc here.
480 static irqreturn_t
pn544_hci_i2c_irq_thread_fn(int irq
, void *phy_id
)
482 struct pn544_i2c_phy
*phy
= phy_id
;
483 struct i2c_client
*client
;
484 struct sk_buff
*skb
= NULL
;
487 if (!phy
|| irq
!= phy
->i2c_dev
->irq
) {
492 client
= phy
->i2c_dev
;
493 dev_dbg(&client
->dev
, "IRQ\n");
495 if (phy
->hard_fault
!= 0)
498 if (phy
->run_mode
== PN544_FW_MODE
) {
499 phy
->fw_cmd_result
= pn544_hci_i2c_fw_read_status(phy
);
500 schedule_work(&phy
->fw_work
);
502 r
= pn544_hci_i2c_read(phy
, &skb
);
503 if (r
== -EREMOTEIO
) {
506 nfc_hci_recv_frame(phy
->hdev
, NULL
);
509 } else if ((r
== -ENOMEM
) || (r
== -EBADMSG
)) {
513 nfc_hci_recv_frame(phy
->hdev
, skb
);
518 static struct nfc_phy_ops i2c_phy_ops
= {
519 .write
= pn544_hci_i2c_write
,
520 .enable
= pn544_hci_i2c_enable
,
521 .disable
= pn544_hci_i2c_disable
,
524 static int pn544_hci_i2c_fw_download(void *phy_id
, const char *firmware_name
,
527 struct pn544_i2c_phy
*phy
= phy_id
;
529 pr_info("Starting Firmware Download (%s)\n", firmware_name
);
531 strcpy(phy
->firmware_name
, firmware_name
);
533 phy
->hw_variant
= hw_variant
;
534 phy
->fw_work_state
= FW_WORK_STATE_START
;
536 schedule_work(&phy
->fw_work
);
541 static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy
*phy
,
544 pr_info("Firmware Download Complete, result=%d\n", result
);
546 pn544_hci_i2c_disable(phy
);
548 phy
->fw_work_state
= FW_WORK_STATE_IDLE
;
551 release_firmware(phy
->fw
);
555 nfc_fw_download_done(phy
->hdev
->ndev
, phy
->firmware_name
, (u32
) -result
);
558 static int pn544_hci_i2c_fw_write_cmd(struct i2c_client
*client
, u32 dest_addr
,
559 const u8
*data
, u16 datalen
)
561 u8 frame
[PN544_FW_I2C_MAX_PAYLOAD
];
562 struct pn544_i2c_fw_frame_write
*framep
;
567 if (datalen
> PN544_FW_I2C_WRITE_DATA_MAX_LEN
)
568 datalen
= PN544_FW_I2C_WRITE_DATA_MAX_LEN
;
570 framep
= (struct pn544_i2c_fw_frame_write
*) frame
;
572 params_len
= sizeof(framep
->be_dest_addr
) +
573 sizeof(framep
->be_datalen
) + datalen
;
574 framelen
= params_len
+ sizeof(framep
->cmd
) +
575 sizeof(framep
->be_length
);
577 framep
->cmd
= PN544_FW_CMD_WRITE
;
579 put_unaligned_be16(params_len
, &framep
->be_length
);
581 framep
->be_dest_addr
[0] = (dest_addr
& 0xff0000) >> 16;
582 framep
->be_dest_addr
[1] = (dest_addr
& 0xff00) >> 8;
583 framep
->be_dest_addr
[2] = dest_addr
& 0xff;
585 put_unaligned_be16(datalen
, &framep
->be_datalen
);
587 memcpy(framep
->data
, data
, datalen
);
589 r
= i2c_master_send(client
, frame
, framelen
);
599 static int pn544_hci_i2c_fw_check_cmd(struct i2c_client
*client
, u32 start_addr
,
600 const u8
*data
, u16 datalen
)
602 struct pn544_i2c_fw_frame_check frame
;
606 /* calculate local crc for the data we want to check */
607 crc
= crc_ccitt(0xffff, data
, datalen
);
609 frame
.cmd
= PN544_FW_CMD_CHECK
;
611 put_unaligned_be16(sizeof(frame
.be_start_addr
) +
612 sizeof(frame
.be_datalen
) + sizeof(frame
.be_crc
),
615 /* tell the chip the memory region to which our crc applies */
616 frame
.be_start_addr
[0] = (start_addr
& 0xff0000) >> 16;
617 frame
.be_start_addr
[1] = (start_addr
& 0xff00) >> 8;
618 frame
.be_start_addr
[2] = start_addr
& 0xff;
620 put_unaligned_be16(datalen
, &frame
.be_datalen
);
623 * and give our local crc. Chip will calculate its own crc for the
624 * region and compare with ours.
626 put_unaligned_be16(crc
, &frame
.be_crc
);
628 r
= i2c_master_send(client
, (const char *) &frame
, sizeof(frame
));
630 if (r
== sizeof(frame
))
638 static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy
*phy
)
642 r
= pn544_hci_i2c_fw_write_cmd(phy
->i2c_dev
,
643 phy
->fw_blob_dest_addr
+ phy
->fw_written
,
644 phy
->fw_blob_data
+ phy
->fw_written
,
645 phy
->fw_blob_size
- phy
->fw_written
);
649 phy
->fw_written
+= r
;
650 phy
->fw_work_state
= FW_WORK_STATE_WAIT_WRITE_ANSWER
;
655 static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy
*phy
,
656 const u8
*data
, u16 datalen
)
658 u8 buf
[PN544_FW_I2C_MAX_PAYLOAD
];
659 struct pn544_i2c_fw_secure_frame
*chunk
;
663 if (datalen
> PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN
)
664 datalen
= PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN
;
666 chunk
= (struct pn544_i2c_fw_secure_frame
*) buf
;
668 chunk
->cmd
= PN544_FW_CMD_SECURE_CHUNK_WRITE
;
670 put_unaligned_be16(datalen
, &chunk
->be_datalen
);
672 memcpy(chunk
->data
, data
, datalen
);
674 chunklen
= sizeof(chunk
->cmd
) + sizeof(chunk
->be_datalen
) + datalen
;
676 r
= i2c_master_send(phy
->i2c_dev
, buf
, chunklen
);
687 static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy
*phy
)
689 struct pn544_i2c_fw_secure_frame
*framep
;
692 framep
= (struct pn544_i2c_fw_secure_frame
*) phy
->fw_blob_data
;
693 if (phy
->fw_written
== 0)
694 phy
->fw_blob_size
= get_unaligned_be16(&framep
->be_datalen
)
695 + PN544_FW_SECURE_FRAME_HEADER_LEN
;
697 /* Only secure write command can be chunked*/
698 if (phy
->fw_blob_size
> PN544_FW_I2C_MAX_PAYLOAD
&&
699 framep
->cmd
!= PN544_FW_CMD_SECURE_WRITE
)
702 /* The firmware also have other commands, we just send them directly */
703 if (phy
->fw_blob_size
< PN544_FW_I2C_MAX_PAYLOAD
) {
704 r
= i2c_master_send(phy
->i2c_dev
,
705 (const char *) phy
->fw_blob_data
, phy
->fw_blob_size
);
707 if (r
== phy
->fw_blob_size
)
715 r
= pn544_hci_i2c_fw_secure_write_frame_cmd(phy
,
716 phy
->fw_blob_data
+ phy
->fw_written
,
717 phy
->fw_blob_size
- phy
->fw_written
);
722 phy
->fw_written
+= r
;
723 phy
->fw_work_state
= FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER
;
725 /* SW reset command will not trig any response from PN544 */
726 if (framep
->cmd
== PN544_FW_CMD_RESET
) {
727 pn544_hci_i2c_enable_mode(phy
, PN544_FW_MODE
);
728 phy
->fw_cmd_result
= 0;
729 schedule_work(&phy
->fw_work
);
735 static void pn544_hci_i2c_fw_work(struct work_struct
*work
)
737 struct pn544_i2c_phy
*phy
= container_of(work
, struct pn544_i2c_phy
,
740 struct pn544_i2c_fw_blob
*blob
;
741 struct pn544_i2c_fw_secure_blob
*secure_blob
;
743 switch (phy
->fw_work_state
) {
744 case FW_WORK_STATE_START
:
745 pn544_hci_i2c_enable_mode(phy
, PN544_FW_MODE
);
747 r
= request_firmware(&phy
->fw
, phy
->firmware_name
,
750 goto exit_state_start
;
754 switch (phy
->hw_variant
) {
755 case PN544_HW_VARIANT_C2
:
756 blob
= (struct pn544_i2c_fw_blob
*) phy
->fw
->data
;
757 phy
->fw_blob_size
= get_unaligned_be32(&blob
->be_size
);
758 phy
->fw_blob_dest_addr
= get_unaligned_be32(
760 phy
->fw_blob_data
= blob
->data
;
762 r
= pn544_hci_i2c_fw_write_chunk(phy
);
764 case PN544_HW_VARIANT_C3
:
765 secure_blob
= (struct pn544_i2c_fw_secure_blob
*)
767 phy
->fw_blob_data
= secure_blob
->data
;
768 phy
->fw_size
= phy
->fw
->size
;
769 r
= pn544_hci_i2c_fw_secure_write_frame(phy
);
778 pn544_hci_i2c_fw_work_complete(phy
, r
);
781 case FW_WORK_STATE_WAIT_WRITE_ANSWER
:
782 r
= phy
->fw_cmd_result
;
784 goto exit_state_wait_write_answer
;
786 if (phy
->fw_written
== phy
->fw_blob_size
) {
787 r
= pn544_hci_i2c_fw_check_cmd(phy
->i2c_dev
,
788 phy
->fw_blob_dest_addr
,
792 goto exit_state_wait_write_answer
;
793 phy
->fw_work_state
= FW_WORK_STATE_WAIT_CHECK_ANSWER
;
797 r
= pn544_hci_i2c_fw_write_chunk(phy
);
799 exit_state_wait_write_answer
:
801 pn544_hci_i2c_fw_work_complete(phy
, r
);
804 case FW_WORK_STATE_WAIT_CHECK_ANSWER
:
805 r
= phy
->fw_cmd_result
;
807 goto exit_state_wait_check_answer
;
809 blob
= (struct pn544_i2c_fw_blob
*) (phy
->fw_blob_data
+
811 phy
->fw_blob_size
= get_unaligned_be32(&blob
->be_size
);
812 if (phy
->fw_blob_size
!= 0) {
813 phy
->fw_blob_dest_addr
=
814 get_unaligned_be32(&blob
->be_destaddr
);
815 phy
->fw_blob_data
= blob
->data
;
818 r
= pn544_hci_i2c_fw_write_chunk(phy
);
821 exit_state_wait_check_answer
:
822 if (r
< 0 || phy
->fw_blob_size
== 0)
823 pn544_hci_i2c_fw_work_complete(phy
, r
);
826 case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER
:
827 r
= phy
->fw_cmd_result
;
829 goto exit_state_wait_secure_write_answer
;
831 if (r
== PN544_FW_CMD_RESULT_CHUNK_OK
) {
832 r
= pn544_hci_i2c_fw_secure_write_frame(phy
);
833 goto exit_state_wait_secure_write_answer
;
836 if (phy
->fw_written
== phy
->fw_blob_size
) {
837 secure_blob
= (struct pn544_i2c_fw_secure_blob
*)
838 (phy
->fw_blob_data
+ phy
->fw_blob_size
);
839 phy
->fw_size
-= phy
->fw_blob_size
+
840 PN544_FW_SECURE_BLOB_HEADER_LEN
;
841 if (phy
->fw_size
>= PN544_FW_SECURE_BLOB_HEADER_LEN
842 + PN544_FW_SECURE_FRAME_HEADER_LEN
) {
843 phy
->fw_blob_data
= secure_blob
->data
;
846 r
= pn544_hci_i2c_fw_secure_write_frame(phy
);
850 exit_state_wait_secure_write_answer
:
851 if (r
< 0 || phy
->fw_size
== 0)
852 pn544_hci_i2c_fw_work_complete(phy
, r
);
860 static int pn544_hci_i2c_probe(struct i2c_client
*client
,
861 const struct i2c_device_id
*id
)
863 struct pn544_i2c_phy
*phy
;
864 struct pn544_nfc_platform_data
*pdata
;
867 dev_dbg(&client
->dev
, "%s\n", __func__
);
868 dev_dbg(&client
->dev
, "IRQ: %d\n", client
->irq
);
870 if (!i2c_check_functionality(client
->adapter
, I2C_FUNC_I2C
)) {
871 nfc_err(&client
->dev
, "Need I2C_FUNC_I2C\n");
875 phy
= devm_kzalloc(&client
->dev
, sizeof(struct pn544_i2c_phy
),
878 nfc_err(&client
->dev
,
879 "Cannot allocate memory for pn544 i2c phy.\n");
883 INIT_WORK(&phy
->fw_work
, pn544_hci_i2c_fw_work
);
884 phy
->fw_work_state
= FW_WORK_STATE_IDLE
;
886 phy
->i2c_dev
= client
;
887 i2c_set_clientdata(client
, phy
);
889 pdata
= client
->dev
.platform_data
;
891 nfc_err(&client
->dev
, "No platform data\n");
895 if (pdata
->request_resources
== NULL
) {
896 nfc_err(&client
->dev
, "request_resources() missing\n");
900 r
= pdata
->request_resources(client
);
902 nfc_err(&client
->dev
, "Cannot get platform resources\n");
906 phy
->gpio_en
= pdata
->get_gpio(NFC_GPIO_ENABLE
);
907 phy
->gpio_fw
= pdata
->get_gpio(NFC_GPIO_FW_RESET
);
908 phy
->gpio_irq
= pdata
->get_gpio(NFC_GPIO_IRQ
);
910 pn544_hci_i2c_platform_init(phy
);
912 r
= request_threaded_irq(client
->irq
, NULL
, pn544_hci_i2c_irq_thread_fn
,
913 IRQF_TRIGGER_RISING
| IRQF_ONESHOT
,
914 PN544_HCI_I2C_DRIVER_NAME
, phy
);
916 nfc_err(&client
->dev
, "Unable to register IRQ handler\n");
920 r
= pn544_hci_probe(phy
, &i2c_phy_ops
, LLC_SHDLC_NAME
,
921 PN544_I2C_FRAME_HEADROOM
, PN544_I2C_FRAME_TAILROOM
,
922 PN544_HCI_I2C_LLC_MAX_PAYLOAD
,
923 pn544_hci_i2c_fw_download
, &phy
->hdev
);
930 free_irq(client
->irq
, phy
);
933 if (pdata
->free_resources
!= NULL
)
934 pdata
->free_resources();
939 static int pn544_hci_i2c_remove(struct i2c_client
*client
)
941 struct pn544_i2c_phy
*phy
= i2c_get_clientdata(client
);
942 struct pn544_nfc_platform_data
*pdata
= client
->dev
.platform_data
;
944 dev_dbg(&client
->dev
, "%s\n", __func__
);
946 cancel_work_sync(&phy
->fw_work
);
947 if (phy
->fw_work_state
!= FW_WORK_STATE_IDLE
)
948 pn544_hci_i2c_fw_work_complete(phy
, -ENODEV
);
950 pn544_hci_remove(phy
->hdev
);
953 pn544_hci_i2c_disable(phy
);
955 free_irq(client
->irq
, phy
);
956 if (pdata
->free_resources
)
957 pdata
->free_resources();
962 static struct i2c_driver pn544_hci_i2c_driver
= {
964 .name
= PN544_HCI_I2C_DRIVER_NAME
,
966 .probe
= pn544_hci_i2c_probe
,
967 .id_table
= pn544_hci_i2c_id_table
,
968 .remove
= pn544_hci_i2c_remove
,
971 module_i2c_driver(pn544_hci_i2c_driver
);
973 MODULE_LICENSE("GPL");
974 MODULE_DESCRIPTION(DRIVER_DESC
);