| blob | 1fa61ca4a3889439061ccfd25ed149373730ddd2 |
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/interrupt.h>
40 #include <linux/tcp.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/cpu.h>
48 #include <linux/smp.h>
49 #include <linux/pm_qos.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/aer.h>
52 #include <linux/prefetch.h>
62 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
82 };
85 u32 ofs;
87 };
90 /* General Registers */
95 /* Interrupt Registers */
98 /* Rx Registers */
114 /* Tx Registers */
131 /* List Terminator */
133 };
135 /**
136 * e1000_regdump - register printout routine
137 * @hw: pointer to the HW structure
138 * @reginfo: pointer to the register info table
139 **/
141 {
163 }
167 }
171 {
183 }
184 }
185 }
187 /**
188 * e1000e_dump - Print registers, Tx-ring and Rx-ring
189 * @adapter: board private structure
190 **/
192 {
199 __le64 a;
200 __le64 b;
207 __le64 a;
208 __le64 b;
209 __le64 c;
210 __le64 d;
212 u32 staterr;
218 /* Print netdevice Info */
225 }
227 /* Print Registers */
233 }
235 /* Print Tx Ring Summary */
249 /* Print Tx Ring */
255 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
256 *
257 * Legacy Transmit Descriptor
258 * +--------------------------------------------------------------+
259 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
260 * +--------------------------------------------------------------+
261 * 8 | Special | CSS | Status | CMD | CSO | Length |
262 * +--------------------------------------------------------------+
263 * 63 48 47 36 35 32 31 24 23 16 15 0
264 *
265 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
266 * 63 48 47 40 39 32 31 16 15 8 7 0
267 * +----------------------------------------------------------------+
268 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
269 * +----------------------------------------------------------------+
270 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
271 * +----------------------------------------------------------------+
272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
273 *
274 * Extended Data Descriptor (DTYP=0x1)
275 * +----------------------------------------------------------------+
276 * 0 | Buffer Address [63:0] |
277 * +----------------------------------------------------------------+
278 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
279 * +----------------------------------------------------------------+
280 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
281 */
282 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
283 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
284 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
296 else
301 i,
313 }
315 /* Print Rx Ring Summary */
316 rx_ring_summary:
322 /* Print Rx Ring */
331 /* [Extended] Packet Split Receive Descriptor Format
332 *
333 * +-----------------------------------------------------+
334 * 0 | Buffer Address 0 [63:0] |
335 * +-----------------------------------------------------+
336 * 8 | Buffer Address 1 [63:0] |
337 * +-----------------------------------------------------+
338 * 16 | Buffer Address 2 [63:0] |
339 * +-----------------------------------------------------+
340 * 24 | Buffer Address 3 [63:0] |
341 * +-----------------------------------------------------+
342 */
343 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
344 /* [Extended] Receive Descriptor (Write-Back) Format
345 *
346 * 63 48 47 32 31 13 12 8 7 4 3 0
347 * +------------------------------------------------------+
348 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
349 * | Checksum | Ident | | Queue | | Type |
350 * +------------------------------------------------------+
351 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
352 * +------------------------------------------------------+
353 * 63 48 47 32 31 20 19 0
354 */
355 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
361 staterr =
368 else
372 /* Descriptor Done */
392 buffer_info);
393 }
394 }
398 /* Extended Receive Descriptor (Read) Format
399 *
400 * +-----------------------------------------------------+
401 * 0 | Buffer Address [63:0] |
402 * +-----------------------------------------------------+
403 * 8 | Reserved |
404 * +-----------------------------------------------------+
405 */
406 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
407 /* Extended Receive Descriptor (Write-Back) Format
408 *
409 * 63 48 47 32 31 24 23 4 3 0
410 * +------------------------------------------------------+
411 * | RSS Hash | | | |
412 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
413 * | Packet | IP | | | Type |
414 * | Checksum | Ident | | | |
415 * +------------------------------------------------------+
416 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
417 * +------------------------------------------------------+
418 * 63 48 47 32 31 20 19 0
419 */
434 else
438 /* Descriptor Done */
460 }
461 }
462 }
463 }
465 /**
466 * e1000_desc_unused - calculate if we have unused descriptors
467 **/
469 {
474 }
476 /**
477 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
478 * @adapter: board private structure
479 * @hwtstamps: time stamp structure to update
480 * @systim: unsigned 64bit system time value.
481 *
482 * Convert the system time value stored in the RX/TXSTMP registers into a
483 * hwtstamp which can be used by the upper level time stamping functions.
484 *
485 * The 'systim_lock' spinlock is used to protect the consistency of the
486 * system time value. This is needed because reading the 64 bit time
487 * value involves reading two 32 bit registers. The first read latches the
488 * value.
489 **/
492 u64 systim)
493 {
494 u64 ns;
503 }
505 /**
506 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
507 * @adapter: board private structure
508 * @status: descriptor extended error and status field
509 * @skb: particular skb to include time stamp
510 *
511 * If the time stamp is valid, convert it into the timecounter ns value
512 * and store that result into the shhwtstamps structure which is passed
513 * up the network stack.
514 **/
517 {
519 u64 rxstmp;
526 /* The Rx time stamp registers contain the time stamp. No other
527 * received packet will be time stamped until the Rx time stamp
528 * registers are read. Because only one packet can be time stamped
529 * at a time, the register values must belong to this packet and
530 * therefore none of the other additional attributes need to be
531 * compared.
532 */
538 }
540 /**
541 * e1000_receive_skb - helper function to handle Rx indications
542 * @adapter: board private structure
543 * @staterr: descriptor extended error and status field as written by hardware
544 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
545 * @skb: pointer to sk_buff to be indicated to stack
546 **/
550 {
561 }
563 /**
564 * e1000_rx_checksum - Receive Checksum Offload
565 * @adapter: board private structure
566 * @status_err: receive descriptor status and error fields
567 * @csum: receive descriptor csum field
568 * @sk_buff: socket buffer with received data
569 **/
572 {
578 /* Rx checksum disabled */
582 /* Ignore Checksum bit is set */
586 /* TCP/UDP checksum error bit or IP checksum error bit is set */
588 /* let the stack verify checksum errors */
591 }
593 /* TCP/UDP Checksum has not been calculated */
597 /* It must be a TCP or UDP packet with a valid checksum */
600 }
603 {
615 }
616 }
619 {
631 }
632 }
634 /**
635 * e1000_alloc_rx_buffers - Replace used receive buffers
636 * @rx_ring: Rx descriptor ring
637 **/
640 {
658 }
662 /* Better luck next round */
665 }
668 map_skb:
671 DMA_FROM_DEVICE);
676 }
682 /* Force memory writes to complete before letting h/w
683 * know there are new descriptors to fetch. (Only
684 * applicable for weak-ordered memory model archs,
685 * such as IA-64).
686 */
690 else
692 }
693 i++;
697 }
700 }
702 /**
703 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
704 * @rx_ring: Rx descriptor ring
705 **/
708 {
727 /* all unused desc entries get hw null ptr */
731 }
737 }
741 DMA_FROM_DEVICE);
748 }
749 }
750 /* Refresh the desc even if buffer_addrs
751 * didn't change because each write-back
752 * erases this info.
753 */
756 }
760 gfp);
765 }
770 DMA_FROM_DEVICE);
774 /* cleanup skb */
778 }
783 /* Force memory writes to complete before letting h/w
784 * know there are new descriptors to fetch. (Only
785 * applicable for weak-ordered memory model archs,
786 * such as IA-64).
787 */
791 else
793 }
795 i++;
799 }
801 no_buffers:
803 }
805 /**
806 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
807 * @rx_ring: Rx descriptor ring
808 * @cleaned_count: number of buffers to allocate this pass
809 **/
813 {
831 }
835 /* Better luck next round */
838 }
841 check_page:
842 /* allocate a new page if necessary */
848 }
849 }
854 PAGE_SIZE,
855 DMA_FROM_DEVICE);
863 }
870 /* Force memory writes to complete before letting h/w
871 * know there are new descriptors to fetch. (Only
872 * applicable for weak-ordered memory model archs,
873 * such as IA-64).
874 */
878 else
880 }
881 }
885 {
888 }
890 /**
891 * e1000_clean_rx_irq - Send received data up the network stack
892 * @rx_ring: Rx descriptor ring
893 *
894 * the return value indicates whether actual cleaning was done, there
895 * is no guarantee that everything was cleaned
896 **/
899 {
930 i++;
939 cleaned_count++;
943 DMA_FROM_DEVICE);
948 /* !EOP means multiple descriptors were used to store a single
949 * packet, if that's the case we need to toss it. In fact, we
950 * need to toss every packet with the EOP bit clear and the
951 * next frame that _does_ have the EOP bit set, as it is by
952 * definition only a frame fragment
953 */
958 /* All receives must fit into a single buffer */
960 /* recycle */
965 }
969 /* recycle */
972 }
974 /* adjust length to remove Ethernet CRC */
976 /* If configured to store CRC, don't subtract FCS,
977 * but keep the FCS bytes out of the total_rx_bytes
978 * counter
979 */
982 else
984 }
987 total_rx_packets++;
989 /* code added for copybreak, this should improve
990 * performance for small packets with large amounts
991 * of reassembly being done in the stack
992 */
1000 NET_IP_ALIGN),
1002 NET_IP_ALIGN));
1003 /* save the skb in buffer_info as good */
1006 }
1007 /* else just continue with the old one */
1008 }
1009 /* end copybreak code */
1012 /* Receive Checksum Offload */
1020 next_desc:
1023 /* return some buffers to hardware, one at a time is too slow */
1026 GFP_ATOMIC);
1028 }
1030 /* use prefetched values */
1035 }
1045 }
1049 {
1056 else
1060 }
1064 }
1066 }
1069 {
1072 print_hang_task);
1080 u16 pci_status;
1087 /* May be block on write-back, flush and detect again
1088 * flush pending descriptor writebacks to memory
1089 */
1091 /* execute the writes immediately */
1093 /* Due to rare timing issues, write to TIDV again to ensure
1094 * the write is successful
1095 */
1097 /* execute the writes immediately */
1101 }
1102 /* Real hang detected */
1112 /* detected Hardware unit hang */
1133 eop,
1134 jiffies,
1137 phy_status,
1138 phy_1000t_status,
1139 phy_ext_status,
1140 pci_status);
1142 /* Suggest workaround for known h/w issue */
1145 }
1147 /**
1148 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1149 * @work: pointer to work struct
1150 *
1151 * This work function polls the TSYNCTXCTL valid bit to determine when a
1152 * timestamp has been taken for the current stored skb. The timestamp must
1153 * be for this skb because only one such packet is allowed in the queue.
1154 */
1156 {
1158 tx_hwtstamp_work);
1166 u64 txstmp;
1177 /* reschedule to check later */
1179 }
1180 }
1182 /**
1183 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1184 * @tx_ring: Tx descriptor ring
1185 *
1186 * the return value indicates whether actual cleaning was done, there
1187 * is no guarantee that everything was cleaned
1188 **/
1190 {
1219 pkts_compl++;
1220 }
1221 }
1226 i++;
1229 }
1235 }
1241 #define TX_WAKE_THRESHOLD 32
1244 /* Make sure that anybody stopping the queue after this
1245 * sees the new next_to_clean.
1246 */
1253 }
1254 }
1257 /* Detect a transmit hang in hardware, this serializes the
1258 * check with the clearing of time_stamp and movement of i
1259 */
1266 else
1268 }
1272 }
1274 /**
1275 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1276 * @rx_ring: Rx descriptor ring
1277 *
1278 * the return value indicates whether actual cleaning was done, there
1279 * is no guarantee that everything was cleaned
1280 **/
1283 {
1310 /* in the packet split case this is header only */
1313 i++;
1322 cleaned_count++;
1327 /* see !EOP comment in other Rx routine */
1337 }
1343 }
1351 }
1353 /* Good Receive */
1356 {
1357 /* this looks ugly, but it seems compiler issues make
1358 * it more efficient than reusing j
1359 */
1362 /* page alloc/put takes too long and effects small
1363 * packet throughput, so unsplit small packets and
1364 * save the alloc/put only valid in softirq (napi)
1365 * context to call kmap_*
1366 */
1373 /* there is no documentation about how to call
1374 * kmap_atomic, so we can't hold the mapping
1375 * very long
1376 */
1379 PAGE_SIZE,
1380 DMA_FROM_DEVICE);
1386 PAGE_SIZE,
1387 DMA_FROM_DEVICE);
1389 /* remove the CRC */
1393 }
1398 }
1407 DMA_FROM_DEVICE);
1414 }
1416 /* strip the ethernet crc, problem is we're using pages now so
1417 * this whole operation can get a little cpu intensive
1418 */
1422 }
1424 copydone:
1426 total_rx_packets++;
1439 next_desc:
1443 /* return some buffers to hardware, one at a time is too slow */
1446 GFP_ATOMIC);
1448 }
1450 /* use prefetched values */
1455 }
1465 }
1467 /**
1468 * e1000_consume_page - helper function
1469 **/
1471 u16 length)
1472 {
1477 }
1479 /**
1480 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1481 * @adapter: board private structure
1482 *
1483 * the return value indicates whether actual cleaning was done, there
1484 * is no guarantee that everything was cleaned
1485 **/
1488 {
1525 cleaned_count++;
1527 DMA_FROM_DEVICE);
1532 /* errors is only valid for DD + EOP descriptors */
1536 /* recycle both page and skb */
1538 /* an error means any chain goes out the window too */
1543 }
1545 #define rxtop (rx_ring->rx_skb_top)
1547 /* this descriptor is only the beginning (or middle) */
1549 /* this is the beginning of a chain */
1554 /* this is the middle of a chain */
1558 /* re-use the skb, only consumed the page */
1560 }
1565 /* end of the chain */
1569 /* re-use the current skb, we only consumed the
1570 * page
1571 */
1577 /* no chain, got EOP, this buf is the packet
1578 * copybreak to save the put_page/alloc_page
1579 */
1585 length);
1587 /* re-use the page, so don't erase
1588 * buffer_info->page
1589 */
1594 length);
1596 length);
1597 }
1598 }
1599 }
1601 /* Receive Checksum Offload */
1606 /* probably a little skewed due to removing CRC */
1608 total_rx_packets++;
1610 /* eth type trans needs skb->data to point to something */
1615 }
1620 next_desc:
1623 /* return some buffers to hardware, one at a time is too slow */
1626 GFP_ATOMIC);
1628 }
1630 /* use prefetched values */
1635 }
1645 }
1647 /**
1648 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1649 * @rx_ring: Rx descriptor ring
1650 **/
1652 {
1659 /* Free all the Rx ring sk_buffs */
1666 DMA_FROM_DEVICE);
1673 DMA_FROM_DEVICE);
1675 }
1680 }
1685 }
1692 DMA_FROM_DEVICE);
1696 }
1697 }
1699 /* there also may be some cached data from a chained receive */
1703 }
1705 /* Zero out the descriptor ring */
1715 else
1717 }
1720 {
1728 }
1730 /**
1731 * e1000_intr_msi - Interrupt Handler
1732 * @irq: interrupt number
1733 * @data: pointer to a network interface device structure
1734 **/
1736 {
1742 /* read ICR disables interrupts using IAM */
1745 /* ICH8 workaround-- Call gig speed drop workaround on cable
1746 * disconnect (LSC) before accessing any PHY registers
1747 */
1752 /* 80003ES2LAN workaround-- For packet buffer work-around on
1753 * link down event; disable receives here in the ISR and reset
1754 * adapter in watchdog
1755 */
1758 /* disable receives */
1762 }
1763 /* guard against interrupt when we're going down */
1766 }
1768 /* Reset on uncorrectable ECC error */
1776 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1778 /* Do the reset outside of interrupt context */
1781 /* return immediately since reset is imminent */
1783 }
1791 }
1794 }
1796 /**
1797 * e1000_intr - Interrupt Handler
1798 * @irq: interrupt number
1799 * @data: pointer to a network interface device structure
1800 **/
1802 {
1811 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1812 * not set, then the adapter didn't send an interrupt
1813 */
1817 /* Interrupt Auto-Mask...upon reading ICR,
1818 * interrupts are masked. No need for the
1819 * IMC write
1820 */
1824 /* ICH8 workaround-- Call gig speed drop workaround on cable
1825 * disconnect (LSC) before accessing any PHY registers
1826 */
1831 /* 80003ES2LAN workaround--
1832 * For packet buffer work-around on link down event;
1833 * disable receives here in the ISR and
1834 * reset adapter in watchdog
1835 */
1838 /* disable receives */
1842 }
1843 /* guard against interrupt when we're going down */
1846 }
1848 /* Reset on uncorrectable ECC error */
1856 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1858 /* Do the reset outside of interrupt context */
1861 /* return immediately since reset is imminent */
1863 }
1871 }
1874 }
1877 {
1887 }
1896 /* guard against interrupt when we're going down */
1899 }
1901 no_link_interrupt:
1906 }
1909 {
1920 /* Ring was not completely cleaned, so fire another interrupt */
1924 }
1927 {
1932 /* Write the ITR value calculated at the end of the
1933 * previous interrupt.
1934 */
1939 }
1945 }
1947 }
1949 /**
1950 * e1000_configure_msix - Configure MSI-X hardware
1951 *
1952 * e1000_configure_msix sets up the hardware to properly
1953 * generate MSI-X interrupts.
1954 **/
1956 {
1965 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1970 }
1972 #define E1000_IVAR_INT_ALLOC_VALID 0x8
1973 /* Configure Rx vector */
1979 else
1983 /* Configure Tx vector */
1985 vector++;
1989 else
1994 /* set vector for Other Causes, e.g. link changes */
1995 vector++;
2000 else
2003 /* Cause Tx interrupts on every write back */
2008 /* enable MSI-X PBA support */
2012 /* Auto-Mask Other interrupts upon ICR read */
2017 }
2020 {
2028 }
2029 }
2031 /**
2032 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2033 *
2034 * Attempt to configure interrupts using the best available
2035 * capabilities of the hardware and kernel.
2036 **/
2038 {
2048 GFP_KERNEL);
2058 }
2059 /* MSI-X failed, so fall through and try MSI */
2062 }
2064 /* Fall through */
2071 }
2072 /* Fall through */
2074 /* Don't do anything; this is the system default */
2076 }
2078 /* store the number of vectors being used */
2080 }
2082 /**
2083 * e1000_request_msix - Initialize MSI-X interrupts
2084 *
2085 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2086 * kernel.
2087 **/
2089 {
2097 else
2101 netdev);
2107 vector++;
2113 else
2117 netdev);
2123 vector++;
2133 }
2135 /**
2136 * e1000_request_irq - initialize interrupts
2137 *
2138 * Attempts to configure interrupts using the best available
2139 * capabilities of the hardware and kernel.
2140 **/
2142 {
2150 /* fall back to MSI */
2154 }
2161 /* fall back to legacy interrupt */
2164 }
2172 }
2175 {
2182 vector++;
2185 vector++;
2187 /* Other Causes interrupt vector */
2190 }
2193 }
2195 /**
2196 * e1000_irq_disable - Mask off interrupt generation on the NIC
2197 **/
2199 {
2213 }
2214 }
2216 /**
2217 * e1000_irq_enable - Enable default interrupt generation settings
2218 **/
2220 {
2230 }
2232 }
2234 /**
2235 * e1000e_get_hw_control - get control of the h/w from f/w
2236 * @adapter: address of board private structure
2237 *
2238 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2239 * For ASF and Pass Through versions of f/w this means that
2240 * the driver is loaded. For AMT version (only with 82573)
2241 * of the f/w this means that the network i/f is open.
2242 **/
2244 {
2246 u32 ctrl_ext;
2247 u32 swsm;
2249 /* Let firmware know the driver has taken over */
2256 }
2257 }
2259 /**
2260 * e1000e_release_hw_control - release control of the h/w to f/w
2261 * @adapter: address of board private structure
2262 *
2263 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2264 * For ASF and Pass Through versions of f/w this means that the
2265 * driver is no longer loaded. For AMT version (only with 82573) i
2266 * of the f/w this means that the network i/f is closed.
2267 *
2268 **/
2270 {
2272 u32 ctrl_ext;
2273 u32 swsm;
2275 /* Let firmware taken over control of h/w */
2282 }
2283 }
2285 /**
2286 * e1000_alloc_ring_dma - allocate memory for a ring structure
2287 **/
2290 {
2294 GFP_KERNEL);
2299 }
2301 /**
2302 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2303 * @tx_ring: Tx descriptor ring
2304 *
2305 * Return 0 on success, negative on failure
2306 **/
2308 {
2317 /* round up to nearest 4K */
2329 err:
2333 }
2335 /**
2336 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2337 * @rx_ring: Rx descriptor ring
2338 *
2339 * Returns 0 on success, negative on failure
2340 **/
2342 {
2356 GFP_KERNEL);
2359 }
2363 /* Round up to nearest 4K */
2377 err_pages:
2381 }
2382 err:
2386 }
2388 /**
2389 * e1000_clean_tx_ring - Free Tx Buffers
2390 * @tx_ring: Tx descriptor ring
2391 **/
2393 {
2402 }
2416 else
2418 }
2420 /**
2421 * e1000e_free_tx_resources - Free Tx Resources per Queue
2422 * @tx_ring: Tx descriptor ring
2423 *
2424 * Free all transmit software resources
2425 **/
2427 {
2439 }
2441 /**
2442 * e1000e_free_rx_resources - Free Rx Resources
2443 * @rx_ring: Rx descriptor ring
2444 *
2445 * Free all receive software resources
2446 **/
2448 {
2464 }
2466 /**
2467 * e1000_update_itr - update the dynamic ITR value based on statistics
2468 * @adapter: pointer to adapter
2469 * @itr_setting: current adapter->itr
2470 * @packets: the number of packets during this measurement interval
2471 * @bytes: the number of bytes during this measurement interval
2472 *
2473 * Stores a new ITR value based on packets and byte
2474 * counts during the last interrupt. The advantage of per interrupt
2475 * computation is faster updates and more accurate ITR for the current
2476 * traffic pattern. Constants in this function were computed
2477 * based on theoretical maximum wire speed and thresholds were set based
2478 * on testing data as well as attempting to minimize response time
2479 * while increasing bulk throughput. This functionality is controlled
2480 * by the InterruptThrottleRate module parameter.
2481 **/
2483 {
2491 /* handle TSO and jumbo frames */
2499 /* this if handles the TSO accounting */
2510 }
2518 }
2520 }
2523 }
2526 {
2527 u16 current_itr;
2530 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2535 }
2540 }
2545 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2552 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2559 /* counts and packets in update_itr are dependent on these numbers */
2571 }
2573 set_itr_now:
2575 /* this attempts to bias the interrupt rate towards Bulk
2576 * by adding intermediate steps when interrupt rate is
2577 * increasing
2578 */
2585 else
2587 }
2588 }
2590 /**
2591 * e1000e_write_itr - write the ITR value to the appropriate registers
2592 * @adapter: address of board private structure
2593 * @itr: new ITR value to program
2594 *
2595 * e1000e_write_itr determines if the adapter is in MSI-X mode
2596 * and, if so, writes the EITR registers with the ITR value.
2597 * Otherwise, it writes the ITR value into the ITR register.
2598 **/
2600 {
2611 }
2612 }
2614 /**
2615 * e1000_alloc_queues - Allocate memory for all rings
2616 * @adapter: board private structure to initialize
2617 **/
2619 {
2635 err:
2640 }
2642 /**
2643 * e1000e_poll - NAPI Rx polling callback
2644 * @napi: struct associated with this polling callback
2645 * @weight: number of packets driver is allowed to process this poll
2646 **/
2648 {
2650 napi);
2666 /* If weight not fully consumed, exit the polling mode */
2674 else
2676 }
2677 }
2680 }
2683 {
2688 /* don't update vlan cookie if already programmed */
2690 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2694 /* add VID to filter table */
2700 }
2705 }
2708 {
2714 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2716 /* release control to f/w */
2719 }
2721 /* remove VID from filter table */
2727 }
2732 }
2734 /**
2735 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2736 * @adapter: board private structure to initialize
2737 **/
2739 {
2742 u32 rctl;
2745 /* disable VLAN receive filtering */
2753 }
2754 }
2755 }
2757 /**
2758 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2759 * @adapter: board private structure to initialize
2760 **/
2762 {
2764 u32 rctl;
2767 /* enable VLAN receive filtering */
2772 }
2773 }
2775 /**
2776 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2777 * @adapter: board private structure to initialize
2778 **/
2780 {
2782 u32 ctrl;
2784 /* disable VLAN tag insert/strip */
2788 }
2790 /**
2791 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2792 * @adapter: board private structure to initialize
2793 **/
2795 {
2797 u32 ctrl;
2799 /* enable VLAN tag insert/strip */
2803 }
2806 {
2812 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2815 }
2819 }
2822 {
2823 u16 vid;
2829 }
2832 {
2841 /* enable receiving management packets to the host. this will probably
2842 * generate destination unreachable messages from the host OS, but
2843 * the packets will be handled on SMBUS
2844 */
2854 /* Check if IPMI pass-through decision filter already exists;
2855 * if so, enable it.
2856 */
2860 /* Ignore filters with anything other than IPMI ports */
2864 /* Enable this decision filter in MANC2H */
2869 }
2874 /* Create new decision filter in an empty filter */
2878 E1000_MDEF_PORT_664));
2880 j++;
2882 }
2887 }
2891 }
2893 /**
2894 * e1000_configure_tx - Configure Transmit Unit after Reset
2895 * @adapter: board private structure
2896 *
2897 * Configure the Tx unit of the MAC after a reset.
2898 **/
2900 {
2903 u64 tdba;
2906 /* Setup the HW Tx Head and Tail descriptor pointers */
2917 /* Set the Tx Interrupt Delay register */
2919 /* Tx irq moderation */
2925 E1000_TXDCTL_WTHRESH);
2926 /* set up some performance related parameters to encourage the
2927 * hardware to use the bus more efficiently in bursts, depends
2928 * on the tx_int_delay to be enabled,
2929 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2930 * hthresh = 1 ==> prefetch when one or more available
2931 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2932 * BEWARE: this seems to work but should be considered first if
2933 * there are Tx hangs or other Tx related bugs
2934 */
2937 }
2938 /* erratum work around: set txdctl the same for both queues */
2943 /* set the speed mode bit, we'll clear it if we're not at
2944 * gigabit link later
2945 */
2946 #define SPEED_MODE_BIT (1 << 21)
2949 }
2951 /* errata: program both queues to unweighted RR */
2959 }
2961 /* Setup Transmit Descriptor Settings for eop descriptor */
2964 /* only set IDE if we are delaying interrupts using the timers */
2968 /* enable Report Status bit */
2972 }
2974 /**
2975 * e1000_setup_rctl - configure the receive control registers
2976 * @adapter: Board private structure
2977 **/
2978 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2979 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2981 {
2986 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2988 s32 ret_val;
2992 else
2997 }
2999 /* Program MC offset vector base */
3006 /* Do not Store bad packets */
3009 /* Enable Long Packet receive */
3012 else
3015 /* Some systems expect that the CRC is included in SMBUS traffic. The
3016 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3017 * host memory when this is enabled
3018 */
3022 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3024 u16 phy_data;
3037 }
3039 /* Setup buffer sizes */
3057 }
3059 /* Enable Extended Status in all Receive Descriptors */
3064 /* 82571 and greater support packet-split where the protocol
3065 * header is placed in skb->data and the packet data is
3066 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3067 * In the case of a non-split, skb->data is linearly filled,
3068 * followed by the page buffers. Therefore, skb->data is
3069 * sized to hold the largest protocol header.
3070 *
3071 * allocations using alloc_page take too long for regular MTU
3072 * so only enable packet split for jumbo frames
3073 *
3074 * Using pages when the page size is greater than 16k wastes
3075 * a lot of memory, since we allocate 3 pages at all times
3076 * per packet.
3077 */
3081 else
3087 /* Enable Packet split descriptors */
3091 E1000_PSRCTL_BSIZE0_SHIFT;
3096 E1000_PSRCTL_BSIZE3_SHIFT;
3099 E1000_PSRCTL_BSIZE2_SHIFT;
3102 E1000_PSRCTL_BSIZE1_SHIFT;
3104 }
3107 }
3109 /* This is useful for sniffing bad packets. */
3111 /* UPE and MPE will be handled by normal PROMISC logic
3112 * in e1000e_set_rx_mode
3113 */
3121 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3122 * and that breaks VLANs.
3123 */
3124 }
3127 /* just started the receive unit, no need to restart */
3129 }
3131 /**
3132 * e1000_configure_rx - Configure Receive Unit after Reset
3133 * @adapter: board private structure
3134 *
3135 * Configure the Rx unit of the MAC after a reset.
3136 **/
3138 {
3141 u64 rdba;
3145 /* this is a 32 byte descriptor */
3158 }
3160 /* disable receives while setting up the descriptors */
3168 /* set the writeback threshold (only takes effect if the RDTR
3169 * is set). set GRAN=1 and write back up to 0x4 worth, and
3170 * enable prefetching of 0x20 Rx descriptors
3171 * granularity = 01
3172 * wthresh = 04,
3173 * hthresh = 04,
3174 * pthresh = 0x20
3175 */
3179 /* override the delay timers for enabling bursting, only if
3180 * the value was not set by the user via module options
3181 */
3186 }
3188 /* set the Receive Delay Timer Register */
3191 /* irq moderation */
3197 /* Auto-Mask interrupts upon ICR access */
3203 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3204 * the Base and Length of the Rx Descriptor Ring
3205 */
3215 /* Enable Receive Checksum Offload for TCP and UDP */
3219 else
3223 /* With jumbo frames, excessive C-state transition latencies result
3224 * in dropped transactions.
3225 */
3227 u32 lat =
3234 }
3239 PM_QOS_DEFAULT_VALUE);
3240 }
3242 /* Enable Receives */
3244 }
3246 /**
3247 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3248 * @netdev: network interface device structure
3249 *
3250 * Writes multicast address list to the MTA hash table.
3251 * Returns: -ENOMEM on failure
3252 * 0 on no addresses written
3253 * X on writing X addresses to MTA
3254 */
3256 {
3264 /* nothing to program, so clear mc list */
3267 }
3273 /* update_mc_addr_list expects a packed array of only addresses. */
3282 }
3284 /**
3285 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3286 * @netdev: network interface device structure
3287 *
3288 * Writes unicast address list to the RAR table.
3289 * Returns: -ENOMEM on failure/insufficient address space
3290 * 0 on no addresses written
3291 * X on writing X addresses to the RAR table
3292 **/
3294 {
3300 /* save a rar entry for our hardware address */
3301 rar_entries--;
3303 /* save a rar entry for the LAA workaround */
3305 rar_entries--;
3307 /* return ENOMEM indicating insufficient memory for addresses */
3314 /* write the addresses in reverse order to avoid write
3315 * combining
3316 */
3321 count++;
3322 }
3323 }
3325 /* zero out the remaining RAR entries not used above */
3329 }
3333 }
3335 /**
3336 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3337 * @netdev: network interface device structure
3338 *
3339 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3340 * address list or the network interface flags are updated. This routine is
3341 * responsible for configuring the hardware for proper unicast, multicast,
3342 * promiscuous mode, and all-multi behavior.
3343 **/
3345 {
3348 u32 rctl;
3350 /* Check for Promiscuous and All Multicast modes */
3353 /* clear the affected bits */
3358 /* Do not hardware filter VLANs in promisc mode */
3366 /* Write addresses to the MTA, if the attempt fails
3367 * then we should just turn on promiscuous mode so
3368 * that we can at least receive multicast traffic
3369 */
3373 }
3375 /* Write addresses to available RAR registers, if there is not
3376 * sufficient space to store all the addresses then enable
3377 * unicast promiscuous mode
3378 */
3382 }
3388 else
3390 }
3393 {
3400 };
3402 /* Fill out hash function seed */
3406 /* Direct all traffic to queue 0 */
3410 /* Disable raw packet checksumming so that RSS hash is placed in
3411 * descriptor on writeback.
3412 */
3419 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3420 E1000_MRQC_RSS_FIELD_IPV6 |
3421 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3422 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3425 }
3427 /**
3428 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3429 * @adapter: board private structure
3430 * @timinca: pointer to returned time increment attributes
3431 *
3432 * Get attributes for incrementing the System Time Register SYSTIML/H at
3433 * the default base frequency, and set the cyclecounter shift value.
3434 **/
3436 {
3440 /* Make sure clock is enabled on I217 before checking the frequency */
3449 }
3450 }
3455 /* On I217, the clock frequency is 25MHz or 96MHz as
3456 * indicated by the System Clock Frequency Indication
3457 */
3460 /* Stable 96MHz frequency */
3466 }
3467 /* fall-through */
3470 /* Stable 25MHz frequency */
3478 }
3484 }
3486 /**
3487 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3488 * @adapter: board private structure
3489 *
3490 * Outgoing time stamping can be enabled and disabled. Play nice and
3491 * disable it when requested, although it shouldn't cause any overhead
3492 * when no packet needs it. At most one packet in the queue may be
3493 * marked for time stamping, otherwise it would be impossible to tell
3494 * for sure to which packet the hardware time stamp belongs.
3495 *
3496 * Incoming time stamping has to be configured via the hardware filters.
3497 * Not all combinations are supported, in particular event type has to be
3498 * specified. Matching the kind of event packet is not supported, with the
3499 * exception of "all V2 events regardless of level 2 or 4".
3500 **/
3502 {
3511 u32 regval;
3512 s32 ret_val;
3517 /* flags reserved for future extensions - must be zero */
3529 }
3546 /* Also time stamps V2 L2 Path Delay Request/Response */
3552 /* Also time stamps V2 L2 Path Delay Request/Response. */
3558 /* Hardware cannot filter just V2 L4 Sync messages;
3559 * fall-through to V2 (both L2 and L4) Sync.
3560 */
3562 /* Also time stamps V2 Path Delay Request/Response. */
3569 /* Hardware cannot filter just V2 L4 Delay Request messages;
3570 * fall-through to V2 (both L2 and L4) Delay Request.
3571 */
3573 /* Also time stamps V2 Path Delay Request/Response. */
3581 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3582 * fall-through to all V2 (both L2 and L4) Events.
3583 */
3591 /* For V1, the hardware can only filter Sync messages or
3592 * Delay Request messages but not both so fall-through to
3593 * time stamp all packets.
3594 */
3603 }
3605 /* enable/disable Tx h/w time stamping */
3614 }
3616 /* enable/disable Rx h/w time stamping */
3622 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3624 E1000_TSYNCRXCTL_TYPE_MASK))) {
3627 }
3629 /* L2: define ethertype filter for time stamped packets */
3633 /* define which PTP packets get time stamped */
3636 /* Filter by destination port */
3640 }
3645 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3649 /* Get and set the System Time Register SYSTIM base frequency */
3655 /* reset the ns time counter */
3660 }
3662 /**
3663 * e1000_configure - configure the hardware for Rx and Tx
3664 * @adapter: private board structure
3665 **/
3667 {
3682 }
3684 /**
3685 * e1000e_power_up_phy - restore link in case the phy was powered down
3686 * @adapter: address of board private structure
3687 *
3688 * The phy may be powered down to save power and turn off link when the
3689 * driver is unloaded and wake on lan is not enabled (among others)
3690 * *** this routine MUST be followed by a call to e1000e_reset ***
3691 **/
3693 {
3698 }
3700 /**
3701 * e1000_power_down_phy - Power down the PHY
3702 *
3703 * Power down the PHY so no link is implied when interface is down.
3704 * The PHY cannot be powered down if management or WoL is active.
3705 */
3707 {
3708 /* WoL is enabled */
3714 }
3716 /**
3717 * e1000e_reset - bring the hardware into a known good state
3718 *
3719 * This function boots the hardware and enables some settings that
3720 * require a configuration cycle of the hardware - those cannot be
3721 * set/changed during runtime. After reset the device needs to be
3722 * properly configured for Rx, Tx etc.
3723 */
3725 {
3731 u16 hwm;
3733 /* reset Packet Buffer Allocation to default */
3737 /* To maintain wire speed transmits, the Tx FIFO should be
3738 * large enough to accommodate two full transmit packets,
3739 * rounded up to the next 1KB and expressed in KB. Likewise,
3740 * the Rx FIFO should be large enough to accommodate at least
3741 * one full receive packet and is similarly rounded up and
3742 * expressed in KB.
3743 */
3745 /* upper 16 bits has Tx packet buffer allocation size in KB */
3747 /* lower 16 bits has Rx packet buffer allocation size in KB */
3749 /* the Tx fifo also stores 16 bytes of information about the Tx
3750 * but don't include ethernet FCS because hardware appends it
3751 */
3757 /* software strips receive CRC, so leave room for it */
3762 /* If current Tx allocation is less than the min Tx FIFO size,
3763 * and the min Tx FIFO size is less than the current Rx FIFO
3764 * allocation, take space away from current Rx allocation
3765 */
3770 /* if short on Rx space, Rx wins and must trump Tx
3771 * adjustment
3772 */
3775 }
3778 }
3780 /* flow control settings
3781 *
3782 * The high water mark must be low enough to fit one full frame
3783 * (or the size used for early receive) above it in the Rx FIFO.
3784 * Set it to the lower of:
3785 * - 90% of the Rx FIFO size, and
3786 * - the full Rx FIFO size minus one full frame
3787 */
3790 else
3804 }
3805 /* fall-through */
3814 /* Workaround PCH LOM adapter hangs with certain network
3815 * loads. If hangs persist, try disabling Tx flow control.
3816 */
3823 }
3835 }
3840 }
3842 /* Alignment of Tx data is on an arbitrary byte boundary with the
3843 * maximum size per Tx descriptor limited only to the transmit
3844 * allocation of the packet buffer minus 96 bytes with an upper
3845 * limit of 24KB due to receive synchronization limitations.
3846 */
3850 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
3851 * fit in receive buffer.
3852 */
3860 }
3867 }
3868 }
3870 /* Allow time for pending master requests to run */
3873 /* For parts with AMT enabled, let the firmware know
3874 * that the network interface is in control
3875 */
3886 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3891 /* initialize systim and reset the ns time counter */
3898 }
3905 /* speed up time to link by disabling smart power down, ignore
3906 * the return value of this function because there is nothing
3907 * different we would do if it failed
3908 */
3912 }
3913 }
3916 {
3919 /* hardware has been reset, we need to reload some things */
3930 /* fire a link change interrupt to start the watchdog */
3933 else
3937 }
3940 {
3946 /* flush pending descriptor writebacks to memory */
3950 /* execute the writes immediately */
3953 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
3954 * write is successful
3955 */
3959 /* execute the writes immediately */
3961 }
3966 {
3971 /* signal that we're down so the interrupt handler does not
3972 * reschedule our watchdog timer
3973 */
3976 /* disable receives in the hardware */
3980 /* flush and sleep below */
3984 /* disable transmits in the hardware */
3989 /* flush both disables and wait for them to finish */
4014 /* TODO: for power management, we could drop the link and
4015 * pci_disable_device here.
4016 */
4017 }
4020 {
4027 }
4029 /**
4030 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4031 * @cc: cyclecounter structure
4032 **/
4034 {
4036 cc);
4038 cycle_t systim;
4040 /* latch SYSTIMH on read of SYSTIML */
4045 }
4047 /**
4048 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4049 * @adapter: board private structure to initialize
4050 *
4051 * e1000_sw_init initializes the Adapter private data structure.
4052 * Fields are initialized based on PCI device information and
4053 * OS network device settings (MTU size).
4054 **/
4056 {
4073 /* Setup hardware time stamping cyclecounter */
4078 /* cc.shift set in e1000e_get_base_tininca() */
4082 }
4084 /* Explicitly disable IRQ since the NIC can be in any state. */
4089 }
4091 /**
4092 * e1000_intr_msi_test - Interrupt Handler
4093 * @irq: interrupt number
4094 * @data: pointer to a network interface device structure
4095 **/
4097 {
4106 /* Force memory writes to complete before acknowledging the
4107 * interrupt is handled.
4108 */
4110 }
4113 }
4115 /**
4116 * e1000_test_msi_interrupt - Returns 0 for successful test
4117 * @adapter: board private struct
4118 *
4119 * code flow taken from tg3.c
4120 **/
4122 {
4127 /* poll_enable hasn't been called yet, so don't need disable */
4128 /* clear any pending events */
4131 /* free the real vector and request a test handler */
4135 /* Assume that the test fails, if it succeeds then the test
4136 * MSI irq handler will unset this flag
4137 */
4149 }
4151 /* Force memory writes to complete before enabling and firing an
4152 * interrupt.
4153 */
4158 /* fire an unusual interrupt on the test handler */
4172 }
4177 msi_test_failed:
4180 }
4182 /**
4183 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4184 * @adapter: board private struct
4185 *
4186 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4187 **/
4189 {
4191 u16 pci_cmd;
4196 /* disable SERR in case the MSI write causes a master abort */
4204 /* re-enable SERR */
4209 }
4212 }
4214 /**
4215 * e1000_open - Called when a network interface is made active
4216 * @netdev: network interface device structure
4217 *
4218 * Returns 0 on success, negative value on failure
4219 *
4220 * The open entry point is called when a network interface is made
4221 * active by the system (IFF_UP). At this point all resources needed
4222 * for transmit and receive operations are allocated, the interrupt
4223 * handler is registered with the OS, the watchdog timer is started,
4224 * and the stack is notified that the interface is ready.
4225 **/
4227 {
4233 /* disallow open during test */
4241 /* allocate transmit descriptors */
4246 /* allocate receive descriptors */
4251 /* If AMT is enabled, let the firmware know that the network
4252 * interface is now open and reset the part to a known state.
4253 */
4257 }
4263 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4266 /* DMA latency requirement to workaround jumbo issue */
4268 PM_QOS_DEFAULT_VALUE);
4270 /* before we allocate an interrupt, we must be ready to handle it.
4271 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4272 * as soon as we call pci_request_irq, so we have to setup our
4273 * clean_rx handler before we do so.
4274 */
4281 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4282 * ignore e1000e MSI messages, which means we need to test our MSI
4283 * interrupt now
4284 */
4290 }
4291 }
4293 /* From here on the code is the same as e1000e_up() */
4306 /* fire a link status change interrupt to start the watchdog */
4309 else
4314 err_req_irq:
4318 err_setup_rx:
4320 err_setup_tx:
4325 }
4327 /**
4328 * e1000_close - Disables a network interface
4329 * @netdev: network interface device structure
4330 *
4331 * Returns 0, this is not allowed to fail
4332 *
4333 * The close entry point is called when an interface is de-activated
4334 * by the OS. The hardware is still under the drivers control, but
4335 * needs to be disabled. A global MAC reset is issued to stop the
4336 * hardware, and all transmit and receive resources are freed.
4337 **/
4339 {
4356 }
4362 /* kill manageability vlan ID if supported, but not if a vlan with
4363 * the same ID is registered on the host OS (let 8021q kill it)
4364 */
4366 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4369 /* If AMT is enabled, let the firmware know that the network
4370 * interface is now closed
4371 */
4381 }
4382 /**
4383 * e1000_set_mac - Change the Ethernet Address of the NIC
4384 * @netdev: network interface device structure
4385 * @p: pointer to an address structure
4386 *
4387 * Returns 0 on success, negative on failure
4388 **/
4390 {
4404 /* activate the work around */
4407 /* Hold a copy of the LAA in RAR[14] This is done so that
4408 * between the time RAR[0] gets clobbered and the time it
4409 * gets fixed (in e1000_watchdog), the actual LAA is in one
4410 * of the RARs and no incoming packets directed to this port
4411 * are dropped. Eventually the LAA will be in RAR[0] and
4412 * RAR[14]
4413 */
4416 }
4419 }
4421 /**
4422 * e1000e_update_phy_task - work thread to update phy
4423 * @work: pointer to our work struct
4424 *
4425 * this worker thread exists because we must acquire a
4426 * semaphore to read the phy, which we could msleep while
4427 * waiting for it, and we can't msleep in a timer.
4428 **/
4430 {
4438 }
4440 /**
4441 * e1000_update_phy_info - timre call-back to update PHY info
4442 * @data: pointer to adapter cast into an unsigned long
4443 *
4444 * Need to wait a few seconds after link up to get diagnostic information from
4445 * the phy
4446 **/
4448 {
4455 }
4457 /**
4458 * e1000e_update_phy_stats - Update the PHY statistics counters
4459 * @adapter: board private structure
4460 *
4461 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4462 **/
4464 {
4466 s32 ret_val;
4467 u16 phy_data;
4473 /* A page set is expensive so check if already on desired page.
4474 * If not, set to the page with the PHY status registers.
4475 */
4486 }
4488 /* Single Collision Count */
4494 /* Excessive Collision Count */
4500 /* Multiple Collision Count */
4506 /* Late Collision Count */
4512 /* Collision Count - also used for adaptive IFS */
4518 /* Defer Count */
4524 /* Transmit with no CRS */
4530 release:
4532 }
4534 /**
4535 * e1000e_update_stats - Update the board statistics counters
4536 * @adapter: board private structure
4537 **/
4539 {
4544 /* Prevent stats update while adapter is being reset, or if the pci
4545 * connection is down.
4546 */
4562 /* Half-duplex statistics */
4578 }
4580 }
4595 /* used for adaptive IFS */
4606 /* Fill out the OS statistics structure */
4610 /* Rx Errors */
4612 /* RLEC on some newer hardware can be incorrect so build
4613 * our own version based on RUC and ROC
4614 */
4624 /* Tx Errors */
4630 /* Tx Dropped needs to be maintained elsewhere */
4632 /* Management Stats */
4637 /* Correctable ECC Errors */
4644 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4645 }
4646 }
4648 /**
4649 * e1000_phy_read_status - Update the PHY register status snapshot
4650 * @adapter: board private structure
4651 **/
4653 {
4672 /* Do not read PHY registers if link is not up
4673 * Set values to typical power-on defaults
4674 */
4678 BMSR_ERCAP);
4686 }
4687 }
4690 {
4694 /* Link status message must follow this format for user tools */
4701 }
4704 {
4709 /* get_link_status is set on LSC (link status) interrupt or
4710 * Rx sequence error interrupt. get_link_status will stay
4711 * false until the check_for_link establishes link
4712 * for copper adapters ONLY
4713 */
4721 }
4734 }
4738 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
4740 }
4743 }
4746 {
4747 /* make sure the receive unit is started */
4754 }
4755 }
4758 {
4761 /* With 82574 controllers, PHY needs to be checked periodically
4762 * for hung state and reset, if two calls return true
4763 */
4766 else
4772 }
4773 }
4775 /**
4776 * e1000_watchdog - Timer Call-back
4777 * @data: pointer to adapter cast into an unsigned long
4778 **/
4780 {
4783 /* Do the rest outside of interrupt context */
4786 /* TODO: make this use queue_delayed_work() */
4787 }
4790 {
4805 /* Cancel scheduled suspend requests. */
4810 }
4820 /* Cancel scheduled suspend requests. */
4823 /* update snapshot of PHY registers on LSC */
4830 /* check if SmartSpeed worked */
4836 /* On supported PHYs, check for duplex mismatch only
4837 * if link has autonegotiated at 10/100 half
4838 */
4845 u16 autoneg_exp;
4850 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
4851 }
4853 /* adjust timeout factor according to speed/duplex */
4864 }
4866 /* workaround: re-program speed mode bit after
4867 * link-up event
4868 */
4871 u32 tarc0;
4875 }
4877 /* disable TSO for pcie and 10/100 speeds, to avoid
4878 * some hardware issues
4879 */
4893 /* oops */
4895 }
4896 }
4898 /* enable transmits in the hardware, need to do this
4899 * after setting TARC(0)
4900 */
4905 /* Perform any post-link-up configuration before
4906 * reporting link up.
4907 */
4916 }
4921 /* Link status message must follow this format */
4928 /* The link is lost so the controller stops DMA.
4929 * If there is queued Tx work that cannot be done
4930 * or if on an 8000ES2LAN which requires a Rx packet
4931 * buffer work-around on link down event, reset the
4932 * controller to flush the Tx/Rx packet buffers.
4933 * (Do the reset outside of interrupt context).
4934 */
4938 else
4940 LINK_TIMEOUT);
4941 }
4942 }
4944 link_up:
4961 /* return immediately since reset is imminent */
4963 }
4967 /* Simple mode for Interrupt Throttle Rate (ITR) */
4969 /* Symmetric Tx/Rx gets a reduced ITR=2000;
4970 * Total asymmetrical Tx or Rx gets ITR=8000;
4971 * everyone else is between 2000-8000.
4972 */
4980 }
4982 /* Cause software interrupt to ensure Rx ring is cleaned */
4985 else
4988 /* flush pending descriptors to memory before detecting Tx hang */
4991 /* Force detection of hung controller every watchdog period */
4994 /* With 82571 controllers, LAA may be overwritten due to controller
4995 * reset from the other port. Set the appropriate LAA in RAR[0]
4996 */
5003 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5011 }
5012 }
5014 /* Reset the timer */
5018 }
5020 #define E1000_TX_FLAGS_CSUM 0x00000001
5021 #define E1000_TX_FLAGS_VLAN 0x00000002
5022 #define E1000_TX_FLAGS_TSO 0x00000004
5023 #define E1000_TX_FLAGS_IPV4 0x00000008
5024 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5025 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5026 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5027 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5030 {
5046 }
5064 }
5090 i++;
5096 }
5099 {
5104 u8 css;
5106 __be16 protocol;
5113 else
5122 /* XXX not handling all IPV6 headers */
5131 }
5149 i++;
5155 }
5160 {
5186 count++;
5189 i++;
5192 }
5193 }
5203 i++;
5221 count++;
5222 }
5223 }
5226 /* multiply data chunks by size of headers */
5236 dma_error:
5240 count--;
5245 i--;
5248 }
5251 }
5254 {
5263 E1000_TXD_CMD_TSE;
5268 }
5273 }
5278 }
5286 }
5298 i++;
5305 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5309 /* Force memory writes to complete before letting h/w
5310 * know there are new descriptors to fetch. (Only
5311 * applicable for weak-ordered memory model archs,
5312 * such as IA-64).
5313 */
5320 else
5323 /* we need this if more than one processor can write to our tail
5324 * at a time, it synchronizes IO on IA64/Altix systems
5325 */
5327 }
5329 #define MINIMUM_DHCP_PACKET_SIZE 282
5332 {
5339 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5348 {
5362 }
5365 }
5368 {
5372 /* Herbert's original patch had:
5373 * smp_mb__after_netif_stop_queue();
5374 * but since that doesn't exist yet, just open code it.
5375 */
5378 /* We need to check again in a case another CPU has just
5379 * made room available.
5380 */
5384 /* A reprieve! */
5388 }
5391 {
5397 }
5401 {
5416 }
5421 }
5423 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5424 * pad skb in order to meet this minimum size requirement
5425 */
5431 }
5435 u8 hdr_len;
5437 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5438 * points to just header, pull a few bytes of payload from
5439 * frags into skb->data
5440 */
5442 /* we do this workaround for ES2LAN, but it is un-necessary,
5443 * avoiding it could save a lot of cycles
5444 */
5453 }
5455 }
5456 }
5458 /* reserve a descriptor for the offload context */
5460 count++;
5461 count++;
5473 /* need: count + 2 desc gap to keep tail from touching
5474 * head, otherwise try next time
5475 */
5482 }
5490 }
5497 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5498 * 82571 hardware supports TSO capabilities for IPv6 as well...
5499 * no longer assume, we must.
5500 */
5507 /* if count is 0 then mapping error has occurred */
5509 nr_frags);
5519 }
5523 /* Make sure there is space in the ring for the next send. */
5532 }
5535 }
5537 /**
5538 * e1000_tx_timeout - Respond to a Tx Hang
5539 * @netdev: network interface device structure
5540 **/
5542 {
5545 /* Do the reset outside of interrupt context */
5548 }
5551 {
5555 /* don't run the task if already down */
5562 }
5564 }
5566 /**
5567 * e1000_get_stats64 - Get System Network Statistics
5568 * @netdev: network interface device structure
5569 * @stats: rtnl_link_stats64 pointer
5570 *
5571 * Returns the address of the device statistics structure.
5572 **/
5575 {
5581 /* Fill out the OS statistics structure */
5589 /* Rx Errors */
5591 /* RLEC on some newer hardware can be incorrect so build
5592 * our own version based on RUC and ROC
5593 */
5602 /* Tx Errors */
5608 /* Tx Dropped needs to be maintained elsewhere */
5612 }
5614 /**
5615 * e1000_change_mtu - Change the Maximum Transfer Unit
5616 * @netdev: network interface device structure
5617 * @new_mtu: new value for maximum frame size
5618 *
5619 * Returns 0 on success, negative on failure
5620 **/
5622 {
5626 /* Jumbo frame support */
5631 }
5633 /* Supported frame sizes */
5638 }
5640 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5646 }
5650 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
5657 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5658 * means we reserve 2 more, this pushes us to allocate from the next
5659 * larger slab size.
5660 * i.e. RXBUFFER_2048 --> size-4096 slab
5661 * However with the new *_jumbo_rx* routines, jumbo receives will use
5662 * fragmented skbs
5663 */
5667 else
5670 /* adjust allocation if LPE protects us, and we aren't using SBP */
5678 else
5684 }
5688 {
5735 }
5740 }
5742 }
5744 /**
5745 * e1000e_hwtstamp_ioctl - control hardware time stamping
5746 * @netdev: network interface device structure
5747 * @ifreq: interface request
5748 *
5749 * Outgoing time stamping can be enabled and disabled. Play nice and
5750 * disable it when requested, although it shouldn't cause any overhead
5751 * when no packet needs it. At most one packet in the queue may be
5752 * marked for time stamping, otherwise it would be impossible to tell
5753 * for sure to which packet the hardware time stamp belongs.
5754 *
5755 * Incoming time stamping has to be configured via the hardware filters.
5756 * Not all combinations are supported, in particular event type has to be
5757 * specified. Matching the kind of event packet is not supported, with the
5758 * exception of "all V2 events regardless of level 2 or 4".
5759 **/
5761 {
5784 /* With V2 type filters which specify a Sync or Delay Request,
5785 * Path Delay Request/Response messages are also time stamped
5786 * by hardware so notify the caller the requested packets plus
5787 * some others are time stamped.
5788 */
5793 }
5797 }
5800 {
5810 }
5811 }
5814 {
5820 /* copy MAC RARs to PHY RARs */
5827 }
5829 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5834 /* copy MAC MTA to PHY MTA - only needed for pchlan */
5841 }
5843 /* configure PHY Rx Control register */
5863 /* enable PHY wakeup in MAC register */
5867 /* configure and enable PHY wakeup in PHY registers */
5871 /* activate PHY wakeup */
5876 release:
5880 }
5884 {
5889 /* Runtime suspend should only enable wakeup for link changes */
5904 }
5919 /* turn on all-multi mode if wake on multicast is enabled */
5924 }
5927 /* advertise wake from D3Cold */
5928 #define E1000_CTRL_ADVD3WUC 0x00100000
5929 /* phy power management enable */
5930 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5938 e1000_media_type_internal_serdes) {
5939 /* keep the laser running in D3 */
5943 }
5948 /* Allow time for pending master requests to run */
5952 /* enable wakeup by the PHY */
5957 /* enable wakeup by the MAC */
5960 }
5964 }
5968 /* make sure adapter isn't asleep if manageability is enabled */
5976 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5977 * would have already happened in close and is redundant.
5978 */
5984 }
5987 {
5991 }
5995 }
5998 {
6002 /* The pci-e switch on some quad port adapters will report a
6003 * correctable error when the MAC transitions from D0 to D3. To
6004 * prevent this we need to mask off the correctable errors on the
6005 * downstream port of the pci-e switch.
6006 */
6009 u16 devctl;
6020 }
6021 }
6023 #ifdef CONFIG_PCIEASPM
6025 {
6027 }
6028 #else
6030 {
6038 /* Both device and parent should have the same ASPM setting.
6039 * Disable ASPM in downstream component first and then upstream.
6040 */
6045 aspm_ctl);
6046 }
6047 #endif
6049 {
6055 }
6057 #ifdef CONFIG_PM
6059 {
6061 }
6064 {
6069 u32 err;
6087 }
6094 /* report the system wakeup cause from S3/S4 */
6096 u16 phy_data;
6107 }
6119 }
6121 }
6132 /* If the controller has AMT, do not set DRV_LOAD until the interface
6133 * is up. For all other cases, let the f/w know that the h/w is now
6134 * under the control of the driver.
6135 */
6140 }
6142 #ifdef CONFIG_PM_SLEEP
6144 {
6154 }
6157 {
6166 }
6169 #ifdef CONFIG_PM_RUNTIME
6171 {
6180 }
6183 }
6186 {
6198 }
6201 }
6204 {
6214 }
6219 {
6226 }
6228 #ifdef CONFIG_NET_POLL_CONTROLLER
6231 {
6244 vector++;
6250 vector++;
6255 }
6258 }
6260 /**
6261 * e1000_netpoll
6262 * @netdev: network interface device structure
6263 *
6264 * Polling 'interrupt' - used by things like netconsole to send skbs
6265 * without having to re-enable interrupts. It's not called while
6266 * the interrupt routine is executing.
6267 */
6269 {
6286 }
6287 }
6288 #endif
6290 /**
6291 * e1000_io_error_detected - called when PCI error is detected
6292 * @pdev: Pointer to PCI device
6293 * @state: The current pci connection state
6294 *
6295 * This function is called after a PCI bus error affecting
6296 * this device has been detected.
6297 */
6299 pci_channel_state_t state)
6300 {
6313 /* Request a slot slot reset. */
6315 }
6317 /**
6318 * e1000_io_slot_reset - called after the pci bus has been reset.
6319 * @pdev: Pointer to PCI device
6320 *
6321 * Restart the card from scratch, as if from a cold-boot. Implementation
6322 * resembles the first-half of the e1000_resume routine.
6323 */
6325 {
6331 pci_ers_result_t result;
6356 }
6361 }
6363 /**
6364 * e1000_io_resume - called when traffic can start flowing again.
6365 * @pdev: Pointer to PCI device
6366 *
6367 * This callback is called when the error recovery driver tells us that
6368 * its OK to resume normal operation. Implementation resembles the
6369 * second-half of the e1000_resume routine.
6370 */
6372 {
6383 }
6384 }
6388 /* If the controller has AMT, do not set DRV_LOAD until the interface
6389 * is up. For all other cases, let the f/w know that the h/w is now
6390 * under the control of the driver.
6391 */
6394 }
6397 {
6400 u32 ret_val;
6403 /* print bus type/speed/width info */
6405 /* bus width */
6408 /* MAC address */
6413 E1000_PBANUM_LENGTH);
6418 }
6421 {
6432 /* Deep Smart Power Down (DSPD) */
6435 }
6436 }
6439 netdev_features_t features)
6440 {
6449 NETIF_F_RXALL)))
6456 /* We need to take it back to defaults, which might mean
6457 * stripping is still disabled at the adapter level.
6458 */
6461 else
6463 }
6464 }
6470 else
6474 }
6490 #ifdef CONFIG_NET_POLL_CONTROLLER
6492 #endif
6494 };
6496 /**
6497 * e1000_probe - Device Initialization Routine
6498 * @pdev: PCI device information struct
6499 * @ent: entry in e1000_pci_tbl
6500 *
6501 * Returns 0 on success, negative on failure
6502 *
6503 * e1000_probe initializes an adapter identified by a pci_dev structure.
6504 * The OS initialization, configuring of the adapter private structure,
6505 * and a hardware reset occur.
6506 **/
6508 {
6547 }
6548 }
6549 }
6553 e1000e_driver_name);
6557 /* AER (Advanced Error Reporting) hooks */
6561 /* PCI config space info */
6604 }
6606 /* construct the net_device struct */
6620 /* setup adapter struct */
6641 /* Copper options */
6646 }
6652 /* Set initial default active device features */
6654 NETIF_F_HW_VLAN_RX |
6655 NETIF_F_HW_VLAN_TX |
6656 NETIF_F_TSO |
6657 NETIF_F_TSO6 |
6658 NETIF_F_RXHASH |
6659 NETIF_F_RXCSUM |
6660 NETIF_F_HW_CSUM);
6662 /* Set user-changeable features (subset of all device features) */
6672 NETIF_F_TSO |
6673 NETIF_F_TSO6 |
6674 NETIF_F_HW_CSUM);
6681 }
6686 /* before reading the NVM, reset the controller to
6687 * put the device in a known good starting state
6688 */
6691 /* systems with ASPM and others may see the checksum fail on the first
6692 * attempt. Let's give it a few tries
6693 */
6701 }
6702 }
6706 /* copy the MAC address */
6718 }
6734 /* Initialize link parameters. User can change them with ethtool */
6741 /* ring size defaults */
6745 /* Initial Wake on LAN setting - If APM wake is enabled in
6746 * the EEPROM, enable the ACPI Magic Packet filter
6747 */
6749 /* APME bit in EEPROM is mapped to WUC.APME */
6760 else
6763 }
6765 /* fetch WoL from EEPROM */
6769 /* now that we have the eeprom settings, apply the special cases
6770 * where the eeprom may be wrong or the board simply won't support
6771 * wake on lan on a particular port
6772 */
6776 /* initialize the wol settings based on the eeprom settings */
6780 /* save off EEPROM version number */
6783 /* reset the hardware with the new settings */
6786 /* If the controller has AMT, do not set DRV_LOAD until the interface
6787 * is up. For all other cases, let the f/w know that the h/w is now
6788 * under the control of the driver.
6789 */
6798 /* carrier off reporting is important to ethtool even BEFORE open */
6801 /* init PTP hardware clock */
6811 err_register:
6814 err_eeprom:
6817 err_hw_init:
6820 err_sw_init:
6824 err_flashmap:
6826 err_ioremap:
6828 err_alloc_etherdev:
6831 err_pci_reg:
6832 err_dma:
6835 }
6837 /**
6838 * e1000_remove - Device Removal Routine
6839 * @pdev: PCI device information struct
6840 *
6841 * e1000_remove is called by the PCI subsystem to alert the driver
6842 * that it should release a PCI device. The could be caused by a
6843 * Hot-Plug event, or because the driver is going to be removed from
6844 * memory.
6845 **/
6847 {
6854 /* The timers may be rescheduled, so explicitly disable them
6855 * from being rescheduled.
6856 */
6873 }
6874 }
6879 /* Don't lie to e1000_close() down the road. */
6887 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6888 * would have already happened in close and is redundant.
6889 */
6904 /* AER disable */
6908 }
6910 /* PCI Error Recovery (ERS) */
6915 };
6922 board_82571 },
6943 board_80003es2lan },
6945 board_80003es2lan },
6947 board_80003es2lan },
6949 board_80003es2lan },
6992 };
6995 #ifdef CONFIG_PM
7000 };
7001 #endif
7003 /* PCI Device API Driver */
7009 #ifdef CONFIG_PM
7012 },
7013 #endif
7016 };
7018 /**
7019 * e1000_init_module - Driver Registration Routine
7020 *
7021 * e1000_init_module is the first routine called when the driver is
7022 * loaded. All it does is register with the PCI subsystem.
7023 **/
7025 {
7028 e1000e_driver_version);
7033 }
7036 /**
7037 * e1000_exit_module - Driver Exit Cleanup Routine
7038 *
7039 * e1000_exit_module is called just before the driver is removed
7040 * from memory.
7041 **/
7043 {
7045 }
7054 /* netdev.c */