?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mmc: dw_mmc: exynos: dw_mci_exynos_prepare_hs400_tuning() can be static
[linux-2.6/btrfs-unstable.git] / drivers / mmc / host / dw_mmc.c
blob47dfd0eafb7a0f9b28805bf7e66e3830ce2be4dc
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/of.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
41
42 #include "dw_mmc.h"
43
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
55
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
59 #ifdef CONFIG_MMC_DW_IDMAC
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
65 struct idmac_desc_64addr {
66 u32 des0; /* Control Descriptor */
67
68 u32 des1; /* Reserved */
69
70 u32 des2; /*Buffer sizes */
71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
72 ((d)->des2 = ((d)->des2 & 0x03ffe000) | ((s) & 0x1fff))
73
74 u32 des3; /* Reserved */
75
76 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
77 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
78
79 u32 des6; /* Lower 32-bits of Next Descriptor Address */
80 u32 des7; /* Upper 32-bits of Next Descriptor Address */
81 };
82
83 struct idmac_desc {
84 u32 des0; /* Control Descriptor */
85 #define IDMAC_DES0_DIC BIT(1)
86 #define IDMAC_DES0_LD BIT(2)
87 #define IDMAC_DES0_FD BIT(3)
88 #define IDMAC_DES0_CH BIT(4)
89 #define IDMAC_DES0_ER BIT(5)
90 #define IDMAC_DES0_CES BIT(30)
91 #define IDMAC_DES0_OWN BIT(31)
92
93 u32 des1; /* Buffer sizes */
94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
95 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
96
97 u32 des2; /* buffer 1 physical address */
98
99 u32 des3; /* buffer 2 physical address */
100 };
101 #endif /* CONFIG_MMC_DW_IDMAC */
102
103 static bool dw_mci_reset(struct dw_mci *host);
104 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
105 static int dw_mci_card_busy(struct mmc_host *mmc);
106
107 #if defined(CONFIG_DEBUG_FS)
108 static int dw_mci_req_show(struct seq_file *s, void *v)
109 {
110 struct dw_mci_slot *slot = s->private;
111 struct mmc_request *mrq;
112 struct mmc_command *cmd;
113 struct mmc_command *stop;
114 struct mmc_data *data;
115
116 /* Make sure we get a consistent snapshot */
117 spin_lock_bh(&slot->host->lock);
118 mrq = slot->mrq;
119
120 if (mrq) {
121 cmd = mrq->cmd;
122 data = mrq->data;
123 stop = mrq->stop;
124
125 if (cmd)
126 seq_printf(s,
127 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
128 cmd->opcode, cmd->arg, cmd->flags,
129 cmd->resp[0], cmd->resp[1], cmd->resp[2],
130 cmd->resp[2], cmd->error);
131 if (data)
132 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
133 data->bytes_xfered, data->blocks,
134 data->blksz, data->flags, data->error);
135 if (stop)
136 seq_printf(s,
137 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
138 stop->opcode, stop->arg, stop->flags,
139 stop->resp[0], stop->resp[1], stop->resp[2],
140 stop->resp[2], stop->error);
141 }
142
143 spin_unlock_bh(&slot->host->lock);
144
145 return 0;
146 }
147
148 static int dw_mci_req_open(struct inode *inode, struct file *file)
149 {
150 return single_open(file, dw_mci_req_show, inode->i_private);
151 }
152
153 static const struct file_operations dw_mci_req_fops = {
154 .owner = THIS_MODULE,
155 .open = dw_mci_req_open,
156 .read = seq_read,
157 .llseek = seq_lseek,
158 .release = single_release,
159 };
160
161 static int dw_mci_regs_show(struct seq_file *s, void *v)
162 {
163 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
164 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
165 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
166 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
167 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
168 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
169
170 return 0;
171 }
172
173 static int dw_mci_regs_open(struct inode *inode, struct file *file)
174 {
175 return single_open(file, dw_mci_regs_show, inode->i_private);
176 }
177
178 static const struct file_operations dw_mci_regs_fops = {
179 .owner = THIS_MODULE,
180 .open = dw_mci_regs_open,
181 .read = seq_read,
182 .llseek = seq_lseek,
183 .release = single_release,
184 };
185
186 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
187 {
188 struct mmc_host *mmc = slot->mmc;
189 struct dw_mci *host = slot->host;
190 struct dentry *root;
191 struct dentry *node;
192
193 root = mmc->debugfs_root;
194 if (!root)
195 return;
196
197 node = debugfs_create_file("regs", S_IRUSR, root, host,
198 &dw_mci_regs_fops);
199 if (!node)
200 goto err;
201
202 node = debugfs_create_file("req", S_IRUSR, root, slot,
203 &dw_mci_req_fops);
204 if (!node)
205 goto err;
206
207 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
208 if (!node)
209 goto err;
210
211 node = debugfs_create_x32("pending_events", S_IRUSR, root,
212 (u32 *)&host->pending_events);
213 if (!node)
214 goto err;
215
216 node = debugfs_create_x32("completed_events", S_IRUSR, root,
217 (u32 *)&host->completed_events);
218 if (!node)
219 goto err;
220
221 return;
222
223 err:
224 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
225 }
226 #endif /* defined(CONFIG_DEBUG_FS) */
227
228 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
229
230 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
231 {
232 struct mmc_data *data;
233 struct dw_mci_slot *slot = mmc_priv(mmc);
234 struct dw_mci *host = slot->host;
235 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
236 u32 cmdr;
237 cmd->error = -EINPROGRESS;
238
239 cmdr = cmd->opcode;
240
241 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
242 cmd->opcode == MMC_GO_IDLE_STATE ||
243 cmd->opcode == MMC_GO_INACTIVE_STATE ||
244 (cmd->opcode == SD_IO_RW_DIRECT &&
245 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
246 cmdr |= SDMMC_CMD_STOP;
247 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
248 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
249
250 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
251 u32 clk_en_a;
252
253 /* Special bit makes CMD11 not die */
254 cmdr |= SDMMC_CMD_VOLT_SWITCH;
255
256 /* Change state to continue to handle CMD11 weirdness */
257 WARN_ON(slot->host->state != STATE_SENDING_CMD);
258 slot->host->state = STATE_SENDING_CMD11;
259
260 /*
261 * We need to disable low power mode (automatic clock stop)
262 * while doing voltage switch so we don't confuse the card,
263 * since stopping the clock is a specific part of the UHS
264 * voltage change dance.
265 *
266 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
267 * unconditionally turned back on in dw_mci_setup_bus() if it's
268 * ever called with a non-zero clock. That shouldn't happen
269 * until the voltage change is all done.
270 */
271 clk_en_a = mci_readl(host, CLKENA);
272 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
273 mci_writel(host, CLKENA, clk_en_a);
274 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
275 SDMMC_CMD_PRV_DAT_WAIT, 0);
276 }
277
278 if (cmd->flags & MMC_RSP_PRESENT) {
279 /* We expect a response, so set this bit */
280 cmdr |= SDMMC_CMD_RESP_EXP;
281 if (cmd->flags & MMC_RSP_136)
282 cmdr |= SDMMC_CMD_RESP_LONG;
283 }
284
285 if (cmd->flags & MMC_RSP_CRC)
286 cmdr |= SDMMC_CMD_RESP_CRC;
287
288 data = cmd->data;
289 if (data) {
290 cmdr |= SDMMC_CMD_DAT_EXP;
291 if (data->flags & MMC_DATA_STREAM)
292 cmdr |= SDMMC_CMD_STRM_MODE;
293 if (data->flags & MMC_DATA_WRITE)
294 cmdr |= SDMMC_CMD_DAT_WR;
295 }
296
297 if (drv_data && drv_data->prepare_command)
298 drv_data->prepare_command(slot->host, &cmdr);
299
300 return cmdr;
301 }
302
303 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
304 {
305 struct mmc_command *stop;
306 u32 cmdr;
307
308 if (!cmd->data)
309 return 0;
310
311 stop = &host->stop_abort;
312 cmdr = cmd->opcode;
313 memset(stop, 0, sizeof(struct mmc_command));
314
315 if (cmdr == MMC_READ_SINGLE_BLOCK ||
316 cmdr == MMC_READ_MULTIPLE_BLOCK ||
317 cmdr == MMC_WRITE_BLOCK ||
318 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
319 cmdr == MMC_SEND_TUNING_BLOCK ||
320 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
321 stop->opcode = MMC_STOP_TRANSMISSION;
322 stop->arg = 0;
323 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
324 } else if (cmdr == SD_IO_RW_EXTENDED) {
325 stop->opcode = SD_IO_RW_DIRECT;
326 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
327 ((cmd->arg >> 28) & 0x7);
328 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
329 } else {
330 return 0;
331 }
332
333 cmdr = stop->opcode | SDMMC_CMD_STOP |
334 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
335
336 return cmdr;
337 }
338
339 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
340 {
341 unsigned long timeout = jiffies + msecs_to_jiffies(500);
342
343 /*
344 * Databook says that before issuing a new data transfer command
345 * we need to check to see if the card is busy. Data transfer commands
346 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
347 *
348 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
349 * expected.
350 */
351 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
352 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
353 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
354 if (time_after(jiffies, timeout)) {
355 /* Command will fail; we'll pass error then */
356 dev_err(host->dev, "Busy; trying anyway\n");
357 break;
358 }
359 udelay(10);
360 }
361 }
362 }
363
364 static void dw_mci_start_command(struct dw_mci *host,
365 struct mmc_command *cmd, u32 cmd_flags)
366 {
367 host->cmd = cmd;
368 dev_vdbg(host->dev,
369 "start command: ARGR=0x%08x CMDR=0x%08x\n",
370 cmd->arg, cmd_flags);
371
372 mci_writel(host, CMDARG, cmd->arg);
373 wmb();
374 dw_mci_wait_while_busy(host, cmd_flags);
375
376 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
377 }
378
379 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
380 {
381 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
382 dw_mci_start_command(host, stop, host->stop_cmdr);
383 }
384
385 /* DMA interface functions */
386 static void dw_mci_stop_dma(struct dw_mci *host)
387 {
388 if (host->using_dma) {
389 host->dma_ops->stop(host);
390 host->dma_ops->cleanup(host);
391 }
392
393 /* Data transfer was stopped by the interrupt handler */
394 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
395 }
396
397 static int dw_mci_get_dma_dir(struct mmc_data *data)
398 {
399 if (data->flags & MMC_DATA_WRITE)
400 return DMA_TO_DEVICE;
401 else
402 return DMA_FROM_DEVICE;
403 }
404
405 #ifdef CONFIG_MMC_DW_IDMAC
406 static void dw_mci_dma_cleanup(struct dw_mci *host)
407 {
408 struct mmc_data *data = host->data;
409
410 if (data)
411 if (!data->host_cookie)
412 dma_unmap_sg(host->dev,
413 data->sg,
414 data->sg_len,
415 dw_mci_get_dma_dir(data));
416 }
417
418 static void dw_mci_idmac_reset(struct dw_mci *host)
419 {
420 u32 bmod = mci_readl(host, BMOD);
421 /* Software reset of DMA */
422 bmod |= SDMMC_IDMAC_SWRESET;
423 mci_writel(host, BMOD, bmod);
424 }
425
426 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
427 {
428 u32 temp;
429
430 /* Disable and reset the IDMAC interface */
431 temp = mci_readl(host, CTRL);
432 temp &= ~SDMMC_CTRL_USE_IDMAC;
433 temp |= SDMMC_CTRL_DMA_RESET;
434 mci_writel(host, CTRL, temp);
435
436 /* Stop the IDMAC running */
437 temp = mci_readl(host, BMOD);
438 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
439 temp |= SDMMC_IDMAC_SWRESET;
440 mci_writel(host, BMOD, temp);
441 }
442
443 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
444 {
445 struct mmc_data *data = host->data;
446
447 dev_vdbg(host->dev, "DMA complete\n");
448
449 host->dma_ops->cleanup(host);
450
451 /*
452 * If the card was removed, data will be NULL. No point in trying to
453 * send the stop command or waiting for NBUSY in this case.
454 */
455 if (data) {
456 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
457 tasklet_schedule(&host->tasklet);
458 }
459 }
460
461 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
462 unsigned int sg_len)
463 {
464 int i;
465 if (host->dma_64bit_address == 1) {
466 struct idmac_desc_64addr *desc = host->sg_cpu;
467
468 for (i = 0; i < sg_len; i++, desc++) {
469 unsigned int length = sg_dma_len(&data->sg[i]);
470 u64 mem_addr = sg_dma_address(&data->sg[i]);
471
472 /*
473 * Set the OWN bit and disable interrupts for this
474 * descriptor
475 */
476 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
477 IDMAC_DES0_CH;
478 /* Buffer length */
479 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length);
480
481 /* Physical address to DMA to/from */
482 desc->des4 = mem_addr & 0xffffffff;
483 desc->des5 = mem_addr >> 32;
484 }
485
486 /* Set first descriptor */
487 desc = host->sg_cpu;
488 desc->des0 |= IDMAC_DES0_FD;
489
490 /* Set last descriptor */
491 desc = host->sg_cpu + (i - 1) *
492 sizeof(struct idmac_desc_64addr);
493 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
494 desc->des0 |= IDMAC_DES0_LD;
495
496 } else {
497 struct idmac_desc *desc = host->sg_cpu;
498
499 for (i = 0; i < sg_len; i++, desc++) {
500 unsigned int length = sg_dma_len(&data->sg[i]);
501 u32 mem_addr = sg_dma_address(&data->sg[i]);
502
503 /*
504 * Set the OWN bit and disable interrupts for this
505 * descriptor
506 */
507 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
508 IDMAC_DES0_CH;
509 /* Buffer length */
510 IDMAC_SET_BUFFER1_SIZE(desc, length);
511
512 /* Physical address to DMA to/from */
513 desc->des2 = mem_addr;
514 }
515
516 /* Set first descriptor */
517 desc = host->sg_cpu;
518 desc->des0 |= IDMAC_DES0_FD;
519
520 /* Set last descriptor */
521 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
522 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
523 desc->des0 |= IDMAC_DES0_LD;
524 }
525
526 wmb();
527 }
528
529 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
530 {
531 u32 temp;
532
533 dw_mci_translate_sglist(host, host->data, sg_len);
534
535 /* Make sure to reset DMA in case we did PIO before this */
536 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
537 dw_mci_idmac_reset(host);
538
539 /* Select IDMAC interface */
540 temp = mci_readl(host, CTRL);
541 temp |= SDMMC_CTRL_USE_IDMAC;
542 mci_writel(host, CTRL, temp);
543
544 wmb();
545
546 /* Enable the IDMAC */
547 temp = mci_readl(host, BMOD);
548 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
549 mci_writel(host, BMOD, temp);
550
551 /* Start it running */
552 mci_writel(host, PLDMND, 1);
553 }
554
555 static int dw_mci_idmac_init(struct dw_mci *host)
556 {
557 int i;
558
559 if (host->dma_64bit_address == 1) {
560 struct idmac_desc_64addr *p;
561 /* Number of descriptors in the ring buffer */
562 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
563
564 /* Forward link the descriptor list */
565 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
566 i++, p++) {
567 p->des6 = (host->sg_dma +
568 (sizeof(struct idmac_desc_64addr) *
569 (i + 1))) & 0xffffffff;
570
571 p->des7 = (u64)(host->sg_dma +
572 (sizeof(struct idmac_desc_64addr) *
573 (i + 1))) >> 32;
574 /* Initialize reserved and buffer size fields to "0" */
575 p->des1 = 0;
576 p->des2 = 0;
577 p->des3 = 0;
578 }
579
580 /* Set the last descriptor as the end-of-ring descriptor */
581 p->des6 = host->sg_dma & 0xffffffff;
582 p->des7 = (u64)host->sg_dma >> 32;
583 p->des0 = IDMAC_DES0_ER;
584
585 } else {
586 struct idmac_desc *p;
587 /* Number of descriptors in the ring buffer */
588 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
589
590 /* Forward link the descriptor list */
591 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
592 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) *
593 (i + 1));
594
595 /* Set the last descriptor as the end-of-ring descriptor */
596 p->des3 = host->sg_dma;
597 p->des0 = IDMAC_DES0_ER;
598 }
599
600 dw_mci_idmac_reset(host);
601
602 if (host->dma_64bit_address == 1) {
603 /* Mask out interrupts - get Tx & Rx complete only */
604 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
605 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
606 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
607
608 /* Set the descriptor base address */
609 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
610 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
611
612 } else {
613 /* Mask out interrupts - get Tx & Rx complete only */
614 mci_writel(host, IDSTS, IDMAC_INT_CLR);
615 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
616 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
617
618 /* Set the descriptor base address */
619 mci_writel(host, DBADDR, host->sg_dma);
620 }
621
622 return 0;
623 }
624
625 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
626 .init = dw_mci_idmac_init,
627 .start = dw_mci_idmac_start_dma,
628 .stop = dw_mci_idmac_stop_dma,
629 .complete = dw_mci_idmac_complete_dma,
630 .cleanup = dw_mci_dma_cleanup,
631 };
632 #endif /* CONFIG_MMC_DW_IDMAC */
633
634 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
635 struct mmc_data *data,
636 bool next)
637 {
638 struct scatterlist *sg;
639 unsigned int i, sg_len;
640
641 if (!next && data->host_cookie)
642 return data->host_cookie;
643
644 /*
645 * We don't do DMA on "complex" transfers, i.e. with
646 * non-word-aligned buffers or lengths. Also, we don't bother
647 * with all the DMA setup overhead for short transfers.
648 */
649 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
650 return -EINVAL;
651
652 if (data->blksz & 3)
653 return -EINVAL;
654
655 for_each_sg(data->sg, sg, data->sg_len, i) {
656 if (sg->offset & 3 || sg->length & 3)
657 return -EINVAL;
658 }
659
660 sg_len = dma_map_sg(host->dev,
661 data->sg,
662 data->sg_len,
663 dw_mci_get_dma_dir(data));
664 if (sg_len == 0)
665 return -EINVAL;
666
667 if (next)
668 data->host_cookie = sg_len;
669
670 return sg_len;
671 }
672
673 static void dw_mci_pre_req(struct mmc_host *mmc,
674 struct mmc_request *mrq,
675 bool is_first_req)
676 {
677 struct dw_mci_slot *slot = mmc_priv(mmc);
678 struct mmc_data *data = mrq->data;
679
680 if (!slot->host->use_dma || !data)
681 return;
682
683 if (data->host_cookie) {
684 data->host_cookie = 0;
685 return;
686 }
687
688 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
689 data->host_cookie = 0;
690 }
691
692 static void dw_mci_post_req(struct mmc_host *mmc,
693 struct mmc_request *mrq,
694 int err)
695 {
696 struct dw_mci_slot *slot = mmc_priv(mmc);
697 struct mmc_data *data = mrq->data;
698
699 if (!slot->host->use_dma || !data)
700 return;
701
702 if (data->host_cookie)
703 dma_unmap_sg(slot->host->dev,
704 data->sg,
705 data->sg_len,
706 dw_mci_get_dma_dir(data));
707 data->host_cookie = 0;
708 }
709
710 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
711 {
712 #ifdef CONFIG_MMC_DW_IDMAC
713 unsigned int blksz = data->blksz;
714 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
715 u32 fifo_width = 1 << host->data_shift;
716 u32 blksz_depth = blksz / fifo_width, fifoth_val;
717 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
718 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
719
720 tx_wmark = (host->fifo_depth) / 2;
721 tx_wmark_invers = host->fifo_depth - tx_wmark;
722
723 /*
724 * MSIZE is '1',
725 * if blksz is not a multiple of the FIFO width
726 */
727 if (blksz % fifo_width) {
728 msize = 0;
729 rx_wmark = 1;
730 goto done;
731 }
732
733 do {
734 if (!((blksz_depth % mszs[idx]) ||
735 (tx_wmark_invers % mszs[idx]))) {
736 msize = idx;
737 rx_wmark = mszs[idx] - 1;
738 break;
739 }
740 } while (--idx > 0);
741 /*
742 * If idx is '0', it won't be tried
743 * Thus, initial values are uesed
744 */
745 done:
746 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
747 mci_writel(host, FIFOTH, fifoth_val);
748 #endif
749 }
750
751 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
752 {
753 unsigned int blksz = data->blksz;
754 u32 blksz_depth, fifo_depth;
755 u16 thld_size;
756
757 WARN_ON(!(data->flags & MMC_DATA_READ));
758
759 /*
760 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
761 * in the FIFO region, so we really shouldn't access it).
762 */
763 if (host->verid < DW_MMC_240A)
764 return;
765
766 if (host->timing != MMC_TIMING_MMC_HS200 &&
767 host->timing != MMC_TIMING_UHS_SDR104)
768 goto disable;
769
770 blksz_depth = blksz / (1 << host->data_shift);
771 fifo_depth = host->fifo_depth;
772
773 if (blksz_depth > fifo_depth)
774 goto disable;
775
776 /*
777 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
778 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
779 * Currently just choose blksz.
780 */
781 thld_size = blksz;
782 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
783 return;
784
785 disable:
786 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
787 }
788
789 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
790 {
791 unsigned long irqflags;
792 int sg_len;
793 u32 temp;
794
795 host->using_dma = 0;
796
797 /* If we don't have a channel, we can't do DMA */
798 if (!host->use_dma)
799 return -ENODEV;
800
801 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
802 if (sg_len < 0) {
803 host->dma_ops->stop(host);
804 return sg_len;
805 }
806
807 host->using_dma = 1;
808
809 dev_vdbg(host->dev,
810 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
811 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
812 sg_len);
813
814 /*
815 * Decide the MSIZE and RX/TX Watermark.
816 * If current block size is same with previous size,
817 * no need to update fifoth.
818 */
819 if (host->prev_blksz != data->blksz)
820 dw_mci_adjust_fifoth(host, data);
821
822 /* Enable the DMA interface */
823 temp = mci_readl(host, CTRL);
824 temp |= SDMMC_CTRL_DMA_ENABLE;
825 mci_writel(host, CTRL, temp);
826
827 /* Disable RX/TX IRQs, let DMA handle it */
828 spin_lock_irqsave(&host->irq_lock, irqflags);
829 temp = mci_readl(host, INTMASK);
830 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
831 mci_writel(host, INTMASK, temp);
832 spin_unlock_irqrestore(&host->irq_lock, irqflags);
833
834 host->dma_ops->start(host, sg_len);
835
836 return 0;
837 }
838
839 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
840 {
841 unsigned long irqflags;
842 u32 temp;
843
844 data->error = -EINPROGRESS;
845
846 WARN_ON(host->data);
847 host->sg = NULL;
848 host->data = data;
849
850 if (data->flags & MMC_DATA_READ) {
851 host->dir_status = DW_MCI_RECV_STATUS;
852 dw_mci_ctrl_rd_thld(host, data);
853 } else {
854 host->dir_status = DW_MCI_SEND_STATUS;
855 }
856
857 if (dw_mci_submit_data_dma(host, data)) {
858 int flags = SG_MITER_ATOMIC;
859 if (host->data->flags & MMC_DATA_READ)
860 flags |= SG_MITER_TO_SG;
861 else
862 flags |= SG_MITER_FROM_SG;
863
864 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
865 host->sg = data->sg;
866 host->part_buf_start = 0;
867 host->part_buf_count = 0;
868
869 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
870
871 spin_lock_irqsave(&host->irq_lock, irqflags);
872 temp = mci_readl(host, INTMASK);
873 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
874 mci_writel(host, INTMASK, temp);
875 spin_unlock_irqrestore(&host->irq_lock, irqflags);
876
877 temp = mci_readl(host, CTRL);
878 temp &= ~SDMMC_CTRL_DMA_ENABLE;
879 mci_writel(host, CTRL, temp);
880
881 /*
882 * Use the initial fifoth_val for PIO mode.
883 * If next issued data may be transfered by DMA mode,
884 * prev_blksz should be invalidated.
885 */
886 mci_writel(host, FIFOTH, host->fifoth_val);
887 host->prev_blksz = 0;
888 } else {
889 /*
890 * Keep the current block size.
891 * It will be used to decide whether to update
892 * fifoth register next time.
893 */
894 host->prev_blksz = data->blksz;
895 }
896 }
897
898 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
899 {
900 struct dw_mci *host = slot->host;
901 unsigned long timeout = jiffies + msecs_to_jiffies(500);
902 unsigned int cmd_status = 0;
903
904 mci_writel(host, CMDARG, arg);
905 wmb();
906 dw_mci_wait_while_busy(host, cmd);
907 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
908
909 while (time_before(jiffies, timeout)) {
910 cmd_status = mci_readl(host, CMD);
911 if (!(cmd_status & SDMMC_CMD_START))
912 return;
913 }
914 dev_err(&slot->mmc->class_dev,
915 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
916 cmd, arg, cmd_status);
917 }
918
919 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
920 {
921 struct dw_mci *host = slot->host;
922 unsigned int clock = slot->clock;
923 u32 div;
924 u32 clk_en_a;
925 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
926
927 /* We must continue to set bit 28 in CMD until the change is complete */
928 if (host->state == STATE_WAITING_CMD11_DONE)
929 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
930
931 if (!clock) {
932 mci_writel(host, CLKENA, 0);
933 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
934 } else if (clock != host->current_speed || force_clkinit) {
935 div = host->bus_hz / clock;
936 if (host->bus_hz % clock && host->bus_hz > clock)
937 /*
938 * move the + 1 after the divide to prevent
939 * over-clocking the card.
940 */
941 div += 1;
942
943 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
944
945 if ((clock << div) != slot->__clk_old || force_clkinit)
946 dev_info(&slot->mmc->class_dev,
947 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
948 slot->id, host->bus_hz, clock,
949 div ? ((host->bus_hz / div) >> 1) :
950 host->bus_hz, div);
951
952 /* disable clock */
953 mci_writel(host, CLKENA, 0);
954 mci_writel(host, CLKSRC, 0);
955
956 /* inform CIU */
957 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
958
959 /* set clock to desired speed */
960 mci_writel(host, CLKDIV, div);
961
962 /* inform CIU */
963 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
964
965 /* enable clock; only low power if no SDIO */
966 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
967 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
968 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
969 mci_writel(host, CLKENA, clk_en_a);
970
971 /* inform CIU */
972 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
973
974 /* keep the clock with reflecting clock dividor */
975 slot->__clk_old = clock << div;
976 }
977
978 host->current_speed = clock;
979
980 /* Set the current slot bus width */
981 mci_writel(host, CTYPE, (slot->ctype << slot->id));
982 }
983
984 static void __dw_mci_start_request(struct dw_mci *host,
985 struct dw_mci_slot *slot,
986 struct mmc_command *cmd)
987 {
988 struct mmc_request *mrq;
989 struct mmc_data *data;
990 u32 cmdflags;
991
992 mrq = slot->mrq;
993
994 host->cur_slot = slot;
995 host->mrq = mrq;
996
997 host->pending_events = 0;
998 host->completed_events = 0;
999 host->cmd_status = 0;
1000 host->data_status = 0;
1001 host->dir_status = 0;
1002
1003 data = cmd->data;
1004 if (data) {
1005 mci_writel(host, TMOUT, 0xFFFFFFFF);
1006 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1007 mci_writel(host, BLKSIZ, data->blksz);
1008 }
1009
1010 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1011
1012 /* this is the first command, send the initialization clock */
1013 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1014 cmdflags |= SDMMC_CMD_INIT;
1015
1016 if (data) {
1017 dw_mci_submit_data(host, data);
1018 wmb();
1019 }
1020
1021 dw_mci_start_command(host, cmd, cmdflags);
1022
1023 if (mrq->stop)
1024 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1025 else
1026 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1027 }
1028
1029 static void dw_mci_start_request(struct dw_mci *host,
1030 struct dw_mci_slot *slot)
1031 {
1032 struct mmc_request *mrq = slot->mrq;
1033 struct mmc_command *cmd;
1034
1035 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1036 __dw_mci_start_request(host, slot, cmd);
1037 }
1038
1039 /* must be called with host->lock held */
1040 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1041 struct mmc_request *mrq)
1042 {
1043 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1044 host->state);
1045
1046 slot->mrq = mrq;
1047
1048 if (host->state == STATE_WAITING_CMD11_DONE) {
1049 dev_warn(&slot->mmc->class_dev,
1050 "Voltage change didn't complete\n");
1051 /*
1052 * this case isn't expected to happen, so we can
1053 * either crash here or just try to continue on
1054 * in the closest possible state
1055 */
1056 host->state = STATE_IDLE;
1057 }
1058
1059 if (host->state == STATE_IDLE) {
1060 host->state = STATE_SENDING_CMD;
1061 dw_mci_start_request(host, slot);
1062 } else {
1063 list_add_tail(&slot->queue_node, &host->queue);
1064 }
1065 }
1066
1067 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1068 {
1069 struct dw_mci_slot *slot = mmc_priv(mmc);
1070 struct dw_mci *host = slot->host;
1071
1072 WARN_ON(slot->mrq);
1073
1074 /*
1075 * The check for card presence and queueing of the request must be
1076 * atomic, otherwise the card could be removed in between and the
1077 * request wouldn't fail until another card was inserted.
1078 */
1079 spin_lock_bh(&host->lock);
1080
1081 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1082 spin_unlock_bh(&host->lock);
1083 mrq->cmd->error = -ENOMEDIUM;
1084 mmc_request_done(mmc, mrq);
1085 return;
1086 }
1087
1088 dw_mci_queue_request(host, slot, mrq);
1089
1090 spin_unlock_bh(&host->lock);
1091 }
1092
1093 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1094 {
1095 struct dw_mci_slot *slot = mmc_priv(mmc);
1096 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1097 u32 regs;
1098 int ret;
1099
1100 switch (ios->bus_width) {
1101 case MMC_BUS_WIDTH_4:
1102 slot->ctype = SDMMC_CTYPE_4BIT;
1103 break;
1104 case MMC_BUS_WIDTH_8:
1105 slot->ctype = SDMMC_CTYPE_8BIT;
1106 break;
1107 default:
1108 /* set default 1 bit mode */
1109 slot->ctype = SDMMC_CTYPE_1BIT;
1110 }
1111
1112 regs = mci_readl(slot->host, UHS_REG);
1113
1114 /* DDR mode set */
1115 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1116 ios->timing == MMC_TIMING_MMC_HS400)
1117 regs |= ((0x1 << slot->id) << 16);
1118 else
1119 regs &= ~((0x1 << slot->id) << 16);
1120
1121 mci_writel(slot->host, UHS_REG, regs);
1122 slot->host->timing = ios->timing;
1123
1124 /*
1125 * Use mirror of ios->clock to prevent race with mmc
1126 * core ios update when finding the minimum.
1127 */
1128 slot->clock = ios->clock;
1129
1130 if (drv_data && drv_data->set_ios)
1131 drv_data->set_ios(slot->host, ios);
1132
1133 switch (ios->power_mode) {
1134 case MMC_POWER_UP:
1135 if (!IS_ERR(mmc->supply.vmmc)) {
1136 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1137 ios->vdd);
1138 if (ret) {
1139 dev_err(slot->host->dev,
1140 "failed to enable vmmc regulator\n");
1141 /*return, if failed turn on vmmc*/
1142 return;
1143 }
1144 }
1145 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1146 regs = mci_readl(slot->host, PWREN);
1147 regs |= (1 << slot->id);
1148 mci_writel(slot->host, PWREN, regs);
1149 break;
1150 case MMC_POWER_ON:
1151 if (!slot->host->vqmmc_enabled) {
1152 if (!IS_ERR(mmc->supply.vqmmc)) {
1153 ret = regulator_enable(mmc->supply.vqmmc);
1154 if (ret < 0)
1155 dev_err(slot->host->dev,
1156 "failed to enable vqmmc\n");
1157 else
1158 slot->host->vqmmc_enabled = true;
1159
1160 } else {
1161 /* Keep track so we don't reset again */
1162 slot->host->vqmmc_enabled = true;
1163 }
1164
1165 /* Reset our state machine after powering on */
1166 dw_mci_ctrl_reset(slot->host,
1167 SDMMC_CTRL_ALL_RESET_FLAGS);
1168 }
1169
1170 /* Adjust clock / bus width after power is up */
1171 dw_mci_setup_bus(slot, false);
1172
1173 break;
1174 case MMC_POWER_OFF:
1175 /* Turn clock off before power goes down */
1176 dw_mci_setup_bus(slot, false);
1177
1178 if (!IS_ERR(mmc->supply.vmmc))
1179 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1180
1181 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1182 regulator_disable(mmc->supply.vqmmc);
1183 slot->host->vqmmc_enabled = false;
1184
1185 regs = mci_readl(slot->host, PWREN);
1186 regs &= ~(1 << slot->id);
1187 mci_writel(slot->host, PWREN, regs);
1188 break;
1189 default:
1190 break;
1191 }
1192
1193 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1194 slot->host->state = STATE_IDLE;
1195 }
1196
1197 static int dw_mci_card_busy(struct mmc_host *mmc)
1198 {
1199 struct dw_mci_slot *slot = mmc_priv(mmc);
1200 u32 status;
1201
1202 /*
1203 * Check the busy bit which is low when DAT[3:0]
1204 * (the data lines) are 0000
1205 */
1206 status = mci_readl(slot->host, STATUS);
1207
1208 return !!(status & SDMMC_STATUS_BUSY);
1209 }
1210
1211 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1212 {
1213 struct dw_mci_slot *slot = mmc_priv(mmc);
1214 struct dw_mci *host = slot->host;
1215 u32 uhs;
1216 u32 v18 = SDMMC_UHS_18V << slot->id;
1217 int min_uv, max_uv;
1218 int ret;
1219
1220 /*
1221 * Program the voltage. Note that some instances of dw_mmc may use
1222 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1223 * does no harm but you need to set the regulator directly. Try both.
1224 */
1225 uhs = mci_readl(host, UHS_REG);
1226 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1227 min_uv = 2700000;
1228 max_uv = 3600000;
1229 uhs &= ~v18;
1230 } else {
1231 min_uv = 1700000;
1232 max_uv = 1950000;
1233 uhs |= v18;
1234 }
1235 if (!IS_ERR(mmc->supply.vqmmc)) {
1236 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1237
1238 if (ret) {
1239 dev_dbg(&mmc->class_dev,
1240 "Regulator set error %d: %d - %d\n",
1241 ret, min_uv, max_uv);
1242 return ret;
1243 }
1244 }
1245 mci_writel(host, UHS_REG, uhs);
1246
1247 return 0;
1248 }
1249
1250 static int dw_mci_get_ro(struct mmc_host *mmc)
1251 {
1252 int read_only;
1253 struct dw_mci_slot *slot = mmc_priv(mmc);
1254 int gpio_ro = mmc_gpio_get_ro(mmc);
1255
1256 /* Use platform get_ro function, else try on board write protect */
1257 if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
1258 (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
1259 read_only = 0;
1260 else if (!IS_ERR_VALUE(gpio_ro))
1261 read_only = gpio_ro;
1262 else
1263 read_only =
1264 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1265
1266 dev_dbg(&mmc->class_dev, "card is %s\n",
1267 read_only ? "read-only" : "read-write");
1268
1269 return read_only;
1270 }
1271
1272 static int dw_mci_get_cd(struct mmc_host *mmc)
1273 {
1274 int present;
1275 struct dw_mci_slot *slot = mmc_priv(mmc);
1276 struct dw_mci_board *brd = slot->host->pdata;
1277 struct dw_mci *host = slot->host;
1278 int gpio_cd = mmc_gpio_get_cd(mmc);
1279
1280 /* Use platform get_cd function, else try onboard card detect */
1281 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1282 present = 1;
1283 else if (!IS_ERR_VALUE(gpio_cd))
1284 present = gpio_cd;
1285 else
1286 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1287 == 0 ? 1 : 0;
1288
1289 spin_lock_bh(&host->lock);
1290 if (present) {
1291 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1292 dev_dbg(&mmc->class_dev, "card is present\n");
1293 } else {
1294 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1295 dev_dbg(&mmc->class_dev, "card is not present\n");
1296 }
1297 spin_unlock_bh(&host->lock);
1298
1299 return present;
1300 }
1301
1302 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1303 {
1304 struct dw_mci_slot *slot = mmc_priv(mmc);
1305 struct dw_mci *host = slot->host;
1306
1307 /*
1308 * Low power mode will stop the card clock when idle. According to the
1309 * description of the CLKENA register we should disable low power mode
1310 * for SDIO cards if we need SDIO interrupts to work.
1311 */
1312 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1313 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1314 u32 clk_en_a_old;
1315 u32 clk_en_a;
1316
1317 clk_en_a_old = mci_readl(host, CLKENA);
1318
1319 if (card->type == MMC_TYPE_SDIO ||
1320 card->type == MMC_TYPE_SD_COMBO) {
1321 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1322 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1323 } else {
1324 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1325 clk_en_a = clk_en_a_old | clken_low_pwr;
1326 }
1327
1328 if (clk_en_a != clk_en_a_old) {
1329 mci_writel(host, CLKENA, clk_en_a);
1330 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1331 SDMMC_CMD_PRV_DAT_WAIT, 0);
1332 }
1333 }
1334 }
1335
1336 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1337 {
1338 struct dw_mci_slot *slot = mmc_priv(mmc);
1339 struct dw_mci *host = slot->host;
1340 unsigned long irqflags;
1341 u32 int_mask;
1342
1343 spin_lock_irqsave(&host->irq_lock, irqflags);
1344
1345 /* Enable/disable Slot Specific SDIO interrupt */
1346 int_mask = mci_readl(host, INTMASK);
1347 if (enb)
1348 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1349 else
1350 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1351 mci_writel(host, INTMASK, int_mask);
1352
1353 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1354 }
1355
1356 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1357 {
1358 struct dw_mci_slot *slot = mmc_priv(mmc);
1359 struct dw_mci *host = slot->host;
1360 const struct dw_mci_drv_data *drv_data = host->drv_data;
1361 int err = -ENOSYS;
1362
1363 if (drv_data && drv_data->execute_tuning)
1364 err = drv_data->execute_tuning(slot);
1365 return err;
1366 }
1367
1368 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1369 {
1370 struct dw_mci_slot *slot = mmc_priv(mmc);
1371 struct dw_mci *host = slot->host;
1372 const struct dw_mci_drv_data *drv_data = host->drv_data;
1373
1374 if (drv_data && drv_data->prepare_hs400_tuning)
1375 return drv_data->prepare_hs400_tuning(host, ios);
1376
1377 return 0;
1378 }
1379
1380 static const struct mmc_host_ops dw_mci_ops = {
1381 .request = dw_mci_request,
1382 .pre_req = dw_mci_pre_req,
1383 .post_req = dw_mci_post_req,
1384 .set_ios = dw_mci_set_ios,
1385 .get_ro = dw_mci_get_ro,
1386 .get_cd = dw_mci_get_cd,
1387 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1388 .execute_tuning = dw_mci_execute_tuning,
1389 .card_busy = dw_mci_card_busy,
1390 .start_signal_voltage_switch = dw_mci_switch_voltage,
1391 .init_card = dw_mci_init_card,
1392 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1393 };
1394
1395 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1396 __releases(&host->lock)
1397 __acquires(&host->lock)
1398 {
1399 struct dw_mci_slot *slot;
1400 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1401
1402 WARN_ON(host->cmd || host->data);
1403
1404 host->cur_slot->mrq = NULL;
1405 host->mrq = NULL;
1406 if (!list_empty(&host->queue)) {
1407 slot = list_entry(host->queue.next,
1408 struct dw_mci_slot, queue_node);
1409 list_del(&slot->queue_node);
1410 dev_vdbg(host->dev, "list not empty: %s is next\n",
1411 mmc_hostname(slot->mmc));
1412 host->state = STATE_SENDING_CMD;
1413 dw_mci_start_request(host, slot);
1414 } else {
1415 dev_vdbg(host->dev, "list empty\n");
1416
1417 if (host->state == STATE_SENDING_CMD11)
1418 host->state = STATE_WAITING_CMD11_DONE;
1419 else
1420 host->state = STATE_IDLE;
1421 }
1422
1423 spin_unlock(&host->lock);
1424 mmc_request_done(prev_mmc, mrq);
1425 spin_lock(&host->lock);
1426 }
1427
1428 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1429 {
1430 u32 status = host->cmd_status;
1431
1432 host->cmd_status = 0;
1433
1434 /* Read the response from the card (up to 16 bytes) */
1435 if (cmd->flags & MMC_RSP_PRESENT) {
1436 if (cmd->flags & MMC_RSP_136) {
1437 cmd->resp[3] = mci_readl(host, RESP0);
1438 cmd->resp[2] = mci_readl(host, RESP1);
1439 cmd->resp[1] = mci_readl(host, RESP2);
1440 cmd->resp[0] = mci_readl(host, RESP3);
1441 } else {
1442 cmd->resp[0] = mci_readl(host, RESP0);
1443 cmd->resp[1] = 0;
1444 cmd->resp[2] = 0;
1445 cmd->resp[3] = 0;
1446 }
1447 }
1448
1449 if (status & SDMMC_INT_RTO)
1450 cmd->error = -ETIMEDOUT;
1451 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1452 cmd->error = -EILSEQ;
1453 else if (status & SDMMC_INT_RESP_ERR)
1454 cmd->error = -EIO;
1455 else
1456 cmd->error = 0;
1457
1458 if (cmd->error) {
1459 /* newer ip versions need a delay between retries */
1460 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1461 mdelay(20);
1462 }
1463
1464 return cmd->error;
1465 }
1466
1467 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1468 {
1469 u32 status = host->data_status;
1470
1471 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1472 if (status & SDMMC_INT_DRTO) {
1473 data->error = -ETIMEDOUT;
1474 } else if (status & SDMMC_INT_DCRC) {
1475 data->error = -EILSEQ;
1476 } else if (status & SDMMC_INT_EBE) {
1477 if (host->dir_status ==
1478 DW_MCI_SEND_STATUS) {
1479 /*
1480 * No data CRC status was returned.
1481 * The number of bytes transferred
1482 * will be exaggerated in PIO mode.
1483 */
1484 data->bytes_xfered = 0;
1485 data->error = -ETIMEDOUT;
1486 } else if (host->dir_status ==
1487 DW_MCI_RECV_STATUS) {
1488 data->error = -EIO;
1489 }
1490 } else {
1491 /* SDMMC_INT_SBE is included */
1492 data->error = -EIO;
1493 }
1494
1495 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1496
1497 /*
1498 * After an error, there may be data lingering
1499 * in the FIFO
1500 */
1501 dw_mci_reset(host);
1502 } else {
1503 data->bytes_xfered = data->blocks * data->blksz;
1504 data->error = 0;
1505 }
1506
1507 return data->error;
1508 }
1509
1510 static void dw_mci_tasklet_func(unsigned long priv)
1511 {
1512 struct dw_mci *host = (struct dw_mci *)priv;
1513 struct mmc_data *data;
1514 struct mmc_command *cmd;
1515 struct mmc_request *mrq;
1516 enum dw_mci_state state;
1517 enum dw_mci_state prev_state;
1518 unsigned int err;
1519
1520 spin_lock(&host->lock);
1521
1522 state = host->state;
1523 data = host->data;
1524 mrq = host->mrq;
1525
1526 do {
1527 prev_state = state;
1528
1529 switch (state) {
1530 case STATE_IDLE:
1531 case STATE_WAITING_CMD11_DONE:
1532 break;
1533
1534 case STATE_SENDING_CMD11:
1535 case STATE_SENDING_CMD:
1536 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1537 &host->pending_events))
1538 break;
1539
1540 cmd = host->cmd;
1541 host->cmd = NULL;
1542 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1543 err = dw_mci_command_complete(host, cmd);
1544 if (cmd == mrq->sbc && !err) {
1545 prev_state = state = STATE_SENDING_CMD;
1546 __dw_mci_start_request(host, host->cur_slot,
1547 mrq->cmd);
1548 goto unlock;
1549 }
1550
1551 if (cmd->data && err) {
1552 dw_mci_stop_dma(host);
1553 send_stop_abort(host, data);
1554 state = STATE_SENDING_STOP;
1555 break;
1556 }
1557
1558 if (!cmd->data || err) {
1559 dw_mci_request_end(host, mrq);
1560 goto unlock;
1561 }
1562
1563 prev_state = state = STATE_SENDING_DATA;
1564 /* fall through */
1565
1566 case STATE_SENDING_DATA:
1567 /*
1568 * We could get a data error and never a transfer
1569 * complete so we'd better check for it here.
1570 *
1571 * Note that we don't really care if we also got a
1572 * transfer complete; stopping the DMA and sending an
1573 * abort won't hurt.
1574 */
1575 if (test_and_clear_bit(EVENT_DATA_ERROR,
1576 &host->pending_events)) {
1577 dw_mci_stop_dma(host);
1578 if (data->stop ||
1579 !(host->data_status & (SDMMC_INT_DRTO |
1580 SDMMC_INT_EBE)))
1581 send_stop_abort(host, data);
1582 state = STATE_DATA_ERROR;
1583 break;
1584 }
1585
1586 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1587 &host->pending_events))
1588 break;
1589
1590 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1591
1592 /*
1593 * Handle an EVENT_DATA_ERROR that might have shown up
1594 * before the transfer completed. This might not have
1595 * been caught by the check above because the interrupt
1596 * could have gone off between the previous check and
1597 * the check for transfer complete.
1598 *
1599 * Technically this ought not be needed assuming we
1600 * get a DATA_COMPLETE eventually (we'll notice the
1601 * error and end the request), but it shouldn't hurt.
1602 *
1603 * This has the advantage of sending the stop command.
1604 */
1605 if (test_and_clear_bit(EVENT_DATA_ERROR,
1606 &host->pending_events)) {
1607 dw_mci_stop_dma(host);
1608 if (data->stop ||
1609 !(host->data_status & (SDMMC_INT_DRTO |
1610 SDMMC_INT_EBE)))
1611 send_stop_abort(host, data);
1612 state = STATE_DATA_ERROR;
1613 break;
1614 }
1615 prev_state = state = STATE_DATA_BUSY;
1616
1617 /* fall through */
1618
1619 case STATE_DATA_BUSY:
1620 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1621 &host->pending_events))
1622 break;
1623
1624 host->data = NULL;
1625 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1626 err = dw_mci_data_complete(host, data);
1627
1628 if (!err) {
1629 if (!data->stop || mrq->sbc) {
1630 if (mrq->sbc && data->stop)
1631 data->stop->error = 0;
1632 dw_mci_request_end(host, mrq);
1633 goto unlock;
1634 }
1635
1636 /* stop command for open-ended transfer*/
1637 if (data->stop)
1638 send_stop_abort(host, data);
1639 } else {
1640 /*
1641 * If we don't have a command complete now we'll
1642 * never get one since we just reset everything;
1643 * better end the request.
1644 *
1645 * If we do have a command complete we'll fall
1646 * through to the SENDING_STOP command and
1647 * everything will be peachy keen.
1648 */
1649 if (!test_bit(EVENT_CMD_COMPLETE,
1650 &host->pending_events)) {
1651 host->cmd = NULL;
1652 dw_mci_request_end(host, mrq);
1653 goto unlock;
1654 }
1655 }
1656
1657 /*
1658 * If err has non-zero,
1659 * stop-abort command has been already issued.
1660 */
1661 prev_state = state = STATE_SENDING_STOP;
1662
1663 /* fall through */
1664
1665 case STATE_SENDING_STOP:
1666 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1667 &host->pending_events))
1668 break;
1669
1670 /* CMD error in data command */
1671 if (mrq->cmd->error && mrq->data)
1672 dw_mci_reset(host);
1673
1674 host->cmd = NULL;
1675 host->data = NULL;
1676
1677 if (mrq->stop)
1678 dw_mci_command_complete(host, mrq->stop);
1679 else
1680 host->cmd_status = 0;
1681
1682 dw_mci_request_end(host, mrq);
1683 goto unlock;
1684
1685 case STATE_DATA_ERROR:
1686 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1687 &host->pending_events))
1688 break;
1689
1690 state = STATE_DATA_BUSY;
1691 break;
1692 }
1693 } while (state != prev_state);
1694
1695 host->state = state;
1696 unlock:
1697 spin_unlock(&host->lock);
1698
1699 }
1700
1701 /* push final bytes to part_buf, only use during push */
1702 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1703 {
1704 memcpy((void *)&host->part_buf, buf, cnt);
1705 host->part_buf_count = cnt;
1706 }
1707
1708 /* append bytes to part_buf, only use during push */
1709 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1710 {
1711 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1712 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1713 host->part_buf_count += cnt;
1714 return cnt;
1715 }
1716
1717 /* pull first bytes from part_buf, only use during pull */
1718 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1719 {
1720 cnt = min(cnt, (int)host->part_buf_count);
1721 if (cnt) {
1722 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1723 cnt);
1724 host->part_buf_count -= cnt;
1725 host->part_buf_start += cnt;
1726 }
1727 return cnt;
1728 }
1729
1730 /* pull final bytes from the part_buf, assuming it's just been filled */
1731 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1732 {
1733 memcpy(buf, &host->part_buf, cnt);
1734 host->part_buf_start = cnt;
1735 host->part_buf_count = (1 << host->data_shift) - cnt;
1736 }
1737
1738 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1739 {
1740 struct mmc_data *data = host->data;
1741 int init_cnt = cnt;
1742
1743 /* try and push anything in the part_buf */
1744 if (unlikely(host->part_buf_count)) {
1745 int len = dw_mci_push_part_bytes(host, buf, cnt);
1746 buf += len;
1747 cnt -= len;
1748 if (host->part_buf_count == 2) {
1749 mci_writew(host, DATA(host->data_offset),
1750 host->part_buf16);
1751 host->part_buf_count = 0;
1752 }
1753 }
1754 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1755 if (unlikely((unsigned long)buf & 0x1)) {
1756 while (cnt >= 2) {
1757 u16 aligned_buf[64];
1758 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1759 int items = len >> 1;
1760 int i;
1761 /* memcpy from input buffer into aligned buffer */
1762 memcpy(aligned_buf, buf, len);
1763 buf += len;
1764 cnt -= len;
1765 /* push data from aligned buffer into fifo */
1766 for (i = 0; i < items; ++i)
1767 mci_writew(host, DATA(host->data_offset),
1768 aligned_buf[i]);
1769 }
1770 } else
1771 #endif
1772 {
1773 u16 *pdata = buf;
1774 for (; cnt >= 2; cnt -= 2)
1775 mci_writew(host, DATA(host->data_offset), *pdata++);
1776 buf = pdata;
1777 }
1778 /* put anything remaining in the part_buf */
1779 if (cnt) {
1780 dw_mci_set_part_bytes(host, buf, cnt);
1781 /* Push data if we have reached the expected data length */
1782 if ((data->bytes_xfered + init_cnt) ==
1783 (data->blksz * data->blocks))
1784 mci_writew(host, DATA(host->data_offset),
1785 host->part_buf16);
1786 }
1787 }
1788
1789 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1790 {
1791 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1792 if (unlikely((unsigned long)buf & 0x1)) {
1793 while (cnt >= 2) {
1794 /* pull data from fifo into aligned buffer */
1795 u16 aligned_buf[64];
1796 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1797 int items = len >> 1;
1798 int i;
1799 for (i = 0; i < items; ++i)
1800 aligned_buf[i] = mci_readw(host,
1801 DATA(host->data_offset));
1802 /* memcpy from aligned buffer into output buffer */
1803 memcpy(buf, aligned_buf, len);
1804 buf += len;
1805 cnt -= len;
1806 }
1807 } else
1808 #endif
1809 {
1810 u16 *pdata = buf;
1811 for (; cnt >= 2; cnt -= 2)
1812 *pdata++ = mci_readw(host, DATA(host->data_offset));
1813 buf = pdata;
1814 }
1815 if (cnt) {
1816 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1817 dw_mci_pull_final_bytes(host, buf, cnt);
1818 }
1819 }
1820
1821 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1822 {
1823 struct mmc_data *data = host->data;
1824 int init_cnt = cnt;
1825
1826 /* try and push anything in the part_buf */
1827 if (unlikely(host->part_buf_count)) {
1828 int len = dw_mci_push_part_bytes(host, buf, cnt);
1829 buf += len;
1830 cnt -= len;
1831 if (host->part_buf_count == 4) {
1832 mci_writel(host, DATA(host->data_offset),
1833 host->part_buf32);
1834 host->part_buf_count = 0;
1835 }
1836 }
1837 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1838 if (unlikely((unsigned long)buf & 0x3)) {
1839 while (cnt >= 4) {
1840 u32 aligned_buf[32];
1841 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1842 int items = len >> 2;
1843 int i;
1844 /* memcpy from input buffer into aligned buffer */
1845 memcpy(aligned_buf, buf, len);
1846 buf += len;
1847 cnt -= len;
1848 /* push data from aligned buffer into fifo */
1849 for (i = 0; i < items; ++i)
1850 mci_writel(host, DATA(host->data_offset),
1851 aligned_buf[i]);
1852 }
1853 } else
1854 #endif
1855 {
1856 u32 *pdata = buf;
1857 for (; cnt >= 4; cnt -= 4)
1858 mci_writel(host, DATA(host->data_offset), *pdata++);
1859 buf = pdata;
1860 }
1861 /* put anything remaining in the part_buf */
1862 if (cnt) {
1863 dw_mci_set_part_bytes(host, buf, cnt);
1864 /* Push data if we have reached the expected data length */
1865 if ((data->bytes_xfered + init_cnt) ==
1866 (data->blksz * data->blocks))
1867 mci_writel(host, DATA(host->data_offset),
1868 host->part_buf32);
1869 }
1870 }
1871
1872 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1873 {
1874 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1875 if (unlikely((unsigned long)buf & 0x3)) {
1876 while (cnt >= 4) {
1877 /* pull data from fifo into aligned buffer */
1878 u32 aligned_buf[32];
1879 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1880 int items = len >> 2;
1881 int i;
1882 for (i = 0; i < items; ++i)
1883 aligned_buf[i] = mci_readl(host,
1884 DATA(host->data_offset));
1885 /* memcpy from aligned buffer into output buffer */
1886 memcpy(buf, aligned_buf, len);
1887 buf += len;
1888 cnt -= len;
1889 }
1890 } else
1891 #endif
1892 {
1893 u32 *pdata = buf;
1894 for (; cnt >= 4; cnt -= 4)
1895 *pdata++ = mci_readl(host, DATA(host->data_offset));
1896 buf = pdata;
1897 }
1898 if (cnt) {
1899 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1900 dw_mci_pull_final_bytes(host, buf, cnt);
1901 }
1902 }
1903
1904 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1905 {
1906 struct mmc_data *data = host->data;
1907 int init_cnt = cnt;
1908
1909 /* try and push anything in the part_buf */
1910 if (unlikely(host->part_buf_count)) {
1911 int len = dw_mci_push_part_bytes(host, buf, cnt);
1912 buf += len;
1913 cnt -= len;
1914
1915 if (host->part_buf_count == 8) {
1916 mci_writeq(host, DATA(host->data_offset),
1917 host->part_buf);
1918 host->part_buf_count = 0;
1919 }
1920 }
1921 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1922 if (unlikely((unsigned long)buf & 0x7)) {
1923 while (cnt >= 8) {
1924 u64 aligned_buf[16];
1925 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1926 int items = len >> 3;
1927 int i;
1928 /* memcpy from input buffer into aligned buffer */
1929 memcpy(aligned_buf, buf, len);
1930 buf += len;
1931 cnt -= len;
1932 /* push data from aligned buffer into fifo */
1933 for (i = 0; i < items; ++i)
1934 mci_writeq(host, DATA(host->data_offset),
1935 aligned_buf[i]);
1936 }
1937 } else
1938 #endif
1939 {
1940 u64 *pdata = buf;
1941 for (; cnt >= 8; cnt -= 8)
1942 mci_writeq(host, DATA(host->data_offset), *pdata++);
1943 buf = pdata;
1944 }
1945 /* put anything remaining in the part_buf */
1946 if (cnt) {
1947 dw_mci_set_part_bytes(host, buf, cnt);
1948 /* Push data if we have reached the expected data length */
1949 if ((data->bytes_xfered + init_cnt) ==
1950 (data->blksz * data->blocks))
1951 mci_writeq(host, DATA(host->data_offset),
1952 host->part_buf);
1953 }
1954 }
1955
1956 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1957 {
1958 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1959 if (unlikely((unsigned long)buf & 0x7)) {
1960 while (cnt >= 8) {
1961 /* pull data from fifo into aligned buffer */
1962 u64 aligned_buf[16];
1963 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1964 int items = len >> 3;
1965 int i;
1966 for (i = 0; i < items; ++i)
1967 aligned_buf[i] = mci_readq(host,
1968 DATA(host->data_offset));
1969 /* memcpy from aligned buffer into output buffer */
1970 memcpy(buf, aligned_buf, len);
1971 buf += len;
1972 cnt -= len;
1973 }
1974 } else
1975 #endif
1976 {
1977 u64 *pdata = buf;
1978 for (; cnt >= 8; cnt -= 8)
1979 *pdata++ = mci_readq(host, DATA(host->data_offset));
1980 buf = pdata;
1981 }
1982 if (cnt) {
1983 host->part_buf = mci_readq(host, DATA(host->data_offset));
1984 dw_mci_pull_final_bytes(host, buf, cnt);
1985 }
1986 }
1987
1988 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1989 {
1990 int len;
1991
1992 /* get remaining partial bytes */
1993 len = dw_mci_pull_part_bytes(host, buf, cnt);
1994 if (unlikely(len == cnt))
1995 return;
1996 buf += len;
1997 cnt -= len;
1998
1999 /* get the rest of the data */
2000 host->pull_data(host, buf, cnt);
2001 }
2002
2003 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2004 {
2005 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2006 void *buf;
2007 unsigned int offset;
2008 struct mmc_data *data = host->data;
2009 int shift = host->data_shift;
2010 u32 status;
2011 unsigned int len;
2012 unsigned int remain, fcnt;
2013
2014 do {
2015 if (!sg_miter_next(sg_miter))
2016 goto done;
2017
2018 host->sg = sg_miter->piter.sg;
2019 buf = sg_miter->addr;
2020 remain = sg_miter->length;
2021 offset = 0;
2022
2023 do {
2024 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2025 << shift) + host->part_buf_count;
2026 len = min(remain, fcnt);
2027 if (!len)
2028 break;
2029 dw_mci_pull_data(host, (void *)(buf + offset), len);
2030 data->bytes_xfered += len;
2031 offset += len;
2032 remain -= len;
2033 } while (remain);
2034
2035 sg_miter->consumed = offset;
2036 status = mci_readl(host, MINTSTS);
2037 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2038 /* if the RXDR is ready read again */
2039 } while ((status & SDMMC_INT_RXDR) ||
2040 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2041
2042 if (!remain) {
2043 if (!sg_miter_next(sg_miter))
2044 goto done;
2045 sg_miter->consumed = 0;
2046 }
2047 sg_miter_stop(sg_miter);
2048 return;
2049
2050 done:
2051 sg_miter_stop(sg_miter);
2052 host->sg = NULL;
2053 smp_wmb();
2054 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2055 }
2056
2057 static void dw_mci_write_data_pio(struct dw_mci *host)
2058 {
2059 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2060 void *buf;
2061 unsigned int offset;
2062 struct mmc_data *data = host->data;
2063 int shift = host->data_shift;
2064 u32 status;
2065 unsigned int len;
2066 unsigned int fifo_depth = host->fifo_depth;
2067 unsigned int remain, fcnt;
2068
2069 do {
2070 if (!sg_miter_next(sg_miter))
2071 goto done;
2072
2073 host->sg = sg_miter->piter.sg;
2074 buf = sg_miter->addr;
2075 remain = sg_miter->length;
2076 offset = 0;
2077
2078 do {
2079 fcnt = ((fifo_depth -
2080 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2081 << shift) - host->part_buf_count;
2082 len = min(remain, fcnt);
2083 if (!len)
2084 break;
2085 host->push_data(host, (void *)(buf + offset), len);
2086 data->bytes_xfered += len;
2087 offset += len;
2088 remain -= len;
2089 } while (remain);
2090
2091 sg_miter->consumed = offset;
2092 status = mci_readl(host, MINTSTS);
2093 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2094 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2095
2096 if (!remain) {
2097 if (!sg_miter_next(sg_miter))
2098 goto done;
2099 sg_miter->consumed = 0;
2100 }
2101 sg_miter_stop(sg_miter);
2102 return;
2103
2104 done:
2105 sg_miter_stop(sg_miter);
2106 host->sg = NULL;
2107 smp_wmb();
2108 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2109 }
2110
2111 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2112 {
2113 if (!host->cmd_status)
2114 host->cmd_status = status;
2115
2116 smp_wmb();
2117
2118 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2119 tasklet_schedule(&host->tasklet);
2120 }
2121
2122 static void dw_mci_handle_cd(struct dw_mci *host)
2123 {
2124 int i;
2125
2126 for (i = 0; i < host->num_slots; i++) {
2127 struct dw_mci_slot *slot = host->slot[i];
2128
2129 if (!slot)
2130 continue;
2131
2132 if (slot->mmc->ops->card_event)
2133 slot->mmc->ops->card_event(slot->mmc);
2134 mmc_detect_change(slot->mmc,
2135 msecs_to_jiffies(host->pdata->detect_delay_ms));
2136 }
2137 }
2138
2139 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2140 {
2141 struct dw_mci *host = dev_id;
2142 u32 pending;
2143 int i;
2144
2145 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2146
2147 /*
2148 * DTO fix - version 2.10a and below, and only if internal DMA
2149 * is configured.
2150 */
2151 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2152 if (!pending &&
2153 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2154 pending |= SDMMC_INT_DATA_OVER;
2155 }
2156
2157 if (pending) {
2158 /* Check volt switch first, since it can look like an error */
2159 if ((host->state == STATE_SENDING_CMD11) &&
2160 (pending & SDMMC_INT_VOLT_SWITCH)) {
2161 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2162 pending &= ~SDMMC_INT_VOLT_SWITCH;
2163 dw_mci_cmd_interrupt(host, pending);
2164 }
2165
2166 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2167 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2168 host->cmd_status = pending;
2169 smp_wmb();
2170 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2171 }
2172
2173 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2174 /* if there is an error report DATA_ERROR */
2175 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2176 host->data_status = pending;
2177 smp_wmb();
2178 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2179 tasklet_schedule(&host->tasklet);
2180 }
2181
2182 if (pending & SDMMC_INT_DATA_OVER) {
2183 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2184 if (!host->data_status)
2185 host->data_status = pending;
2186 smp_wmb();
2187 if (host->dir_status == DW_MCI_RECV_STATUS) {
2188 if (host->sg != NULL)
2189 dw_mci_read_data_pio(host, true);
2190 }
2191 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2192 tasklet_schedule(&host->tasklet);
2193 }
2194
2195 if (pending & SDMMC_INT_RXDR) {
2196 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2197 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2198 dw_mci_read_data_pio(host, false);
2199 }
2200
2201 if (pending & SDMMC_INT_TXDR) {
2202 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2203 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2204 dw_mci_write_data_pio(host);
2205 }
2206
2207 if (pending & SDMMC_INT_CMD_DONE) {
2208 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2209 dw_mci_cmd_interrupt(host, pending);
2210 }
2211
2212 if (pending & SDMMC_INT_CD) {
2213 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2214 dw_mci_handle_cd(host);
2215 }
2216
2217 /* Handle SDIO Interrupts */
2218 for (i = 0; i < host->num_slots; i++) {
2219 struct dw_mci_slot *slot = host->slot[i];
2220
2221 if (!slot)
2222 continue;
2223
2224 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2225 mci_writel(host, RINTSTS,
2226 SDMMC_INT_SDIO(slot->sdio_id));
2227 mmc_signal_sdio_irq(slot->mmc);
2228 }
2229 }
2230
2231 }
2232
2233 #ifdef CONFIG_MMC_DW_IDMAC
2234 /* Handle DMA interrupts */
2235 if (host->dma_64bit_address == 1) {
2236 pending = mci_readl(host, IDSTS64);
2237 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2238 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2239 SDMMC_IDMAC_INT_RI);
2240 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2241 host->dma_ops->complete(host);
2242 }
2243 } else {
2244 pending = mci_readl(host, IDSTS);
2245 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2246 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2247 SDMMC_IDMAC_INT_RI);
2248 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2249 host->dma_ops->complete(host);
2250 }
2251 }
2252 #endif
2253
2254 return IRQ_HANDLED;
2255 }
2256
2257 #ifdef CONFIG_OF
2258 /* given a slot id, find out the device node representing that slot */
2259 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2260 {
2261 struct device_node *np;
2262 const __be32 *addr;
2263 int len;
2264
2265 if (!dev || !dev->of_node)
2266 return NULL;
2267
2268 for_each_child_of_node(dev->of_node, np) {
2269 addr = of_get_property(np, "reg", &len);
2270 if (!addr || (len < sizeof(int)))
2271 continue;
2272 if (be32_to_cpup(addr) == slot)
2273 return np;
2274 }
2275 return NULL;
2276 }
2277
2278 static struct dw_mci_of_slot_quirks {
2279 char *quirk;
2280 int id;
2281 } of_slot_quirks[] = {
2282 {
2283 .quirk = "disable-wp",
2284 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
2285 },
2286 };
2287
2288 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2289 {
2290 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2291 int quirks = 0;
2292 int idx;
2293
2294 /* get quirks */
2295 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
2296 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
2297 dev_warn(dev, "Slot quirk %s is deprecated\n",
2298 of_slot_quirks[idx].quirk);
2299 quirks |= of_slot_quirks[idx].id;
2300 }
2301
2302 return quirks;
2303 }
2304 #else /* CONFIG_OF */
2305 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2306 {
2307 return 0;
2308 }
2309 #endif /* CONFIG_OF */
2310
2311 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2312 {
2313 struct mmc_host *mmc;
2314 struct dw_mci_slot *slot;
2315 const struct dw_mci_drv_data *drv_data = host->drv_data;
2316 int ctrl_id, ret;
2317 u32 freq[2];
2318
2319 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2320 if (!mmc)
2321 return -ENOMEM;
2322
2323 slot = mmc_priv(mmc);
2324 slot->id = id;
2325 slot->sdio_id = host->sdio_id0 + id;
2326 slot->mmc = mmc;
2327 slot->host = host;
2328 host->slot[id] = slot;
2329
2330 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2331
2332 mmc->ops = &dw_mci_ops;
2333 if (of_property_read_u32_array(host->dev->of_node,
2334 "clock-freq-min-max", freq, 2)) {
2335 mmc->f_min = DW_MCI_FREQ_MIN;
2336 mmc->f_max = DW_MCI_FREQ_MAX;
2337 } else {
2338 mmc->f_min = freq[0];
2339 mmc->f_max = freq[1];
2340 }
2341
2342 /*if there are external regulators, get them*/
2343 ret = mmc_regulator_get_supply(mmc);
2344 if (ret == -EPROBE_DEFER)
2345 goto err_host_allocated;
2346
2347 if (!mmc->ocr_avail)
2348 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2349
2350 if (host->pdata->caps)
2351 mmc->caps = host->pdata->caps;
2352
2353 if (host->pdata->pm_caps)
2354 mmc->pm_caps = host->pdata->pm_caps;
2355
2356 if (host->dev->of_node) {
2357 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2358 if (ctrl_id < 0)
2359 ctrl_id = 0;
2360 } else {
2361 ctrl_id = to_platform_device(host->dev)->id;
2362 }
2363 if (drv_data && drv_data->caps)
2364 mmc->caps |= drv_data->caps[ctrl_id];
2365
2366 if (host->pdata->caps2)
2367 mmc->caps2 = host->pdata->caps2;
2368
2369 ret = mmc_of_parse(mmc);
2370 if (ret)
2371 goto err_host_allocated;
2372
2373 if (host->pdata->blk_settings) {
2374 mmc->max_segs = host->pdata->blk_settings->max_segs;
2375 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2376 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2377 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2378 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2379 } else {
2380 /* Useful defaults if platform data is unset. */
2381 #ifdef CONFIG_MMC_DW_IDMAC
2382 mmc->max_segs = host->ring_size;
2383 mmc->max_blk_size = 65536;
2384 mmc->max_seg_size = 0x1000;
2385 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2386 mmc->max_blk_count = mmc->max_req_size / 512;
2387 #else
2388 mmc->max_segs = 64;
2389 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2390 mmc->max_blk_count = 512;
2391 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2392 mmc->max_seg_size = mmc->max_req_size;
2393 #endif /* CONFIG_MMC_DW_IDMAC */
2394 }
2395
2396 if (dw_mci_get_cd(mmc))
2397 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2398 else
2399 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2400
2401 ret = mmc_add_host(mmc);
2402 if (ret)
2403 goto err_host_allocated;
2404
2405 #if defined(CONFIG_DEBUG_FS)
2406 dw_mci_init_debugfs(slot);
2407 #endif
2408
2409 return 0;
2410
2411 err_host_allocated:
2412 mmc_free_host(mmc);
2413 return ret;
2414 }
2415
2416 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2417 {
2418 /* Debugfs stuff is cleaned up by mmc core */
2419 mmc_remove_host(slot->mmc);
2420 slot->host->slot[id] = NULL;
2421 mmc_free_host(slot->mmc);
2422 }
2423
2424 static void dw_mci_init_dma(struct dw_mci *host)
2425 {
2426 int addr_config;
2427 /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
2428 addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
2429
2430 if (addr_config == 1) {
2431 /* host supports IDMAC in 64-bit address mode */
2432 host->dma_64bit_address = 1;
2433 dev_info(host->dev, "IDMAC supports 64-bit address mode.\n");
2434 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2435 dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64));
2436 } else {
2437 /* host supports IDMAC in 32-bit address mode */
2438 host->dma_64bit_address = 0;
2439 dev_info(host->dev, "IDMAC supports 32-bit address mode.\n");
2440 }
2441
2442 /* Alloc memory for sg translation */
2443 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2444 &host->sg_dma, GFP_KERNEL);
2445 if (!host->sg_cpu) {
2446 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2447 __func__);
2448 goto no_dma;
2449 }
2450
2451 /* Determine which DMA interface to use */
2452 #ifdef CONFIG_MMC_DW_IDMAC
2453 host->dma_ops = &dw_mci_idmac_ops;
2454 dev_info(host->dev, "Using internal DMA controller.\n");
2455 #endif
2456
2457 if (!host->dma_ops)
2458 goto no_dma;
2459
2460 if (host->dma_ops->init && host->dma_ops->start &&
2461 host->dma_ops->stop && host->dma_ops->cleanup) {
2462 if (host->dma_ops->init(host)) {
2463 dev_err(host->dev, "%s: Unable to initialize "
2464 "DMA Controller.\n", __func__);
2465 goto no_dma;
2466 }
2467 } else {
2468 dev_err(host->dev, "DMA initialization not found.\n");
2469 goto no_dma;
2470 }
2471
2472 host->use_dma = 1;
2473 return;
2474
2475 no_dma:
2476 dev_info(host->dev, "Using PIO mode.\n");
2477 host->use_dma = 0;
2478 return;
2479 }
2480
2481 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2482 {
2483 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2484 u32 ctrl;
2485
2486 ctrl = mci_readl(host, CTRL);
2487 ctrl |= reset;
2488 mci_writel(host, CTRL, ctrl);
2489
2490 /* wait till resets clear */
2491 do {
2492 ctrl = mci_readl(host, CTRL);
2493 if (!(ctrl & reset))
2494 return true;
2495 } while (time_before(jiffies, timeout));
2496
2497 dev_err(host->dev,
2498 "Timeout resetting block (ctrl reset %#x)\n",
2499 ctrl & reset);
2500
2501 return false;
2502 }
2503
2504 static bool dw_mci_reset(struct dw_mci *host)
2505 {
2506 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2507 bool ret = false;
2508
2509 /*
2510 * Reseting generates a block interrupt, hence setting
2511 * the scatter-gather pointer to NULL.
2512 */
2513 if (host->sg) {
2514 sg_miter_stop(&host->sg_miter);
2515 host->sg = NULL;
2516 }
2517
2518 if (host->use_dma)
2519 flags |= SDMMC_CTRL_DMA_RESET;
2520
2521 if (dw_mci_ctrl_reset(host, flags)) {
2522 /*
2523 * In all cases we clear the RAWINTS register to clear any
2524 * interrupts.
2525 */
2526 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2527
2528 /* if using dma we wait for dma_req to clear */
2529 if (host->use_dma) {
2530 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2531 u32 status;
2532 do {
2533 status = mci_readl(host, STATUS);
2534 if (!(status & SDMMC_STATUS_DMA_REQ))
2535 break;
2536 cpu_relax();
2537 } while (time_before(jiffies, timeout));
2538
2539 if (status & SDMMC_STATUS_DMA_REQ) {
2540 dev_err(host->dev,
2541 "%s: Timeout waiting for dma_req to "
2542 "clear during reset\n", __func__);
2543 goto ciu_out;
2544 }
2545
2546 /* when using DMA next we reset the fifo again */
2547 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2548 goto ciu_out;
2549 }
2550 } else {
2551 /* if the controller reset bit did clear, then set clock regs */
2552 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2553 dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2554 "clear but ciu was reset, doing clock update\n",
2555 __func__);
2556 goto ciu_out;
2557 }
2558 }
2559
2560 #if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2561 /* It is also recommended that we reset and reprogram idmac */
2562 dw_mci_idmac_reset(host);
2563 #endif
2564
2565 ret = true;
2566
2567 ciu_out:
2568 /* After a CTRL reset we need to have CIU set clock registers */
2569 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2570
2571 return ret;
2572 }
2573
2574 #ifdef CONFIG_OF
2575 static struct dw_mci_of_quirks {
2576 char *quirk;
2577 int id;
2578 } of_quirks[] = {
2579 {
2580 .quirk = "broken-cd",
2581 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2582 }, {
2583 .quirk = "disable-wp",
2584 .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
2585 },
2586 };
2587
2588 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2589 {
2590 struct dw_mci_board *pdata;
2591 struct device *dev = host->dev;
2592 struct device_node *np = dev->of_node;
2593 const struct dw_mci_drv_data *drv_data = host->drv_data;
2594 int idx, ret;
2595 u32 clock_frequency;
2596
2597 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2598 if (!pdata)
2599 return ERR_PTR(-ENOMEM);
2600
2601 /* find out number of slots supported */
2602 if (of_property_read_u32(dev->of_node, "num-slots",
2603 &pdata->num_slots)) {
2604 dev_info(dev, "num-slots property not found, "
2605 "assuming 1 slot is available\n");
2606 pdata->num_slots = 1;
2607 }
2608
2609 /* get quirks */
2610 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2611 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2612 pdata->quirks |= of_quirks[idx].id;
2613
2614 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2615 dev_info(dev, "fifo-depth property not found, using "
2616 "value of FIFOTH register as default\n");
2617
2618 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2619
2620 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2621 pdata->bus_hz = clock_frequency;
2622
2623 if (drv_data && drv_data->parse_dt) {
2624 ret = drv_data->parse_dt(host);
2625 if (ret)
2626 return ERR_PTR(ret);
2627 }
2628
2629 if (of_find_property(np, "supports-highspeed", NULL))
2630 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2631
2632 return pdata;
2633 }
2634
2635 #else /* CONFIG_OF */
2636 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2637 {
2638 return ERR_PTR(-EINVAL);
2639 }
2640 #endif /* CONFIG_OF */
2641
2642 static void dw_mci_enable_cd(struct dw_mci *host)
2643 {
2644 struct dw_mci_board *brd = host->pdata;
2645 unsigned long irqflags;
2646 u32 temp;
2647 int i;
2648
2649 /* No need for CD if broken card detection */
2650 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2651 return;
2652
2653 /* No need for CD if all slots have a non-error GPIO */
2654 for (i = 0; i < host->num_slots; i++) {
2655 struct dw_mci_slot *slot = host->slot[i];
2656
2657 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2658 break;
2659 }
2660 if (i == host->num_slots)
2661 return;
2662
2663 spin_lock_irqsave(&host->irq_lock, irqflags);
2664 temp = mci_readl(host, INTMASK);
2665 temp |= SDMMC_INT_CD;
2666 mci_writel(host, INTMASK, temp);
2667 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2668 }
2669
2670 int dw_mci_probe(struct dw_mci *host)
2671 {
2672 const struct dw_mci_drv_data *drv_data = host->drv_data;
2673 int width, i, ret = 0;
2674 u32 fifo_size;
2675 int init_slots = 0;
2676
2677 if (!host->pdata) {
2678 host->pdata = dw_mci_parse_dt(host);
2679 if (IS_ERR(host->pdata)) {
2680 dev_err(host->dev, "platform data not available\n");
2681 return -EINVAL;
2682 }
2683 }
2684
2685 if (host->pdata->num_slots > 1) {
2686 dev_err(host->dev,
2687 "Platform data must supply num_slots.\n");
2688 return -ENODEV;
2689 }
2690
2691 host->biu_clk = devm_clk_get(host->dev, "biu");
2692 if (IS_ERR(host->biu_clk)) {
2693 dev_dbg(host->dev, "biu clock not available\n");
2694 } else {
2695 ret = clk_prepare_enable(host->biu_clk);
2696 if (ret) {
2697 dev_err(host->dev, "failed to enable biu clock\n");
2698 return ret;
2699 }
2700 }
2701
2702 host->ciu_clk = devm_clk_get(host->dev, "ciu");
2703 if (IS_ERR(host->ciu_clk)) {
2704 dev_dbg(host->dev, "ciu clock not available\n");
2705 host->bus_hz = host->pdata->bus_hz;
2706 } else {
2707 ret = clk_prepare_enable(host->ciu_clk);
2708 if (ret) {
2709 dev_err(host->dev, "failed to enable ciu clock\n");
2710 goto err_clk_biu;
2711 }
2712
2713 if (host->pdata->bus_hz) {
2714 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2715 if (ret)
2716 dev_warn(host->dev,
2717 "Unable to set bus rate to %uHz\n",
2718 host->pdata->bus_hz);
2719 }
2720 host->bus_hz = clk_get_rate(host->ciu_clk);
2721 }
2722
2723 if (!host->bus_hz) {
2724 dev_err(host->dev,
2725 "Platform data must supply bus speed\n");
2726 ret = -ENODEV;
2727 goto err_clk_ciu;
2728 }
2729
2730 if (drv_data && drv_data->init) {
2731 ret = drv_data->init(host);
2732 if (ret) {
2733 dev_err(host->dev,
2734 "implementation specific init failed\n");
2735 goto err_clk_ciu;
2736 }
2737 }
2738
2739 if (drv_data && drv_data->setup_clock) {
2740 ret = drv_data->setup_clock(host);
2741 if (ret) {
2742 dev_err(host->dev,
2743 "implementation specific clock setup failed\n");
2744 goto err_clk_ciu;
2745 }
2746 }
2747
2748 host->quirks = host->pdata->quirks;
2749
2750 spin_lock_init(&host->lock);
2751 spin_lock_init(&host->irq_lock);
2752 INIT_LIST_HEAD(&host->queue);
2753
2754 /*
2755 * Get the host data width - this assumes that HCON has been set with
2756 * the correct values.
2757 */
2758 i = (mci_readl(host, HCON) >> 7) & 0x7;
2759 if (!i) {
2760 host->push_data = dw_mci_push_data16;
2761 host->pull_data = dw_mci_pull_data16;
2762 width = 16;
2763 host->data_shift = 1;
2764 } else if (i == 2) {
2765 host->push_data = dw_mci_push_data64;
2766 host->pull_data = dw_mci_pull_data64;
2767 width = 64;
2768 host->data_shift = 3;
2769 } else {
2770 /* Check for a reserved value, and warn if it is */
2771 WARN((i != 1),
2772 "HCON reports a reserved host data width!\n"
2773 "Defaulting to 32-bit access.\n");
2774 host->push_data = dw_mci_push_data32;
2775 host->pull_data = dw_mci_pull_data32;
2776 width = 32;
2777 host->data_shift = 2;
2778 }
2779
2780 /* Reset all blocks */
2781 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2782 return -ENODEV;
2783
2784 host->dma_ops = host->pdata->dma_ops;
2785 dw_mci_init_dma(host);
2786
2787 /* Clear the interrupts for the host controller */
2788 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2789 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2790
2791 /* Put in max timeout */
2792 mci_writel(host, TMOUT, 0xFFFFFFFF);
2793
2794 /*
2795 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2796 * Tx Mark = fifo_size / 2 DMA Size = 8
2797 */
2798 if (!host->pdata->fifo_depth) {
2799 /*
2800 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2801 * have been overwritten by the bootloader, just like we're
2802 * about to do, so if you know the value for your hardware, you
2803 * should put it in the platform data.
2804 */
2805 fifo_size = mci_readl(host, FIFOTH);
2806 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2807 } else {
2808 fifo_size = host->pdata->fifo_depth;
2809 }
2810 host->fifo_depth = fifo_size;
2811 host->fifoth_val =
2812 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
2813 mci_writel(host, FIFOTH, host->fifoth_val);
2814
2815 /* disable clock to CIU */
2816 mci_writel(host, CLKENA, 0);
2817 mci_writel(host, CLKSRC, 0);
2818
2819 /*
2820 * In 2.40a spec, Data offset is changed.
2821 * Need to check the version-id and set data-offset for DATA register.
2822 */
2823 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2824 dev_info(host->dev, "Version ID is %04x\n", host->verid);
2825
2826 if (host->verid < DW_MMC_240A)
2827 host->data_offset = DATA_OFFSET;
2828 else
2829 host->data_offset = DATA_240A_OFFSET;
2830
2831 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2832 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2833 host->irq_flags, "dw-mci", host);
2834 if (ret)
2835 goto err_dmaunmap;
2836
2837 if (host->pdata->num_slots)
2838 host->num_slots = host->pdata->num_slots;
2839 else
2840 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2841
2842 /*
2843 * Enable interrupts for command done, data over, data empty,
2844 * receive ready and error such as transmit, receive timeout, crc error
2845 */
2846 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2847 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2848 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2849 DW_MCI_ERROR_FLAGS);
2850 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2851
2852 dev_info(host->dev, "DW MMC controller at irq %d, "
2853 "%d bit host data width, "
2854 "%u deep fifo\n",
2855 host->irq, width, fifo_size);
2856
2857 /* We need at least one slot to succeed */
2858 for (i = 0; i < host->num_slots; i++) {
2859 ret = dw_mci_init_slot(host, i);
2860 if (ret)
2861 dev_dbg(host->dev, "slot %d init failed\n", i);
2862 else
2863 init_slots++;
2864 }
2865
2866 /* Now that slots are all setup, we can enable card detect */
2867 dw_mci_enable_cd(host);
2868
2869 if (init_slots) {
2870 dev_info(host->dev, "%d slots initialized\n", init_slots);
2871 } else {
2872 dev_dbg(host->dev, "attempted to initialize %d slots, "
2873 "but failed on all\n", host->num_slots);
2874 goto err_dmaunmap;
2875 }
2876
2877 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2878 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2879
2880 return 0;
2881
2882 err_dmaunmap:
2883 if (host->use_dma && host->dma_ops->exit)
2884 host->dma_ops->exit(host);
2885
2886 err_clk_ciu:
2887 if (!IS_ERR(host->ciu_clk))
2888 clk_disable_unprepare(host->ciu_clk);
2889
2890 err_clk_biu:
2891 if (!IS_ERR(host->biu_clk))
2892 clk_disable_unprepare(host->biu_clk);
2893
2894 return ret;
2895 }
2896 EXPORT_SYMBOL(dw_mci_probe);
2897
2898 void dw_mci_remove(struct dw_mci *host)
2899 {
2900 int i;
2901
2902 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2903 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2904
2905 for (i = 0; i < host->num_slots; i++) {
2906 dev_dbg(host->dev, "remove slot %d\n", i);
2907 if (host->slot[i])
2908 dw_mci_cleanup_slot(host->slot[i], i);
2909 }
2910
2911 /* disable clock to CIU */
2912 mci_writel(host, CLKENA, 0);
2913 mci_writel(host, CLKSRC, 0);
2914
2915 if (host->use_dma && host->dma_ops->exit)
2916 host->dma_ops->exit(host);
2917
2918 if (!IS_ERR(host->ciu_clk))
2919 clk_disable_unprepare(host->ciu_clk);
2920
2921 if (!IS_ERR(host->biu_clk))
2922 clk_disable_unprepare(host->biu_clk);
2923 }
2924 EXPORT_SYMBOL(dw_mci_remove);
2925
2926
2927
2928 #ifdef CONFIG_PM_SLEEP
2929 /*
2930 * TODO: we should probably disable the clock to the card in the suspend path.
2931 */
2932 int dw_mci_suspend(struct dw_mci *host)
2933 {
2934 return 0;
2935 }
2936 EXPORT_SYMBOL(dw_mci_suspend);
2937
2938 int dw_mci_resume(struct dw_mci *host)
2939 {
2940 int i, ret;
2941
2942 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2943 ret = -ENODEV;
2944 return ret;
2945 }
2946
2947 if (host->use_dma && host->dma_ops->init)
2948 host->dma_ops->init(host);
2949
2950 /*
2951 * Restore the initial value at FIFOTH register
2952 * And Invalidate the prev_blksz with zero
2953 */
2954 mci_writel(host, FIFOTH, host->fifoth_val);
2955 host->prev_blksz = 0;
2956
2957 /* Put in max timeout */
2958 mci_writel(host, TMOUT, 0xFFFFFFFF);
2959
2960 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2961 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2962 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2963 DW_MCI_ERROR_FLAGS);
2964 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2965
2966 for (i = 0; i < host->num_slots; i++) {
2967 struct dw_mci_slot *slot = host->slot[i];
2968 if (!slot)
2969 continue;
2970 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2971 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2972 dw_mci_setup_bus(slot, true);
2973 }
2974 }
2975
2976 /* Now that slots are all setup, we can enable card detect */
2977 dw_mci_enable_cd(host);
2978
2979 return 0;
2980 }
2981 EXPORT_SYMBOL(dw_mci_resume);
2982 #endif /* CONFIG_PM_SLEEP */
2983
2984 static int __init dw_mci_init(void)
2985 {
2986 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
2987 return 0;
2988 }
2989
2990 static void __exit dw_mci_exit(void)
2991 {
2992 }
2993
2994 module_init(dw_mci_init);
2995 module_exit(dw_mci_exit);
2996
2997 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2998 MODULE_AUTHOR("NXP Semiconductor VietNam");
2999 MODULE_AUTHOR("Imagination Technologies Ltd");
3000 MODULE_LICENSE("GPL v2");
(deprecated) Btrfs devel tree