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iwlwifi: clean up driver names for 1000/5000/6000
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
blob7f9e448fe5e16f564cae1dc882b392b35a32c5fe
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <net/mac80211.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40
41 #include "iwl-eeprom.h"
42 #include "iwl-dev.h"
43 #include "iwl-core.h"
44 #include "iwl-io.h"
45 #include "iwl-helpers.h"
46 #include "iwl-calib.h"
47 #include "iwl-sta.h"
48 #include "iwl-agn-led.h"
49
50 static int iwl4965_send_tx_power(struct iwl_priv *priv);
51 static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
52
53 /* Highest firmware API version supported */
54 #define IWL4965_UCODE_API_MAX 2
55
56 /* Lowest firmware API version supported */
57 #define IWL4965_UCODE_API_MIN 2
58
59 #define IWL4965_FW_PRE "iwlwifi-4965-"
60 #define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode"
61 #define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api)
62
63
64 /* module parameters */
65 static struct iwl_mod_params iwl4965_mod_params = {
66 .amsdu_size_8K = 1,
67 .restart_fw = 1,
68 /* the rest are 0 by default */
69 };
70
71 /* check contents of special bootstrap uCode SRAM */
72 static int iwl4965_verify_bsm(struct iwl_priv *priv)
73 {
74 __le32 *image = priv->ucode_boot.v_addr;
75 u32 len = priv->ucode_boot.len;
76 u32 reg;
77 u32 val;
78
79 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
80
81 /* verify BSM SRAM contents */
82 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
83 for (reg = BSM_SRAM_LOWER_BOUND;
84 reg < BSM_SRAM_LOWER_BOUND + len;
85 reg += sizeof(u32), image++) {
86 val = iwl_read_prph(priv, reg);
87 if (val != le32_to_cpu(*image)) {
88 IWL_ERR(priv, "BSM uCode verification failed at "
89 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
90 BSM_SRAM_LOWER_BOUND,
91 reg - BSM_SRAM_LOWER_BOUND, len,
92 val, le32_to_cpu(*image));
93 return -EIO;
94 }
95 }
96
97 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
98
99 return 0;
100 }
101
102 /**
103 * iwl4965_load_bsm - Load bootstrap instructions
104 *
105 * BSM operation:
106 *
107 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
108 * in special SRAM that does not power down during RFKILL. When powering back
109 * up after power-saving sleeps (or during initial uCode load), the BSM loads
110 * the bootstrap program into the on-board processor, and starts it.
111 *
112 * The bootstrap program loads (via DMA) instructions and data for a new
113 * program from host DRAM locations indicated by the host driver in the
114 * BSM_DRAM_* registers. Once the new program is loaded, it starts
115 * automatically.
116 *
117 * When initializing the NIC, the host driver points the BSM to the
118 * "initialize" uCode image. This uCode sets up some internal data, then
119 * notifies host via "initialize alive" that it is complete.
120 *
121 * The host then replaces the BSM_DRAM_* pointer values to point to the
122 * normal runtime uCode instructions and a backup uCode data cache buffer
123 * (filled initially with starting data values for the on-board processor),
124 * then triggers the "initialize" uCode to load and launch the runtime uCode,
125 * which begins normal operation.
126 *
127 * When doing a power-save shutdown, runtime uCode saves data SRAM into
128 * the backup data cache in DRAM before SRAM is powered down.
129 *
130 * When powering back up, the BSM loads the bootstrap program. This reloads
131 * the runtime uCode instructions and the backup data cache into SRAM,
132 * and re-launches the runtime uCode from where it left off.
133 */
134 static int iwl4965_load_bsm(struct iwl_priv *priv)
135 {
136 __le32 *image = priv->ucode_boot.v_addr;
137 u32 len = priv->ucode_boot.len;
138 dma_addr_t pinst;
139 dma_addr_t pdata;
140 u32 inst_len;
141 u32 data_len;
142 int i;
143 u32 done;
144 u32 reg_offset;
145 int ret;
146
147 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
148
149 priv->ucode_type = UCODE_RT;
150
151 /* make sure bootstrap program is no larger than BSM's SRAM size */
152 if (len > IWL49_MAX_BSM_SIZE)
153 return -EINVAL;
154
155 /* Tell bootstrap uCode where to find the "Initialize" uCode
156 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
157 * NOTE: iwl_init_alive_start() will replace these values,
158 * after the "initialize" uCode has run, to point to
159 * runtime/protocol instructions and backup data cache.
160 */
161 pinst = priv->ucode_init.p_addr >> 4;
162 pdata = priv->ucode_init_data.p_addr >> 4;
163 inst_len = priv->ucode_init.len;
164 data_len = priv->ucode_init_data.len;
165
166 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
167 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
168 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
169 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
170
171 /* Fill BSM memory with bootstrap instructions */
172 for (reg_offset = BSM_SRAM_LOWER_BOUND;
173 reg_offset < BSM_SRAM_LOWER_BOUND + len;
174 reg_offset += sizeof(u32), image++)
175 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
176
177 ret = iwl4965_verify_bsm(priv);
178 if (ret)
179 return ret;
180
181 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
182 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
183 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
184 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
185
186 /* Load bootstrap code into instruction SRAM now,
187 * to prepare to load "initialize" uCode */
188 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
189
190 /* Wait for load of bootstrap uCode to finish */
191 for (i = 0; i < 100; i++) {
192 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
193 if (!(done & BSM_WR_CTRL_REG_BIT_START))
194 break;
195 udelay(10);
196 }
197 if (i < 100)
198 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
199 else {
200 IWL_ERR(priv, "BSM write did not complete!\n");
201 return -EIO;
202 }
203
204 /* Enable future boot loads whenever power management unit triggers it
205 * (e.g. when powering back up after power-save shutdown) */
206 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
207
208
209 return 0;
210 }
211
212 /**
213 * iwl4965_set_ucode_ptrs - Set uCode address location
214 *
215 * Tell initialization uCode where to find runtime uCode.
216 *
217 * BSM registers initially contain pointers to initialization uCode.
218 * We need to replace them to load runtime uCode inst and data,
219 * and to save runtime data when powering down.
220 */
221 static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
222 {
223 dma_addr_t pinst;
224 dma_addr_t pdata;
225 int ret = 0;
226
227 /* bits 35:4 for 4965 */
228 pinst = priv->ucode_code.p_addr >> 4;
229 pdata = priv->ucode_data_backup.p_addr >> 4;
230
231 /* Tell bootstrap uCode where to find image to load */
232 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
233 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
234 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
235 priv->ucode_data.len);
236
237 /* Inst byte count must be last to set up, bit 31 signals uCode
238 * that all new ptr/size info is in place */
239 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
240 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
241 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
242
243 return ret;
244 }
245
246 /**
247 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
248 *
249 * Called after REPLY_ALIVE notification received from "initialize" uCode.
250 *
251 * The 4965 "initialize" ALIVE reply contains calibration data for:
252 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
253 * (3945 does not contain this data).
254 *
255 * Tell "initialize" uCode to go ahead and load the runtime uCode.
256 */
257 static void iwl4965_init_alive_start(struct iwl_priv *priv)
258 {
259 /* Check alive response for "valid" sign from uCode */
260 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
261 /* We had an error bringing up the hardware, so take it
262 * all the way back down so we can try again */
263 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
264 goto restart;
265 }
266
267 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
268 * This is a paranoid check, because we would not have gotten the
269 * "initialize" alive if code weren't properly loaded. */
270 if (iwl_verify_ucode(priv)) {
271 /* Runtime instruction load was bad;
272 * take it all the way back down so we can try again */
273 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
274 goto restart;
275 }
276
277 /* Calculate temperature */
278 priv->temperature = iwl4965_hw_get_temperature(priv);
279
280 /* Send pointers to protocol/runtime uCode image ... init code will
281 * load and launch runtime uCode, which will send us another "Alive"
282 * notification. */
283 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
284 if (iwl4965_set_ucode_ptrs(priv)) {
285 /* Runtime instruction load won't happen;
286 * take it all the way back down so we can try again */
287 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
288 goto restart;
289 }
290 return;
291
292 restart:
293 queue_work(priv->workqueue, &priv->restart);
294 }
295
296 static bool is_ht40_channel(__le32 rxon_flags)
297 {
298 int chan_mod = le32_to_cpu(rxon_flags & RXON_FLG_CHANNEL_MODE_MSK)
299 >> RXON_FLG_CHANNEL_MODE_POS;
300 return ((chan_mod == CHANNEL_MODE_PURE_40) ||
301 (chan_mod == CHANNEL_MODE_MIXED));
302 }
303
304 /*
305 * EEPROM handlers
306 */
307 static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
308 {
309 return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
310 }
311
312 /*
313 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
314 * must be called under priv->lock and mac access
315 */
316 static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
317 {
318 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
319 }
320
321 static void iwl4965_nic_config(struct iwl_priv *priv)
322 {
323 unsigned long flags;
324 u16 radio_cfg;
325
326 spin_lock_irqsave(&priv->lock, flags);
327
328 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
329
330 /* write radio config values to register */
331 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
332 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
333 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
334 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
335 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
336
337 /* set CSR_HW_CONFIG_REG for uCode use */
338 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
339 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
340 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
341
342 priv->calib_info = (struct iwl_eeprom_calib_info *)
343 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
344
345 spin_unlock_irqrestore(&priv->lock, flags);
346 }
347
348 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
349 * Called after every association, but this runs only once!
350 * ... once chain noise is calibrated the first time, it's good forever. */
351 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
352 {
353 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
354
355 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
356 struct iwl_calib_diff_gain_cmd cmd;
357
358 memset(&cmd, 0, sizeof(cmd));
359 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
360 cmd.diff_gain_a = 0;
361 cmd.diff_gain_b = 0;
362 cmd.diff_gain_c = 0;
363 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
364 sizeof(cmd), &cmd))
365 IWL_ERR(priv,
366 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
367 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
368 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
369 }
370 }
371
372 static void iwl4965_gain_computation(struct iwl_priv *priv,
373 u32 *average_noise,
374 u16 min_average_noise_antenna_i,
375 u32 min_average_noise,
376 u8 default_chain)
377 {
378 int i, ret;
379 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
380
381 data->delta_gain_code[min_average_noise_antenna_i] = 0;
382
383 for (i = default_chain; i < NUM_RX_CHAINS; i++) {
384 s32 delta_g = 0;
385
386 if (!(data->disconn_array[i]) &&
387 (data->delta_gain_code[i] ==
388 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
389 delta_g = average_noise[i] - min_average_noise;
390 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
391 data->delta_gain_code[i] =
392 min(data->delta_gain_code[i],
393 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
394
395 data->delta_gain_code[i] =
396 (data->delta_gain_code[i] | (1 << 2));
397 } else {
398 data->delta_gain_code[i] = 0;
399 }
400 }
401 IWL_DEBUG_CALIB(priv, "delta_gain_codes: a %d b %d c %d\n",
402 data->delta_gain_code[0],
403 data->delta_gain_code[1],
404 data->delta_gain_code[2]);
405
406 /* Differential gain gets sent to uCode only once */
407 if (!data->radio_write) {
408 struct iwl_calib_diff_gain_cmd cmd;
409 data->radio_write = 1;
410
411 memset(&cmd, 0, sizeof(cmd));
412 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
413 cmd.diff_gain_a = data->delta_gain_code[0];
414 cmd.diff_gain_b = data->delta_gain_code[1];
415 cmd.diff_gain_c = data->delta_gain_code[2];
416 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
417 sizeof(cmd), &cmd);
418 if (ret)
419 IWL_DEBUG_CALIB(priv, "fail sending cmd "
420 "REPLY_PHY_CALIBRATION_CMD \n");
421
422 /* TODO we might want recalculate
423 * rx_chain in rxon cmd */
424
425 /* Mark so we run this algo only once! */
426 data->state = IWL_CHAIN_NOISE_CALIBRATED;
427 }
428 data->chain_noise_a = 0;
429 data->chain_noise_b = 0;
430 data->chain_noise_c = 0;
431 data->chain_signal_a = 0;
432 data->chain_signal_b = 0;
433 data->chain_signal_c = 0;
434 data->beacon_count = 0;
435 }
436
437 static void iwl4965_bg_txpower_work(struct work_struct *work)
438 {
439 struct iwl_priv *priv = container_of(work, struct iwl_priv,
440 txpower_work);
441
442 /* If a scan happened to start before we got here
443 * then just return; the statistics notification will
444 * kick off another scheduled work to compensate for
445 * any temperature delta we missed here. */
446 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
447 test_bit(STATUS_SCANNING, &priv->status))
448 return;
449
450 mutex_lock(&priv->mutex);
451
452 /* Regardless of if we are associated, we must reconfigure the
453 * TX power since frames can be sent on non-radar channels while
454 * not associated */
455 iwl4965_send_tx_power(priv);
456
457 /* Update last_temperature to keep is_calib_needed from running
458 * when it isn't needed... */
459 priv->last_temperature = priv->temperature;
460
461 mutex_unlock(&priv->mutex);
462 }
463
464 /*
465 * Acquire priv->lock before calling this function !
466 */
467 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
468 {
469 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
470 (index & 0xff) | (txq_id << 8));
471 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
472 }
473
474 /**
475 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
476 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
477 * @scd_retry: (1) Indicates queue will be used in aggregation mode
478 *
479 * NOTE: Acquire priv->lock before calling this function !
480 */
481 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
482 struct iwl_tx_queue *txq,
483 int tx_fifo_id, int scd_retry)
484 {
485 int txq_id = txq->q.id;
486
487 /* Find out whether to activate Tx queue */
488 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
489
490 /* Set up and activate */
491 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
492 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
493 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
494 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
495 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
496 IWL49_SCD_QUEUE_STTS_REG_MSK);
497
498 txq->sched_retry = scd_retry;
499
500 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
501 active ? "Activate" : "Deactivate",
502 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
503 }
504
505 static const s8 default_queue_to_tx_fifo[] = {
506 IWL_TX_FIFO_VO,
507 IWL_TX_FIFO_VI,
508 IWL_TX_FIFO_BE,
509 IWL_TX_FIFO_BK,
510 IWL49_CMD_FIFO_NUM,
511 IWL_TX_FIFO_UNUSED,
512 IWL_TX_FIFO_UNUSED,
513 };
514
515 static int iwl4965_alive_notify(struct iwl_priv *priv)
516 {
517 u32 a;
518 unsigned long flags;
519 int i, chan;
520 u32 reg_val;
521
522 spin_lock_irqsave(&priv->lock, flags);
523
524 /* Clear 4965's internal Tx Scheduler data base */
525 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
526 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
527 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
528 iwl_write_targ_mem(priv, a, 0);
529 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
530 iwl_write_targ_mem(priv, a, 0);
531 for (; a < priv->scd_base_addr +
532 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
533 iwl_write_targ_mem(priv, a, 0);
534
535 /* Tel 4965 where to find Tx byte count tables */
536 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
537 priv->scd_bc_tbls.dma >> 10);
538
539 /* Enable DMA channel */
540 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
541 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
542 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
543 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
544
545 /* Update FH chicken bits */
546 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
547 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
548 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
549
550 /* Disable chain mode for all queues */
551 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
552
553 /* Initialize each Tx queue (including the command queue) */
554 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
555
556 /* TFD circular buffer read/write indexes */
557 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
558 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
559
560 /* Max Tx Window size for Scheduler-ACK mode */
561 iwl_write_targ_mem(priv, priv->scd_base_addr +
562 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
563 (SCD_WIN_SIZE <<
564 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
565 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
566
567 /* Frame limit */
568 iwl_write_targ_mem(priv, priv->scd_base_addr +
569 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
570 sizeof(u32),
571 (SCD_FRAME_LIMIT <<
572 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
573 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
574
575 }
576 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
577 (1 << priv->hw_params.max_txq_num) - 1);
578
579 /* Activate all Tx DMA/FIFO channels */
580 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
581
582 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
583
584 /* make sure all queue are not stopped */
585 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
586 for (i = 0; i < 4; i++)
587 atomic_set(&priv->queue_stop_count[i], 0);
588
589 /* reset to 0 to enable all the queue first */
590 priv->txq_ctx_active_msk = 0;
591 /* Map each Tx/cmd queue to its corresponding fifo */
592 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
593 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
594 int ac = default_queue_to_tx_fifo[i];
595
596 iwl_txq_ctx_activate(priv, i);
597
598 if (ac == IWL_TX_FIFO_UNUSED)
599 continue;
600
601 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
602 }
603
604 spin_unlock_irqrestore(&priv->lock, flags);
605
606 return 0;
607 }
608
609 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
610 .min_nrg_cck = 97,
611 .max_nrg_cck = 0, /* not used, set to 0 */
612
613 .auto_corr_min_ofdm = 85,
614 .auto_corr_min_ofdm_mrc = 170,
615 .auto_corr_min_ofdm_x1 = 105,
616 .auto_corr_min_ofdm_mrc_x1 = 220,
617
618 .auto_corr_max_ofdm = 120,
619 .auto_corr_max_ofdm_mrc = 210,
620 .auto_corr_max_ofdm_x1 = 140,
621 .auto_corr_max_ofdm_mrc_x1 = 270,
622
623 .auto_corr_min_cck = 125,
624 .auto_corr_max_cck = 200,
625 .auto_corr_min_cck_mrc = 200,
626 .auto_corr_max_cck_mrc = 400,
627
628 .nrg_th_cck = 100,
629 .nrg_th_ofdm = 100,
630
631 .barker_corr_th_min = 190,
632 .barker_corr_th_min_mrc = 390,
633 .nrg_th_cca = 62,
634 };
635
636 static void iwl4965_set_ct_threshold(struct iwl_priv *priv)
637 {
638 /* want Kelvin */
639 priv->hw_params.ct_kill_threshold =
640 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
641 }
642
643 /**
644 * iwl4965_hw_set_hw_params
645 *
646 * Called when initializing driver
647 */
648 static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
649 {
650 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
651 priv->cfg->mod_params->num_of_queues <= IWL49_NUM_QUEUES)
652 priv->cfg->num_of_queues =
653 priv->cfg->mod_params->num_of_queues;
654
655 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
656 priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
657 priv->hw_params.scd_bc_tbls_size =
658 priv->cfg->num_of_queues *
659 sizeof(struct iwl4965_scd_bc_tbl);
660 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
661 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
662 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
663 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
664 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
665 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
666 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
667
668 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
669
670 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
671 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
672 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
673 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
674 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
675 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
676
677 priv->hw_params.sens = &iwl4965_sensitivity;
678
679 return 0;
680 }
681
682 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
683 {
684 s32 sign = 1;
685
686 if (num < 0) {
687 sign = -sign;
688 num = -num;
689 }
690 if (denom < 0) {
691 sign = -sign;
692 denom = -denom;
693 }
694 *res = 1;
695 *res = ((num * 2 + denom) / (denom * 2)) * sign;
696
697 return 1;
698 }
699
700 /**
701 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
702 *
703 * Determines power supply voltage compensation for txpower calculations.
704 * Returns number of 1/2-dB steps to subtract from gain table index,
705 * to compensate for difference between power supply voltage during
706 * factory measurements, vs. current power supply voltage.
707 *
708 * Voltage indication is higher for lower voltage.
709 * Lower voltage requires more gain (lower gain table index).
710 */
711 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
712 s32 current_voltage)
713 {
714 s32 comp = 0;
715
716 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
717 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
718 return 0;
719
720 iwl4965_math_div_round(current_voltage - eeprom_voltage,
721 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
722
723 if (current_voltage > eeprom_voltage)
724 comp *= 2;
725 if ((comp < -2) || (comp > 2))
726 comp = 0;
727
728 return comp;
729 }
730
731 static s32 iwl4965_get_tx_atten_grp(u16 channel)
732 {
733 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
734 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
735 return CALIB_CH_GROUP_5;
736
737 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
738 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
739 return CALIB_CH_GROUP_1;
740
741 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
742 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
743 return CALIB_CH_GROUP_2;
744
745 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
746 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
747 return CALIB_CH_GROUP_3;
748
749 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
750 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
751 return CALIB_CH_GROUP_4;
752
753 return -1;
754 }
755
756 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
757 {
758 s32 b = -1;
759
760 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
761 if (priv->calib_info->band_info[b].ch_from == 0)
762 continue;
763
764 if ((channel >= priv->calib_info->band_info[b].ch_from)
765 && (channel <= priv->calib_info->band_info[b].ch_to))
766 break;
767 }
768
769 return b;
770 }
771
772 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
773 {
774 s32 val;
775
776 if (x2 == x1)
777 return y1;
778 else {
779 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
780 return val + y2;
781 }
782 }
783
784 /**
785 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
786 *
787 * Interpolates factory measurements from the two sample channels within a
788 * sub-band, to apply to channel of interest. Interpolation is proportional to
789 * differences in channel frequencies, which is proportional to differences
790 * in channel number.
791 */
792 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
793 struct iwl_eeprom_calib_ch_info *chan_info)
794 {
795 s32 s = -1;
796 u32 c;
797 u32 m;
798 const struct iwl_eeprom_calib_measure *m1;
799 const struct iwl_eeprom_calib_measure *m2;
800 struct iwl_eeprom_calib_measure *omeas;
801 u32 ch_i1;
802 u32 ch_i2;
803
804 s = iwl4965_get_sub_band(priv, channel);
805 if (s >= EEPROM_TX_POWER_BANDS) {
806 IWL_ERR(priv, "Tx Power can not find channel %d\n", channel);
807 return -1;
808 }
809
810 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
811 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
812 chan_info->ch_num = (u8) channel;
813
814 IWL_DEBUG_TXPOWER(priv, "channel %d subband %d factory cal ch %d & %d\n",
815 channel, s, ch_i1, ch_i2);
816
817 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
818 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
819 m1 = &(priv->calib_info->band_info[s].ch1.
820 measurements[c][m]);
821 m2 = &(priv->calib_info->band_info[s].ch2.
822 measurements[c][m]);
823 omeas = &(chan_info->measurements[c][m]);
824
825 omeas->actual_pow =
826 (u8) iwl4965_interpolate_value(channel, ch_i1,
827 m1->actual_pow,
828 ch_i2,
829 m2->actual_pow);
830 omeas->gain_idx =
831 (u8) iwl4965_interpolate_value(channel, ch_i1,
832 m1->gain_idx, ch_i2,
833 m2->gain_idx);
834 omeas->temperature =
835 (u8) iwl4965_interpolate_value(channel, ch_i1,
836 m1->temperature,
837 ch_i2,
838 m2->temperature);
839 omeas->pa_det =
840 (s8) iwl4965_interpolate_value(channel, ch_i1,
841 m1->pa_det, ch_i2,
842 m2->pa_det);
843
844 IWL_DEBUG_TXPOWER(priv,
845 "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
846 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
847 IWL_DEBUG_TXPOWER(priv,
848 "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
849 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
850 IWL_DEBUG_TXPOWER(priv,
851 "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
852 m1->pa_det, m2->pa_det, omeas->pa_det);
853 IWL_DEBUG_TXPOWER(priv,
854 "chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
855 m1->temperature, m2->temperature,
856 omeas->temperature);
857 }
858 }
859
860 return 0;
861 }
862
863 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
864 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
865 static s32 back_off_table[] = {
866 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
867 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
868 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
869 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
870 10 /* CCK */
871 };
872
873 /* Thermal compensation values for txpower for various frequency ranges ...
874 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
875 static struct iwl4965_txpower_comp_entry {
876 s32 degrees_per_05db_a;
877 s32 degrees_per_05db_a_denom;
878 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
879 {9, 2}, /* group 0 5.2, ch 34-43 */
880 {4, 1}, /* group 1 5.2, ch 44-70 */
881 {4, 1}, /* group 2 5.2, ch 71-124 */
882 {4, 1}, /* group 3 5.2, ch 125-200 */
883 {3, 1} /* group 4 2.4, ch all */
884 };
885
886 static s32 get_min_power_index(s32 rate_power_index, u32 band)
887 {
888 if (!band) {
889 if ((rate_power_index & 7) <= 4)
890 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
891 }
892 return MIN_TX_GAIN_INDEX;
893 }
894
895 struct gain_entry {
896 u8 dsp;
897 u8 radio;
898 };
899
900 static const struct gain_entry gain_table[2][108] = {
901 /* 5.2GHz power gain index table */
902 {
903 {123, 0x3F}, /* highest txpower */
904 {117, 0x3F},
905 {110, 0x3F},
906 {104, 0x3F},
907 {98, 0x3F},
908 {110, 0x3E},
909 {104, 0x3E},
910 {98, 0x3E},
911 {110, 0x3D},
912 {104, 0x3D},
913 {98, 0x3D},
914 {110, 0x3C},
915 {104, 0x3C},
916 {98, 0x3C},
917 {110, 0x3B},
918 {104, 0x3B},
919 {98, 0x3B},
920 {110, 0x3A},
921 {104, 0x3A},
922 {98, 0x3A},
923 {110, 0x39},
924 {104, 0x39},
925 {98, 0x39},
926 {110, 0x38},
927 {104, 0x38},
928 {98, 0x38},
929 {110, 0x37},
930 {104, 0x37},
931 {98, 0x37},
932 {110, 0x36},
933 {104, 0x36},
934 {98, 0x36},
935 {110, 0x35},
936 {104, 0x35},
937 {98, 0x35},
938 {110, 0x34},
939 {104, 0x34},
940 {98, 0x34},
941 {110, 0x33},
942 {104, 0x33},
943 {98, 0x33},
944 {110, 0x32},
945 {104, 0x32},
946 {98, 0x32},
947 {110, 0x31},
948 {104, 0x31},
949 {98, 0x31},
950 {110, 0x30},
951 {104, 0x30},
952 {98, 0x30},
953 {110, 0x25},
954 {104, 0x25},
955 {98, 0x25},
956 {110, 0x24},
957 {104, 0x24},
958 {98, 0x24},
959 {110, 0x23},
960 {104, 0x23},
961 {98, 0x23},
962 {110, 0x22},
963 {104, 0x18},
964 {98, 0x18},
965 {110, 0x17},
966 {104, 0x17},
967 {98, 0x17},
968 {110, 0x16},
969 {104, 0x16},
970 {98, 0x16},
971 {110, 0x15},
972 {104, 0x15},
973 {98, 0x15},
974 {110, 0x14},
975 {104, 0x14},
976 {98, 0x14},
977 {110, 0x13},
978 {104, 0x13},
979 {98, 0x13},
980 {110, 0x12},
981 {104, 0x08},
982 {98, 0x08},
983 {110, 0x07},
984 {104, 0x07},
985 {98, 0x07},
986 {110, 0x06},
987 {104, 0x06},
988 {98, 0x06},
989 {110, 0x05},
990 {104, 0x05},
991 {98, 0x05},
992 {110, 0x04},
993 {104, 0x04},
994 {98, 0x04},
995 {110, 0x03},
996 {104, 0x03},
997 {98, 0x03},
998 {110, 0x02},
999 {104, 0x02},
1000 {98, 0x02},
1001 {110, 0x01},
1002 {104, 0x01},
1003 {98, 0x01},
1004 {110, 0x00},
1005 {104, 0x00},
1006 {98, 0x00},
1007 {93, 0x00},
1008 {88, 0x00},
1009 {83, 0x00},
1010 {78, 0x00},
1011 },
1012 /* 2.4GHz power gain index table */
1013 {
1014 {110, 0x3f}, /* highest txpower */
1015 {104, 0x3f},
1016 {98, 0x3f},
1017 {110, 0x3e},
1018 {104, 0x3e},
1019 {98, 0x3e},
1020 {110, 0x3d},
1021 {104, 0x3d},
1022 {98, 0x3d},
1023 {110, 0x3c},
1024 {104, 0x3c},
1025 {98, 0x3c},
1026 {110, 0x3b},
1027 {104, 0x3b},
1028 {98, 0x3b},
1029 {110, 0x3a},
1030 {104, 0x3a},
1031 {98, 0x3a},
1032 {110, 0x39},
1033 {104, 0x39},
1034 {98, 0x39},
1035 {110, 0x38},
1036 {104, 0x38},
1037 {98, 0x38},
1038 {110, 0x37},
1039 {104, 0x37},
1040 {98, 0x37},
1041 {110, 0x36},
1042 {104, 0x36},
1043 {98, 0x36},
1044 {110, 0x35},
1045 {104, 0x35},
1046 {98, 0x35},
1047 {110, 0x34},
1048 {104, 0x34},
1049 {98, 0x34},
1050 {110, 0x33},
1051 {104, 0x33},
1052 {98, 0x33},
1053 {110, 0x32},
1054 {104, 0x32},
1055 {98, 0x32},
1056 {110, 0x31},
1057 {104, 0x31},
1058 {98, 0x31},
1059 {110, 0x30},
1060 {104, 0x30},
1061 {98, 0x30},
1062 {110, 0x6},
1063 {104, 0x6},
1064 {98, 0x6},
1065 {110, 0x5},
1066 {104, 0x5},
1067 {98, 0x5},
1068 {110, 0x4},
1069 {104, 0x4},
1070 {98, 0x4},
1071 {110, 0x3},
1072 {104, 0x3},
1073 {98, 0x3},
1074 {110, 0x2},
1075 {104, 0x2},
1076 {98, 0x2},
1077 {110, 0x1},
1078 {104, 0x1},
1079 {98, 0x1},
1080 {110, 0x0},
1081 {104, 0x0},
1082 {98, 0x0},
1083 {97, 0},
1084 {96, 0},
1085 {95, 0},
1086 {94, 0},
1087 {93, 0},
1088 {92, 0},
1089 {91, 0},
1090 {90, 0},
1091 {89, 0},
1092 {88, 0},
1093 {87, 0},
1094 {86, 0},
1095 {85, 0},
1096 {84, 0},
1097 {83, 0},
1098 {82, 0},
1099 {81, 0},
1100 {80, 0},
1101 {79, 0},
1102 {78, 0},
1103 {77, 0},
1104 {76, 0},
1105 {75, 0},
1106 {74, 0},
1107 {73, 0},
1108 {72, 0},
1109 {71, 0},
1110 {70, 0},
1111 {69, 0},
1112 {68, 0},
1113 {67, 0},
1114 {66, 0},
1115 {65, 0},
1116 {64, 0},
1117 {63, 0},
1118 {62, 0},
1119 {61, 0},
1120 {60, 0},
1121 {59, 0},
1122 }
1123 };
1124
1125 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1126 u8 is_ht40, u8 ctrl_chan_high,
1127 struct iwl4965_tx_power_db *tx_power_tbl)
1128 {
1129 u8 saturation_power;
1130 s32 target_power;
1131 s32 user_target_power;
1132 s32 power_limit;
1133 s32 current_temp;
1134 s32 reg_limit;
1135 s32 current_regulatory;
1136 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1137 int i;
1138 int c;
1139 const struct iwl_channel_info *ch_info = NULL;
1140 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1141 const struct iwl_eeprom_calib_measure *measurement;
1142 s16 voltage;
1143 s32 init_voltage;
1144 s32 voltage_compensation;
1145 s32 degrees_per_05db_num;
1146 s32 degrees_per_05db_denom;
1147 s32 factory_temp;
1148 s32 temperature_comp[2];
1149 s32 factory_gain_index[2];
1150 s32 factory_actual_pwr[2];
1151 s32 power_index;
1152
1153 /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units
1154 * are used for indexing into txpower table) */
1155 user_target_power = 2 * priv->tx_power_user_lmt;
1156
1157 /* Get current (RXON) channel, band, width */
1158 IWL_DEBUG_TXPOWER(priv, "chan %d band %d is_ht40 %d\n", channel, band,
1159 is_ht40);
1160
1161 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1162
1163 if (!is_channel_valid(ch_info))
1164 return -EINVAL;
1165
1166 /* get txatten group, used to select 1) thermal txpower adjustment
1167 * and 2) mimo txpower balance between Tx chains. */
1168 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1169 if (txatten_grp < 0) {
1170 IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
1171 channel);
1172 return -EINVAL;
1173 }
1174
1175 IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
1176 channel, txatten_grp);
1177
1178 if (is_ht40) {
1179 if (ctrl_chan_high)
1180 channel -= 2;
1181 else
1182 channel += 2;
1183 }
1184
1185 /* hardware txpower limits ...
1186 * saturation (clipping distortion) txpowers are in half-dBm */
1187 if (band)
1188 saturation_power = priv->calib_info->saturation_power24;
1189 else
1190 saturation_power = priv->calib_info->saturation_power52;
1191
1192 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1193 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1194 if (band)
1195 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1196 else
1197 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1198 }
1199
1200 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1201 * max_power_avg values are in dBm, convert * 2 */
1202 if (is_ht40)
1203 reg_limit = ch_info->ht40_max_power_avg * 2;
1204 else
1205 reg_limit = ch_info->max_power_avg * 2;
1206
1207 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1208 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1209 if (band)
1210 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1211 else
1212 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1213 }
1214
1215 /* Interpolate txpower calibration values for this channel,
1216 * based on factory calibration tests on spaced channels. */
1217 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1218
1219 /* calculate tx gain adjustment based on power supply voltage */
1220 voltage = le16_to_cpu(priv->calib_info->voltage);
1221 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1222 voltage_compensation =
1223 iwl4965_get_voltage_compensation(voltage, init_voltage);
1224
1225 IWL_DEBUG_TXPOWER(priv, "curr volt %d eeprom volt %d volt comp %d\n",
1226 init_voltage,
1227 voltage, voltage_compensation);
1228
1229 /* get current temperature (Celsius) */
1230 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1231 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1232 current_temp = KELVIN_TO_CELSIUS(current_temp);
1233
1234 /* select thermal txpower adjustment params, based on channel group
1235 * (same frequency group used for mimo txatten adjustment) */
1236 degrees_per_05db_num =
1237 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1238 degrees_per_05db_denom =
1239 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1240
1241 /* get per-chain txpower values from factory measurements */
1242 for (c = 0; c < 2; c++) {
1243 measurement = &ch_eeprom_info.measurements[c][1];
1244
1245 /* txgain adjustment (in half-dB steps) based on difference
1246 * between factory and current temperature */
1247 factory_temp = measurement->temperature;
1248 iwl4965_math_div_round((current_temp - factory_temp) *
1249 degrees_per_05db_denom,
1250 degrees_per_05db_num,
1251 &temperature_comp[c]);
1252
1253 factory_gain_index[c] = measurement->gain_idx;
1254 factory_actual_pwr[c] = measurement->actual_pow;
1255
1256 IWL_DEBUG_TXPOWER(priv, "chain = %d\n", c);
1257 IWL_DEBUG_TXPOWER(priv, "fctry tmp %d, "
1258 "curr tmp %d, comp %d steps\n",
1259 factory_temp, current_temp,
1260 temperature_comp[c]);
1261
1262 IWL_DEBUG_TXPOWER(priv, "fctry idx %d, fctry pwr %d\n",
1263 factory_gain_index[c],
1264 factory_actual_pwr[c]);
1265 }
1266
1267 /* for each of 33 bit-rates (including 1 for CCK) */
1268 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1269 u8 is_mimo_rate;
1270 union iwl4965_tx_power_dual_stream tx_power;
1271
1272 /* for mimo, reduce each chain's txpower by half
1273 * (3dB, 6 steps), so total output power is regulatory
1274 * compliant. */
1275 if (i & 0x8) {
1276 current_regulatory = reg_limit -
1277 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1278 is_mimo_rate = 1;
1279 } else {
1280 current_regulatory = reg_limit;
1281 is_mimo_rate = 0;
1282 }
1283
1284 /* find txpower limit, either hardware or regulatory */
1285 power_limit = saturation_power - back_off_table[i];
1286 if (power_limit > current_regulatory)
1287 power_limit = current_regulatory;
1288
1289 /* reduce user's txpower request if necessary
1290 * for this rate on this channel */
1291 target_power = user_target_power;
1292 if (target_power > power_limit)
1293 target_power = power_limit;
1294
1295 IWL_DEBUG_TXPOWER(priv, "rate %d sat %d reg %d usr %d tgt %d\n",
1296 i, saturation_power - back_off_table[i],
1297 current_regulatory, user_target_power,
1298 target_power);
1299
1300 /* for each of 2 Tx chains (radio transmitters) */
1301 for (c = 0; c < 2; c++) {
1302 s32 atten_value;
1303
1304 if (is_mimo_rate)
1305 atten_value =
1306 (s32)le32_to_cpu(priv->card_alive_init.
1307 tx_atten[txatten_grp][c]);
1308 else
1309 atten_value = 0;
1310
1311 /* calculate index; higher index means lower txpower */
1312 power_index = (u8) (factory_gain_index[c] -
1313 (target_power -
1314 factory_actual_pwr[c]) -
1315 temperature_comp[c] -
1316 voltage_compensation +
1317 atten_value);
1318
1319 /* IWL_DEBUG_TXPOWER(priv, "calculated txpower index %d\n",
1320 power_index); */
1321
1322 if (power_index < get_min_power_index(i, band))
1323 power_index = get_min_power_index(i, band);
1324
1325 /* adjust 5 GHz index to support negative indexes */
1326 if (!band)
1327 power_index += 9;
1328
1329 /* CCK, rate 32, reduce txpower for CCK */
1330 if (i == POWER_TABLE_CCK_ENTRY)
1331 power_index +=
1332 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1333
1334 /* stay within the table! */
1335 if (power_index > 107) {
1336 IWL_WARN(priv, "txpower index %d > 107\n",
1337 power_index);
1338 power_index = 107;
1339 }
1340 if (power_index < 0) {
1341 IWL_WARN(priv, "txpower index %d < 0\n",
1342 power_index);
1343 power_index = 0;
1344 }
1345
1346 /* fill txpower command for this rate/chain */
1347 tx_power.s.radio_tx_gain[c] =
1348 gain_table[band][power_index].radio;
1349 tx_power.s.dsp_predis_atten[c] =
1350 gain_table[band][power_index].dsp;
1351
1352 IWL_DEBUG_TXPOWER(priv, "chain %d mimo %d index %d "
1353 "gain 0x%02x dsp %d\n",
1354 c, atten_value, power_index,
1355 tx_power.s.radio_tx_gain[c],
1356 tx_power.s.dsp_predis_atten[c]);
1357 } /* for each chain */
1358
1359 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1360
1361 } /* for each rate */
1362
1363 return 0;
1364 }
1365
1366 /**
1367 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
1368 *
1369 * Uses the active RXON for channel, band, and characteristics (ht40, high)
1370 * The power limit is taken from priv->tx_power_user_lmt.
1371 */
1372 static int iwl4965_send_tx_power(struct iwl_priv *priv)
1373 {
1374 struct iwl4965_txpowertable_cmd cmd = { 0 };
1375 int ret;
1376 u8 band = 0;
1377 bool is_ht40 = false;
1378 u8 ctrl_chan_high = 0;
1379
1380 if (test_bit(STATUS_SCANNING, &priv->status)) {
1381 /* If this gets hit a lot, switch it to a BUG() and catch
1382 * the stack trace to find out who is calling this during
1383 * a scan. */
1384 IWL_WARN(priv, "TX Power requested while scanning!\n");
1385 return -EAGAIN;
1386 }
1387
1388 band = priv->band == IEEE80211_BAND_2GHZ;
1389
1390 is_ht40 = is_ht40_channel(priv->active_rxon.flags);
1391
1392 if (is_ht40 &&
1393 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1394 ctrl_chan_high = 1;
1395
1396 cmd.band = band;
1397 cmd.channel = priv->active_rxon.channel;
1398
1399 ret = iwl4965_fill_txpower_tbl(priv, band,
1400 le16_to_cpu(priv->active_rxon.channel),
1401 is_ht40, ctrl_chan_high, &cmd.tx_power);
1402 if (ret)
1403 goto out;
1404
1405 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1406
1407 out:
1408 return ret;
1409 }
1410
1411 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1412 {
1413 int ret = 0;
1414 struct iwl4965_rxon_assoc_cmd rxon_assoc;
1415 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1416 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1417
1418 if ((rxon1->flags == rxon2->flags) &&
1419 (rxon1->filter_flags == rxon2->filter_flags) &&
1420 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1421 (rxon1->ofdm_ht_single_stream_basic_rates ==
1422 rxon2->ofdm_ht_single_stream_basic_rates) &&
1423 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1424 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1425 (rxon1->rx_chain == rxon2->rx_chain) &&
1426 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1427 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1428 return 0;
1429 }
1430
1431 rxon_assoc.flags = priv->staging_rxon.flags;
1432 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1433 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1434 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1435 rxon_assoc.reserved = 0;
1436 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1437 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1438 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1439 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1440 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1441
1442 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1443 sizeof(rxon_assoc), &rxon_assoc, NULL);
1444 if (ret)
1445 return ret;
1446
1447 return ret;
1448 }
1449
1450 static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1451 {
1452 int rc;
1453 u8 band = 0;
1454 bool is_ht40 = false;
1455 u8 ctrl_chan_high = 0;
1456 struct iwl4965_channel_switch_cmd cmd;
1457 const struct iwl_channel_info *ch_info;
1458
1459 band = priv->band == IEEE80211_BAND_2GHZ;
1460
1461 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1462
1463 is_ht40 = is_ht40_channel(priv->staging_rxon.flags);
1464
1465 if (is_ht40 &&
1466 (priv->staging_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1467 ctrl_chan_high = 1;
1468
1469 cmd.band = band;
1470 cmd.expect_beacon = 0;
1471 cmd.channel = cpu_to_le16(channel);
1472 cmd.rxon_flags = priv->staging_rxon.flags;
1473 cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1474 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1475 if (ch_info)
1476 cmd.expect_beacon = is_channel_radar(ch_info);
1477 else {
1478 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1479 priv->active_rxon.channel, channel);
1480 return -EFAULT;
1481 }
1482
1483 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_ht40,
1484 ctrl_chan_high, &cmd.tx_power);
1485 if (rc) {
1486 IWL_DEBUG_11H(priv, "error:%d fill txpower_tbl\n", rc);
1487 return rc;
1488 }
1489
1490 priv->switch_rxon.channel = cpu_to_le16(channel);
1491 priv->switch_rxon.switch_in_progress = true;
1492
1493 return iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
1494 }
1495
1496 /**
1497 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
1498 */
1499 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
1500 struct iwl_tx_queue *txq,
1501 u16 byte_cnt)
1502 {
1503 struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
1504 int txq_id = txq->q.id;
1505 int write_ptr = txq->q.write_ptr;
1506 int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1507 __le16 bc_ent;
1508
1509 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
1510
1511 bc_ent = cpu_to_le16(len & 0xFFF);
1512 /* Set up byte count within first 256 entries */
1513 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
1514
1515 /* If within first 64 entries, duplicate at end */
1516 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
1517 scd_bc_tbl[txq_id].
1518 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
1519 }
1520
1521 /**
1522 * sign_extend - Sign extend a value using specified bit as sign-bit
1523 *
1524 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1525 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1526 *
1527 * @param oper value to sign extend
1528 * @param index 0 based bit index (0<=index<32) to sign bit
1529 */
1530 static s32 sign_extend(u32 oper, int index)
1531 {
1532 u8 shift = 31 - index;
1533
1534 return (s32)(oper << shift) >> shift;
1535 }
1536
1537 /**
1538 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
1539 * @statistics: Provides the temperature reading from the uCode
1540 *
1541 * A return of <0 indicates bogus data in the statistics
1542 */
1543 static int iwl4965_hw_get_temperature(struct iwl_priv *priv)
1544 {
1545 s32 temperature;
1546 s32 vt;
1547 s32 R1, R2, R3;
1548 u32 R4;
1549
1550 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1551 (priv->statistics.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)) {
1552 IWL_DEBUG_TEMP(priv, "Running HT40 temperature calibration\n");
1553 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1554 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1555 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1556 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1557 } else {
1558 IWL_DEBUG_TEMP(priv, "Running temperature calibration\n");
1559 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1560 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1561 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1562 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1563 }
1564
1565 /*
1566 * Temperature is only 23 bits, so sign extend out to 32.
1567 *
1568 * NOTE If we haven't received a statistics notification yet
1569 * with an updated temperature, use R4 provided to us in the
1570 * "initialize" ALIVE response.
1571 */
1572 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1573 vt = sign_extend(R4, 23);
1574 else
1575 vt = sign_extend(
1576 le32_to_cpu(priv->statistics.general.temperature), 23);
1577
1578 IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
1579
1580 if (R3 == R1) {
1581 IWL_ERR(priv, "Calibration conflict R1 == R3\n");
1582 return -1;
1583 }
1584
1585 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1586 * Add offset to center the adjustment around 0 degrees Centigrade. */
1587 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1588 temperature /= (R3 - R1);
1589 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
1590
1591 IWL_DEBUG_TEMP(priv, "Calibrated temperature: %dK, %dC\n",
1592 temperature, KELVIN_TO_CELSIUS(temperature));
1593
1594 return temperature;
1595 }
1596
1597 /* Adjust Txpower only if temperature variance is greater than threshold. */
1598 #define IWL_TEMPERATURE_THRESHOLD 3
1599
1600 /**
1601 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1602 *
1603 * If the temperature changed has changed sufficiently, then a recalibration
1604 * is needed.
1605 *
1606 * Assumes caller will replace priv->last_temperature once calibration
1607 * executed.
1608 */
1609 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
1610 {
1611 int temp_diff;
1612
1613 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1614 IWL_DEBUG_TEMP(priv, "Temperature not updated -- no statistics.\n");
1615 return 0;
1616 }
1617
1618 temp_diff = priv->temperature - priv->last_temperature;
1619
1620 /* get absolute value */
1621 if (temp_diff < 0) {
1622 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d, \n", temp_diff);
1623 temp_diff = -temp_diff;
1624 } else if (temp_diff == 0)
1625 IWL_DEBUG_POWER(priv, "Same temp, \n");
1626 else
1627 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d, \n", temp_diff);
1628
1629 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1630 IWL_DEBUG_POWER(priv, "Thermal txpower calib not needed\n");
1631 return 0;
1632 }
1633
1634 IWL_DEBUG_POWER(priv, "Thermal txpower calib needed\n");
1635
1636 return 1;
1637 }
1638
1639 static void iwl4965_temperature_calib(struct iwl_priv *priv)
1640 {
1641 s32 temp;
1642
1643 temp = iwl4965_hw_get_temperature(priv);
1644 if (temp < 0)
1645 return;
1646
1647 if (priv->temperature != temp) {
1648 if (priv->temperature)
1649 IWL_DEBUG_TEMP(priv, "Temperature changed "
1650 "from %dC to %dC\n",
1651 KELVIN_TO_CELSIUS(priv->temperature),
1652 KELVIN_TO_CELSIUS(temp));
1653 else
1654 IWL_DEBUG_TEMP(priv, "Temperature "
1655 "initialized to %dC\n",
1656 KELVIN_TO_CELSIUS(temp));
1657 }
1658
1659 priv->temperature = temp;
1660 iwl_tt_handler(priv);
1661 set_bit(STATUS_TEMPERATURE, &priv->status);
1662
1663 if (!priv->disable_tx_power_cal &&
1664 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1665 iwl4965_is_temp_calib_needed(priv))
1666 queue_work(priv->workqueue, &priv->txpower_work);
1667 }
1668
1669 /**
1670 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1671 */
1672 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
1673 u16 txq_id)
1674 {
1675 /* Simply stop the queue, but don't change any configuration;
1676 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1677 iwl_write_prph(priv,
1678 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1679 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1680 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1681 }
1682
1683 /**
1684 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
1685 * priv->lock must be held by the caller
1686 */
1687 static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1688 u16 ssn_idx, u8 tx_fifo)
1689 {
1690 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1691 (IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
1692 <= txq_id)) {
1693 IWL_WARN(priv,
1694 "queue number out of range: %d, must be %d to %d\n",
1695 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1696 IWL49_FIRST_AMPDU_QUEUE +
1697 priv->cfg->num_of_ampdu_queues - 1);
1698 return -EINVAL;
1699 }
1700
1701 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1702
1703 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1704
1705 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1706 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1707 /* supposes that ssn_idx is valid (!= 0xFFF) */
1708 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1709
1710 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1711 iwl_txq_ctx_deactivate(priv, txq_id);
1712 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1713
1714 return 0;
1715 }
1716
1717 /**
1718 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1719 */
1720 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
1721 u16 txq_id)
1722 {
1723 u32 tbl_dw_addr;
1724 u32 tbl_dw;
1725 u16 scd_q2ratid;
1726
1727 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1728
1729 tbl_dw_addr = priv->scd_base_addr +
1730 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1731
1732 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1733
1734 if (txq_id & 0x1)
1735 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1736 else
1737 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1738
1739 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1740
1741 return 0;
1742 }
1743
1744
1745 /**
1746 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1747 *
1748 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
1749 * i.e. it must be one of the higher queues used for aggregation
1750 */
1751 static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1752 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1753 {
1754 unsigned long flags;
1755 u16 ra_tid;
1756
1757 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1758 (IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
1759 <= txq_id)) {
1760 IWL_WARN(priv,
1761 "queue number out of range: %d, must be %d to %d\n",
1762 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1763 IWL49_FIRST_AMPDU_QUEUE +
1764 priv->cfg->num_of_ampdu_queues - 1);
1765 return -EINVAL;
1766 }
1767
1768 ra_tid = BUILD_RAxTID(sta_id, tid);
1769
1770 /* Modify device's station table to Tx this TID */
1771 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1772
1773 spin_lock_irqsave(&priv->lock, flags);
1774
1775 /* Stop this Tx queue before configuring it */
1776 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1777
1778 /* Map receiver-address / traffic-ID to this queue */
1779 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1780
1781 /* Set this queue as a chain-building queue */
1782 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1783
1784 /* Place first TFD at index corresponding to start sequence number.
1785 * Assumes that ssn_idx is valid (!= 0xFFF) */
1786 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1787 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1788 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1789
1790 /* Set up Tx window size and frame limit for this queue */
1791 iwl_write_targ_mem(priv,
1792 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1793 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1794 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1795
1796 iwl_write_targ_mem(priv, priv->scd_base_addr +
1797 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1798 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1799 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1800
1801 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1802
1803 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1804 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1805
1806 spin_unlock_irqrestore(&priv->lock, flags);
1807
1808 return 0;
1809 }
1810
1811
1812 static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1813 {
1814 switch (cmd_id) {
1815 case REPLY_RXON:
1816 return (u16) sizeof(struct iwl4965_rxon_cmd);
1817 default:
1818 return len;
1819 }
1820 }
1821
1822 static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1823 {
1824 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1825 addsta->mode = cmd->mode;
1826 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1827 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1828 addsta->station_flags = cmd->station_flags;
1829 addsta->station_flags_msk = cmd->station_flags_msk;
1830 addsta->tid_disable_tx = cmd->tid_disable_tx;
1831 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1832 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1833 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1834 addsta->sleep_tx_count = cmd->sleep_tx_count;
1835 addsta->reserved1 = cpu_to_le16(0);
1836 addsta->reserved2 = cpu_to_le16(0);
1837
1838 return (u16)sizeof(struct iwl4965_addsta_cmd);
1839 }
1840
1841 static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
1842 {
1843 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
1844 }
1845
1846 /**
1847 * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
1848 */
1849 static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
1850 struct iwl_ht_agg *agg,
1851 struct iwl4965_tx_resp *tx_resp,
1852 int txq_id, u16 start_idx)
1853 {
1854 u16 status;
1855 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
1856 struct ieee80211_tx_info *info = NULL;
1857 struct ieee80211_hdr *hdr = NULL;
1858 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1859 int i, sh, idx;
1860 u16 seq;
1861 if (agg->wait_for_ba)
1862 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1863
1864 agg->frame_count = tx_resp->frame_count;
1865 agg->start_idx = start_idx;
1866 agg->rate_n_flags = rate_n_flags;
1867 agg->bitmap = 0;
1868
1869 /* num frames attempted by Tx command */
1870 if (agg->frame_count == 1) {
1871 /* Only one frame was attempted; no block-ack will arrive */
1872 status = le16_to_cpu(frame_status[0].status);
1873 idx = start_idx;
1874
1875 /* FIXME: code repetition */
1876 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1877 agg->frame_count, agg->start_idx, idx);
1878
1879 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1880 info->status.rates[0].count = tx_resp->failure_frame + 1;
1881 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1882 info->flags |= iwl_tx_status_to_mac80211(status);
1883 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1884 /* FIXME: code repetition end */
1885
1886 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1887 status & 0xff, tx_resp->failure_frame);
1888 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1889
1890 agg->wait_for_ba = 0;
1891 } else {
1892 /* Two or more frames were attempted; expect block-ack */
1893 u64 bitmap = 0;
1894 int start = agg->start_idx;
1895
1896 /* Construct bit-map of pending frames within Tx window */
1897 for (i = 0; i < agg->frame_count; i++) {
1898 u16 sc;
1899 status = le16_to_cpu(frame_status[i].status);
1900 seq = le16_to_cpu(frame_status[i].sequence);
1901 idx = SEQ_TO_INDEX(seq);
1902 txq_id = SEQ_TO_QUEUE(seq);
1903
1904 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1905 AGG_TX_STATE_ABORT_MSK))
1906 continue;
1907
1908 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1909 agg->frame_count, txq_id, idx);
1910
1911 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1912 if (!hdr) {
1913 IWL_ERR(priv,
1914 "BUG_ON idx doesn't point to valid skb"
1915 " idx=%d, txq_id=%d\n", idx, txq_id);
1916 return -1;
1917 }
1918
1919 sc = le16_to_cpu(hdr->seq_ctrl);
1920 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1921 IWL_ERR(priv,
1922 "BUG_ON idx doesn't match seq control"
1923 " idx=%d, seq_idx=%d, seq=%d\n",
1924 idx, SEQ_TO_SN(sc), hdr->seq_ctrl);
1925 return -1;
1926 }
1927
1928 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1929 i, idx, SEQ_TO_SN(sc));
1930
1931 sh = idx - start;
1932 if (sh > 64) {
1933 sh = (start - idx) + 0xff;
1934 bitmap = bitmap << sh;
1935 sh = 0;
1936 start = idx;
1937 } else if (sh < -64)
1938 sh = 0xff - (start - idx);
1939 else if (sh < 0) {
1940 sh = start - idx;
1941 start = idx;
1942 bitmap = bitmap << sh;
1943 sh = 0;
1944 }
1945 bitmap |= 1ULL << sh;
1946 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1947 start, (unsigned long long)bitmap);
1948 }
1949
1950 agg->bitmap = bitmap;
1951 agg->start_idx = start;
1952 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1953 agg->frame_count, agg->start_idx,
1954 (unsigned long long)agg->bitmap);
1955
1956 if (bitmap)
1957 agg->wait_for_ba = 1;
1958 }
1959 return 0;
1960 }
1961
1962 /**
1963 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
1964 */
1965 static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
1966 struct iwl_rx_mem_buffer *rxb)
1967 {
1968 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1969 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1970 int txq_id = SEQ_TO_QUEUE(sequence);
1971 int index = SEQ_TO_INDEX(sequence);
1972 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1973 struct ieee80211_hdr *hdr;
1974 struct ieee80211_tx_info *info;
1975 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1976 u32 status = le32_to_cpu(tx_resp->u.status);
1977 int uninitialized_var(tid);
1978 int sta_id;
1979 int freed;
1980 u8 *qc = NULL;
1981
1982 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1983 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1984 "is out of range [0-%d] %d %d\n", txq_id,
1985 index, txq->q.n_bd, txq->q.write_ptr,
1986 txq->q.read_ptr);
1987 return;
1988 }
1989
1990 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1991 memset(&info->status, 0, sizeof(info->status));
1992
1993 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
1994 if (ieee80211_is_data_qos(hdr->frame_control)) {
1995 qc = ieee80211_get_qos_ctl(hdr);
1996 tid = qc[0] & 0xf;
1997 }
1998
1999 sta_id = iwl_get_ra_sta_id(priv, hdr);
2000 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2001 IWL_ERR(priv, "Station not known\n");
2002 return;
2003 }
2004
2005 if (txq->sched_retry) {
2006 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2007 struct iwl_ht_agg *agg = NULL;
2008
2009 WARN_ON(!qc);
2010
2011 agg = &priv->stations[sta_id].tid[tid].agg;
2012
2013 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
2014
2015 /* check if BAR is needed */
2016 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2017 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2018
2019 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2020 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2021 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
2022 "%d index %d\n", scd_ssn , index);
2023 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2024 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
2025
2026 if (priv->mac80211_registered &&
2027 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2028 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
2029 if (agg->state == IWL_AGG_OFF)
2030 iwl_wake_queue(priv, txq_id);
2031 else
2032 iwl_wake_queue(priv, txq->swq_id);
2033 }
2034 }
2035 } else {
2036 info->status.rates[0].count = tx_resp->failure_frame + 1;
2037 info->flags |= iwl_tx_status_to_mac80211(status);
2038 iwl_hwrate_to_tx_control(priv,
2039 le32_to_cpu(tx_resp->rate_n_flags),
2040 info);
2041
2042 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) "
2043 "rate_n_flags 0x%x retries %d\n",
2044 txq_id,
2045 iwl_get_tx_fail_reason(status), status,
2046 le32_to_cpu(tx_resp->rate_n_flags),
2047 tx_resp->failure_frame);
2048
2049 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2050 if (qc && likely(sta_id != IWL_INVALID_STATION))
2051 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2052
2053 if (priv->mac80211_registered &&
2054 (iwl_queue_space(&txq->q) > txq->q.low_mark))
2055 iwl_wake_queue(priv, txq_id);
2056 }
2057
2058 if (qc && likely(sta_id != IWL_INVALID_STATION))
2059 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
2060
2061 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2062 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
2063 }
2064
2065 static int iwl4965_calc_rssi(struct iwl_priv *priv,
2066 struct iwl_rx_phy_res *rx_resp)
2067 {
2068 /* data from PHY/DSP regarding signal strength, etc.,
2069 * contents are always there, not configurable by host. */
2070 struct iwl4965_rx_non_cfg_phy *ncphy =
2071 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2072 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2073 >> IWL49_AGC_DB_POS;
2074
2075 u32 valid_antennae =
2076 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2077 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2078 u8 max_rssi = 0;
2079 u32 i;
2080
2081 /* Find max rssi among 3 possible receivers.
2082 * These values are measured by the digital signal processor (DSP).
2083 * They should stay fairly constant even as the signal strength varies,
2084 * if the radio's automatic gain control (AGC) is working right.
2085 * AGC value (see below) will provide the "interesting" info. */
2086 for (i = 0; i < 3; i++)
2087 if (valid_antennae & (1 << i))
2088 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2089
2090 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2091 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2092 max_rssi, agc);
2093
2094 /* dBm = max_rssi dB - agc dB - constant.
2095 * Higher AGC (higher radio gain) means lower signal. */
2096 return max_rssi - agc - IWL49_RSSI_OFFSET;
2097 }
2098
2099
2100 /* Set up 4965-specific Rx frame reply handlers */
2101 static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
2102 {
2103 /* Legacy Rx frames */
2104 priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
2105 /* Tx response */
2106 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
2107 }
2108
2109 static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
2110 {
2111 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
2112 }
2113
2114 static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
2115 {
2116 cancel_work_sync(&priv->txpower_work);
2117 }
2118
2119 #define IWL4965_UCODE_GET(item) \
2120 static u32 iwl4965_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2121 u32 api_ver) \
2122 { \
2123 return le32_to_cpu(ucode->u.v1.item); \
2124 }
2125
2126 static u32 iwl4965_ucode_get_header_size(u32 api_ver)
2127 {
2128 return UCODE_HEADER_SIZE(1);
2129 }
2130 static u32 iwl4965_ucode_get_build(const struct iwl_ucode_header *ucode,
2131 u32 api_ver)
2132 {
2133 return 0;
2134 }
2135 static u8 *iwl4965_ucode_get_data(const struct iwl_ucode_header *ucode,
2136 u32 api_ver)
2137 {
2138 return (u8 *) ucode->u.v1.data;
2139 }
2140
2141 IWL4965_UCODE_GET(inst_size);
2142 IWL4965_UCODE_GET(data_size);
2143 IWL4965_UCODE_GET(init_size);
2144 IWL4965_UCODE_GET(init_data_size);
2145 IWL4965_UCODE_GET(boot_size);
2146
2147 static struct iwl_hcmd_ops iwl4965_hcmd = {
2148 .rxon_assoc = iwl4965_send_rxon_assoc,
2149 .commit_rxon = iwl_commit_rxon,
2150 .set_rxon_chain = iwl_set_rxon_chain,
2151 };
2152
2153 static struct iwl_ucode_ops iwl4965_ucode = {
2154 .get_header_size = iwl4965_ucode_get_header_size,
2155 .get_build = iwl4965_ucode_get_build,
2156 .get_inst_size = iwl4965_ucode_get_inst_size,
2157 .get_data_size = iwl4965_ucode_get_data_size,
2158 .get_init_size = iwl4965_ucode_get_init_size,
2159 .get_init_data_size = iwl4965_ucode_get_init_data_size,
2160 .get_boot_size = iwl4965_ucode_get_boot_size,
2161 .get_data = iwl4965_ucode_get_data,
2162 };
2163 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
2164 .get_hcmd_size = iwl4965_get_hcmd_size,
2165 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
2166 .chain_noise_reset = iwl4965_chain_noise_reset,
2167 .gain_computation = iwl4965_gain_computation,
2168 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2169 .calc_rssi = iwl4965_calc_rssi,
2170 };
2171
2172 static struct iwl_lib_ops iwl4965_lib = {
2173 .set_hw_params = iwl4965_hw_set_hw_params,
2174 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
2175 .txq_set_sched = iwl4965_txq_set_sched,
2176 .txq_agg_enable = iwl4965_txq_agg_enable,
2177 .txq_agg_disable = iwl4965_txq_agg_disable,
2178 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
2179 .txq_free_tfd = iwl_hw_txq_free_tfd,
2180 .txq_init = iwl_hw_tx_queue_init,
2181 .rx_handler_setup = iwl4965_rx_handler_setup,
2182 .setup_deferred_work = iwl4965_setup_deferred_work,
2183 .cancel_deferred_work = iwl4965_cancel_deferred_work,
2184 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2185 .alive_notify = iwl4965_alive_notify,
2186 .init_alive_start = iwl4965_init_alive_start,
2187 .load_ucode = iwl4965_load_bsm,
2188 .dump_nic_event_log = iwl_dump_nic_event_log,
2189 .dump_nic_error_log = iwl_dump_nic_error_log,
2190 .dump_fh = iwl_dump_fh,
2191 .set_channel_switch = iwl4965_hw_channel_switch,
2192 .apm_ops = {
2193 .init = iwl_apm_init,
2194 .stop = iwl_apm_stop,
2195 .config = iwl4965_nic_config,
2196 .set_pwr_src = iwl_set_pwr_src,
2197 },
2198 .eeprom_ops = {
2199 .regulatory_bands = {
2200 EEPROM_REGULATORY_BAND_1_CHANNELS,
2201 EEPROM_REGULATORY_BAND_2_CHANNELS,
2202 EEPROM_REGULATORY_BAND_3_CHANNELS,
2203 EEPROM_REGULATORY_BAND_4_CHANNELS,
2204 EEPROM_REGULATORY_BAND_5_CHANNELS,
2205 EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS,
2206 EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS
2207 },
2208 .verify_signature = iwlcore_eeprom_verify_signature,
2209 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2210 .release_semaphore = iwlcore_eeprom_release_semaphore,
2211 .calib_version = iwl4965_eeprom_calib_version,
2212 .query_addr = iwlcore_eeprom_query_addr,
2213 },
2214 .send_tx_power = iwl4965_send_tx_power,
2215 .update_chain_flags = iwl_update_chain_flags,
2216 .post_associate = iwl_post_associate,
2217 .config_ap = iwl_config_ap,
2218 .isr = iwl_isr_legacy,
2219 .temp_ops = {
2220 .temperature = iwl4965_temperature_calib,
2221 .set_ct_kill = iwl4965_set_ct_threshold,
2222 },
2223 .add_bcast_station = iwl_add_bcast_station,
2224 };
2225
2226 static const struct iwl_ops iwl4965_ops = {
2227 .ucode = &iwl4965_ucode,
2228 .lib = &iwl4965_lib,
2229 .hcmd = &iwl4965_hcmd,
2230 .utils = &iwl4965_hcmd_utils,
2231 .led = &iwlagn_led_ops,
2232 };
2233
2234 struct iwl_cfg iwl4965_agn_cfg = {
2235 .name = "Intel(R) Wireless WiFi Link 4965AGN",
2236 .fw_name_pre = IWL4965_FW_PRE,
2237 .ucode_api_max = IWL4965_UCODE_API_MAX,
2238 .ucode_api_min = IWL4965_UCODE_API_MIN,
2239 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
2240 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
2241 .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2242 .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
2243 .ops = &iwl4965_ops,
2244 .num_of_queues = IWL49_NUM_QUEUES,
2245 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
2246 .mod_params = &iwl4965_mod_params,
2247 .valid_tx_ant = ANT_AB,
2248 .valid_rx_ant = ANT_ABC,
2249 .pll_cfg_val = 0,
2250 .set_l0s = true,
2251 .use_bsm = true,
2252 .use_isr_legacy = true,
2253 .ht_greenfield_support = false,
2254 .broken_powersave = true,
2255 .led_compensation = 61,
2256 .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS,
2257 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2258 };
2259
2260 /* Module firmware */
2261 MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX));
2262
2263 module_param_named(antenna, iwl4965_mod_params.antenna, int, S_IRUGO);
2264 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2265 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, S_IRUGO);
2266 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
2267 module_param_named(
2268 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, S_IRUGO);
2269 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2270
2271 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, S_IRUGO);
2272 MODULE_PARM_DESC(queues_num, "number of hw queues.");
2273 /* 11n */
2274 module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, S_IRUGO);
2275 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
2276 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K,
2277 int, S_IRUGO);
2278 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
2279
2280 module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, S_IRUGO);
2281 MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
(deprecated) Btrfs devel tree