drivers/cpufreq/exynos4x12-cpufreq.c

   1 /*
   2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4X12 - CPU frequency scaling support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17 #include <linux/slab.h>
  18 #include <linux/cpufreq.h>
  19
  20 #include "exynos-cpufreq.h"
  21
  22 static struct clk *cpu_clk;
  23 static struct clk *moutcore;
  24 static struct clk *mout_mpll;
  25 static struct clk *mout_apll;
  26
  27 static unsigned int exynos4x12_volt_table[] = {
  28         1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
  29         1000000,  987500,  975000,  950000,  925000,  900000,  900000
  30 };
  31
  32 static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
  33         {CPUFREQ_BOOST_FREQ, 1500 * 1000},
  34         {L1, 1400 * 1000},
  35         {L2, 1300 * 1000},
  36         {L3, 1200 * 1000},
  37         {L4, 1100 * 1000},
  38         {L5, 1000 * 1000},
  39         {L6,  900 * 1000},
  40         {L7,  800 * 1000},
  41         {L8,  700 * 1000},
  42         {L9,  600 * 1000},
  43         {L10, 500 * 1000},
  44         {L11, 400 * 1000},
  45         {L12, 300 * 1000},
  46         {L13, 200 * 1000},
  47         {0, CPUFREQ_TABLE_END},
  48 };
  49
  50 static struct apll_freq *apll_freq_4x12;
  51
  52 static struct apll_freq apll_freq_4212[] = {
  53         /*
  54          * values:
  55          * freq
  56          * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
  57          * clock divider for COPY, HPM, RESERVED
  58          * PLL M, P, S
  59          */
  60         APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
  61         APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
  62         APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
  63         APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
  64         APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
  65         APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
  66         APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
  67         APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
  68         APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
  69         APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
  70         APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
  71         APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
  72         APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
  73         APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
  74 };
  75
  76 static struct apll_freq apll_freq_4412[] = {
  77         /*
  78          * values:
  79          * freq
  80          * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
  81          * clock divider for COPY, HPM, CORES
  82          * PLL M, P, S
  83          */
  84         APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
  85         APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
  86         APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
  87         APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
  88         APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
  89         APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
  90         APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
  91         APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
  92         APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
  93         APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
  94         APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
  95         APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
  96         APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
  97         APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
  98 };
  99
 100 static void exynos4x12_set_clkdiv(unsigned int div_index)
 101 {
 102         unsigned int tmp;
 103         unsigned int stat_cpu1;
 104
 105         /* Change Divider - CPU0 */
 106
 107         tmp = apll_freq_4x12[div_index].clk_div_cpu0;
 108
 109         __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
 110
 111         while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
 112                 cpu_relax();
 113
 114         /* Change Divider - CPU1 */
 115         tmp = apll_freq_4x12[div_index].clk_div_cpu1;
 116
 117         __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
 118         if (soc_is_exynos4212())
 119                 stat_cpu1 = 0x11;
 120         else
 121                 stat_cpu1 = 0x111;
 122
 123         while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
 124                 cpu_relax();
 125 }
 126
 127 static void exynos4x12_set_apll(unsigned int index)
 128 {
 129         unsigned int tmp, freq = apll_freq_4x12[index].freq;
 130
 131         /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
 132         clk_set_parent(moutcore, mout_mpll);
 133
 134         do {
 135                 cpu_relax();
 136                 tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
 137                         >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 138                 tmp &= 0x7;
 139         } while (tmp != 0x2);
 140
 141         clk_set_rate(mout_apll, freq * 1000);
 142
 143         /* MUX_CORE_SEL = APLL */
 144         clk_set_parent(moutcore, mout_apll);
 145
 146         do {
 147                 cpu_relax();
 148                 tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
 149                 tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 150         } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 151 }
 152
 153 static void exynos4x12_set_frequency(unsigned int old_index,
 154                                   unsigned int new_index)
 155 {
 156         if (old_index > new_index) {
 157                 exynos4x12_set_clkdiv(new_index);
 158                 exynos4x12_set_apll(new_index);
 159         } else if (old_index < new_index) {
 160                 exynos4x12_set_apll(new_index);
 161                 exynos4x12_set_clkdiv(new_index);
 162         }
 163 }
 164
 165 int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 166 {
 167         unsigned long rate;
 168
 169         cpu_clk = clk_get(NULL, "armclk");
 170         if (IS_ERR(cpu_clk))
 171                 return PTR_ERR(cpu_clk);
 172
 173         moutcore = clk_get(NULL, "moutcore");
 174         if (IS_ERR(moutcore))
 175                 goto err_moutcore;
 176
 177         mout_mpll = clk_get(NULL, "mout_mpll");
 178         if (IS_ERR(mout_mpll))
 179                 goto err_mout_mpll;
 180
 181         rate = clk_get_rate(mout_mpll) / 1000;
 182
 183         mout_apll = clk_get(NULL, "mout_apll");
 184         if (IS_ERR(mout_apll))
 185                 goto err_mout_apll;
 186
 187         if (soc_is_exynos4212())
 188                 apll_freq_4x12 = apll_freq_4212;
 189         else
 190                 apll_freq_4x12 = apll_freq_4412;
 191
 192         info->mpll_freq_khz = rate;
 193         /* 800Mhz */
 194         info->pll_safe_idx = L7;
 195         info->cpu_clk = cpu_clk;
 196         info->volt_table = exynos4x12_volt_table;
 197         info->freq_table = exynos4x12_freq_table;
 198         info->set_freq = exynos4x12_set_frequency;
 199
 200         return 0;
 201
 202 err_mout_apll:
 203         clk_put(mout_mpll);
 204 err_mout_mpll:
 205         clk_put(moutcore);
 206 err_moutcore:
 207         clk_put(cpu_clk);
 208
 209         pr_debug("%s: failed initialization\n", __func__);
 210         return -EINVAL;
 211 }