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[SCSI] be2iscsi: Alloc only one EQ if intr mode
[linux-2.6/btrfs-unstable.git] / drivers / pci / probe.c
blob2a943090a3b7838b3a8fcb86a9caa89dfe611133
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include <acpi/acpi_hest.h>
14 #include "pci.h"
15
16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17 #define CARDBUS_RESERVE_BUSNR 3
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23
24 static int find_anything(struct device *dev, void *data)
25 {
26 return 1;
27 }
28
29 /*
30 * Some device drivers need know if pci is initiated.
31 * Basically, we think pci is not initiated when there
32 * is no device to be found on the pci_bus_type.
33 */
34 int no_pci_devices(void)
35 {
36 struct device *dev;
37 int no_devices;
38
39 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
40 no_devices = (dev == NULL);
41 put_device(dev);
42 return no_devices;
43 }
44 EXPORT_SYMBOL(no_pci_devices);
45
46 /*
47 * PCI Bus Class Devices
48 */
49 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
50 int type,
51 struct device_attribute *attr,
52 char *buf)
53 {
54 int ret;
55 const struct cpumask *cpumask;
56
57 cpumask = cpumask_of_pcibus(to_pci_bus(dev));
58 ret = type?
59 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
60 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
61 buf[ret++] = '\n';
62 buf[ret] = '\0';
63 return ret;
64 }
65
66 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
67 struct device_attribute *attr,
68 char *buf)
69 {
70 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
71 }
72
73 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
74 struct device_attribute *attr,
75 char *buf)
76 {
77 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
78 }
79
80 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
81 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
82
83 /*
84 * PCI Bus Class
85 */
86 static void release_pcibus_dev(struct device *dev)
87 {
88 struct pci_bus *pci_bus = to_pci_bus(dev);
89
90 if (pci_bus->bridge)
91 put_device(pci_bus->bridge);
92 pci_bus_remove_resources(pci_bus);
93 kfree(pci_bus);
94 }
95
96 static struct class pcibus_class = {
97 .name = "pci_bus",
98 .dev_release = &release_pcibus_dev,
99 };
100
101 static int __init pcibus_class_init(void)
102 {
103 return class_register(&pcibus_class);
104 }
105 postcore_initcall(pcibus_class_init);
106
107 /*
108 * Translate the low bits of the PCI base
109 * to the resource type
110 */
111 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
112 {
113 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
114 return IORESOURCE_IO;
115
116 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
117 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
118
119 return IORESOURCE_MEM;
120 }
121
122 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
123 {
124 u64 size = mask & maxbase; /* Find the significant bits */
125 if (!size)
126 return 0;
127
128 /* Get the lowest of them to find the decode size, and
129 from that the extent. */
130 size = (size & ~(size-1)) - 1;
131
132 /* base == maxbase can be valid only if the BAR has
133 already been programmed with all 1s. */
134 if (base == maxbase && ((base | size) & mask) != mask)
135 return 0;
136
137 return size;
138 }
139
140 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
141 {
142 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
143 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
144 return pci_bar_io;
145 }
146
147 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
148
149 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
150 return pci_bar_mem64;
151 return pci_bar_mem32;
152 }
153
154 /**
155 * pci_read_base - read a PCI BAR
156 * @dev: the PCI device
157 * @type: type of the BAR
158 * @res: resource buffer to be filled in
159 * @pos: BAR position in the config space
160 *
161 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
162 */
163 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
164 struct resource *res, unsigned int pos)
165 {
166 u32 l, sz, mask;
167
168 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
169
170 res->name = pci_name(dev);
171
172 pci_read_config_dword(dev, pos, &l);
173 pci_write_config_dword(dev, pos, l | mask);
174 pci_read_config_dword(dev, pos, &sz);
175 pci_write_config_dword(dev, pos, l);
176
177 /*
178 * All bits set in sz means the device isn't working properly.
179 * If the BAR isn't implemented, all bits must be 0. If it's a
180 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
181 * 1 must be clear.
182 */
183 if (!sz || sz == 0xffffffff)
184 goto fail;
185
186 /*
187 * I don't know how l can have all bits set. Copied from old code.
188 * Maybe it fixes a bug on some ancient platform.
189 */
190 if (l == 0xffffffff)
191 l = 0;
192
193 if (type == pci_bar_unknown) {
194 type = decode_bar(res, l);
195 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
196 if (type == pci_bar_io) {
197 l &= PCI_BASE_ADDRESS_IO_MASK;
198 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
199 } else {
200 l &= PCI_BASE_ADDRESS_MEM_MASK;
201 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
202 }
203 } else {
204 res->flags |= (l & IORESOURCE_ROM_ENABLE);
205 l &= PCI_ROM_ADDRESS_MASK;
206 mask = (u32)PCI_ROM_ADDRESS_MASK;
207 }
208
209 if (type == pci_bar_mem64) {
210 u64 l64 = l;
211 u64 sz64 = sz;
212 u64 mask64 = mask | (u64)~0 << 32;
213
214 pci_read_config_dword(dev, pos + 4, &l);
215 pci_write_config_dword(dev, pos + 4, ~0);
216 pci_read_config_dword(dev, pos + 4, &sz);
217 pci_write_config_dword(dev, pos + 4, l);
218
219 l64 |= ((u64)l << 32);
220 sz64 |= ((u64)sz << 32);
221
222 sz64 = pci_size(l64, sz64, mask64);
223
224 if (!sz64)
225 goto fail;
226
227 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
228 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
229 pos);
230 goto fail;
231 }
232
233 res->flags |= IORESOURCE_MEM_64;
234 if ((sizeof(resource_size_t) < 8) && l) {
235 /* Address above 32-bit boundary; disable the BAR */
236 pci_write_config_dword(dev, pos, 0);
237 pci_write_config_dword(dev, pos + 4, 0);
238 res->start = 0;
239 res->end = sz64;
240 } else {
241 res->start = l64;
242 res->end = l64 + sz64;
243 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
244 pos, res);
245 }
246 } else {
247 sz = pci_size(l, sz, mask);
248
249 if (!sz)
250 goto fail;
251
252 res->start = l;
253 res->end = l + sz;
254
255 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
256 }
257
258 out:
259 return (type == pci_bar_mem64) ? 1 : 0;
260 fail:
261 res->flags = 0;
262 goto out;
263 }
264
265 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
266 {
267 unsigned int pos, reg;
268
269 for (pos = 0; pos < howmany; pos++) {
270 struct resource *res = &dev->resource[pos];
271 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
272 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
273 }
274
275 if (rom) {
276 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
277 dev->rom_base_reg = rom;
278 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
279 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
280 IORESOURCE_SIZEALIGN;
281 __pci_read_base(dev, pci_bar_mem32, res, rom);
282 }
283 }
284
285 static void __devinit pci_read_bridge_io(struct pci_bus *child)
286 {
287 struct pci_dev *dev = child->self;
288 u8 io_base_lo, io_limit_lo;
289 unsigned long base, limit;
290 struct resource *res;
291
292 res = child->resource[0];
293 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
294 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
295 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
296 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
297
298 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
299 u16 io_base_hi, io_limit_hi;
300 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
301 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
302 base |= (io_base_hi << 16);
303 limit |= (io_limit_hi << 16);
304 }
305
306 if (base && base <= limit) {
307 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
308 if (!res->start)
309 res->start = base;
310 if (!res->end)
311 res->end = limit + 0xfff;
312 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
313 } else {
314 dev_printk(KERN_DEBUG, &dev->dev,
315 " bridge window [io %04lx - %04lx] reg reading\n",
316 base, limit);
317 }
318 }
319
320 static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
321 {
322 struct pci_dev *dev = child->self;
323 u16 mem_base_lo, mem_limit_lo;
324 unsigned long base, limit;
325 struct resource *res;
326
327 res = child->resource[1];
328 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
329 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
330 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
331 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
332 if (base && base <= limit) {
333 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
334 res->start = base;
335 res->end = limit + 0xfffff;
336 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
337 } else {
338 dev_printk(KERN_DEBUG, &dev->dev,
339 " bridge window [mem 0x%08lx - 0x%08lx] reg reading\n",
340 base, limit + 0xfffff);
341 }
342 }
343
344 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
345 {
346 struct pci_dev *dev = child->self;
347 u16 mem_base_lo, mem_limit_lo;
348 unsigned long base, limit;
349 struct resource *res;
350
351 res = child->resource[2];
352 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
353 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
354 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
355 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
356
357 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
358 u32 mem_base_hi, mem_limit_hi;
359 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
360 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
361
362 /*
363 * Some bridges set the base > limit by default, and some
364 * (broken) BIOSes do not initialize them. If we find
365 * this, just assume they are not being used.
366 */
367 if (mem_base_hi <= mem_limit_hi) {
368 #if BITS_PER_LONG == 64
369 base |= ((long) mem_base_hi) << 32;
370 limit |= ((long) mem_limit_hi) << 32;
371 #else
372 if (mem_base_hi || mem_limit_hi) {
373 dev_err(&dev->dev, "can't handle 64-bit "
374 "address space for bridge\n");
375 return;
376 }
377 #endif
378 }
379 }
380 if (base && base <= limit) {
381 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
382 IORESOURCE_MEM | IORESOURCE_PREFETCH;
383 if (res->flags & PCI_PREF_RANGE_TYPE_64)
384 res->flags |= IORESOURCE_MEM_64;
385 res->start = base;
386 res->end = limit + 0xfffff;
387 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
388 } else {
389 dev_printk(KERN_DEBUG, &dev->dev,
390 " bridge window [mem 0x%08lx - %08lx pref] reg reading\n",
391 base, limit + 0xfffff);
392 }
393 }
394
395 void __devinit pci_read_bridge_bases(struct pci_bus *child)
396 {
397 struct pci_dev *dev = child->self;
398 struct resource *res;
399 int i;
400
401 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
402 return;
403
404 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
405 child->secondary, child->subordinate,
406 dev->transparent ? " (subtractive decode)" : "");
407
408 pci_bus_remove_resources(child);
409 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
410 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
411
412 pci_read_bridge_io(child);
413 pci_read_bridge_mmio(child);
414 pci_read_bridge_mmio_pref(child);
415
416 if (dev->transparent) {
417 pci_bus_for_each_resource(child->parent, res, i) {
418 if (res) {
419 pci_bus_add_resource(child, res,
420 PCI_SUBTRACTIVE_DECODE);
421 dev_printk(KERN_DEBUG, &dev->dev,
422 " bridge window %pR (subtractive decode)\n",
423 res);
424 }
425 }
426 }
427 }
428
429 static struct pci_bus * pci_alloc_bus(void)
430 {
431 struct pci_bus *b;
432
433 b = kzalloc(sizeof(*b), GFP_KERNEL);
434 if (b) {
435 INIT_LIST_HEAD(&b->node);
436 INIT_LIST_HEAD(&b->children);
437 INIT_LIST_HEAD(&b->devices);
438 INIT_LIST_HEAD(&b->slots);
439 INIT_LIST_HEAD(&b->resources);
440 b->max_bus_speed = PCI_SPEED_UNKNOWN;
441 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
442 }
443 return b;
444 }
445
446 static unsigned char pcix_bus_speed[] = {
447 PCI_SPEED_UNKNOWN, /* 0 */
448 PCI_SPEED_66MHz_PCIX, /* 1 */
449 PCI_SPEED_100MHz_PCIX, /* 2 */
450 PCI_SPEED_133MHz_PCIX, /* 3 */
451 PCI_SPEED_UNKNOWN, /* 4 */
452 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
453 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
454 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
455 PCI_SPEED_UNKNOWN, /* 8 */
456 PCI_SPEED_66MHz_PCIX_266, /* 9 */
457 PCI_SPEED_100MHz_PCIX_266, /* A */
458 PCI_SPEED_133MHz_PCIX_266, /* B */
459 PCI_SPEED_UNKNOWN, /* C */
460 PCI_SPEED_66MHz_PCIX_533, /* D */
461 PCI_SPEED_100MHz_PCIX_533, /* E */
462 PCI_SPEED_133MHz_PCIX_533 /* F */
463 };
464
465 static unsigned char pcie_link_speed[] = {
466 PCI_SPEED_UNKNOWN, /* 0 */
467 PCIE_SPEED_2_5GT, /* 1 */
468 PCIE_SPEED_5_0GT, /* 2 */
469 PCIE_SPEED_8_0GT, /* 3 */
470 PCI_SPEED_UNKNOWN, /* 4 */
471 PCI_SPEED_UNKNOWN, /* 5 */
472 PCI_SPEED_UNKNOWN, /* 6 */
473 PCI_SPEED_UNKNOWN, /* 7 */
474 PCI_SPEED_UNKNOWN, /* 8 */
475 PCI_SPEED_UNKNOWN, /* 9 */
476 PCI_SPEED_UNKNOWN, /* A */
477 PCI_SPEED_UNKNOWN, /* B */
478 PCI_SPEED_UNKNOWN, /* C */
479 PCI_SPEED_UNKNOWN, /* D */
480 PCI_SPEED_UNKNOWN, /* E */
481 PCI_SPEED_UNKNOWN /* F */
482 };
483
484 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
485 {
486 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
487 }
488 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
489
490 static unsigned char agp_speeds[] = {
491 AGP_UNKNOWN,
492 AGP_1X,
493 AGP_2X,
494 AGP_4X,
495 AGP_8X
496 };
497
498 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
499 {
500 int index = 0;
501
502 if (agpstat & 4)
503 index = 3;
504 else if (agpstat & 2)
505 index = 2;
506 else if (agpstat & 1)
507 index = 1;
508 else
509 goto out;
510
511 if (agp3) {
512 index += 2;
513 if (index == 5)
514 index = 0;
515 }
516
517 out:
518 return agp_speeds[index];
519 }
520
521
522 static void pci_set_bus_speed(struct pci_bus *bus)
523 {
524 struct pci_dev *bridge = bus->self;
525 int pos;
526
527 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
528 if (!pos)
529 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
530 if (pos) {
531 u32 agpstat, agpcmd;
532
533 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
534 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
535
536 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
537 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
538 }
539
540 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
541 if (pos) {
542 u16 status;
543 enum pci_bus_speed max;
544 pci_read_config_word(bridge, pos + 2, &status);
545
546 if (status & 0x8000) {
547 max = PCI_SPEED_133MHz_PCIX_533;
548 } else if (status & 0x4000) {
549 max = PCI_SPEED_133MHz_PCIX_266;
550 } else if (status & 0x0002) {
551 if (((status >> 12) & 0x3) == 2) {
552 max = PCI_SPEED_133MHz_PCIX_ECC;
553 } else {
554 max = PCI_SPEED_133MHz_PCIX;
555 }
556 } else {
557 max = PCI_SPEED_66MHz_PCIX;
558 }
559
560 bus->max_bus_speed = max;
561 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
562
563 return;
564 }
565
566 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
567 if (pos) {
568 u32 linkcap;
569 u16 linksta;
570
571 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
572 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
573
574 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
575 pcie_update_link_speed(bus, linksta);
576 }
577 }
578
579
580 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
581 struct pci_dev *bridge, int busnr)
582 {
583 struct pci_bus *child;
584 int i;
585
586 /*
587 * Allocate a new bus, and inherit stuff from the parent..
588 */
589 child = pci_alloc_bus();
590 if (!child)
591 return NULL;
592
593 child->parent = parent;
594 child->ops = parent->ops;
595 child->sysdata = parent->sysdata;
596 child->bus_flags = parent->bus_flags;
597
598 /* initialize some portions of the bus device, but don't register it
599 * now as the parent is not properly set up yet. This device will get
600 * registered later in pci_bus_add_devices()
601 */
602 child->dev.class = &pcibus_class;
603 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
604
605 /*
606 * Set up the primary, secondary and subordinate
607 * bus numbers.
608 */
609 child->number = child->secondary = busnr;
610 child->primary = parent->secondary;
611 child->subordinate = 0xff;
612
613 if (!bridge)
614 return child;
615
616 child->self = bridge;
617 child->bridge = get_device(&bridge->dev);
618
619 pci_set_bus_speed(child);
620
621 /* Set up default resource pointers and names.. */
622 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
623 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
624 child->resource[i]->name = child->name;
625 }
626 bridge->subordinate = child;
627
628 return child;
629 }
630
631 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
632 {
633 struct pci_bus *child;
634
635 child = pci_alloc_child_bus(parent, dev, busnr);
636 if (child) {
637 down_write(&pci_bus_sem);
638 list_add_tail(&child->node, &parent->children);
639 up_write(&pci_bus_sem);
640 }
641 return child;
642 }
643
644 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
645 {
646 struct pci_bus *parent = child->parent;
647
648 /* Attempts to fix that up are really dangerous unless
649 we're going to re-assign all bus numbers. */
650 if (!pcibios_assign_all_busses())
651 return;
652
653 while (parent->parent && parent->subordinate < max) {
654 parent->subordinate = max;
655 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
656 parent = parent->parent;
657 }
658 }
659
660 /*
661 * If it's a bridge, configure it and scan the bus behind it.
662 * For CardBus bridges, we don't scan behind as the devices will
663 * be handled by the bridge driver itself.
664 *
665 * We need to process bridges in two passes -- first we scan those
666 * already configured by the BIOS and after we are done with all of
667 * them, we proceed to assigning numbers to the remaining buses in
668 * order to avoid overlaps between old and new bus numbers.
669 */
670 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
671 {
672 struct pci_bus *child;
673 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
674 u32 buses, i, j = 0;
675 u16 bctl;
676 int broken = 0;
677
678 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
679
680 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
681 buses & 0xffffff, pass);
682
683 /* Check if setup is sensible at all */
684 if (!pass &&
685 ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) {
686 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
687 broken = 1;
688 }
689
690 /* Disable MasterAbortMode during probing to avoid reporting
691 of bus errors (in some architectures) */
692 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
693 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
694 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
695
696 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) {
697 unsigned int cmax, busnr;
698 /*
699 * Bus already configured by firmware, process it in the first
700 * pass and just note the configuration.
701 */
702 if (pass)
703 goto out;
704 busnr = (buses >> 8) & 0xFF;
705
706 /*
707 * If we already got to this bus through a different bridge,
708 * don't re-add it. This can happen with the i450NX chipset.
709 *
710 * However, we continue to descend down the hierarchy and
711 * scan remaining child buses.
712 */
713 child = pci_find_bus(pci_domain_nr(bus), busnr);
714 if (!child) {
715 child = pci_add_new_bus(bus, dev, busnr);
716 if (!child)
717 goto out;
718 child->primary = buses & 0xFF;
719 child->subordinate = (buses >> 16) & 0xFF;
720 child->bridge_ctl = bctl;
721 }
722
723 cmax = pci_scan_child_bus(child);
724 if (cmax > max)
725 max = cmax;
726 if (child->subordinate > max)
727 max = child->subordinate;
728 } else {
729 /*
730 * We need to assign a number to this bus which we always
731 * do in the second pass.
732 */
733 if (!pass) {
734 if (pcibios_assign_all_busses() || broken)
735 /* Temporarily disable forwarding of the
736 configuration cycles on all bridges in
737 this bus segment to avoid possible
738 conflicts in the second pass between two
739 bridges programmed with overlapping
740 bus ranges. */
741 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
742 buses & ~0xffffff);
743 goto out;
744 }
745
746 /* Clear errors */
747 pci_write_config_word(dev, PCI_STATUS, 0xffff);
748
749 /* Prevent assigning a bus number that already exists.
750 * This can happen when a bridge is hot-plugged */
751 if (pci_find_bus(pci_domain_nr(bus), max+1))
752 goto out;
753 child = pci_add_new_bus(bus, dev, ++max);
754 buses = (buses & 0xff000000)
755 | ((unsigned int)(child->primary) << 0)
756 | ((unsigned int)(child->secondary) << 8)
757 | ((unsigned int)(child->subordinate) << 16);
758
759 /*
760 * yenta.c forces a secondary latency timer of 176.
761 * Copy that behaviour here.
762 */
763 if (is_cardbus) {
764 buses &= ~0xff000000;
765 buses |= CARDBUS_LATENCY_TIMER << 24;
766 }
767
768 /*
769 * We need to blast all three values with a single write.
770 */
771 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
772
773 if (!is_cardbus) {
774 child->bridge_ctl = bctl;
775 /*
776 * Adjust subordinate busnr in parent buses.
777 * We do this before scanning for children because
778 * some devices may not be detected if the bios
779 * was lazy.
780 */
781 pci_fixup_parent_subordinate_busnr(child, max);
782 /* Now we can scan all subordinate buses... */
783 max = pci_scan_child_bus(child);
784 /*
785 * now fix it up again since we have found
786 * the real value of max.
787 */
788 pci_fixup_parent_subordinate_busnr(child, max);
789 } else {
790 /*
791 * For CardBus bridges, we leave 4 bus numbers
792 * as cards with a PCI-to-PCI bridge can be
793 * inserted later.
794 */
795 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
796 struct pci_bus *parent = bus;
797 if (pci_find_bus(pci_domain_nr(bus),
798 max+i+1))
799 break;
800 while (parent->parent) {
801 if ((!pcibios_assign_all_busses()) &&
802 (parent->subordinate > max) &&
803 (parent->subordinate <= max+i)) {
804 j = 1;
805 }
806 parent = parent->parent;
807 }
808 if (j) {
809 /*
810 * Often, there are two cardbus bridges
811 * -- try to leave one valid bus number
812 * for each one.
813 */
814 i /= 2;
815 break;
816 }
817 }
818 max += i;
819 pci_fixup_parent_subordinate_busnr(child, max);
820 }
821 /*
822 * Set the subordinate bus number to its real value.
823 */
824 child->subordinate = max;
825 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
826 }
827
828 sprintf(child->name,
829 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
830 pci_domain_nr(bus), child->number);
831
832 /* Has only triggered on CardBus, fixup is in yenta_socket */
833 while (bus->parent) {
834 if ((child->subordinate > bus->subordinate) ||
835 (child->number > bus->subordinate) ||
836 (child->number < bus->number) ||
837 (child->subordinate < bus->number)) {
838 dev_info(&child->dev, "[bus %02x-%02x] %s "
839 "hidden behind%s bridge %s [bus %02x-%02x]\n",
840 child->number, child->subordinate,
841 (bus->number > child->subordinate &&
842 bus->subordinate < child->number) ?
843 "wholly" : "partially",
844 bus->self->transparent ? " transparent" : "",
845 dev_name(&bus->dev),
846 bus->number, bus->subordinate);
847 }
848 bus = bus->parent;
849 }
850
851 out:
852 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
853
854 return max;
855 }
856
857 /*
858 * Read interrupt line and base address registers.
859 * The architecture-dependent code can tweak these, of course.
860 */
861 static void pci_read_irq(struct pci_dev *dev)
862 {
863 unsigned char irq;
864
865 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
866 dev->pin = irq;
867 if (irq)
868 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
869 dev->irq = irq;
870 }
871
872 void set_pcie_port_type(struct pci_dev *pdev)
873 {
874 int pos;
875 u16 reg16;
876
877 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
878 if (!pos)
879 return;
880 pdev->is_pcie = 1;
881 pdev->pcie_cap = pos;
882 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
883 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
884 }
885
886 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
887 {
888 int pos;
889 u16 reg16;
890 u32 reg32;
891
892 pos = pci_pcie_cap(pdev);
893 if (!pos)
894 return;
895 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
896 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
897 return;
898 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
899 if (reg32 & PCI_EXP_SLTCAP_HPC)
900 pdev->is_hotplug_bridge = 1;
901 }
902
903 static void set_pci_aer_firmware_first(struct pci_dev *pdev)
904 {
905 if (acpi_hest_firmware_first_pci(pdev))
906 pdev->aer_firmware_first = 1;
907 }
908
909 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
910
911 /**
912 * pci_setup_device - fill in class and map information of a device
913 * @dev: the device structure to fill
914 *
915 * Initialize the device structure with information about the device's
916 * vendor,class,memory and IO-space addresses,IRQ lines etc.
917 * Called at initialisation of the PCI subsystem and by CardBus services.
918 * Returns 0 on success and negative if unknown type of device (not normal,
919 * bridge or CardBus).
920 */
921 int pci_setup_device(struct pci_dev *dev)
922 {
923 u32 class;
924 u8 hdr_type;
925 struct pci_slot *slot;
926 int pos = 0;
927
928 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
929 return -EIO;
930
931 dev->sysdata = dev->bus->sysdata;
932 dev->dev.parent = dev->bus->bridge;
933 dev->dev.bus = &pci_bus_type;
934 dev->hdr_type = hdr_type & 0x7f;
935 dev->multifunction = !!(hdr_type & 0x80);
936 dev->error_state = pci_channel_io_normal;
937 set_pcie_port_type(dev);
938 set_pci_aer_firmware_first(dev);
939
940 list_for_each_entry(slot, &dev->bus->slots, list)
941 if (PCI_SLOT(dev->devfn) == slot->number)
942 dev->slot = slot;
943
944 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
945 set this higher, assuming the system even supports it. */
946 dev->dma_mask = 0xffffffff;
947
948 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
949 dev->bus->number, PCI_SLOT(dev->devfn),
950 PCI_FUNC(dev->devfn));
951
952 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
953 dev->revision = class & 0xff;
954 class >>= 8; /* upper 3 bytes */
955 dev->class = class;
956 class >>= 8;
957
958 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
959 dev->vendor, dev->device, class, dev->hdr_type);
960
961 /* need to have dev->class ready */
962 dev->cfg_size = pci_cfg_space_size(dev);
963
964 /* "Unknown power state" */
965 dev->current_state = PCI_UNKNOWN;
966
967 /* Early fixups, before probing the BARs */
968 pci_fixup_device(pci_fixup_early, dev);
969 /* device class may be changed after fixup */
970 class = dev->class >> 8;
971
972 switch (dev->hdr_type) { /* header type */
973 case PCI_HEADER_TYPE_NORMAL: /* standard header */
974 if (class == PCI_CLASS_BRIDGE_PCI)
975 goto bad;
976 pci_read_irq(dev);
977 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
978 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
979 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
980
981 /*
982 * Do the ugly legacy mode stuff here rather than broken chip
983 * quirk code. Legacy mode ATA controllers have fixed
984 * addresses. These are not always echoed in BAR0-3, and
985 * BAR0-3 in a few cases contain junk!
986 */
987 if (class == PCI_CLASS_STORAGE_IDE) {
988 u8 progif;
989 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
990 if ((progif & 1) == 0) {
991 dev->resource[0].start = 0x1F0;
992 dev->resource[0].end = 0x1F7;
993 dev->resource[0].flags = LEGACY_IO_RESOURCE;
994 dev->resource[1].start = 0x3F6;
995 dev->resource[1].end = 0x3F6;
996 dev->resource[1].flags = LEGACY_IO_RESOURCE;
997 }
998 if ((progif & 4) == 0) {
999 dev->resource[2].start = 0x170;
1000 dev->resource[2].end = 0x177;
1001 dev->resource[2].flags = LEGACY_IO_RESOURCE;
1002 dev->resource[3].start = 0x376;
1003 dev->resource[3].end = 0x376;
1004 dev->resource[3].flags = LEGACY_IO_RESOURCE;
1005 }
1006 }
1007 break;
1008
1009 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1010 if (class != PCI_CLASS_BRIDGE_PCI)
1011 goto bad;
1012 /* The PCI-to-PCI bridge spec requires that subtractive
1013 decoding (i.e. transparent) bridge must have programming
1014 interface code of 0x01. */
1015 pci_read_irq(dev);
1016 dev->transparent = ((dev->class & 0xff) == 1);
1017 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1018 set_pcie_hotplug_bridge(dev);
1019 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1020 if (pos) {
1021 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1022 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1023 }
1024 break;
1025
1026 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1027 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1028 goto bad;
1029 pci_read_irq(dev);
1030 pci_read_bases(dev, 1, 0);
1031 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1032 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1033 break;
1034
1035 default: /* unknown header */
1036 dev_err(&dev->dev, "unknown header type %02x, "
1037 "ignoring device\n", dev->hdr_type);
1038 return -EIO;
1039
1040 bad:
1041 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1042 "type %02x)\n", class, dev->hdr_type);
1043 dev->class = PCI_CLASS_NOT_DEFINED;
1044 }
1045
1046 /* We found a fine healthy device, go go go... */
1047 return 0;
1048 }
1049
1050 static void pci_release_capabilities(struct pci_dev *dev)
1051 {
1052 pci_vpd_release(dev);
1053 pci_iov_release(dev);
1054 }
1055
1056 /**
1057 * pci_release_dev - free a pci device structure when all users of it are finished.
1058 * @dev: device that's been disconnected
1059 *
1060 * Will be called only by the device core when all users of this pci device are
1061 * done.
1062 */
1063 static void pci_release_dev(struct device *dev)
1064 {
1065 struct pci_dev *pci_dev;
1066
1067 pci_dev = to_pci_dev(dev);
1068 pci_release_capabilities(pci_dev);
1069 kfree(pci_dev);
1070 }
1071
1072 /**
1073 * pci_cfg_space_size - get the configuration space size of the PCI device.
1074 * @dev: PCI device
1075 *
1076 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1077 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1078 * access it. Maybe we don't have a way to generate extended config space
1079 * accesses, or the device is behind a reverse Express bridge. So we try
1080 * reading the dword at 0x100 which must either be 0 or a valid extended
1081 * capability header.
1082 */
1083 int pci_cfg_space_size_ext(struct pci_dev *dev)
1084 {
1085 u32 status;
1086 int pos = PCI_CFG_SPACE_SIZE;
1087
1088 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1089 goto fail;
1090 if (status == 0xffffffff)
1091 goto fail;
1092
1093 return PCI_CFG_SPACE_EXP_SIZE;
1094
1095 fail:
1096 return PCI_CFG_SPACE_SIZE;
1097 }
1098
1099 int pci_cfg_space_size(struct pci_dev *dev)
1100 {
1101 int pos;
1102 u32 status;
1103 u16 class;
1104
1105 class = dev->class >> 8;
1106 if (class == PCI_CLASS_BRIDGE_HOST)
1107 return pci_cfg_space_size_ext(dev);
1108
1109 pos = pci_pcie_cap(dev);
1110 if (!pos) {
1111 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1112 if (!pos)
1113 goto fail;
1114
1115 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1116 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1117 goto fail;
1118 }
1119
1120 return pci_cfg_space_size_ext(dev);
1121
1122 fail:
1123 return PCI_CFG_SPACE_SIZE;
1124 }
1125
1126 static void pci_release_bus_bridge_dev(struct device *dev)
1127 {
1128 kfree(dev);
1129 }
1130
1131 struct pci_dev *alloc_pci_dev(void)
1132 {
1133 struct pci_dev *dev;
1134
1135 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1136 if (!dev)
1137 return NULL;
1138
1139 INIT_LIST_HEAD(&dev->bus_list);
1140
1141 return dev;
1142 }
1143 EXPORT_SYMBOL(alloc_pci_dev);
1144
1145 /*
1146 * Read the config data for a PCI device, sanity-check it
1147 * and fill in the dev structure...
1148 */
1149 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1150 {
1151 struct pci_dev *dev;
1152 u32 l;
1153 int delay = 1;
1154
1155 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1156 return NULL;
1157
1158 /* some broken boards return 0 or ~0 if a slot is empty: */
1159 if (l == 0xffffffff || l == 0x00000000 ||
1160 l == 0x0000ffff || l == 0xffff0000)
1161 return NULL;
1162
1163 /* Configuration request Retry Status */
1164 while (l == 0xffff0001) {
1165 msleep(delay);
1166 delay *= 2;
1167 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1168 return NULL;
1169 /* Card hasn't responded in 60 seconds? Must be stuck. */
1170 if (delay > 60 * 1000) {
1171 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1172 "responding\n", pci_domain_nr(bus),
1173 bus->number, PCI_SLOT(devfn),
1174 PCI_FUNC(devfn));
1175 return NULL;
1176 }
1177 }
1178
1179 dev = alloc_pci_dev();
1180 if (!dev)
1181 return NULL;
1182
1183 dev->bus = bus;
1184 dev->devfn = devfn;
1185 dev->vendor = l & 0xffff;
1186 dev->device = (l >> 16) & 0xffff;
1187
1188 if (pci_setup_device(dev)) {
1189 kfree(dev);
1190 return NULL;
1191 }
1192
1193 return dev;
1194 }
1195
1196 static void pci_init_capabilities(struct pci_dev *dev)
1197 {
1198 /* MSI/MSI-X list */
1199 pci_msi_init_pci_dev(dev);
1200
1201 /* Buffers for saving PCIe and PCI-X capabilities */
1202 pci_allocate_cap_save_buffers(dev);
1203
1204 /* Power Management */
1205 pci_pm_init(dev);
1206 platform_pci_wakeup_init(dev);
1207
1208 /* Vital Product Data */
1209 pci_vpd_pci22_init(dev);
1210
1211 /* Alternative Routing-ID Forwarding */
1212 pci_enable_ari(dev);
1213
1214 /* Single Root I/O Virtualization */
1215 pci_iov_init(dev);
1216
1217 /* Enable ACS P2P upstream forwarding */
1218 pci_enable_acs(dev);
1219 }
1220
1221 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1222 {
1223 device_initialize(&dev->dev);
1224 dev->dev.release = pci_release_dev;
1225 pci_dev_get(dev);
1226
1227 dev->dev.dma_mask = &dev->dma_mask;
1228 dev->dev.dma_parms = &dev->dma_parms;
1229 dev->dev.coherent_dma_mask = 0xffffffffull;
1230
1231 pci_set_dma_max_seg_size(dev, 65536);
1232 pci_set_dma_seg_boundary(dev, 0xffffffff);
1233
1234 /* Fix up broken headers */
1235 pci_fixup_device(pci_fixup_header, dev);
1236
1237 /* Clear the state_saved flag. */
1238 dev->state_saved = false;
1239
1240 /* Initialize various capabilities */
1241 pci_init_capabilities(dev);
1242
1243 /*
1244 * Add the device to our list of discovered devices
1245 * and the bus list for fixup functions, etc.
1246 */
1247 down_write(&pci_bus_sem);
1248 list_add_tail(&dev->bus_list, &bus->devices);
1249 up_write(&pci_bus_sem);
1250 }
1251
1252 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1253 {
1254 struct pci_dev *dev;
1255
1256 dev = pci_get_slot(bus, devfn);
1257 if (dev) {
1258 pci_dev_put(dev);
1259 return dev;
1260 }
1261
1262 dev = pci_scan_device(bus, devfn);
1263 if (!dev)
1264 return NULL;
1265
1266 pci_device_add(dev, bus);
1267
1268 return dev;
1269 }
1270 EXPORT_SYMBOL(pci_scan_single_device);
1271
1272 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1273 {
1274 u16 cap;
1275 unsigned pos, next_fn;
1276
1277 if (!dev)
1278 return 0;
1279
1280 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1281 if (!pos)
1282 return 0;
1283 pci_read_config_word(dev, pos + 4, &cap);
1284 next_fn = cap >> 8;
1285 if (next_fn <= fn)
1286 return 0;
1287 return next_fn;
1288 }
1289
1290 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1291 {
1292 return (fn + 1) % 8;
1293 }
1294
1295 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1296 {
1297 return 0;
1298 }
1299
1300 static int only_one_child(struct pci_bus *bus)
1301 {
1302 struct pci_dev *parent = bus->self;
1303 if (!parent || !pci_is_pcie(parent))
1304 return 0;
1305 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1306 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1307 return 1;
1308 return 0;
1309 }
1310
1311 /**
1312 * pci_scan_slot - scan a PCI slot on a bus for devices.
1313 * @bus: PCI bus to scan
1314 * @devfn: slot number to scan (must have zero function.)
1315 *
1316 * Scan a PCI slot on the specified PCI bus for devices, adding
1317 * discovered devices to the @bus->devices list. New devices
1318 * will not have is_added set.
1319 *
1320 * Returns the number of new devices found.
1321 */
1322 int pci_scan_slot(struct pci_bus *bus, int devfn)
1323 {
1324 unsigned fn, nr = 0;
1325 struct pci_dev *dev;
1326 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1327
1328 if (only_one_child(bus) && (devfn > 0))
1329 return 0; /* Already scanned the entire slot */
1330
1331 dev = pci_scan_single_device(bus, devfn);
1332 if (!dev)
1333 return 0;
1334 if (!dev->is_added)
1335 nr++;
1336
1337 if (pci_ari_enabled(bus))
1338 next_fn = next_ari_fn;
1339 else if (dev->multifunction)
1340 next_fn = next_trad_fn;
1341
1342 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1343 dev = pci_scan_single_device(bus, devfn + fn);
1344 if (dev) {
1345 if (!dev->is_added)
1346 nr++;
1347 dev->multifunction = 1;
1348 }
1349 }
1350
1351 /* only one slot has pcie device */
1352 if (bus->self && nr)
1353 pcie_aspm_init_link_state(bus->self);
1354
1355 return nr;
1356 }
1357
1358 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1359 {
1360 unsigned int devfn, pass, max = bus->secondary;
1361 struct pci_dev *dev;
1362
1363 dev_dbg(&bus->dev, "scanning bus\n");
1364
1365 /* Go find them, Rover! */
1366 for (devfn = 0; devfn < 0x100; devfn += 8)
1367 pci_scan_slot(bus, devfn);
1368
1369 /* Reserve buses for SR-IOV capability. */
1370 max += pci_iov_bus_range(bus);
1371
1372 /*
1373 * After performing arch-dependent fixup of the bus, look behind
1374 * all PCI-to-PCI bridges on this bus.
1375 */
1376 if (!bus->is_added) {
1377 dev_dbg(&bus->dev, "fixups for bus\n");
1378 pcibios_fixup_bus(bus);
1379 if (pci_is_root_bus(bus))
1380 bus->is_added = 1;
1381 }
1382
1383 for (pass=0; pass < 2; pass++)
1384 list_for_each_entry(dev, &bus->devices, bus_list) {
1385 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1386 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1387 max = pci_scan_bridge(bus, dev, max, pass);
1388 }
1389
1390 /*
1391 * We've scanned the bus and so we know all about what's on
1392 * the other side of any bridges that may be on this bus plus
1393 * any devices.
1394 *
1395 * Return how far we've got finding sub-buses.
1396 */
1397 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1398 return max;
1399 }
1400
1401 struct pci_bus * pci_create_bus(struct device *parent,
1402 int bus, struct pci_ops *ops, void *sysdata)
1403 {
1404 int error;
1405 struct pci_bus *b, *b2;
1406 struct device *dev;
1407
1408 b = pci_alloc_bus();
1409 if (!b)
1410 return NULL;
1411
1412 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1413 if (!dev){
1414 kfree(b);
1415 return NULL;
1416 }
1417
1418 b->sysdata = sysdata;
1419 b->ops = ops;
1420
1421 b2 = pci_find_bus(pci_domain_nr(b), bus);
1422 if (b2) {
1423 /* If we already got to this bus through a different bridge, ignore it */
1424 dev_dbg(&b2->dev, "bus already known\n");
1425 goto err_out;
1426 }
1427
1428 down_write(&pci_bus_sem);
1429 list_add_tail(&b->node, &pci_root_buses);
1430 up_write(&pci_bus_sem);
1431
1432 dev->parent = parent;
1433 dev->release = pci_release_bus_bridge_dev;
1434 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1435 error = device_register(dev);
1436 if (error)
1437 goto dev_reg_err;
1438 b->bridge = get_device(dev);
1439 device_enable_async_suspend(b->bridge);
1440
1441 if (!parent)
1442 set_dev_node(b->bridge, pcibus_to_node(b));
1443
1444 b->dev.class = &pcibus_class;
1445 b->dev.parent = b->bridge;
1446 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1447 error = device_register(&b->dev);
1448 if (error)
1449 goto class_dev_reg_err;
1450 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1451 if (error)
1452 goto dev_create_file_err;
1453
1454 /* Create legacy_io and legacy_mem files for this bus */
1455 pci_create_legacy_files(b);
1456
1457 b->number = b->secondary = bus;
1458 b->resource[0] = &ioport_resource;
1459 b->resource[1] = &iomem_resource;
1460
1461 return b;
1462
1463 dev_create_file_err:
1464 device_unregister(&b->dev);
1465 class_dev_reg_err:
1466 device_unregister(dev);
1467 dev_reg_err:
1468 down_write(&pci_bus_sem);
1469 list_del(&b->node);
1470 up_write(&pci_bus_sem);
1471 err_out:
1472 kfree(dev);
1473 kfree(b);
1474 return NULL;
1475 }
1476
1477 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1478 int bus, struct pci_ops *ops, void *sysdata)
1479 {
1480 struct pci_bus *b;
1481
1482 b = pci_create_bus(parent, bus, ops, sysdata);
1483 if (b)
1484 b->subordinate = pci_scan_child_bus(b);
1485 return b;
1486 }
1487 EXPORT_SYMBOL(pci_scan_bus_parented);
1488
1489 #ifdef CONFIG_HOTPLUG
1490 /**
1491 * pci_rescan_bus - scan a PCI bus for devices.
1492 * @bus: PCI bus to scan
1493 *
1494 * Scan a PCI bus and child buses for new devices, adds them,
1495 * and enables them.
1496 *
1497 * Returns the max number of subordinate bus discovered.
1498 */
1499 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1500 {
1501 unsigned int max;
1502 struct pci_dev *dev;
1503
1504 max = pci_scan_child_bus(bus);
1505
1506 down_read(&pci_bus_sem);
1507 list_for_each_entry(dev, &bus->devices, bus_list)
1508 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1509 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1510 if (dev->subordinate)
1511 pci_bus_size_bridges(dev->subordinate);
1512 up_read(&pci_bus_sem);
1513
1514 pci_bus_assign_resources(bus);
1515 pci_enable_bridges(bus);
1516 pci_bus_add_devices(bus);
1517
1518 return max;
1519 }
1520 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1521
1522 EXPORT_SYMBOL(pci_add_new_bus);
1523 EXPORT_SYMBOL(pci_scan_slot);
1524 EXPORT_SYMBOL(pci_scan_bridge);
1525 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1526 #endif
1527
1528 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1529 {
1530 const struct pci_dev *a = to_pci_dev(d_a);
1531 const struct pci_dev *b = to_pci_dev(d_b);
1532
1533 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1534 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1535
1536 if (a->bus->number < b->bus->number) return -1;
1537 else if (a->bus->number > b->bus->number) return 1;
1538
1539 if (a->devfn < b->devfn) return -1;
1540 else if (a->devfn > b->devfn) return 1;
1541
1542 return 0;
1543 }
1544
1545 void __init pci_sort_breadthfirst(void)
1546 {
1547 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1548 }
(deprecated) Btrfs devel tree