drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  31
  32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
  33
  34 static const char * const forcewake_domain_names[] = {
  35         "render",
  36         "blitter",
  37         "media",
  38 };
  39
  40 const char *
  41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  42 {
  43         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  44
  45         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  46                 return forcewake_domain_names[id];
  47
  48         WARN_ON(id);
  49
  50         return "unknown";
  51 }
  52
  53 static inline void
  54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  55 {
  56         WARN_ON(!i915_mmio_reg_valid(d->reg_set));
  57         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  58 }
  59
  60 static inline void
  61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  62 {
  63         mod_timer_pinned(&d->timer, jiffies + 1);
  64 }
  65
  66 static inline void
  67 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  68 {
  69         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  70                              FORCEWAKE_KERNEL) == 0,
  71                             FORCEWAKE_ACK_TIMEOUT_MS))
  72                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  73                           intel_uncore_forcewake_domain_to_str(d->id));
  74 }
  75
  76 static inline void
  77 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  78 {
  79         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  80 }
  81
  82 static inline void
  83 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
  84 {
  85         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  86                              FORCEWAKE_KERNEL),
  87                             FORCEWAKE_ACK_TIMEOUT_MS))
  88                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
  89                           intel_uncore_forcewake_domain_to_str(d->id));
  90 }
  91
  92 static inline void
  93 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
  94 {
  95         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
  96 }
  97
  98 static inline void
  99 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 100 {
 101         /* something from same cacheline, but not from the set register */
 102         if (i915_mmio_reg_valid(d->reg_post))
 103                 __raw_posting_read(d->i915, d->reg_post);
 104 }
 105
 106 static void
 107 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 108 {
 109         struct intel_uncore_forcewake_domain *d;
 110         enum forcewake_domain_id id;
 111
 112         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 113                 fw_domain_wait_ack_clear(d);
 114                 fw_domain_get(d);
 115                 fw_domain_wait_ack(d);
 116         }
 117 }
 118
 119 static void
 120 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 121 {
 122         struct intel_uncore_forcewake_domain *d;
 123         enum forcewake_domain_id id;
 124
 125         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 126                 fw_domain_put(d);
 127                 fw_domain_posting_read(d);
 128         }
 129 }
 130
 131 static void
 132 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 133 {
 134         struct intel_uncore_forcewake_domain *d;
 135         enum forcewake_domain_id id;
 136
 137         /* No need to do for all, just do for first found */
 138         for_each_fw_domain(d, dev_priv, id) {
 139                 fw_domain_posting_read(d);
 140                 break;
 141         }
 142 }
 143
 144 static void
 145 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 146 {
 147         struct intel_uncore_forcewake_domain *d;
 148         enum forcewake_domain_id id;
 149
 150         if (dev_priv->uncore.fw_domains == 0)
 151                 return;
 152
 153         for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
 154                 fw_domain_reset(d);
 155
 156         fw_domains_posting_read(dev_priv);
 157 }
 158
 159 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 160 {
 161         /* w/a for a sporadic read returning 0 by waiting for the GT
 162          * thread to wake up.
 163          */
 164         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 165                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 166                 DRM_ERROR("GT thread status wait timed out\n");
 167 }
 168
 169 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 170                                               enum forcewake_domains fw_domains)
 171 {
 172         fw_domains_get(dev_priv, fw_domains);
 173
 174         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 175         __gen6_gt_wait_for_thread_c0(dev_priv);
 176 }
 177
 178 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 179 {
 180         u32 gtfifodbg;
 181
 182         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 183         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 184                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 185 }
 186
 187 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 188                                      enum forcewake_domains fw_domains)
 189 {
 190         fw_domains_put(dev_priv, fw_domains);
 191         gen6_gt_check_fifodbg(dev_priv);
 192 }
 193
 194 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 195 {
 196         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 197
 198         return count & GT_FIFO_FREE_ENTRIES_MASK;
 199 }
 200
 201 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 202 {
 203         int ret = 0;
 204
 205         /* On VLV, FIFO will be shared by both SW and HW.
 206          * So, we need to read the FREE_ENTRIES everytime */
 207         if (IS_VALLEYVIEW(dev_priv->dev))
 208                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 209
 210         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 211                 int loop = 500;
 212                 u32 fifo = fifo_free_entries(dev_priv);
 213
 214                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 215                         udelay(10);
 216                         fifo = fifo_free_entries(dev_priv);
 217                 }
 218                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 219                         ++ret;
 220                 dev_priv->uncore.fifo_count = fifo;
 221         }
 222         dev_priv->uncore.fifo_count--;
 223
 224         return ret;
 225 }
 226
 227 static void intel_uncore_fw_release_timer(unsigned long arg)
 228 {
 229         struct intel_uncore_forcewake_domain *domain = (void *)arg;
 230         unsigned long irqflags;
 231
 232         assert_rpm_device_not_suspended(domain->i915);
 233
 234         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 235         if (WARN_ON(domain->wake_count == 0))
 236                 domain->wake_count++;
 237
 238         if (--domain->wake_count == 0)
 239                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 240                                                           1 << domain->id);
 241
 242         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 243 }
 244
 245 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 246 {
 247         struct drm_i915_private *dev_priv = dev->dev_private;
 248         unsigned long irqflags;
 249         struct intel_uncore_forcewake_domain *domain;
 250         int retry_count = 100;
 251         enum forcewake_domain_id id;
 252         enum forcewake_domains fw = 0, active_domains;
 253
 254         /* Hold uncore.lock across reset to prevent any register access
 255          * with forcewake not set correctly. Wait until all pending
 256          * timers are run before holding.
 257          */
 258         while (1) {
 259                 active_domains = 0;
 260
 261                 for_each_fw_domain(domain, dev_priv, id) {
 262                         if (del_timer_sync(&domain->timer) == 0)
 263                                 continue;
 264
 265                         intel_uncore_fw_release_timer((unsigned long)domain);
 266                 }
 267
 268                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 269
 270                 for_each_fw_domain(domain, dev_priv, id) {
 271                         if (timer_pending(&domain->timer))
 272                                 active_domains |= (1 << id);
 273                 }
 274
 275                 if (active_domains == 0)
 276                         break;
 277
 278                 if (--retry_count == 0) {
 279                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 280                         break;
 281                 }
 282
 283                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 284                 cond_resched();
 285         }
 286
 287         WARN_ON(active_domains);
 288
 289         for_each_fw_domain(domain, dev_priv, id)
 290                 if (domain->wake_count)
 291                         fw |= 1 << id;
 292
 293         if (fw)
 294                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 295
 296         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 297
 298         if (restore) { /* If reset with a user forcewake, try to restore */
 299                 if (fw)
 300                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 301
 302                 if (IS_GEN6(dev) || IS_GEN7(dev))
 303                         dev_priv->uncore.fifo_count =
 304                                 fifo_free_entries(dev_priv);
 305         }
 306
 307         if (!restore)
 308                 assert_forcewakes_inactive(dev_priv);
 309
 310         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 311 }
 312
 313 static void intel_uncore_ellc_detect(struct drm_device *dev)
 314 {
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316
 317         if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
 318              INTEL_INFO(dev)->gen >= 9) &&
 319             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
 320                 /* The docs do not explain exactly how the calculation can be
 321                  * made. It is somewhat guessable, but for now, it's always
 322                  * 128MB.
 323                  * NB: We can't write IDICR yet because we do not have gt funcs
 324                  * set up */
 325                 dev_priv->ellc_size = 128;
 326                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 327         }
 328 }
 329
 330 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 331                                           bool restore_forcewake)
 332 {
 333         struct drm_i915_private *dev_priv = dev->dev_private;
 334
 335         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 336                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 337
 338         /* clear out old GT FIFO errors */
 339         if (IS_GEN6(dev) || IS_GEN7(dev))
 340                 __raw_i915_write32(dev_priv, GTFIFODBG,
 341                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 342
 343         /* WaDisableShadowRegForCpd:chv */
 344         if (IS_CHERRYVIEW(dev)) {
 345                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 346                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 347                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 348                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 349         }
 350
 351         intel_uncore_forcewake_reset(dev, restore_forcewake);
 352 }
 353
 354 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 355 {
 356         __intel_uncore_early_sanitize(dev, restore_forcewake);
 357         i915_check_and_clear_faults(dev);
 358 }
 359
 360 void intel_uncore_sanitize(struct drm_device *dev)
 361 {
 362         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 363         intel_disable_gt_powersave(dev);
 364 }
 365
 366 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 367                                          enum forcewake_domains fw_domains)
 368 {
 369         struct intel_uncore_forcewake_domain *domain;
 370         enum forcewake_domain_id id;
 371
 372         if (!dev_priv->uncore.funcs.force_wake_get)
 373                 return;
 374
 375         fw_domains &= dev_priv->uncore.fw_domains;
 376
 377         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 378                 if (domain->wake_count++)
 379                         fw_domains &= ~(1 << id);
 380         }
 381
 382         if (fw_domains)
 383                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 384 }
 385
 386 /**
 387  * intel_uncore_forcewake_get - grab forcewake domain references
 388  * @dev_priv: i915 device instance
 389  * @fw_domains: forcewake domains to get reference on
 390  *
 391  * This function can be used get GT's forcewake domain references.
 392  * Normal register access will handle the forcewake domains automatically.
 393  * However if some sequence requires the GT to not power down a particular
 394  * forcewake domains this function should be called at the beginning of the
 395  * sequence. And subsequently the reference should be dropped by symmetric
 396  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 397  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 398  */
 399 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 400                                 enum forcewake_domains fw_domains)
 401 {
 402         unsigned long irqflags;
 403
 404         if (!dev_priv->uncore.funcs.force_wake_get)
 405                 return;
 406
 407         assert_rpm_wakelock_held(dev_priv);
 408
 409         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 410         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 411         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 412 }
 413
 414 /**
 415  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 416  * @dev_priv: i915 device instance
 417  * @fw_domains: forcewake domains to get reference on
 418  *
 419  * See intel_uncore_forcewake_get(). This variant places the onus
 420  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 421  */
 422 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 423                                         enum forcewake_domains fw_domains)
 424 {
 425         assert_spin_locked(&dev_priv->uncore.lock);
 426
 427         if (!dev_priv->uncore.funcs.force_wake_get)
 428                 return;
 429
 430         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 431 }
 432
 433 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 434                                          enum forcewake_domains fw_domains)
 435 {
 436         struct intel_uncore_forcewake_domain *domain;
 437         enum forcewake_domain_id id;
 438
 439         if (!dev_priv->uncore.funcs.force_wake_put)
 440                 return;
 441
 442         fw_domains &= dev_priv->uncore.fw_domains;
 443
 444         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 445                 if (WARN_ON(domain->wake_count == 0))
 446                         continue;
 447
 448                 if (--domain->wake_count)
 449                         continue;
 450
 451                 domain->wake_count++;
 452                 fw_domain_arm_timer(domain);
 453         }
 454 }
 455
 456 /**
 457  * intel_uncore_forcewake_put - release a forcewake domain reference
 458  * @dev_priv: i915 device instance
 459  * @fw_domains: forcewake domains to put references
 460  *
 461  * This function drops the device-level forcewakes for specified
 462  * domains obtained by intel_uncore_forcewake_get().
 463  */
 464 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 465                                 enum forcewake_domains fw_domains)
 466 {
 467         unsigned long irqflags;
 468
 469         if (!dev_priv->uncore.funcs.force_wake_put)
 470                 return;
 471
 472         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 473         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 474         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 475 }
 476
 477 /**
 478  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 479  * @dev_priv: i915 device instance
 480  * @fw_domains: forcewake domains to get reference on
 481  *
 482  * See intel_uncore_forcewake_put(). This variant places the onus
 483  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 484  */
 485 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 486                                         enum forcewake_domains fw_domains)
 487 {
 488         assert_spin_locked(&dev_priv->uncore.lock);
 489
 490         if (!dev_priv->uncore.funcs.force_wake_put)
 491                 return;
 492
 493         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 494 }
 495
 496 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 497 {
 498         struct intel_uncore_forcewake_domain *domain;
 499         enum forcewake_domain_id id;
 500
 501         if (!dev_priv->uncore.funcs.force_wake_get)
 502                 return;
 503
 504         for_each_fw_domain(domain, dev_priv, id)
 505                 WARN_ON(domain->wake_count);
 506 }
 507
 508 /* We give fast paths for the really cool registers */
 509 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 510
 511 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 512
 513 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 514         (REG_RANGE((reg), 0x2000, 0x4000) || \
 515          REG_RANGE((reg), 0x5000, 0x8000) || \
 516          REG_RANGE((reg), 0xB000, 0x12000) || \
 517          REG_RANGE((reg), 0x2E000, 0x30000))
 518
 519 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 520         (REG_RANGE((reg), 0x12000, 0x14000) || \
 521          REG_RANGE((reg), 0x22000, 0x24000) || \
 522          REG_RANGE((reg), 0x30000, 0x40000))
 523
 524 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 525         (REG_RANGE((reg), 0x2000, 0x4000) || \
 526          REG_RANGE((reg), 0x5200, 0x8000) || \
 527          REG_RANGE((reg), 0x8300, 0x8500) || \
 528          REG_RANGE((reg), 0xB000, 0xB480) || \
 529          REG_RANGE((reg), 0xE000, 0xE800))
 530
 531 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 532         (REG_RANGE((reg), 0x8800, 0x8900) || \
 533          REG_RANGE((reg), 0xD000, 0xD800) || \
 534          REG_RANGE((reg), 0x12000, 0x14000) || \
 535          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 536          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 537          REG_RANGE((reg), 0x30000, 0x38000))
 538
 539 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 540         (REG_RANGE((reg), 0x4000, 0x5000) || \
 541          REG_RANGE((reg), 0x8000, 0x8300) || \
 542          REG_RANGE((reg), 0x8500, 0x8600) || \
 543          REG_RANGE((reg), 0x9000, 0xB000) || \
 544          REG_RANGE((reg), 0xF000, 0x10000))
 545
 546 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 547         REG_RANGE((reg), 0xB00,  0x2000)
 548
 549 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 550         (REG_RANGE((reg), 0x2000, 0x2700) || \
 551          REG_RANGE((reg), 0x3000, 0x4000) || \
 552          REG_RANGE((reg), 0x5200, 0x8000) || \
 553          REG_RANGE((reg), 0x8140, 0x8160) || \
 554          REG_RANGE((reg), 0x8300, 0x8500) || \
 555          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 556          REG_RANGE((reg), 0xB000, 0xB480) || \
 557          REG_RANGE((reg), 0xE000, 0xE900) || \
 558          REG_RANGE((reg), 0x24400, 0x24800))
 559
 560 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 561         (REG_RANGE((reg), 0x8130, 0x8140) || \
 562          REG_RANGE((reg), 0x8800, 0x8A00) || \
 563          REG_RANGE((reg), 0xD000, 0xD800) || \
 564          REG_RANGE((reg), 0x12000, 0x14000) || \
 565          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 566          REG_RANGE((reg), 0x30000, 0x40000))
 567
 568 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 569         REG_RANGE((reg), 0x9400, 0x9800)
 570
 571 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 572         ((reg) < 0x40000 && \
 573          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 574          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 575          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 576          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 577
 578 static void
 579 ilk_dummy_write(struct drm_i915_private *dev_priv)
 580 {
 581         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 582          * the chip from rc6 before touching it for real. MI_MODE is masked,
 583          * hence harmless to write 0 into. */
 584         __raw_i915_write32(dev_priv, MI_MODE, 0);
 585 }
 586
 587 static void
 588 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 589                         i915_reg_t reg, bool read, bool before)
 590 {
 591         const char *op = read ? "reading" : "writing to";
 592         const char *when = before ? "before" : "after";
 593
 594         if (!i915.mmio_debug)
 595                 return;
 596
 597         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 598                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 599                      when, op, i915_mmio_reg_offset(reg));
 600                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 601                 i915.mmio_debug--; /* Only report the first N failures */
 602         }
 603 }
 604
 605 static void
 606 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 607 {
 608         static bool mmio_debug_once = true;
 609
 610         if (i915.mmio_debug || !mmio_debug_once)
 611                 return;
 612
 613         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 614                 DRM_DEBUG("Unclaimed register detected, "
 615                           "enabling oneshot unclaimed register reporting. "
 616                           "Please use i915.mmio_debug=N for more information.\n");
 617                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 618                 i915.mmio_debug = mmio_debug_once--;
 619         }
 620 }
 621
 622 #define GEN2_READ_HEADER(x) \
 623         u##x val = 0; \
 624         assert_rpm_wakelock_held(dev_priv);
 625
 626 #define GEN2_READ_FOOTER \
 627         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 628         return val
 629
 630 #define __gen2_read(x) \
 631 static u##x \
 632 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 633         GEN2_READ_HEADER(x); \
 634         val = __raw_i915_read##x(dev_priv, reg); \
 635         GEN2_READ_FOOTER; \
 636 }
 637
 638 #define __gen5_read(x) \
 639 static u##x \
 640 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 641         GEN2_READ_HEADER(x); \
 642         ilk_dummy_write(dev_priv); \
 643         val = __raw_i915_read##x(dev_priv, reg); \
 644         GEN2_READ_FOOTER; \
 645 }
 646
 647 __gen5_read(8)
 648 __gen5_read(16)
 649 __gen5_read(32)
 650 __gen5_read(64)
 651 __gen2_read(8)
 652 __gen2_read(16)
 653 __gen2_read(32)
 654 __gen2_read(64)
 655
 656 #undef __gen5_read
 657 #undef __gen2_read
 658
 659 #undef GEN2_READ_FOOTER
 660 #undef GEN2_READ_HEADER
 661
 662 #define GEN6_READ_HEADER(x) \
 663         u32 offset = i915_mmio_reg_offset(reg); \
 664         unsigned long irqflags; \
 665         u##x val = 0; \
 666         assert_rpm_wakelock_held(dev_priv); \
 667         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 668
 669 #define GEN6_READ_FOOTER \
 670         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 671         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 672         return val
 673
 674 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 675                                     enum forcewake_domains fw_domains)
 676 {
 677         struct intel_uncore_forcewake_domain *domain;
 678         enum forcewake_domain_id id;
 679
 680         if (WARN_ON(!fw_domains))
 681                 return;
 682
 683         /* Ideally GCC would be constant-fold and eliminate this loop */
 684         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 685                 if (domain->wake_count) {
 686                         fw_domains &= ~(1 << id);
 687                         continue;
 688                 }
 689
 690                 domain->wake_count++;
 691                 fw_domain_arm_timer(domain);
 692         }
 693
 694         if (fw_domains)
 695                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 696 }
 697
 698 #define __gen6_read(x) \
 699 static u##x \
 700 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 701         GEN6_READ_HEADER(x); \
 702         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 703         if (NEEDS_FORCE_WAKE(offset)) \
 704                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 705         val = __raw_i915_read##x(dev_priv, reg); \
 706         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 707         GEN6_READ_FOOTER; \
 708 }
 709
 710 #define __vlv_read(x) \
 711 static u##x \
 712 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 713         enum forcewake_domains fw_engine = 0; \
 714         GEN6_READ_HEADER(x); \
 715         if (!NEEDS_FORCE_WAKE(offset)) \
 716                 fw_engine = 0; \
 717         else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
 718                 fw_engine = FORCEWAKE_RENDER; \
 719         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
 720                 fw_engine = FORCEWAKE_MEDIA; \
 721         if (fw_engine) \
 722                 __force_wake_get(dev_priv, fw_engine); \
 723         val = __raw_i915_read##x(dev_priv, reg); \
 724         GEN6_READ_FOOTER; \
 725 }
 726
 727 #define __chv_read(x) \
 728 static u##x \
 729 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 730         enum forcewake_domains fw_engine = 0; \
 731         GEN6_READ_HEADER(x); \
 732         if (!NEEDS_FORCE_WAKE(offset)) \
 733                 fw_engine = 0; \
 734         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 735                 fw_engine = FORCEWAKE_RENDER; \
 736         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 737                 fw_engine = FORCEWAKE_MEDIA; \
 738         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 739                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 740         if (fw_engine) \
 741                 __force_wake_get(dev_priv, fw_engine); \
 742         val = __raw_i915_read##x(dev_priv, reg); \
 743         GEN6_READ_FOOTER; \
 744 }
 745
 746 #define SKL_NEEDS_FORCE_WAKE(reg) \
 747         ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 748
 749 #define __gen9_read(x) \
 750 static u##x \
 751 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 752         enum forcewake_domains fw_engine; \
 753         GEN6_READ_HEADER(x); \
 754         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 755         if (!SKL_NEEDS_FORCE_WAKE(offset)) \
 756                 fw_engine = 0; \
 757         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 758                 fw_engine = FORCEWAKE_RENDER; \
 759         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 760                 fw_engine = FORCEWAKE_MEDIA; \
 761         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 762                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 763         else \
 764                 fw_engine = FORCEWAKE_BLITTER; \
 765         if (fw_engine) \
 766                 __force_wake_get(dev_priv, fw_engine); \
 767         val = __raw_i915_read##x(dev_priv, reg); \
 768         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 769         GEN6_READ_FOOTER; \
 770 }
 771
 772 __gen9_read(8)
 773 __gen9_read(16)
 774 __gen9_read(32)
 775 __gen9_read(64)
 776 __chv_read(8)
 777 __chv_read(16)
 778 __chv_read(32)
 779 __chv_read(64)
 780 __vlv_read(8)
 781 __vlv_read(16)
 782 __vlv_read(32)
 783 __vlv_read(64)
 784 __gen6_read(8)
 785 __gen6_read(16)
 786 __gen6_read(32)
 787 __gen6_read(64)
 788
 789 #undef __gen9_read
 790 #undef __chv_read
 791 #undef __vlv_read
 792 #undef __gen6_read
 793 #undef GEN6_READ_FOOTER
 794 #undef GEN6_READ_HEADER
 795
 796 #define VGPU_READ_HEADER(x) \
 797         unsigned long irqflags; \
 798         u##x val = 0; \
 799         assert_rpm_device_not_suspended(dev_priv); \
 800         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 801
 802 #define VGPU_READ_FOOTER \
 803         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 804         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 805         return val
 806
 807 #define __vgpu_read(x) \
 808 static u##x \
 809 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 810         VGPU_READ_HEADER(x); \
 811         val = __raw_i915_read##x(dev_priv, reg); \
 812         VGPU_READ_FOOTER; \
 813 }
 814
 815 __vgpu_read(8)
 816 __vgpu_read(16)
 817 __vgpu_read(32)
 818 __vgpu_read(64)
 819
 820 #undef __vgpu_read
 821 #undef VGPU_READ_FOOTER
 822 #undef VGPU_READ_HEADER
 823
 824 #define GEN2_WRITE_HEADER \
 825         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 826         assert_rpm_wakelock_held(dev_priv); \
 827
 828 #define GEN2_WRITE_FOOTER
 829
 830 #define __gen2_write(x) \
 831 static void \
 832 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 833         GEN2_WRITE_HEADER; \
 834         __raw_i915_write##x(dev_priv, reg, val); \
 835         GEN2_WRITE_FOOTER; \
 836 }
 837
 838 #define __gen5_write(x) \
 839 static void \
 840 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 841         GEN2_WRITE_HEADER; \
 842         ilk_dummy_write(dev_priv); \
 843         __raw_i915_write##x(dev_priv, reg, val); \
 844         GEN2_WRITE_FOOTER; \
 845 }
 846
 847 __gen5_write(8)
 848 __gen5_write(16)
 849 __gen5_write(32)
 850 __gen5_write(64)
 851 __gen2_write(8)
 852 __gen2_write(16)
 853 __gen2_write(32)
 854 __gen2_write(64)
 855
 856 #undef __gen5_write
 857 #undef __gen2_write
 858
 859 #undef GEN2_WRITE_FOOTER
 860 #undef GEN2_WRITE_HEADER
 861
 862 #define GEN6_WRITE_HEADER \
 863         u32 offset = i915_mmio_reg_offset(reg); \
 864         unsigned long irqflags; \
 865         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 866         assert_rpm_wakelock_held(dev_priv); \
 867         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 868
 869 #define GEN6_WRITE_FOOTER \
 870         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 871
 872 #define __gen6_write(x) \
 873 static void \
 874 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 875         u32 __fifo_ret = 0; \
 876         GEN6_WRITE_HEADER; \
 877         if (NEEDS_FORCE_WAKE(offset)) { \
 878                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 879         } \
 880         __raw_i915_write##x(dev_priv, reg, val); \
 881         if (unlikely(__fifo_ret)) { \
 882                 gen6_gt_check_fifodbg(dev_priv); \
 883         } \
 884         GEN6_WRITE_FOOTER; \
 885 }
 886
 887 #define __hsw_write(x) \
 888 static void \
 889 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 890         u32 __fifo_ret = 0; \
 891         GEN6_WRITE_HEADER; \
 892         if (NEEDS_FORCE_WAKE(offset)) { \
 893                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 894         } \
 895         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 896         __raw_i915_write##x(dev_priv, reg, val); \
 897         if (unlikely(__fifo_ret)) { \
 898                 gen6_gt_check_fifodbg(dev_priv); \
 899         } \
 900         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 901         hsw_unclaimed_reg_detect(dev_priv); \
 902         GEN6_WRITE_FOOTER; \
 903 }
 904
 905 static const i915_reg_t gen8_shadowed_regs[] = {
 906         FORCEWAKE_MT,
 907         GEN6_RPNSWREQ,
 908         GEN6_RC_VIDEO_FREQ,
 909         RING_TAIL(RENDER_RING_BASE),
 910         RING_TAIL(GEN6_BSD_RING_BASE),
 911         RING_TAIL(VEBOX_RING_BASE),
 912         RING_TAIL(BLT_RING_BASE),
 913         /* TODO: Other registers are not yet used */
 914 };
 915
 916 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv,
 917                              i915_reg_t reg)
 918 {
 919         int i;
 920         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 921                 if (i915_mmio_reg_equal(reg, gen8_shadowed_regs[i]))
 922                         return true;
 923
 924         return false;
 925 }
 926
 927 #define __gen8_write(x) \
 928 static void \
 929 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 930         GEN6_WRITE_HEADER; \
 931         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 932         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \
 933                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 934         __raw_i915_write##x(dev_priv, reg, val); \
 935         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 936         hsw_unclaimed_reg_detect(dev_priv); \
 937         GEN6_WRITE_FOOTER; \
 938 }
 939
 940 #define __chv_write(x) \
 941 static void \
 942 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 943         enum forcewake_domains fw_engine = 0; \
 944         GEN6_WRITE_HEADER; \
 945         if (!NEEDS_FORCE_WAKE(offset) || \
 946             is_gen8_shadowed(dev_priv, reg)) \
 947                 fw_engine = 0; \
 948         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 949                 fw_engine = FORCEWAKE_RENDER; \
 950         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 951                 fw_engine = FORCEWAKE_MEDIA; \
 952         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 953                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 954         if (fw_engine) \
 955                 __force_wake_get(dev_priv, fw_engine); \
 956         __raw_i915_write##x(dev_priv, reg, val); \
 957         GEN6_WRITE_FOOTER; \
 958 }
 959
 960 static const i915_reg_t gen9_shadowed_regs[] = {
 961         RING_TAIL(RENDER_RING_BASE),
 962         RING_TAIL(GEN6_BSD_RING_BASE),
 963         RING_TAIL(VEBOX_RING_BASE),
 964         RING_TAIL(BLT_RING_BASE),
 965         FORCEWAKE_BLITTER_GEN9,
 966         FORCEWAKE_RENDER_GEN9,
 967         FORCEWAKE_MEDIA_GEN9,
 968         GEN6_RPNSWREQ,
 969         GEN6_RC_VIDEO_FREQ,
 970         /* TODO: Other registers are not yet used */
 971 };
 972
 973 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv,
 974                              i915_reg_t reg)
 975 {
 976         int i;
 977         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 978                 if (i915_mmio_reg_equal(reg, gen9_shadowed_regs[i]))
 979                         return true;
 980
 981         return false;
 982 }
 983
 984 #define __gen9_write(x) \
 985 static void \
 986 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
 987                 bool trace) { \
 988         enum forcewake_domains fw_engine; \
 989         GEN6_WRITE_HEADER; \
 990         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 991         if (!SKL_NEEDS_FORCE_WAKE(offset) || \
 992             is_gen9_shadowed(dev_priv, reg)) \
 993                 fw_engine = 0; \
 994         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 995                 fw_engine = FORCEWAKE_RENDER; \
 996         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 997                 fw_engine = FORCEWAKE_MEDIA; \
 998         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 999                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
1000         else \
1001                 fw_engine = FORCEWAKE_BLITTER; \
1002         if (fw_engine) \
1003                 __force_wake_get(dev_priv, fw_engine); \
1004         __raw_i915_write##x(dev_priv, reg, val); \
1005         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
1006         hsw_unclaimed_reg_detect(dev_priv); \
1007         GEN6_WRITE_FOOTER; \
1008 }
1009
1010 __gen9_write(8)
1011 __gen9_write(16)
1012 __gen9_write(32)
1013 __gen9_write(64)
1014 __chv_write(8)
1015 __chv_write(16)
1016 __chv_write(32)
1017 __chv_write(64)
1018 __gen8_write(8)
1019 __gen8_write(16)
1020 __gen8_write(32)
1021 __gen8_write(64)
1022 __hsw_write(8)
1023 __hsw_write(16)
1024 __hsw_write(32)
1025 __hsw_write(64)
1026 __gen6_write(8)
1027 __gen6_write(16)
1028 __gen6_write(32)
1029 __gen6_write(64)
1030
1031 #undef __gen9_write
1032 #undef __chv_write
1033 #undef __gen8_write
1034 #undef __hsw_write
1035 #undef __gen6_write
1036 #undef GEN6_WRITE_FOOTER
1037 #undef GEN6_WRITE_HEADER
1038
1039 #define VGPU_WRITE_HEADER \
1040         unsigned long irqflags; \
1041         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1042         assert_rpm_device_not_suspended(dev_priv); \
1043         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1044
1045 #define VGPU_WRITE_FOOTER \
1046         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1047
1048 #define __vgpu_write(x) \
1049 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1050                           i915_reg_t reg, u##x val, bool trace) { \
1051         VGPU_WRITE_HEADER; \
1052         __raw_i915_write##x(dev_priv, reg, val); \
1053         VGPU_WRITE_FOOTER; \
1054 }
1055
1056 __vgpu_write(8)
1057 __vgpu_write(16)
1058 __vgpu_write(32)
1059 __vgpu_write(64)
1060
1061 #undef __vgpu_write
1062 #undef VGPU_WRITE_FOOTER
1063 #undef VGPU_WRITE_HEADER
1064
1065 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1066 do { \
1067         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1068         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1069         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1070         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1071 } while (0)
1072
1073 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1074 do { \
1075         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1076         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1077         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1078         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1079 } while (0)
1080
1081
1082 static void fw_domain_init(struct drm_i915_private *dev_priv,
1083                            enum forcewake_domain_id domain_id,
1084                            i915_reg_t reg_set,
1085                            i915_reg_t reg_ack)
1086 {
1087         struct intel_uncore_forcewake_domain *d;
1088
1089         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1090                 return;
1091
1092         d = &dev_priv->uncore.fw_domain[domain_id];
1093
1094         WARN_ON(d->wake_count);
1095
1096         d->wake_count = 0;
1097         d->reg_set = reg_set;
1098         d->reg_ack = reg_ack;
1099
1100         if (IS_GEN6(dev_priv)) {
1101                 d->val_reset = 0;
1102                 d->val_set = FORCEWAKE_KERNEL;
1103                 d->val_clear = 0;
1104         } else {
1105                 /* WaRsClearFWBitsAtReset:bdw,skl */
1106                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1107                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1108                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1109         }
1110
1111         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1112                 d->reg_post = FORCEWAKE_ACK_VLV;
1113         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1114                 d->reg_post = ECOBUS;
1115
1116         d->i915 = dev_priv;
1117         d->id = domain_id;
1118
1119         setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1120
1121         dev_priv->uncore.fw_domains |= (1 << domain_id);
1122
1123         fw_domain_reset(d);
1124 }
1125
1126 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1127 {
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130         if (INTEL_INFO(dev_priv->dev)->gen <= 5)
1131                 return;
1132
1133         if (IS_GEN9(dev)) {
1134                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1135                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1136                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1137                                FORCEWAKE_RENDER_GEN9,
1138                                FORCEWAKE_ACK_RENDER_GEN9);
1139                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1140                                FORCEWAKE_BLITTER_GEN9,
1141                                FORCEWAKE_ACK_BLITTER_GEN9);
1142                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1143                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1144         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1145                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1146                 if (!IS_CHERRYVIEW(dev))
1147                         dev_priv->uncore.funcs.force_wake_put =
1148                                 fw_domains_put_with_fifo;
1149                 else
1150                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1151                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1152                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1153                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1154                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1155         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1156                 dev_priv->uncore.funcs.force_wake_get =
1157                         fw_domains_get_with_thread_status;
1158                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1159                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1160                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1161         } else if (IS_IVYBRIDGE(dev)) {
1162                 u32 ecobus;
1163
1164                 /* IVB configs may use multi-threaded forcewake */
1165
1166                 /* A small trick here - if the bios hasn't configured
1167                  * MT forcewake, and if the device is in RC6, then
1168                  * force_wake_mt_get will not wake the device and the
1169                  * ECOBUS read will return zero. Which will be
1170                  * (correctly) interpreted by the test below as MT
1171                  * forcewake being disabled.
1172                  */
1173                 dev_priv->uncore.funcs.force_wake_get =
1174                         fw_domains_get_with_thread_status;
1175                 dev_priv->uncore.funcs.force_wake_put =
1176                         fw_domains_put_with_fifo;
1177
1178                 /* We need to init first for ECOBUS access and then
1179                  * determine later if we want to reinit, in case of MT access is
1180                  * not working. In this stage we don't know which flavour this
1181                  * ivb is, so it is better to reset also the gen6 fw registers
1182                  * before the ecobus check.
1183                  */
1184
1185                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1186                 __raw_posting_read(dev_priv, ECOBUS);
1187
1188                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1189                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1190
1191                 mutex_lock(&dev->struct_mutex);
1192                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1193                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1194                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1195                 mutex_unlock(&dev->struct_mutex);
1196
1197                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1198                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1199                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1200                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1201                                        FORCEWAKE, FORCEWAKE_ACK);
1202                 }
1203         } else if (IS_GEN6(dev)) {
1204                 dev_priv->uncore.funcs.force_wake_get =
1205                         fw_domains_get_with_thread_status;
1206                 dev_priv->uncore.funcs.force_wake_put =
1207                         fw_domains_put_with_fifo;
1208                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1209                                FORCEWAKE, FORCEWAKE_ACK);
1210         }
1211
1212         /* All future platforms are expected to require complex power gating */
1213         WARN_ON(dev_priv->uncore.fw_domains == 0);
1214 }
1215
1216 void intel_uncore_init(struct drm_device *dev)
1217 {
1218         struct drm_i915_private *dev_priv = dev->dev_private;
1219
1220         i915_check_vgpu(dev);
1221
1222         intel_uncore_ellc_detect(dev);
1223         intel_uncore_fw_domains_init(dev);
1224         __intel_uncore_early_sanitize(dev, false);
1225
1226         switch (INTEL_INFO(dev)->gen) {
1227         default:
1228         case 9:
1229                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1230                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1231                 break;
1232         case 8:
1233                 if (IS_CHERRYVIEW(dev)) {
1234                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1235                         ASSIGN_READ_MMIO_VFUNCS(chv);
1236
1237                 } else {
1238                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1239                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1240                 }
1241                 break;
1242         case 7:
1243         case 6:
1244                 if (IS_HASWELL(dev)) {
1245                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1246                 } else {
1247                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1248                 }
1249
1250                 if (IS_VALLEYVIEW(dev)) {
1251                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1252                 } else {
1253                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1254                 }
1255                 break;
1256         case 5:
1257                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1258                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1259                 break;
1260         case 4:
1261         case 3:
1262         case 2:
1263                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1264                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1265                 break;
1266         }
1267
1268         if (intel_vgpu_active(dev)) {
1269                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1270                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1271         }
1272
1273         i915_check_and_clear_faults(dev);
1274 }
1275 #undef ASSIGN_WRITE_MMIO_VFUNCS
1276 #undef ASSIGN_READ_MMIO_VFUNCS
1277
1278 void intel_uncore_fini(struct drm_device *dev)
1279 {
1280         /* Paranoia: make sure we have disabled everything before we exit. */
1281         intel_uncore_sanitize(dev);
1282         intel_uncore_forcewake_reset(dev, false);
1283 }
1284
1285 #define GEN_RANGE(l, h) GENMASK(h, l)
1286
1287 static const struct register_whitelist {
1288         i915_reg_t offset_ldw, offset_udw;
1289         uint32_t size;
1290         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1291         uint32_t gen_bitmask;
1292 } whitelist[] = {
1293         { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1294           .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1295           .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1296 };
1297
1298 int i915_reg_read_ioctl(struct drm_device *dev,
1299                         void *data, struct drm_file *file)
1300 {
1301         struct drm_i915_private *dev_priv = dev->dev_private;
1302         struct drm_i915_reg_read *reg = data;
1303         struct register_whitelist const *entry = whitelist;
1304         unsigned size;
1305         i915_reg_t offset_ldw, offset_udw;
1306         int i, ret = 0;
1307
1308         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1309                 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1310                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1311                         break;
1312         }
1313
1314         if (i == ARRAY_SIZE(whitelist))
1315                 return -EINVAL;
1316
1317         /* We use the low bits to encode extra flags as the register should
1318          * be naturally aligned (and those that are not so aligned merely
1319          * limit the available flags for that register).
1320          */
1321         offset_ldw = entry->offset_ldw;
1322         offset_udw = entry->offset_udw;
1323         size = entry->size;
1324         size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1325
1326         intel_runtime_pm_get(dev_priv);
1327
1328         switch (size) {
1329         case 8 | 1:
1330                 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1331                 break;
1332         case 8:
1333                 reg->val = I915_READ64(offset_ldw);
1334                 break;
1335         case 4:
1336                 reg->val = I915_READ(offset_ldw);
1337                 break;
1338         case 2:
1339                 reg->val = I915_READ16(offset_ldw);
1340                 break;
1341         case 1:
1342                 reg->val = I915_READ8(offset_ldw);
1343                 break;
1344         default:
1345                 ret = -EINVAL;
1346                 goto out;
1347         }
1348
1349 out:
1350         intel_runtime_pm_put(dev_priv);
1351         return ret;
1352 }
1353
1354 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1355                                void *data, struct drm_file *file)
1356 {
1357         struct drm_i915_private *dev_priv = dev->dev_private;
1358         struct drm_i915_reset_stats *args = data;
1359         struct i915_ctx_hang_stats *hs;
1360         struct intel_context *ctx;
1361         int ret;
1362
1363         if (args->flags || args->pad)
1364                 return -EINVAL;
1365
1366         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1367                 return -EPERM;
1368
1369         ret = mutex_lock_interruptible(&dev->struct_mutex);
1370         if (ret)
1371                 return ret;
1372
1373         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1374         if (IS_ERR(ctx)) {
1375                 mutex_unlock(&dev->struct_mutex);
1376                 return PTR_ERR(ctx);
1377         }
1378         hs = &ctx->hang_stats;
1379
1380         if (capable(CAP_SYS_ADMIN))
1381                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1382         else
1383                 args->reset_count = 0;
1384
1385         args->batch_active = hs->batch_active;
1386         args->batch_pending = hs->batch_pending;
1387
1388         mutex_unlock(&dev->struct_mutex);
1389
1390         return 0;
1391 }
1392
1393 static int i915_reset_complete(struct drm_device *dev)
1394 {
1395         u8 gdrst;
1396         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1397         return (gdrst & GRDOM_RESET_STATUS) == 0;
1398 }
1399
1400 static int i915_do_reset(struct drm_device *dev)
1401 {
1402         /* assert reset for at least 20 usec */
1403         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1404         udelay(20);
1405         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1406
1407         return wait_for(i915_reset_complete(dev), 500);
1408 }
1409
1410 static int g4x_reset_complete(struct drm_device *dev)
1411 {
1412         u8 gdrst;
1413         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1414         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1415 }
1416
1417 static int g33_do_reset(struct drm_device *dev)
1418 {
1419         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1420         return wait_for(g4x_reset_complete(dev), 500);
1421 }
1422
1423 static int g4x_do_reset(struct drm_device *dev)
1424 {
1425         struct drm_i915_private *dev_priv = dev->dev_private;
1426         int ret;
1427
1428         pci_write_config_byte(dev->pdev, I915_GDRST,
1429                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1430         ret =  wait_for(g4x_reset_complete(dev), 500);
1431         if (ret)
1432                 return ret;
1433
1434         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1435         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1436         POSTING_READ(VDECCLK_GATE_D);
1437
1438         pci_write_config_byte(dev->pdev, I915_GDRST,
1439                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1440         ret =  wait_for(g4x_reset_complete(dev), 500);
1441         if (ret)
1442                 return ret;
1443
1444         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1445         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1446         POSTING_READ(VDECCLK_GATE_D);
1447
1448         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1449
1450         return 0;
1451 }
1452
1453 static int ironlake_do_reset(struct drm_device *dev)
1454 {
1455         struct drm_i915_private *dev_priv = dev->dev_private;
1456         int ret;
1457
1458         I915_WRITE(ILK_GDSR,
1459                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1460         ret = wait_for((I915_READ(ILK_GDSR) &
1461                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1462         if (ret)
1463                 return ret;
1464
1465         I915_WRITE(ILK_GDSR,
1466                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1467         ret = wait_for((I915_READ(ILK_GDSR) &
1468                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1469         if (ret)
1470                 return ret;
1471
1472         I915_WRITE(ILK_GDSR, 0);
1473
1474         return 0;
1475 }
1476
1477 static int gen6_do_reset(struct drm_device *dev)
1478 {
1479         struct drm_i915_private *dev_priv = dev->dev_private;
1480         int     ret;
1481
1482         /* Reset the chip */
1483
1484         /* GEN6_GDRST is not in the gt power well, no need to check
1485          * for fifo space for the write or forcewake the chip for
1486          * the read
1487          */
1488         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1489
1490         /* Spin waiting for the device to ack the reset request */
1491         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1492
1493         intel_uncore_forcewake_reset(dev, true);
1494
1495         return ret;
1496 }
1497
1498 static int wait_for_register(struct drm_i915_private *dev_priv,
1499                              i915_reg_t reg,
1500                              const u32 mask,
1501                              const u32 value,
1502                              const unsigned long timeout_ms)
1503 {
1504         return wait_for((I915_READ(reg) & mask) == value, timeout_ms);
1505 }
1506
1507 static int gen8_do_reset(struct drm_device *dev)
1508 {
1509         struct drm_i915_private *dev_priv = dev->dev_private;
1510         struct intel_engine_cs *engine;
1511         int i;
1512
1513         for_each_ring(engine, dev_priv, i) {
1514                 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1515                            _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1516
1517                 if (wait_for_register(dev_priv,
1518                                       RING_RESET_CTL(engine->mmio_base),
1519                                       RESET_CTL_READY_TO_RESET,
1520                                       RESET_CTL_READY_TO_RESET,
1521                                       700)) {
1522                         DRM_ERROR("%s: reset request timeout\n", engine->name);
1523                         goto not_ready;
1524                 }
1525         }
1526
1527         return gen6_do_reset(dev);
1528
1529 not_ready:
1530         for_each_ring(engine, dev_priv, i)
1531                 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1532                            _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1533
1534         return -EIO;
1535 }
1536
1537 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *)
1538 {
1539         if (!i915.reset)
1540                 return NULL;
1541
1542         if (INTEL_INFO(dev)->gen >= 8)
1543                 return gen8_do_reset;
1544         else if (INTEL_INFO(dev)->gen >= 6)
1545                 return gen6_do_reset;
1546         else if (IS_GEN5(dev))
1547                 return ironlake_do_reset;
1548         else if (IS_G4X(dev))
1549                 return g4x_do_reset;
1550         else if (IS_G33(dev))
1551                 return g33_do_reset;
1552         else if (INTEL_INFO(dev)->gen >= 3)
1553                 return i915_do_reset;
1554         else
1555                 return NULL;
1556 }
1557
1558 int intel_gpu_reset(struct drm_device *dev)
1559 {
1560         struct drm_i915_private *dev_priv = to_i915(dev);
1561         int (*reset)(struct drm_device *);
1562         int ret;
1563
1564         reset = intel_get_gpu_reset(dev);
1565         if (reset == NULL)
1566                 return -ENODEV;
1567
1568         /* If the power well sleeps during the reset, the reset
1569          * request may be dropped and never completes (causing -EIO).
1570          */
1571         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1572         ret = reset(dev);
1573         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1574
1575         return ret;
1576 }
1577
1578 bool intel_has_gpu_reset(struct drm_device *dev)
1579 {
1580         return intel_get_gpu_reset(dev) != NULL;
1581 }
1582
1583 void intel_uncore_check_errors(struct drm_device *dev)
1584 {
1585         struct drm_i915_private *dev_priv = dev->dev_private;
1586
1587         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1588             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1589                 DRM_ERROR("Unclaimed register before interrupt\n");
1590                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1591         }
1592 }