1 /* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/pci_ids.h>
15 #include <asm/pci-direct.h>
17 #include <asm/io_apic.h>
19 #include <asm/iommu.h>
21 #include <asm/irq_remapping.h>
23 static void __init
fix_hypertransport_config(int num
, int slot
, int func
)
27 * we found a hypertransport bus
28 * make sure that we are broadcasting
29 * interrupts to all cpus on the ht bus
30 * if we're using extended apic ids
32 htcfg
= read_pci_config(num
, slot
, func
, 0x68);
33 if (htcfg
& (1 << 18)) {
34 printk(KERN_INFO
"Detected use of extended apic ids "
35 "on hypertransport bus\n");
36 if ((htcfg
& (1 << 17)) == 0) {
37 printk(KERN_INFO
"Enabling hypertransport extended "
38 "apic interrupt broadcast\n");
39 printk(KERN_INFO
"Note this is a bios bug, "
40 "please contact your hw vendor\n");
42 write_pci_config(num
, slot
, func
, 0x68, htcfg
);
49 static void __init
via_bugs(int num
, int slot
, int func
)
51 #ifdef CONFIG_GART_IOMMU
52 if ((max_pfn
> MAX_DMA32_PFN
|| force_iommu
) &&
53 !gart_iommu_aperture_allowed
) {
55 "Looks like a VIA chipset. Disabling IOMMU."
56 " Override with iommu=allowed\n");
57 gart_iommu_aperture_disabled
= 1;
63 #ifdef CONFIG_X86_IO_APIC
65 static int __init
nvidia_hpet_check(struct acpi_table_header
*header
)
69 #endif /* CONFIG_X86_IO_APIC */
70 #endif /* CONFIG_ACPI */
72 static void __init
nvidia_bugs(int num
, int slot
, int func
)
75 #ifdef CONFIG_X86_IO_APIC
77 * All timer overrides on Nvidia are
78 * wrong unless HPET is enabled.
79 * Unfortunately that's not true on many Asus boards.
80 * We don't know yet how to detect this automatically, but
81 * at least allow a command line override.
83 if (acpi_use_timer_override
)
86 if (acpi_table_parse(ACPI_SIG_HPET
, nvidia_hpet_check
)) {
87 acpi_skip_timer_override
= 1;
88 printk(KERN_INFO
"Nvidia board "
89 "detected. Ignoring ACPI "
91 printk(KERN_INFO
"If you got timer trouble "
92 "try acpi_use_timer_override\n");
96 /* RED-PEN skip them on mptables too? */
100 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
101 static u32 __init
ati_ixp4x0_rev(int num
, int slot
, int func
)
106 b
= read_pci_config_byte(num
, slot
, func
, 0xac);
108 write_pci_config_byte(num
, slot
, func
, 0xac, b
);
110 d
= read_pci_config(num
, slot
, func
, 0x70);
112 write_pci_config(num
, slot
, func
, 0x70, d
);
114 d
= read_pci_config(num
, slot
, func
, 0x8);
119 static void __init
ati_bugs(int num
, int slot
, int func
)
124 if (acpi_use_timer_override
)
127 d
= ati_ixp4x0_rev(num
, slot
, func
);
129 acpi_skip_timer_override
= 1;
131 /* check for IRQ0 interrupt swap */
132 outb(0x72, 0xcd6); b
= inb(0xcd7);
134 acpi_skip_timer_override
= 1;
137 if (acpi_skip_timer_override
) {
138 printk(KERN_INFO
"SB4X0 revision 0x%x\n", d
);
139 printk(KERN_INFO
"Ignoring ACPI timer override.\n");
140 printk(KERN_INFO
"If you got timer trouble "
141 "try acpi_use_timer_override\n");
145 static u32 __init
ati_sbx00_rev(int num
, int slot
, int func
)
149 d
= read_pci_config(num
, slot
, func
, 0x8);
155 static void __init
ati_bugs_contd(int num
, int slot
, int func
)
159 rev
= ati_sbx00_rev(num
, slot
, func
);
161 acpi_fix_pin2_polarity
= 1;
164 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
165 * SB700: revisions 0x39, 0x3a, ...
166 * SB800: revisions 0x40, 0x41, ...
171 if (acpi_use_timer_override
)
174 /* check for IRQ0 interrupt swap */
175 d
= read_pci_config(num
, slot
, func
, 0x64);
177 acpi_skip_timer_override
= 1;
179 if (acpi_skip_timer_override
) {
180 printk(KERN_INFO
"SB600 revision 0x%x\n", rev
);
181 printk(KERN_INFO
"Ignoring ACPI timer override.\n");
182 printk(KERN_INFO
"If you got timer trouble "
183 "try acpi_use_timer_override\n");
187 static void __init
ati_bugs(int num
, int slot
, int func
)
191 static void __init
ati_bugs_contd(int num
, int slot
, int func
)
196 static void __init
intel_remapping_check(int num
, int slot
, int func
)
201 device
= read_pci_config_16(num
, slot
, func
, PCI_DEVICE_ID
);
202 revision
= read_pci_config_byte(num
, slot
, func
, PCI_REVISION_ID
);
205 * Revision 13 of all triggering devices id in this quirk have
206 * a problem draining interrupts when irq remapping is enabled,
207 * and should be flagged as broken. Additionally revisions 0x12
208 * and 0x22 of device id 0x3405 has this problem.
210 if (revision
== 0x13)
211 set_irq_remapping_broken();
212 else if ((device
== 0x3405) &&
213 ((revision
== 0x12) ||
215 set_irq_remapping_broken();
219 #define QFLAG_APPLY_ONCE 0x1
220 #define QFLAG_APPLIED 0x2
221 #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
228 void (*f
)(int num
, int slot
, int func
);
232 * Only works for devices on the root bus. If you add any devices
233 * not on bus 0 readd another loop level in early_quirks(). But
234 * be careful because at least the Nvidia quirk here relies on
235 * only matching on bus 0.
237 static struct chipset early_qrk
[] __initdata
= {
238 { PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
239 PCI_CLASS_BRIDGE_PCI
, PCI_ANY_ID
, QFLAG_APPLY_ONCE
, nvidia_bugs
},
240 { PCI_VENDOR_ID_VIA
, PCI_ANY_ID
,
241 PCI_CLASS_BRIDGE_PCI
, PCI_ANY_ID
, QFLAG_APPLY_ONCE
, via_bugs
},
242 { PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_K8_NB
,
243 PCI_CLASS_BRIDGE_HOST
, PCI_ANY_ID
, 0, fix_hypertransport_config
},
244 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP400_SMBUS
,
245 PCI_CLASS_SERIAL_SMBUS
, PCI_ANY_ID
, 0, ati_bugs
},
246 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
247 PCI_CLASS_SERIAL_SMBUS
, PCI_ANY_ID
, 0, ati_bugs_contd
},
248 { PCI_VENDOR_ID_INTEL
, 0x3403, PCI_CLASS_BRIDGE_HOST
,
249 PCI_BASE_CLASS_BRIDGE
, 0, intel_remapping_check
},
250 { PCI_VENDOR_ID_INTEL
, 0x3405, PCI_CLASS_BRIDGE_HOST
,
251 PCI_BASE_CLASS_BRIDGE
, 0, intel_remapping_check
},
252 { PCI_VENDOR_ID_INTEL
, 0x3406, PCI_CLASS_BRIDGE_HOST
,
253 PCI_BASE_CLASS_BRIDGE
, 0, intel_remapping_check
},
258 * check_dev_quirk - apply early quirks to a given PCI device
261 * @func: PCI function
263 * Check the vendor & device ID against the early quirks table.
265 * If the device is single function, let early_quirks() know so we don't
266 * poke at this device again.
268 static int __init
check_dev_quirk(int num
, int slot
, int func
)
276 class = read_pci_config_16(num
, slot
, func
, PCI_CLASS_DEVICE
);
279 return -1; /* no class, treat as single function */
281 vendor
= read_pci_config_16(num
, slot
, func
, PCI_VENDOR_ID
);
283 device
= read_pci_config_16(num
, slot
, func
, PCI_DEVICE_ID
);
285 for (i
= 0; early_qrk
[i
].f
!= NULL
; i
++) {
286 if (((early_qrk
[i
].vendor
== PCI_ANY_ID
) ||
287 (early_qrk
[i
].vendor
== vendor
)) &&
288 ((early_qrk
[i
].device
== PCI_ANY_ID
) ||
289 (early_qrk
[i
].device
== device
)) &&
290 (!((early_qrk
[i
].class ^ class) &
291 early_qrk
[i
].class_mask
))) {
292 if ((early_qrk
[i
].flags
&
293 QFLAG_DONE
) != QFLAG_DONE
)
294 early_qrk
[i
].f(num
, slot
, func
);
295 early_qrk
[i
].flags
|= QFLAG_APPLIED
;
299 type
= read_pci_config_byte(num
, slot
, func
,
307 void __init
early_quirks(void)
311 if (!early_pci_allowed())
314 /* Poor man's PCI discovery */
315 /* Only scan the root bus */
316 for (slot
= 0; slot
< 32; slot
++)
317 for (func
= 0; func
< 8; func
++) {
318 /* Only probe function 0 on single fn devices */
319 if (check_dev_quirk(0, slot
, func
))