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staging: rtl8192e: Convert cck_txbbgain_ch14_table to a table
[linux-2.6/btrfs-unstable.git] / drivers / staging / rtl8192e / r8192E_dm.c
blob319cf59c85032b2151812b6dd207a00992aa4d9e
1 /*++
2 Copyright-c Realtek Semiconductor Corp. All rights reserved.
3
4 Module Name:
5 r8192U_dm.c
6
7 Abstract:
8 HW dynamic mechanism.
9
10 Major Change History:
11 When Who What
12 ---------- --------------- -------------------------------
13 2008-05-14 amy create version 0 porting from windows code.
14
15 --*/
16 #include "r8192E.h"
17 #include "r8192E_dm.h"
18 #include "r8192E_hw.h"
19 #include "r819xE_phy.h"
20 #include "r819xE_phyreg.h"
21 #include "r8190_rtl8256.h"
22
23 #define DRV_NAME "rtl819xE"
24
25 //
26 // Indicate different AP vendor for IOT issue.
27 //
28 #ifdef RTL8190P
29 static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
30 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322};
31 static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
32 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322};
33 #else
34 #ifdef RTL8192E
35 static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
36 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322};
37 static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
38 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322};
39 #else
40 static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
41 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f, 0x5e4322};
42 static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
43 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f, 0x5e4322};
44 #endif
45 #endif
46
47 #define RTK_UL_EDCA 0xa44f
48 #define RTK_DL_EDCA 0x5e4322
49
50
51 dig_t dm_digtable;
52 // For Dynamic Rx Path Selection by Signal Strength
53 DRxPathSel DM_RxPathSelTable;
54
55
56 /*--------------------Define export function prototype-----------------------*/
57 extern void init_hal_dm(struct net_device *dev);
58 extern void deinit_hal_dm(struct net_device *dev);
59
60 extern void hal_dm_watchdog(struct net_device *dev);
61
62
63 extern void init_rate_adaptive(struct net_device *dev);
64 extern void dm_txpower_trackingcallback(struct work_struct *work);
65
66 extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
67 extern void dm_restore_dynamic_mechanism_state(struct net_device *dev);
68 extern void dm_backup_dynamic_mechanism_state(struct net_device *dev);
69 extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
70 u32 dm_type,
71 u32 dm_value);
72 extern void DM_ChangeFsyncSetting(struct net_device *dev,
73 s32 DM_Type,
74 s32 DM_Value);
75 extern void dm_force_tx_fw_info(struct net_device *dev,
76 u32 force_type,
77 u32 force_value);
78 extern void dm_init_edca_turbo(struct net_device *dev);
79 extern void dm_rf_operation_test_callback(unsigned long data);
80 extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
81 extern void dm_fsync_timer_callback(unsigned long data);
82 extern void dm_check_fsync(struct net_device *dev);
83 extern void dm_initialize_txpower_tracking(struct net_device *dev);
84
85 #ifdef RTL8192E
86 extern void dm_gpio_change_rf_callback(struct work_struct *work);
87 #endif
88
89
90 // DM --> Rate Adaptive
91 static void dm_check_rate_adaptive(struct net_device *dev);
92
93 // DM --> Bandwidth switch
94 static void dm_init_bandwidth_autoswitch(struct net_device *dev);
95 static void dm_bandwidth_autoswitch( struct net_device *dev);
96
97 // DM --> TX power control
98 static void dm_check_txpower_tracking(struct net_device *dev);
99
100 // DM --> BB init gain restore
101 #ifndef RTL8192U
102 static void dm_bb_initialgain_restore(struct net_device *dev);
103
104 // DM --> BB init gain backup
105 static void dm_bb_initialgain_backup(struct net_device *dev);
106 #endif
107
108 // DM --> Dynamic Init Gain by RSSI
109 static void dm_dig_init(struct net_device *dev);
110 static void dm_ctrl_initgain_byrssi(struct net_device *dev);
111 static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
112 static void dm_ctrl_initgain_byrssi_by_driverrssi( struct net_device *dev);
113 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
114 static void dm_initial_gain(struct net_device *dev);
115 static void dm_pd_th(struct net_device *dev);
116 static void dm_cs_ratio(struct net_device *dev);
117
118 static void dm_init_ctstoself(struct net_device *dev);
119 // DM --> EDCA turboe mode control
120 static void dm_check_edca_turbo(struct net_device *dev);
121
122 // DM --> HW RF control
123 static void dm_check_rfctrl_gpio(struct net_device *dev);
124
125 // DM --> Check PBC
126 static void dm_check_pbc_gpio(struct net_device *dev);
127
128 // DM --> Check current RX RF path state
129 static void dm_check_rx_path_selection(struct net_device *dev);
130 static void dm_init_rxpath_selection(struct net_device *dev);
131 static void dm_rxpath_sel_byrssi(struct net_device *dev);
132
133 // DM --> Fsync for broadcom ap
134 static void dm_init_fsync(struct net_device *dev);
135 static void dm_deInit_fsync(struct net_device *dev);
136
137 static void dm_check_txrateandretrycount(struct net_device *dev);
138
139
140 /*---------------------Define of Tx Power Control For Near/Far Range --------*/ //Add by Jacken 2008/02/18
141 static void dm_init_dynamic_txpower(struct net_device *dev);
142 static void dm_dynamic_txpower(struct net_device *dev);
143
144 // DM --> For rate adaptive and DIG, we must send RSSI to firmware
145 static void dm_send_rssi_tofw(struct net_device *dev);
146 static void dm_ctstoself(struct net_device *dev);
147
148 /*
149 * Prepare SW resource for HW dynamic mechanism.
150 * This function is only invoked at driver intialization once.
151 */
152 void init_hal_dm(struct net_device *dev)
153 {
154 struct r8192_priv *priv = ieee80211_priv(dev);
155
156 // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism.
157 priv->undecorated_smoothed_pwdb = -1;
158
159 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
160 dm_init_dynamic_txpower(dev);
161 init_rate_adaptive(dev);
162 //dm_initialize_txpower_tracking(dev);
163 dm_dig_init(dev);
164 dm_init_edca_turbo(dev);
165 dm_init_bandwidth_autoswitch(dev);
166 dm_init_fsync(dev);
167 dm_init_rxpath_selection(dev);
168 dm_init_ctstoself(dev);
169 #ifdef RTL8192E
170 INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback);
171 #endif
172
173 }
174
175 void deinit_hal_dm(struct net_device *dev)
176 {
177
178 dm_deInit_fsync(dev);
179
180 }
181
182
183 #ifdef USB_RX_AGGREGATION_SUPPORT
184 void dm_CheckRxAggregation(struct net_device *dev) {
185 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
186 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
187 static unsigned long lastTxOkCnt = 0;
188 static unsigned long lastRxOkCnt = 0;
189 unsigned long curTxOkCnt = 0;
190 unsigned long curRxOkCnt = 0;
191
192 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
193 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
194
195 if((curTxOkCnt + curRxOkCnt) < 15000000) {
196 return;
197 }
198
199 if(curTxOkCnt > 4*curRxOkCnt) {
200 if (priv->bCurrentRxAggrEnable) {
201 write_nic_dword(dev, 0x1a8, 0);
202 priv->bCurrentRxAggrEnable = false;
203 }
204 }else{
205 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
206 u32 ulValue;
207 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
208 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
209 /*
210 * If usb rx firmware aggregation is enabled,
211 * when anyone of three threshold conditions above is reached,
212 * firmware will send aggregated packet to driver.
213 */
214 write_nic_dword(dev, 0x1a8, ulValue);
215 priv->bCurrentRxAggrEnable = true;
216 }
217 }
218
219 lastTxOkCnt = priv->stats.txbytesunicast;
220 lastRxOkCnt = priv->stats.rxbytesunicast;
221 }
222 #endif
223
224
225 // call the script file to enable
226 void dm_check_ac_dc_power(struct net_device *dev)
227 {
228 struct r8192_priv *priv = ieee80211_priv(dev);
229 static char *ac_dc_check_script_path = "/etc/acpi/wireless-rtl-ac-dc-power.sh";
230 char *argv[] = {ac_dc_check_script_path,DRV_NAME,NULL};
231 static char *envp[] = {"HOME=/",
232 "TERM=linux",
233 "PATH=/usr/bin:/bin",
234 NULL};
235
236 if(priv->ResetProgress == RESET_TYPE_SILENT)
237 {
238 RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF), "GPIOChangeRFWorkItemCallBack(): Silent Reseting!!!!!!!\n");
239 return;
240 }
241
242 if(priv->ieee80211->state != IEEE80211_LINKED) {
243 return;
244 }
245 call_usermodehelper(ac_dc_check_script_path,argv,envp,1);
246 }
247
248 void hal_dm_watchdog(struct net_device *dev)
249 {
250 dm_check_ac_dc_power(dev);
251
252 /*Add by amy 2008/05/15 ,porting from windows code.*/
253 dm_check_rate_adaptive(dev);
254 dm_dynamic_txpower(dev);
255 dm_check_txrateandretrycount(dev);
256
257 dm_check_txpower_tracking(dev);
258
259 dm_ctrl_initgain_byrssi(dev);
260 dm_check_edca_turbo(dev);
261 dm_bandwidth_autoswitch(dev);
262
263 dm_check_rfctrl_gpio(dev);
264 dm_check_rx_path_selection(dev);
265 dm_check_fsync(dev);
266
267 // Add by amy 2008-05-15 porting from windows code.
268 dm_check_pbc_gpio(dev);
269 dm_send_rssi_tofw(dev);
270 dm_ctstoself(dev);
271
272 #ifdef USB_RX_AGGREGATION_SUPPORT
273 dm_CheckRxAggregation(dev);
274 #endif
275 }
276
277
278 /*
279 * Decide Rate Adaptive Set according to distance (signal strength)
280 * 01/11/2008 MHC Modify input arguments and RATR table level.
281 * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call
282 * the function after making sure RF_Type.
283 */
284 void init_rate_adaptive(struct net_device * dev)
285 {
286
287 struct r8192_priv *priv = ieee80211_priv(dev);
288 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
289
290 pra->ratr_state = DM_RATR_STA_MAX;
291 pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High;
292 pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5;
293 pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5;
294
295 pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5;
296 pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M;
297 pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M;
298
299 if(priv->CustomerID == RT_CID_819x_Netcore)
300 pra->ping_rssi_enable = 1;
301 else
302 pra->ping_rssi_enable = 0;
303 pra->ping_rssi_thresh_for_ra = 15;
304
305
306 if (priv->rf_type == RF_2T4R)
307 {
308 // 07/10/08 MH Modify for RA smooth scheme.
309 /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/
310 pra->upper_rssi_threshold_ratr = 0x8f0f0000;
311 pra->middle_rssi_threshold_ratr = 0x8f0ff000;
312 pra->low_rssi_threshold_ratr = 0x8f0ff001;
313 pra->low_rssi_threshold_ratr_40M = 0x8f0ff005;
314 pra->low_rssi_threshold_ratr_20M = 0x8f0ff001;
315 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
316 }
317 else if (priv->rf_type == RF_1T2R)
318 {
319 pra->upper_rssi_threshold_ratr = 0x000f0000;
320 pra->middle_rssi_threshold_ratr = 0x000ff000;
321 pra->low_rssi_threshold_ratr = 0x000ff001;
322 pra->low_rssi_threshold_ratr_40M = 0x000ff005;
323 pra->low_rssi_threshold_ratr_20M = 0x000ff001;
324 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
325 }
326
327 }
328
329
330 static void dm_check_rate_adaptive(struct net_device * dev)
331 {
332 struct r8192_priv *priv = ieee80211_priv(dev);
333 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
334 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
335 u32 currentRATR, targetRATR = 0;
336 u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
337 bool bshort_gi_enabled = false;
338 static u8 ping_rssi_state=0;
339
340
341 if(!priv->up)
342 {
343 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
344 return;
345 }
346
347 if(pra->rate_adaptive_disabled)//this variable is set by ioctl.
348 return;
349
350 // TODO: Only 11n mode is implemented currently,
351 if( !(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
352 priv->ieee80211->mode == WIRELESS_MODE_N_5G))
353 return;
354
355 if( priv->ieee80211->state == IEEE80211_LINKED )
356 {
357 // RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");
358
359 //
360 // Check whether Short GI is enabled
361 //
362 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
363 (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
364
365
366 pra->upper_rssi_threshold_ratr =
367 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
368
369 pra->middle_rssi_threshold_ratr =
370 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
371
372 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
373 {
374 pra->low_rssi_threshold_ratr =
375 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
376 }
377 else
378 {
379 pra->low_rssi_threshold_ratr =
380 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
381 }
382 //cosa add for test
383 pra->ping_rssi_ratr =
384 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
385
386 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
387 time to link with AP. We will not change upper/lower threshold. If
388 STA stay in high or low level, we must change two different threshold
389 to prevent jumping frequently. */
390 if (pra->ratr_state == DM_RATR_STA_HIGH)
391 {
392 HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra;
393 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
394 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
395 }
396 else if (pra->ratr_state == DM_RATR_STA_LOW)
397 {
398 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
399 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
400 (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
401 }
402 else
403 {
404 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
405 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
406 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
407 }
408
409 //DbgPrint("[DM] Thresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);
410 if(priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA)
411 {
412 //DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);
413 pra->ratr_state = DM_RATR_STA_HIGH;
414 targetRATR = pra->upper_rssi_threshold_ratr;
415 }else if(priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA)
416 {
417 //DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);
418 pra->ratr_state = DM_RATR_STA_MIDDLE;
419 targetRATR = pra->middle_rssi_threshold_ratr;
420 }else
421 {
422 //DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);
423 pra->ratr_state = DM_RATR_STA_LOW;
424 targetRATR = pra->low_rssi_threshold_ratr;
425 }
426
427 //cosa add for test
428 if(pra->ping_rssi_enable)
429 {
430 //pHalData->UndecoratedSmoothedPWDB = 19;
431 if(priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5))
432 {
433 if( (priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
434 ping_rssi_state )
435 {
436 //DbgPrint("TestRSSI = %d, set RATR to 0x%x \n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);
437 pra->ratr_state = DM_RATR_STA_LOW;
438 targetRATR = pra->ping_rssi_ratr;
439 ping_rssi_state = 1;
440 }
441 //else
442 // DbgPrint("TestRSSI is between the range. \n");
443 }
444 else
445 {
446 //DbgPrint("TestRSSI Recover to 0x%x \n", targetRATR);
447 ping_rssi_state = 0;
448 }
449 }
450
451 // 2008.04.01
452 #if 1
453 // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
454 if(priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
455 targetRATR &= 0xf00fffff;
456 #endif
457
458 //
459 // Check whether updating of RATR0 is required
460 //
461 currentRATR = read_nic_dword(dev, RATR0);
462 if( targetRATR != currentRATR )
463 {
464 u32 ratr_value;
465 ratr_value = targetRATR;
466 RT_TRACE(COMP_RATE,"currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
467 if(priv->rf_type == RF_1T2R)
468 {
469 ratr_value &= ~(RATE_ALL_OFDM_2SS);
470 }
471 write_nic_dword(dev, RATR0, ratr_value);
472 write_nic_byte(dev, UFWP, 1);
473
474 pra->last_ratr = targetRATR;
475 }
476
477 }
478 else
479 {
480 pra->ratr_state = DM_RATR_STA_MAX;
481 }
482
483 }
484
485
486 static void dm_init_bandwidth_autoswitch(struct net_device * dev)
487 {
488 struct r8192_priv *priv = ieee80211_priv(dev);
489
490 priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
491 priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
492 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
493 priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
494
495 }
496
497
498 static void dm_bandwidth_autoswitch(struct net_device * dev)
499 {
500 struct r8192_priv *priv = ieee80211_priv(dev);
501
502 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ||!priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable){
503 return;
504 }else{
505 if(priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz == false){//If send packets in 40 Mhz in 20/40
506 if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
507 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
508 }else{//in force send packets in 20 Mhz in 20/40
509 if(priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
510 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
511
512 }
513 }
514 }
515
516 //OFDM default at 0db, index=6.
517 #ifndef RTL8190P
518 static const u32 OFDMSwingTable[OFDM_Table_Length] = {
519 0x7f8001fe, // 0, +6db
520 0x71c001c7, // 1, +5db
521 0x65400195, // 2, +4db
522 0x5a400169, // 3, +3db
523 0x50800142, // 4, +2db
524 0x47c0011f, // 5, +1db
525 0x40000100, // 6, +0db ===> default, upper for higher temperature, lower for low temperature
526 0x390000e4, // 7, -1db
527 0x32c000cb, // 8, -2db
528 0x2d4000b5, // 9, -3db
529 0x288000a2, // 10, -4db
530 0x24000090, // 11, -5db
531 0x20000080, // 12, -6db
532 0x1c800072, // 13, -7db
533 0x19800066, // 14, -8db
534 0x26c0005b, // 15, -9db
535 0x24400051, // 16, -10db
536 0x12000048, // 17, -11db
537 0x10000040 // 18, -12db
538 };
539 static const u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
540 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0db ===> CCK40M default
541 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 1, -1db
542 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 2, -2db
543 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 3, -3db
544 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 4, -4db
545 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 5, -5db
546 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 6, -6db ===> CCK20M default
547 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 7, -7db
548 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 8, -8db
549 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 9, -9db
550 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 10, -10db
551 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} // 11, -11db
552 };
553
554 static const u8 CCKSwingTable_Ch14[CCK_Table_length][8] = {
555 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0db ===> CCK40M default
556 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 1, -1db
557 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 2, -2db
558 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 3, -3db
559 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 4, -4db
560 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 5, -5db
561 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 6, -6db ===> CCK20M default
562 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 7, -7db
563 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 8, -8db
564 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 9, -9db
565 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db
566 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db
567 };
568 #endif
569 #define Pw_Track_Flag 0x11d
570 #define Tssi_Mea_Value 0x13c
571 #define Tssi_Report_Value1 0x134
572 #define Tssi_Report_Value2 0x13e
573 #define FW_Busy_Flag 0x13f
574 static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
575 {
576 struct r8192_priv *priv = ieee80211_priv(dev);
577 bool bHighpowerstate, viviflag = FALSE;
578 DCMD_TXCMD_T tx_cmd;
579 u8 powerlevelOFDM24G;
580 int i =0, j = 0, k = 0;
581 u8 RF_Type, tmp_report[5]={0, 0, 0, 0, 0};
582 u32 Value;
583 u8 Pwr_Flag;
584 u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0;
585 #ifdef RTL8192U
586 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
587 #endif
588 // bool rtStatus = true;
589 u32 delta=0;
590 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
591 // write_nic_byte(dev, 0x1ba, 0);
592 write_nic_byte(dev, Pw_Track_Flag, 0);
593 write_nic_byte(dev, FW_Busy_Flag, 0);
594 priv->ieee80211->bdynamic_txpower_enable = false;
595 bHighpowerstate = priv->bDynamicTxHighPower;
596
597 powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
598 RF_Type = priv->rf_type;
599 Value = (RF_Type<<8) | powerlevelOFDM24G;
600
601 RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
602
603 for(j = 0; j<=30; j++)
604 { //fill tx_cmd
605
606 tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING;
607 tx_cmd.Length = 4;
608 tx_cmd.Value = Value;
609 #ifdef RTL8192U
610 rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12);
611 if (rtStatus == RT_STATUS_FAILURE)
612 {
613 RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
614 }
615 #else
616 cmpk_message_handle_tx(dev, (u8*)&tx_cmd, DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
617 #endif
618 mdelay(1);
619 //DbgPrint("hi, vivi, strange\n");
620 for(i = 0;i <= 30; i++)
621 {
622 Pwr_Flag = read_nic_byte(dev, Pw_Track_Flag);
623
624 if (Pwr_Flag == 0)
625 {
626 mdelay(1);
627 continue;
628 }
629
630 Avg_TSSI_Meas = read_nic_word(dev, Tssi_Mea_Value);
631
632 if(Avg_TSSI_Meas == 0)
633 {
634 write_nic_byte(dev, Pw_Track_Flag, 0);
635 write_nic_byte(dev, FW_Busy_Flag, 0);
636 return;
637 }
638
639 for(k = 0;k < 5; k++)
640 {
641 if(k !=4)
642 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value1+k);
643 else
644 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value2);
645
646 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
647 }
648
649 //check if the report value is right
650 for(k = 0;k < 5; k++)
651 {
652 if(tmp_report[k] <= 20)
653 {
654 viviflag =TRUE;
655 break;
656 }
657 }
658 if(viviflag ==TRUE)
659 {
660 write_nic_byte(dev, Pw_Track_Flag, 0);
661 viviflag = FALSE;
662 RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n");
663 for(k = 0;k < 5; k++)
664 tmp_report[k] = 0;
665 break;
666 }
667
668 for(k = 0;k < 5; k++)
669 {
670 Avg_TSSI_Meas_from_driver += tmp_report[k];
671 }
672
673 Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
674 RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
675 TSSI_13dBm = priv->TSSI_13dBm;
676 RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
677
678 //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)
679 // For MacOS-compatible
680 if(Avg_TSSI_Meas_from_driver > TSSI_13dBm)
681 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
682 else
683 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
684
685 if(delta <= E_FOR_TX_POWER_TRACK)
686 {
687 priv->ieee80211->bdynamic_txpower_enable = TRUE;
688 write_nic_byte(dev, Pw_Track_Flag, 0);
689 write_nic_byte(dev, FW_Busy_Flag, 0);
690 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
691 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
692 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
693 #ifdef RTL8190P
694 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
695 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
696 #endif
697 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
698 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
699 return;
700 }
701 else
702 {
703 if(Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK)
704 {
705 if (RF_Type == RF_2T4R)
706 {
707
708 if((priv->rfa_txpowertrackingindex > 0) &&(priv->rfc_txpowertrackingindex > 0))
709 {
710 priv->rfa_txpowertrackingindex--;
711 if(priv->rfa_txpowertrackingindex_real > 4)
712 {
713 priv->rfa_txpowertrackingindex_real--;
714 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
715 }
716
717 priv->rfc_txpowertrackingindex--;
718 if(priv->rfc_txpowertrackingindex_real > 4)
719 {
720 priv->rfc_txpowertrackingindex_real--;
721 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
722 }
723 }
724 else
725 {
726 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
727 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
728 }
729 }
730 else
731 {
732 if(priv->rfc_txpowertrackingindex > 0)
733 {
734 priv->rfc_txpowertrackingindex--;
735 if(priv->rfc_txpowertrackingindex_real > 4)
736 {
737 priv->rfc_txpowertrackingindex_real--;
738 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
739 }
740 }
741 else
742 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
743 }
744 }
745 else
746 {
747 if (RF_Type == RF_2T4R)
748 {
749 if((priv->rfa_txpowertrackingindex < TxBBGainTableLength - 1) &&(priv->rfc_txpowertrackingindex < TxBBGainTableLength - 1))
750 {
751 priv->rfa_txpowertrackingindex++;
752 priv->rfa_txpowertrackingindex_real++;
753 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
754 priv->rfc_txpowertrackingindex++;
755 priv->rfc_txpowertrackingindex_real++;
756 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
757 }
758 else
759 {
760 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
761 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
762 }
763 }
764 else
765 {
766 if(priv->rfc_txpowertrackingindex < (TxBBGainTableLength - 1))
767 {
768 priv->rfc_txpowertrackingindex++;
769 priv->rfc_txpowertrackingindex_real++;
770 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
771 }
772 else
773 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
774 }
775 }
776 if (RF_Type == RF_2T4R)
777 priv->CCKPresentAttentuation_difference
778 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
779 else
780 priv->CCKPresentAttentuation_difference
781 = priv->rfc_txpowertrackingindex - priv->rfc_txpowertracking_default;
782
783 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
784 priv->CCKPresentAttentuation
785 = priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
786 else
787 priv->CCKPresentAttentuation
788 = priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
789
790 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
791 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
792 if(priv->CCKPresentAttentuation < 0)
793 priv->CCKPresentAttentuation = 0;
794
795 if(1)
796 {
797 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
798 {
799 priv->bcck_in_ch14 = TRUE;
800 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
801 }
802 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
803 {
804 priv->bcck_in_ch14 = FALSE;
805 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
806 }
807 else
808 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
809 }
810 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
811 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
812 #ifdef RTL8190P
813 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
814 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
815 #endif
816 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
817 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
818
819 if (priv->CCKPresentAttentuation_difference <= -12||priv->CCKPresentAttentuation_difference >= 24)
820 {
821 priv->ieee80211->bdynamic_txpower_enable = TRUE;
822 write_nic_byte(dev, Pw_Track_Flag, 0);
823 write_nic_byte(dev, FW_Busy_Flag, 0);
824 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
825 return;
826 }
827
828
829 }
830 write_nic_byte(dev, Pw_Track_Flag, 0);
831 Avg_TSSI_Meas_from_driver = 0;
832 for(k = 0;k < 5; k++)
833 tmp_report[k] = 0;
834 break;
835 }
836 write_nic_byte(dev, FW_Busy_Flag, 0);
837 }
838 priv->ieee80211->bdynamic_txpower_enable = TRUE;
839 write_nic_byte(dev, Pw_Track_Flag, 0);
840 }
841 #ifndef RTL8190P
842 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
843 {
844 #define ThermalMeterVal 9
845 struct r8192_priv *priv = ieee80211_priv(dev);
846 u32 tmpRegA, TempCCk;
847 u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
848 int i =0, CCKSwingNeedUpdate=0;
849
850 if(!priv->btxpower_trackingInit)
851 {
852 //Query OFDM default setting
853 tmpRegA= rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
854 for(i=0; i<OFDM_Table_Length; i++) //find the index
855 {
856 if(tmpRegA == OFDMSwingTable[i])
857 {
858 priv->OFDM_index= (u8)i;
859 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
860 rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
861 }
862 }
863
864 //Query CCK default setting From 0xa22
865 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
866 for(i=0 ; i<CCK_Table_length ; i++)
867 {
868 if(TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0])
869 {
870 priv->CCK_index =(u8) i;
871 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
872 rCCK0_TxFilter1, TempCCk, priv->CCK_index);
873 break;
874 }
875 }
876 priv->btxpower_trackingInit = TRUE;
877 //pHalData->TXPowercount = 0;
878 return;
879 }
880
881 // read and filter out unreasonable value
882 tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7]
883 RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d \n", tmpRegA);
884 if(tmpRegA < 3 || tmpRegA > 13)
885 return;
886 if(tmpRegA >= 12) // if over 12, TP will be bad when high temperature
887 tmpRegA = 12;
888 RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d \n", tmpRegA);
889 priv->ThermalMeter[0] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
890 priv->ThermalMeter[1] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
891
892 //Get current RF-A temperature index
893 if(priv->ThermalMeter[0] >= (u8)tmpRegA) //lower temperature
894 {
895 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
896 tmpCCK40Mindex = tmpCCK20Mindex - 6;
897 if(tmpOFDMindex >= OFDM_Table_Length)
898 tmpOFDMindex = OFDM_Table_Length-1;
899 if(tmpCCK20Mindex >= CCK_Table_length)
900 tmpCCK20Mindex = CCK_Table_length-1;
901 if(tmpCCK40Mindex >= CCK_Table_length)
902 tmpCCK40Mindex = CCK_Table_length-1;
903 }
904 else
905 {
906 tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]);
907 if(tmpval >= 6) // higher temperature
908 tmpOFDMindex = tmpCCK20Mindex = 0; // max to +6dB
909 else
910 tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval;
911 tmpCCK40Mindex = 0;
912 }
913 //DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
914 //((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
915 //tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);
916 if(priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) //40M
917 tmpCCKindex = tmpCCK40Mindex;
918 else
919 tmpCCKindex = tmpCCK20Mindex;
920
921 //record for bandwidth swith
922 priv->Record_CCK_20Mindex = tmpCCK20Mindex;
923 priv->Record_CCK_40Mindex = tmpCCK40Mindex;
924 RT_TRACE(COMP_POWER_TRACKING, "Record_CCK_20Mindex / Record_CCK_40Mindex = %d / %d.\n",
925 priv->Record_CCK_20Mindex, priv->Record_CCK_40Mindex);
926
927 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
928 {
929 priv->bcck_in_ch14 = TRUE;
930 CCKSwingNeedUpdate = 1;
931 }
932 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
933 {
934 priv->bcck_in_ch14 = FALSE;
935 CCKSwingNeedUpdate = 1;
936 }
937
938 if(priv->CCK_index != tmpCCKindex)
939 {
940 priv->CCK_index = tmpCCKindex;
941 CCKSwingNeedUpdate = 1;
942 }
943
944 if(CCKSwingNeedUpdate)
945 {
946 //DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);
947 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
948 }
949 if(priv->OFDM_index != tmpOFDMindex)
950 {
951 priv->OFDM_index = tmpOFDMindex;
952 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
953 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
954 priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
955 }
956 priv->txpower_count = 0;
957 }
958 #endif
959 void dm_txpower_trackingcallback(struct work_struct *work)
960 {
961 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
962 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq);
963 struct net_device *dev = priv->ieee80211->dev;
964
965 #ifdef RTL8190P
966 dm_TXPowerTrackingCallback_TSSI(dev);
967 #else
968 //if(priv->bDcut == TRUE)
969 if(priv->IC_Cut >= IC_VersionCut_D)
970 dm_TXPowerTrackingCallback_TSSI(dev);
971 else
972 dm_TXPowerTrackingCallback_ThermalMeter(dev);
973 #endif
974 }
975
976
977 static const txbbgain_struct rtl8192_txbbgain_table[] = {
978 { 12, 0x7f8001fe },
979 { 11, 0x788001e2 },
980 { 10, 0x71c001c7 },
981 { 9, 0x6b8001ae },
982 { 8, 0x65400195 },
983 { 7, 0x5fc0017f },
984 { 6, 0x5a400169 },
985 { 5, 0x55400155 },
986 { 4, 0x50800142 },
987 { 3, 0x4c000130 },
988 { 2, 0x47c0011f },
989 { 1, 0x43c0010f },
990 { 0, 0x40000100 },
991 { -1, 0x3c8000f2 },
992 { -2, 0x390000e4 },
993 { -3, 0x35c000d7 },
994 { -4, 0x32c000cb },
995 { -5, 0x300000c0 },
996 { -6, 0x2d4000b5 },
997 { -7, 0x2ac000ab },
998 { -8, 0x288000a2 },
999 { -9, 0x26000098 },
1000 { -10, 0x24000090 },
1001 { -11, 0x22000088 },
1002 { -12, 0x20000080 },
1003 { -13, 0x1a00006c },
1004 { -14, 0x1c800072 },
1005 { -15, 0x18000060 },
1006 { -16, 0x19800066 },
1007 { -17, 0x15800056 },
1008 { -18, 0x26c0005b },
1009 { -19, 0x14400051 },
1010 { -20, 0x24400051 },
1011 { -21, 0x1300004c },
1012 { -22, 0x12000048 },
1013 { -23, 0x11000044 },
1014 { -24, 0x10000040 },
1015 };
1016
1017 /*
1018 * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1019 * This Table is for CH1~CH13
1020 */
1021 static const ccktxbbgain_struct rtl8192_cck_txbbgain_table[] = {
1022 {{ 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 }},
1023 {{ 0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04 }},
1024 {{ 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03 }},
1025 {{ 0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03 }},
1026 {{ 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 }},
1027 {{ 0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03 }},
1028 {{ 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 }},
1029 {{ 0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03 }},
1030 {{ 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02 }},
1031 {{ 0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02 }},
1032 {{ 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02 }},
1033 {{ 0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02 }},
1034 {{ 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02 }},
1035 {{ 0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02 }},
1036 {{ 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02 }},
1037 {{ 0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02 }},
1038 {{ 0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01 }},
1039 {{ 0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02 }},
1040 {{ 0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01 }},
1041 {{ 0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01 }},
1042 {{ 0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01 }},
1043 {{ 0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01 }},
1044 {{ 0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01 }},
1045 };
1046
1047 /*
1048 * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1049 * This Table is for CH14
1050 */
1051 static const ccktxbbgain_struct rtl8192_cck_txbbgain_ch14_table[] = {
1052 {{ 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 }},
1053 {{ 0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00 }},
1054 {{ 0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00 }},
1055 {{ 0x2d, 0x2d, 0x27, 0x17, 0x00, 0x00, 0x00, 0x00 }},
1056 {{ 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 }},
1057 {{ 0x28, 0x28, 0x22, 0x14, 0x00, 0x00, 0x00, 0x00 }},
1058 {{ 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00 }},
1059 {{ 0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00 }},
1060 {{ 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00 }},
1061 {{ 0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00 }},
1062 {{ 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00 }},
1063 {{ 0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00 }},
1064 {{ 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00 }},
1065 {{ 0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00 }},
1066 {{ 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00 }},
1067 {{ 0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00 }},
1068 {{ 0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00 }},
1069 {{ 0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00 }},
1070 {{ 0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00 }},
1071 {{ 0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00 }},
1072 {{ 0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00 }},
1073 {{ 0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00 }},
1074 {{ 0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00 }},
1075 };
1076
1077 static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
1078 {
1079 struct r8192_priv *priv = ieee80211_priv(dev);
1080
1081 priv->txbbgain_table = rtl8192_txbbgain_table;
1082 priv->cck_txbbgain_table = rtl8192_cck_txbbgain_table;
1083 priv->cck_txbbgain_ch14_table = rtl8192_cck_txbbgain_ch14_table;
1084
1085 priv->btxpower_tracking = TRUE;
1086 priv->txpower_count = 0;
1087 priv->btxpower_trackingInit = FALSE;
1088
1089 }
1090 #ifndef RTL8190P
1091 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1092 {
1093 struct r8192_priv *priv = ieee80211_priv(dev);
1094
1095 // Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism
1096 // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1097 // 3-wire by driver cause RF goes into wrong state.
1098 if(priv->ieee80211->FwRWRF)
1099 priv->btxpower_tracking = TRUE;
1100 else
1101 priv->btxpower_tracking = FALSE;
1102 priv->txpower_count = 0;
1103 priv->btxpower_trackingInit = FALSE;
1104 }
1105 #endif
1106
1107 void dm_initialize_txpower_tracking(struct net_device *dev)
1108 {
1109 #ifndef RTL8190P
1110 struct r8192_priv *priv = ieee80211_priv(dev);
1111 #endif
1112 #ifdef RTL8190P
1113 dm_InitializeTXPowerTracking_TSSI(dev);
1114 #else
1115 if(priv->IC_Cut >= IC_VersionCut_D)
1116 dm_InitializeTXPowerTracking_TSSI(dev);
1117 else
1118 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1119 #endif
1120 }
1121
1122
1123 static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1124 {
1125 struct r8192_priv *priv = ieee80211_priv(dev);
1126 static u32 tx_power_track_counter = 0;
1127 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
1128 if(read_nic_byte(dev, 0x11e) ==1)
1129 return;
1130 if(!priv->btxpower_tracking)
1131 return;
1132 tx_power_track_counter++;
1133
1134 if (tx_power_track_counter > 90) {
1135 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1136 tx_power_track_counter =0;
1137 }
1138 }
1139
1140 #ifndef RTL8190P
1141 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1142 {
1143 struct r8192_priv *priv = ieee80211_priv(dev);
1144 static u8 TM_Trigger=0;
1145
1146 //DbgPrint("dm_CheckTXPowerTracking() \n");
1147 if(!priv->btxpower_tracking)
1148 return;
1149 else
1150 {
1151 if(priv->txpower_count <= 2)
1152 {
1153 priv->txpower_count++;
1154 return;
1155 }
1156 }
1157
1158 if(!TM_Trigger)
1159 {
1160 //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash
1161 //actually write reg0x02 bit1=0, then bit1=1.
1162 //DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1163 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1164 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1165 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1166 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1167 TM_Trigger = 1;
1168 return;
1169 }
1170 else {
1171 //DbgPrint("Schedule TxPowerTrackingWorkItem\n");
1172 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1173 TM_Trigger = 0;
1174 }
1175 }
1176 #endif
1177
1178 static void dm_check_txpower_tracking(struct net_device *dev)
1179 {
1180 #ifndef RTL8190P
1181 struct r8192_priv *priv = ieee80211_priv(dev);
1182 //static u32 tx_power_track_counter = 0;
1183 #endif
1184 #ifdef RTL8190P
1185 dm_CheckTXPowerTracking_TSSI(dev);
1186 #else
1187 //if(priv->bDcut == TRUE)
1188 if(priv->IC_Cut >= IC_VersionCut_D)
1189 dm_CheckTXPowerTracking_TSSI(dev);
1190 else
1191 dm_CheckTXPowerTracking_ThermalMeter(dev);
1192 #endif
1193
1194 }
1195
1196
1197 static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14)
1198 {
1199 u32 TempVal;
1200 struct r8192_priv *priv = ieee80211_priv(dev);
1201 //Write 0xa22 0xa23
1202 TempVal = 0;
1203 if(!bInCH14){
1204 //Write 0xa22 0xa23
1205 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1206 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1207
1208 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1209 //Write 0xa24 ~ 0xa27
1210 TempVal = 0;
1211 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1212 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1213 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1214 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1215 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1216 //Write 0xa28 0xa29
1217 TempVal = 0;
1218 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1219 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1220
1221 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1222 }
1223 else
1224 {
1225 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1226 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1227
1228 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1229 //Write 0xa24 ~ 0xa27
1230 TempVal = 0;
1231 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1232 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1233 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1234 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1235 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1236 //Write 0xa28 0xa29
1237 TempVal = 0;
1238 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1239 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1240
1241 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1242 }
1243
1244
1245 }
1246 #ifndef RTL8190P
1247 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14)
1248 {
1249 u32 TempVal;
1250 struct r8192_priv *priv = ieee80211_priv(dev);
1251
1252 TempVal = 0;
1253 if(!bInCH14)
1254 {
1255 //Write 0xa22 0xa23
1256 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1257 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ;
1258 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1259 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1260 rCCK0_TxFilter1, TempVal);
1261 //Write 0xa24 ~ 0xa27
1262 TempVal = 0;
1263 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1264 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1265 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16 )+
1266 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1267 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1268 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1269 rCCK0_TxFilter2, TempVal);
1270 //Write 0xa28 0xa29
1271 TempVal = 0;
1272 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1273 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ;
1274
1275 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1276 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1277 rCCK0_DebugPort, TempVal);
1278 }
1279 else
1280 {
1281 // priv->CCKTxPowerAdjustCntNotCh14++; //cosa add for debug.
1282 //Write 0xa22 0xa23
1283 TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
1284 (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ;
1285
1286 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1287 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1288 rCCK0_TxFilter1, TempVal);
1289 //Write 0xa24 ~ 0xa27
1290 TempVal = 0;
1291 TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] +
1292 (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1293 (CCKSwingTable_Ch14[priv->CCK_index][4]<<16 )+
1294 (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1295 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1296 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1297 rCCK0_TxFilter2, TempVal);
1298 //Write 0xa28 0xa29
1299 TempVal = 0;
1300 TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] +
1301 (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ;
1302
1303 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1304 RT_TRACE(COMP_POWER_TRACKING,"CCK chnl 14, reg 0x%x = 0x%x\n",
1305 rCCK0_DebugPort, TempVal);
1306 }
1307 }
1308 #endif
1309
1310
1311 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1312 {
1313 #ifndef RTL8190P
1314 struct r8192_priv *priv = ieee80211_priv(dev);
1315 #endif
1316 #ifdef RTL8190P
1317 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1318 #else
1319 if(priv->IC_Cut >= IC_VersionCut_D)
1320 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1321 else
1322 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1323 #endif
1324 }
1325
1326
1327 #ifndef RTL8192U
1328 static void dm_txpower_reset_recovery(
1329 struct net_device *dev
1330 )
1331 {
1332 struct r8192_priv *priv = ieee80211_priv(dev);
1333
1334 RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1335 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1336 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1337 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex);
1338 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1339 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->CCKPresentAttentuation);
1340 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1341
1342 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1343 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1344 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex);
1345 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1346
1347 }
1348
1349 void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1350 {
1351 struct r8192_priv *priv = ieee80211_priv(dev);
1352 u32 reg_ratr = priv->rate_adaptive.last_ratr;
1353
1354 if(!priv->up)
1355 {
1356 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1357 return;
1358 }
1359
1360 //
1361 // Restore previous state for rate adaptive
1362 //
1363 if(priv->rate_adaptive.rate_adaptive_disabled)
1364 return;
1365 // TODO: Only 11n mode is implemented currently,
1366 if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G ||
1367 priv->ieee80211->mode==WIRELESS_MODE_N_5G))
1368 return;
1369 {
1370 /* 2007/11/15 MH Copy from 8190PCI. */
1371 u32 ratr_value;
1372 ratr_value = reg_ratr;
1373 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
1374 {
1375 ratr_value &=~ (RATE_ALL_OFDM_2SS);
1376 //DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);
1377 }
1378 //DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);
1379 //cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);
1380 write_nic_dword(dev, RATR0, ratr_value);
1381 write_nic_byte(dev, UFWP, 1);
1382 }
1383 //Resore TX Power Tracking Index
1384 if(priv->btxpower_trackingInit && priv->btxpower_tracking){
1385 dm_txpower_reset_recovery(dev);
1386 }
1387
1388 //
1389 //Restore BB Initial Gain
1390 //
1391 dm_bb_initialgain_restore(dev);
1392
1393 }
1394
1395 static void dm_bb_initialgain_restore(struct net_device *dev)
1396 {
1397 struct r8192_priv *priv = ieee80211_priv(dev);
1398 u32 bit_mask = 0x7f; //Bit0~ Bit6
1399
1400 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1401 return;
1402
1403 //Disable Initial Gain
1404 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1405 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1406 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1407 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1408 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1409 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1410 bit_mask = bMaskByte2;
1411 rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1412
1413 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1414 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1415 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1416 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1417 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1418 //Enable Initial Gain
1419 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
1420 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1421
1422 }
1423
1424
1425 void dm_backup_dynamic_mechanism_state(struct net_device *dev)
1426 {
1427 struct r8192_priv *priv = ieee80211_priv(dev);
1428
1429 // Fsync to avoid reset
1430 priv->bswitch_fsync = false;
1431 priv->bfsync_processing = false;
1432 //Backup BB InitialGain
1433 dm_bb_initialgain_backup(dev);
1434
1435 }
1436
1437
1438 static void dm_bb_initialgain_backup(struct net_device *dev)
1439 {
1440 struct r8192_priv *priv = ieee80211_priv(dev);
1441 u32 bit_mask = bMaskByte0; //Bit0~ Bit6
1442
1443 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1444 return;
1445
1446 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1447 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1448 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1449 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1450 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1451 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1452 bit_mask = bMaskByte2;
1453 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1454
1455 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1456 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1457 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1458 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1459 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1460
1461 }
1462
1463 #endif
1464
1465 void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type, u32 dm_value)
1466 {
1467 if (dm_type == DIG_TYPE_THRESH_HIGH)
1468 {
1469 dm_digtable.rssi_high_thresh = dm_value;
1470 }
1471 else if (dm_type == DIG_TYPE_THRESH_LOW)
1472 {
1473 dm_digtable.rssi_low_thresh = dm_value;
1474 }
1475 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
1476 {
1477 dm_digtable.rssi_high_power_highthresh = dm_value;
1478 }
1479 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
1480 {
1481 dm_digtable.rssi_high_power_highthresh = dm_value;
1482 }
1483 else if (dm_type == DIG_TYPE_ENABLE)
1484 {
1485 dm_digtable.dig_state = DM_STA_DIG_MAX;
1486 dm_digtable.dig_enable_flag = true;
1487 }
1488 else if (dm_type == DIG_TYPE_DISABLE)
1489 {
1490 dm_digtable.dig_state = DM_STA_DIG_MAX;
1491 dm_digtable.dig_enable_flag = false;
1492 }
1493 else if (dm_type == DIG_TYPE_DBG_MODE)
1494 {
1495 if(dm_value >= DM_DBG_MAX)
1496 dm_value = DM_DBG_OFF;
1497 dm_digtable.dbg_mode = (u8)dm_value;
1498 }
1499 else if (dm_type == DIG_TYPE_RSSI)
1500 {
1501 if(dm_value > 100)
1502 dm_value = 30;
1503 dm_digtable.rssi_val = (long)dm_value;
1504 }
1505 else if (dm_type == DIG_TYPE_ALGORITHM)
1506 {
1507 if (dm_value >= DIG_ALGO_MAX)
1508 dm_value = DIG_ALGO_BY_FALSE_ALARM;
1509 if(dm_digtable.dig_algorithm != (u8)dm_value)
1510 dm_digtable.dig_algorithm_switch = 1;
1511 dm_digtable.dig_algorithm = (u8)dm_value;
1512 }
1513 else if (dm_type == DIG_TYPE_BACKOFF)
1514 {
1515 if(dm_value > 30)
1516 dm_value = 30;
1517 dm_digtable.backoff_val = (u8)dm_value;
1518 }
1519 else if(dm_type == DIG_TYPE_RX_GAIN_MIN)
1520 {
1521 if(dm_value == 0)
1522 dm_value = 0x1;
1523 dm_digtable.rx_gain_range_min = (u8)dm_value;
1524 }
1525 else if(dm_type == DIG_TYPE_RX_GAIN_MAX)
1526 {
1527 if(dm_value > 0x50)
1528 dm_value = 0x50;
1529 dm_digtable.rx_gain_range_max = (u8)dm_value;
1530 }
1531 }
1532
1533
1534 /* Set DIG scheme init value. */
1535 static void dm_dig_init(struct net_device *dev)
1536 {
1537 struct r8192_priv *priv = ieee80211_priv(dev);
1538 /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
1539 dm_digtable.dig_enable_flag = true;
1540 dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
1541 dm_digtable.dbg_mode = DM_DBG_OFF; //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig
1542 dm_digtable.dig_algorithm_switch = 0;
1543
1544 /* 2007/10/04 MH Define init gain threshold. */
1545 dm_digtable.dig_state = DM_STA_DIG_MAX;
1546 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1547 dm_digtable.initialgain_lowerbound_state = false;
1548
1549 dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW;
1550 dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH;
1551
1552 dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
1553 dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
1554
1555 dm_digtable.rssi_val = 50; //for new dig debug rssi value
1556 dm_digtable.backoff_val = DM_DIG_BACKOFF;
1557 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
1558 if(priv->CustomerID == RT_CID_819x_Netcore)
1559 dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore;
1560 else
1561 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
1562
1563 }
1564
1565
1566 /*
1567 * Driver must monitor RSSI and notify firmware to change initial
1568 * gain according to different threshold. BB team provide the
1569 * suggested solution.
1570 */
1571 static void dm_ctrl_initgain_byrssi(struct net_device *dev)
1572 {
1573
1574 if (dm_digtable.dig_enable_flag == false)
1575 return;
1576
1577 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1578 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
1579 else if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1580 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
1581 }
1582
1583
1584 static void dm_ctrl_initgain_byrssi_by_driverrssi(
1585 struct net_device *dev)
1586 {
1587 struct r8192_priv *priv = ieee80211_priv(dev);
1588 u8 i;
1589 static u8 fw_dig=0;
1590
1591 if (dm_digtable.dig_enable_flag == false)
1592 return;
1593
1594 //DbgPrint("Dig by Sw Rssi \n");
1595 if(dm_digtable.dig_algorithm_switch) // if swithed algorithm, we have to disable FW Dig.
1596 fw_dig = 0;
1597 if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled
1598 {// FW DIG Off
1599 for(i=0; i<3; i++)
1600 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1601 fw_dig++;
1602 dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off.
1603 }
1604
1605 if(priv->ieee80211->state == IEEE80211_LINKED)
1606 dm_digtable.cur_connect_state = DIG_CONNECT;
1607 else
1608 dm_digtable.cur_connect_state = DIG_DISCONNECT;
1609
1610 //DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d \n",
1611 //DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);
1612
1613 if(dm_digtable.dbg_mode == DM_DBG_OFF)
1614 dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
1615 //DbgPrint("DM_DigTable.Rssi_val = %d \n", DM_DigTable.Rssi_val);
1616 dm_initial_gain(dev);
1617 dm_pd_th(dev);
1618 dm_cs_ratio(dev);
1619 if(dm_digtable.dig_algorithm_switch)
1620 dm_digtable.dig_algorithm_switch = 0;
1621 dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
1622
1623 }
1624
1625 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1626 struct net_device *dev)
1627 {
1628 struct r8192_priv *priv = ieee80211_priv(dev);
1629 static u32 reset_cnt = 0;
1630 u8 i;
1631
1632 if (dm_digtable.dig_enable_flag == false)
1633 return;
1634
1635 if(dm_digtable.dig_algorithm_switch)
1636 {
1637 dm_digtable.dig_state = DM_STA_DIG_MAX;
1638 // Fw DIG On.
1639 for(i=0; i<3; i++)
1640 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1641 dm_digtable.dig_algorithm_switch = 0;
1642 }
1643
1644 if (priv->ieee80211->state != IEEE80211_LINKED)
1645 return;
1646
1647 // For smooth, we can not change DIG state.
1648 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
1649 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
1650 {
1651 return;
1652 }
1653 //DbgPrint("Dig by Fw False Alarm\n");
1654 //if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)
1655 /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
1656 pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
1657 DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
1658 /* 1. When RSSI decrease, We have to judge if it is smaller than a threshold
1659 and then execute below step. */
1660 if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh))
1661 {
1662 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
1663 will be reset to init value. We must prevent the condition. */
1664 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
1665 (priv->reset_count == reset_cnt))
1666 {
1667 return;
1668 }
1669 else
1670 {
1671 reset_cnt = priv->reset_count;
1672 }
1673
1674 // If DIG is off, DIG high power state must reset.
1675 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1676 dm_digtable.dig_state = DM_STA_DIG_OFF;
1677
1678 // 1.1 DIG Off.
1679 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1680
1681 // 1.2 Set initial gain.
1682 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
1683 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
1684 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
1685 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
1686
1687 // 1.3 Lower PD_TH for OFDM.
1688 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1689 {
1690 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1691 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1692 #ifdef RTL8190P
1693 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
1694 #else
1695 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
1696 #endif
1697 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1698 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1699 */
1700 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1701
1702
1703 //else
1704 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1705 }
1706 else
1707 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1708
1709 // 1.4 Lower CS ratio for CCK.
1710 write_nic_byte(dev, 0xa0a, 0x08);
1711
1712 // 1.5 Higher EDCCA.
1713 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
1714 return;
1715
1716 }
1717
1718 /* 2. When RSSI increase, We have to judge if it is larger than a threshold
1719 and then execute below step. */
1720 if ((priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) )
1721 {
1722 u8 reset_flag = 0;
1723
1724 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
1725 (priv->reset_count == reset_cnt))
1726 {
1727 dm_ctrl_initgain_byrssi_highpwr(dev);
1728 return;
1729 }
1730 else
1731 {
1732 if (priv->reset_count != reset_cnt)
1733 reset_flag = 1;
1734
1735 reset_cnt = priv->reset_count;
1736 }
1737
1738 dm_digtable.dig_state = DM_STA_DIG_ON;
1739 //DbgPrint("DIG ON\n\r");
1740
1741 // 2.1 Set initial gain.
1742 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
1743 if (reset_flag == 1)
1744 {
1745 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
1746 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
1747 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
1748 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
1749 }
1750 else
1751 {
1752 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
1753 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
1754 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
1755 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
1756 }
1757
1758 // 2.2 Higher PD_TH for OFDM.
1759 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1760 {
1761 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1762 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1763 #ifdef RTL8190P
1764 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1765 #else
1766 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1767 #endif
1768 /*
1769 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1770 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1771 */
1772 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1773
1774 //else
1775 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
1776 }
1777 else
1778 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1779
1780 // 2.3 Higher CS ratio for CCK.
1781 write_nic_byte(dev, 0xa0a, 0xcd);
1782
1783 // 2.4 Lower EDCCA.
1784 /* 2008/01/11 MH 90/92 series are the same. */
1785 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);
1786
1787 // 2.5 DIG On.
1788 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1789
1790 }
1791
1792 dm_ctrl_initgain_byrssi_highpwr(dev);
1793
1794 }
1795
1796 static void dm_ctrl_initgain_byrssi_highpwr(
1797 struct net_device * dev)
1798 {
1799 struct r8192_priv *priv = ieee80211_priv(dev);
1800 static u32 reset_cnt_highpwr = 0;
1801
1802 // For smooth, we can not change high power DIG state in the range.
1803 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
1804 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
1805 {
1806 return;
1807 }
1808
1809 /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
1810 it is larger than a threshold and then execute below step. */
1811 // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
1812 if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh)
1813 {
1814 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
1815 (priv->reset_count == reset_cnt_highpwr))
1816 return;
1817 else
1818 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
1819
1820 // 3.1 Higher PD_TH for OFDM for high power state.
1821 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1822 {
1823 #ifdef RTL8190P
1824 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
1825 #else
1826 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
1827 #endif
1828
1829 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1830 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
1831 */
1832
1833 }
1834 else
1835 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
1836 }
1837 else
1838 {
1839 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF&&
1840 (priv->reset_count == reset_cnt_highpwr))
1841 return;
1842 else
1843 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
1844
1845 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
1846 priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh)
1847 {
1848 // 3.2 Recover PD_TH for OFDM for normal power region.
1849 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1850 {
1851 #ifdef RTL8190P
1852 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1853 #else
1854 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1855 #endif
1856 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1857 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1858 */
1859
1860 }
1861 else
1862 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1863 }
1864 }
1865
1866 reset_cnt_highpwr = priv->reset_count;
1867
1868 }
1869
1870
1871 static void dm_initial_gain(
1872 struct net_device * dev)
1873 {
1874 struct r8192_priv *priv = ieee80211_priv(dev);
1875 u8 initial_gain=0;
1876 static u8 initialized=0, force_write=0;
1877 static u32 reset_cnt=0;
1878
1879 if(dm_digtable.dig_algorithm_switch)
1880 {
1881 initialized = 0;
1882 reset_cnt = 0;
1883 }
1884
1885 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
1886 {
1887 if(dm_digtable.cur_connect_state == DIG_CONNECT)
1888 {
1889 if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max)
1890 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max;
1891 else if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
1892 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
1893 else
1894 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
1895 }
1896 else //current state is disconnected
1897 {
1898 if(dm_digtable.cur_ig_value == 0)
1899 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1900 else
1901 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
1902 }
1903 }
1904 else // disconnected -> connected or connected -> disconnected
1905 {
1906 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1907 dm_digtable.pre_ig_value = 0;
1908 }
1909 //DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);
1910
1911 // if silent reset happened, we should rewrite the values back
1912 if(priv->reset_count != reset_cnt)
1913 {
1914 force_write = 1;
1915 reset_cnt = priv->reset_count;
1916 }
1917
1918 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1))
1919 force_write = 1;
1920
1921 {
1922 if((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
1923 || !initialized || force_write)
1924 {
1925 initial_gain = (u8)dm_digtable.cur_ig_value;
1926 //DbgPrint("Write initial gain = 0x%x\n", initial_gain);
1927 // Set initial gain.
1928 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1929 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1930 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1931 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1932 dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
1933 initialized = 1;
1934 force_write = 0;
1935 }
1936 }
1937 }
1938
1939 static void dm_pd_th(
1940 struct net_device * dev)
1941 {
1942 struct r8192_priv *priv = ieee80211_priv(dev);
1943 static u8 initialized=0, force_write=0;
1944 static u32 reset_cnt = 0;
1945
1946 if(dm_digtable.dig_algorithm_switch)
1947 {
1948 initialized = 0;
1949 reset_cnt = 0;
1950 }
1951
1952 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
1953 {
1954 if(dm_digtable.cur_connect_state == DIG_CONNECT)
1955 {
1956 if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
1957 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
1958 else if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
1959 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1960 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
1961 (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
1962 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
1963 else
1964 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
1965 }
1966 else
1967 {
1968 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1969 }
1970 }
1971 else // disconnected -> connected or connected -> disconnected
1972 {
1973 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1974 }
1975
1976 // if silent reset happened, we should rewrite the values back
1977 if(priv->reset_count != reset_cnt)
1978 {
1979 force_write = 1;
1980 reset_cnt = priv->reset_count;
1981 }
1982
1983 {
1984 if((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
1985 (initialized<=3) || force_write)
1986 {
1987 //DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);
1988 if(dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER)
1989 {
1990 // Lower PD_TH for OFDM.
1991 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1992 {
1993 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1994 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1995 #ifdef RTL8190P
1996 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
1997 #else
1998 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
1999 #endif
2000 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2001 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2002 */
2003 }
2004 else
2005 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2006 }
2007 else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER)
2008 {
2009 // Higher PD_TH for OFDM.
2010 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2011 {
2012 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2013 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2014 #ifdef RTL8190P
2015 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2016 #else
2017 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2018 #endif
2019 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2020 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2021 */
2022 }
2023 else
2024 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2025 }
2026 else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER)
2027 {
2028 // Higher PD_TH for OFDM for high power state.
2029 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2030 {
2031 #ifdef RTL8190P
2032 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2033 #else
2034 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2035 #endif
2036 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2037 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2038 */
2039 }
2040 else
2041 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2042 }
2043 dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2044 if(initialized <= 3)
2045 initialized++;
2046 force_write = 0;
2047 }
2048 }
2049 }
2050
2051 static void dm_cs_ratio(
2052 struct net_device * dev)
2053 {
2054 struct r8192_priv *priv = ieee80211_priv(dev);
2055 static u8 initialized=0,force_write=0;
2056 static u32 reset_cnt = 0;
2057
2058 if(dm_digtable.dig_algorithm_switch)
2059 {
2060 initialized = 0;
2061 reset_cnt = 0;
2062 }
2063
2064 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2065 {
2066 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2067 {
2068 if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2069 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2070 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) )
2071 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
2072 else
2073 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
2074 }
2075 else
2076 {
2077 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2078 }
2079 }
2080 else // disconnected -> connected or connected -> disconnected
2081 {
2082 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2083 }
2084
2085 // if silent reset happened, we should rewrite the values back
2086 if(priv->reset_count != reset_cnt)
2087 {
2088 force_write = 1;
2089 reset_cnt = priv->reset_count;
2090 }
2091
2092
2093 if((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
2094 !initialized || force_write)
2095 {
2096 //DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);
2097 if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)
2098 {
2099 // Lower CS ratio for CCK.
2100 write_nic_byte(dev, 0xa0a, 0x08);
2101 }
2102 else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)
2103 {
2104 // Higher CS ratio for CCK.
2105 write_nic_byte(dev, 0xa0a, 0xcd);
2106 }
2107 dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2108 initialized = 1;
2109 force_write = 0;
2110 }
2111 }
2112
2113 void dm_init_edca_turbo(struct net_device *dev)
2114 {
2115 struct r8192_priv *priv = ieee80211_priv(dev);
2116
2117 priv->bcurrent_turbo_EDCA = false;
2118 priv->ieee80211->bis_any_nonbepkts = false;
2119 priv->bis_cur_rdlstate = false;
2120 }
2121
2122 #if 1
2123 static void dm_check_edca_turbo(
2124 struct net_device * dev)
2125 {
2126 struct r8192_priv *priv = ieee80211_priv(dev);
2127 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2128 //PSTA_QOS pStaQos = pMgntInfo->pStaQos;
2129
2130 // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
2131 static unsigned long lastTxOkCnt = 0;
2132 static unsigned long lastRxOkCnt = 0;
2133 unsigned long curTxOkCnt = 0;
2134 unsigned long curRxOkCnt = 0;
2135
2136 //
2137 // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2138 // should follow the settings from QAP. By Bruce, 2007-12-07.
2139 //
2140 #if 1
2141 if(priv->ieee80211->state != IEEE80211_LINKED)
2142 goto dm_CheckEdcaTurbo_EXIT;
2143 #endif
2144 // We do not turn on EDCA turbo mode for some AP that has IOT issue
2145 if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
2146 goto dm_CheckEdcaTurbo_EXIT;
2147
2148 // printk("========>%s():bis_any_nonbepkts is %d\n",__FUNCTION__,priv->bis_any_nonbepkts);
2149 // Check the status for current condition.
2150 if(!priv->ieee80211->bis_any_nonbepkts)
2151 {
2152 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2153 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2154 // For RT-AP, we needs to turn it on when Rx>Tx
2155 if(curRxOkCnt > 4*curTxOkCnt)
2156 {
2157 //printk("%s():curRxOkCnt > 4*curTxOkCnt\n");
2158 if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2159 {
2160 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2161 priv->bis_cur_rdlstate = true;
2162 }
2163 }
2164 else
2165 {
2166
2167 //printk("%s():curRxOkCnt < 4*curTxOkCnt\n");
2168 if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2169 {
2170 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2171 priv->bis_cur_rdlstate = false;
2172 }
2173
2174 }
2175
2176 priv->bcurrent_turbo_EDCA = true;
2177 }
2178 else
2179 {
2180 //
2181 // Turn Off EDCA turbo here.
2182 // Restore original EDCA according to the declaration of AP.
2183 //
2184 if(priv->bcurrent_turbo_EDCA)
2185 {
2186
2187 {
2188 u8 u1bAIFS;
2189 u32 u4bAcParam;
2190 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
2191 u8 mode = priv->ieee80211->mode;
2192
2193 // For Each time updating EDCA parameter, reset EDCA turbo mode status.
2194 dm_init_edca_turbo(dev);
2195 u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
2196 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
2197 (((u32)(qos_parameters->cw_max[0]))<< AC_PARAM_ECW_MAX_OFFSET)|
2198 (((u32)(qos_parameters->cw_min[0]))<< AC_PARAM_ECW_MIN_OFFSET)|
2199 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
2200 printk("===>u4bAcParam:%x, ", u4bAcParam);
2201 //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
2202 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
2203
2204 // Check ACM bit.
2205 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2206 {
2207 // TODO: Modified this part and try to set acm control in only 1 IO processing!!
2208
2209 PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
2210 u8 AcmCtrl = read_nic_byte( dev, AcmHwCtrl );
2211 if( pAciAifsn->f.ACM )
2212 { // ACM bit is 1.
2213 AcmCtrl |= AcmHw_BeqEn;
2214 }
2215 else
2216 { // ACM bit is 0.
2217 AcmCtrl &= (~AcmHw_BeqEn);
2218 }
2219
2220 RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ;
2221 write_nic_byte(dev, AcmHwCtrl, AcmCtrl );
2222 }
2223 }
2224 priv->bcurrent_turbo_EDCA = false;
2225 }
2226 }
2227
2228
2229 dm_CheckEdcaTurbo_EXIT:
2230 // Set variables for next time.
2231 priv->ieee80211->bis_any_nonbepkts = false;
2232 lastTxOkCnt = priv->stats.txbytesunicast;
2233 lastRxOkCnt = priv->stats.rxbytesunicast;
2234 }
2235 #endif
2236
2237 static void dm_init_ctstoself(struct net_device * dev)
2238 {
2239 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2240
2241 priv->ieee80211->bCTSToSelfEnable = TRUE;
2242 priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal;
2243 }
2244
2245 static void dm_ctstoself(struct net_device *dev)
2246 {
2247 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2248 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2249 static unsigned long lastTxOkCnt = 0;
2250 static unsigned long lastRxOkCnt = 0;
2251 unsigned long curTxOkCnt = 0;
2252 unsigned long curRxOkCnt = 0;
2253
2254 if(priv->ieee80211->bCTSToSelfEnable != TRUE)
2255 {
2256 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2257 return;
2258 }
2259 /*
2260 1. Uplink
2261 2. Linksys350/Linksys300N
2262 3. <50 disable, >55 enable
2263 */
2264
2265 if(pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
2266 {
2267 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2268 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2269 if(curRxOkCnt > 4*curTxOkCnt) //downlink, disable CTS to self
2270 {
2271 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2272 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");
2273 }
2274 else //uplink
2275 {
2276 #if 1
2277 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2278 #else
2279 if(priv->undecorated_smoothed_pwdb < priv->ieee80211->CTSToSelfTH) // disable CTS to self
2280 {
2281 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2282 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled\n");
2283 }
2284 else if(priv->undecorated_smoothed_pwdb >= (priv->ieee80211->CTSToSelfTH+5)) // enable CTS to self
2285 {
2286 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2287 //DbgPrint("dm_CTSToSelf() ==> CTS to self enabled\n");
2288 }
2289 #endif
2290 }
2291
2292 lastTxOkCnt = priv->stats.txbytesunicast;
2293 lastRxOkCnt = priv->stats.rxbytesunicast;
2294 }
2295 }
2296
2297
2298
2299 /* Copy 8187B template for 9xseries */
2300 #if 1
2301 static void dm_check_rfctrl_gpio(struct net_device * dev)
2302 {
2303 #ifdef RTL8192E
2304 struct r8192_priv *priv = ieee80211_priv(dev);
2305 #endif
2306
2307 // Walk around for DTM test, we will not enable HW - radio on/off because r/w
2308 // page 1 register before Lextra bus is enabled cause system fails when resuming
2309 // from S4. 20080218, Emily
2310
2311 // Stop to execute workitem to prevent S3/S4 bug.
2312 #ifdef RTL8190P
2313 return;
2314 #endif
2315 #ifdef RTL8192U
2316 return;
2317 #endif
2318 #ifdef RTL8192E
2319 queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
2320 #endif
2321
2322 }
2323
2324 #endif
2325 /* Check if PBC button is pressed. */
2326 static void dm_check_pbc_gpio(struct net_device *dev)
2327 {
2328 #ifdef RTL8192U
2329 struct r8192_priv *priv = ieee80211_priv(dev);
2330 u8 tmp1byte;
2331
2332
2333 tmp1byte = read_nic_byte(dev,GPI);
2334 if(tmp1byte == 0xff)
2335 return;
2336
2337 if (tmp1byte&BIT6 || tmp1byte&BIT0)
2338 {
2339 // Here we only set bPbcPressed to TRUE
2340 // After trigger PBC, the variable will be set to FALSE
2341 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
2342 priv->bpbc_pressed = true;
2343 }
2344 #endif
2345
2346 }
2347
2348 #ifdef RTL8192E
2349
2350 /* PCI will not support workitem call back HW radio on-off control. */
2351 void dm_gpio_change_rf_callback(struct work_struct *work)
2352 {
2353 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
2354 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,gpio_change_rf_wq);
2355 struct net_device *dev = priv->ieee80211->dev;
2356 u8 tmp1byte;
2357 RT_RF_POWER_STATE eRfPowerStateToSet;
2358 bool bActuallySet = false;
2359
2360 if (!priv->up) {
2361 RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF),"dm_gpio_change_rf_callback(): Callback function breaks out!!\n");
2362 } else {
2363 // 0x108 GPIO input register is read only
2364 //set 0x108 B1= 1: RF-ON; 0: RF-OFF.
2365 tmp1byte = read_nic_byte(dev,GPI);
2366
2367 eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff;
2368
2369 if (priv->bHwRadioOff && (eRfPowerStateToSet == eRfOn)) {
2370 RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio ON\n");
2371
2372 priv->bHwRadioOff = false;
2373 bActuallySet = true;
2374 } else if ((!priv->bHwRadioOff) && (eRfPowerStateToSet == eRfOff)) {
2375 RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio OFF\n");
2376 priv->bHwRadioOff = true;
2377 bActuallySet = true;
2378 }
2379
2380 if (bActuallySet) {
2381 priv->bHwRfOffAction = 1;
2382 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
2383 //DrvIFIndicateCurrentPhyStatus(pAdapter);
2384 } else {
2385 msleep(2000);
2386 }
2387 }
2388 }
2389
2390 #endif
2391
2392 /* Check if Current RF RX path is enabled */
2393 void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
2394 {
2395 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
2396 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,rfpath_check_wq);
2397 struct net_device *dev =priv->ieee80211->dev;
2398 //bool bactually_set = false;
2399 u8 rfpath = 0, i;
2400
2401
2402 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
2403 always be the same. We only read 0xc04 now. */
2404 rfpath = read_nic_byte(dev, 0xc04);
2405
2406 // Check Bit 0-3, it means if RF A-D is enabled.
2407 for (i = 0; i < RF90_PATH_MAX; i++)
2408 {
2409 if (rfpath & (0x01<<i))
2410 priv->brfpath_rxenable[i] = 1;
2411 else
2412 priv->brfpath_rxenable[i] = 0;
2413 }
2414 if(!DM_RxPathSelTable.Enable)
2415 return;
2416
2417 dm_rxpath_sel_byrssi(dev);
2418 }
2419
2420 static void dm_init_rxpath_selection(struct net_device * dev)
2421 {
2422 u8 i;
2423 struct r8192_priv *priv = ieee80211_priv(dev);
2424 DM_RxPathSelTable.Enable = 1; //default enabled
2425 DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low;
2426 DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH;
2427 if(priv->CustomerID == RT_CID_819x_Netcore)
2428 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;
2429 else
2430 DM_RxPathSelTable.cck_method = CCK_Rx_Version_1;
2431 DM_RxPathSelTable.DbgMode = DM_DBG_OFF;
2432 DM_RxPathSelTable.disabledRF = 0;
2433 for(i=0; i<4; i++)
2434 {
2435 DM_RxPathSelTable.rf_rssi[i] = 50;
2436 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
2437 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2438 }
2439 }
2440
2441 static void dm_rxpath_sel_byrssi(struct net_device * dev)
2442 {
2443 struct r8192_priv *priv = ieee80211_priv(dev);
2444 u8 i, max_rssi_index=0, min_rssi_index=0, sec_rssi_index=0, rf_num=0;
2445 u8 tmp_max_rssi=0, tmp_min_rssi=0, tmp_sec_rssi=0;
2446 u8 cck_default_Rx=0x2; //RF-C
2447 u8 cck_optional_Rx=0x3;//RF-D
2448 long tmp_cck_max_pwdb=0, tmp_cck_min_pwdb=0, tmp_cck_sec_pwdb=0;
2449 u8 cck_rx_ver2_max_index=0, cck_rx_ver2_min_index=0, cck_rx_ver2_sec_index=0;
2450 u8 cur_rf_rssi;
2451 long cur_cck_pwdb;
2452 static u8 disabled_rf_cnt=0, cck_Rx_Path_initialized=0;
2453 u8 update_cck_rx_path;
2454
2455 if(priv->rf_type != RF_2T4R)
2456 return;
2457
2458 if(!cck_Rx_Path_initialized)
2459 {
2460 DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf);
2461 cck_Rx_Path_initialized = 1;
2462 }
2463
2464 DM_RxPathSelTable.disabledRF = 0xf;
2465 DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04));
2466
2467 if(priv->ieee80211->mode == WIRELESS_MODE_B)
2468 {
2469 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; //pure B mode, fixed cck version2
2470 //DbgPrint("Pure B mode, use cck rx version2 \n");
2471 }
2472
2473 //decide max/sec/min rssi index
2474 for (i=0; i<RF90_PATH_MAX; i++)
2475 {
2476 if(!DM_RxPathSelTable.DbgMode)
2477 DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
2478
2479 if(priv->brfpath_rxenable[i])
2480 {
2481 rf_num++;
2482 cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
2483
2484 if(rf_num == 1) // find first enabled rf path and the rssi values
2485 { //initialize, set all rssi index to the same one
2486 max_rssi_index = min_rssi_index = sec_rssi_index = i;
2487 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
2488 }
2489 else if(rf_num == 2)
2490 { // we pick up the max index first, and let sec and min to be the same one
2491 if(cur_rf_rssi >= tmp_max_rssi)
2492 {
2493 tmp_max_rssi = cur_rf_rssi;
2494 max_rssi_index = i;
2495 }
2496 else
2497 {
2498 tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
2499 sec_rssi_index = min_rssi_index = i;
2500 }
2501 }
2502 else
2503 {
2504 if(cur_rf_rssi > tmp_max_rssi)
2505 {
2506 tmp_sec_rssi = tmp_max_rssi;
2507 sec_rssi_index = max_rssi_index;
2508 tmp_max_rssi = cur_rf_rssi;
2509 max_rssi_index = i;
2510 }
2511 else if(cur_rf_rssi == tmp_max_rssi)
2512 { // let sec and min point to the different index
2513 tmp_sec_rssi = cur_rf_rssi;
2514 sec_rssi_index = i;
2515 }
2516 else if((cur_rf_rssi < tmp_max_rssi) &&(cur_rf_rssi > tmp_sec_rssi))
2517 {
2518 tmp_sec_rssi = cur_rf_rssi;
2519 sec_rssi_index = i;
2520 }
2521 else if(cur_rf_rssi == tmp_sec_rssi)
2522 {
2523 if(tmp_sec_rssi == tmp_min_rssi)
2524 { // let sec and min point to the different index
2525 tmp_sec_rssi = cur_rf_rssi;
2526 sec_rssi_index = i;
2527 }
2528 else
2529 {
2530 // This case we don't need to set any index
2531 }
2532 }
2533 else if((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi))
2534 {
2535 // This case we don't need to set any index
2536 }
2537 else if(cur_rf_rssi == tmp_min_rssi)
2538 {
2539 if(tmp_sec_rssi == tmp_min_rssi)
2540 { // let sec and min point to the different index
2541 tmp_min_rssi = cur_rf_rssi;
2542 min_rssi_index = i;
2543 }
2544 else
2545 {
2546 // This case we don't need to set any index
2547 }
2548 }
2549 else if(cur_rf_rssi < tmp_min_rssi)
2550 {
2551 tmp_min_rssi = cur_rf_rssi;
2552 min_rssi_index = i;
2553 }
2554 }
2555 }
2556 }
2557
2558 rf_num = 0;
2559 // decide max/sec/min cck pwdb index
2560 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
2561 {
2562 for (i=0; i<RF90_PATH_MAX; i++)
2563 {
2564 if(priv->brfpath_rxenable[i])
2565 {
2566 rf_num++;
2567 cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i];
2568
2569 if(rf_num == 1) // find first enabled rf path and the rssi values
2570 { //initialize, set all rssi index to the same one
2571 cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
2572 tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
2573 }
2574 else if(rf_num == 2)
2575 { // we pick up the max index first, and let sec and min to be the same one
2576 if(cur_cck_pwdb >= tmp_cck_max_pwdb)
2577 {
2578 tmp_cck_max_pwdb = cur_cck_pwdb;
2579 cck_rx_ver2_max_index = i;
2580 }
2581 else
2582 {
2583 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
2584 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
2585 }
2586 }
2587 else
2588 {
2589 if(cur_cck_pwdb > tmp_cck_max_pwdb)
2590 {
2591 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
2592 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
2593 tmp_cck_max_pwdb = cur_cck_pwdb;
2594 cck_rx_ver2_max_index = i;
2595 }
2596 else if(cur_cck_pwdb == tmp_cck_max_pwdb)
2597 { // let sec and min point to the different index
2598 tmp_cck_sec_pwdb = cur_cck_pwdb;
2599 cck_rx_ver2_sec_index = i;
2600 }
2601 else if((cur_cck_pwdb < tmp_cck_max_pwdb) &&(cur_cck_pwdb > tmp_cck_sec_pwdb))
2602 {
2603 tmp_cck_sec_pwdb = cur_cck_pwdb;
2604 cck_rx_ver2_sec_index = i;
2605 }
2606 else if(cur_cck_pwdb == tmp_cck_sec_pwdb)
2607 {
2608 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
2609 { // let sec and min point to the different index
2610 tmp_cck_sec_pwdb = cur_cck_pwdb;
2611 cck_rx_ver2_sec_index = i;
2612 }
2613 else
2614 {
2615 // This case we don't need to set any index
2616 }
2617 }
2618 else if((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb))
2619 {
2620 // This case we don't need to set any index
2621 }
2622 else if(cur_cck_pwdb == tmp_cck_min_pwdb)
2623 {
2624 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
2625 { // let sec and min point to the different index
2626 tmp_cck_min_pwdb = cur_cck_pwdb;
2627 cck_rx_ver2_min_index = i;
2628 }
2629 else
2630 {
2631 // This case we don't need to set any index
2632 }
2633 }
2634 else if(cur_cck_pwdb < tmp_cck_min_pwdb)
2635 {
2636 tmp_cck_min_pwdb = cur_cck_pwdb;
2637 cck_rx_ver2_min_index = i;
2638 }
2639 }
2640
2641 }
2642 }
2643 }
2644
2645
2646 // Set CCK Rx path
2647 // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
2648 update_cck_rx_path = 0;
2649 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
2650 {
2651 cck_default_Rx = cck_rx_ver2_max_index;
2652 cck_optional_Rx = cck_rx_ver2_sec_index;
2653 if(tmp_cck_max_pwdb != -64)
2654 update_cck_rx_path = 1;
2655 }
2656
2657 if(tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2)
2658 {
2659 if((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH)
2660 {
2661 //record the enabled rssi threshold
2662 DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
2663 //disable the BB Rx path, OFDM
2664 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0]
2665 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0]
2666 disabled_rf_cnt++;
2667 }
2668 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1)
2669 {
2670 cck_default_Rx = max_rssi_index;
2671 cck_optional_Rx = sec_rssi_index;
2672 if(tmp_max_rssi)
2673 update_cck_rx_path = 1;
2674 }
2675 }
2676
2677 if(update_cck_rx_path)
2678 {
2679 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
2680 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);
2681 }
2682
2683 if(DM_RxPathSelTable.disabledRF)
2684 {
2685 for(i=0; i<4; i++)
2686 {
2687 if((DM_RxPathSelTable.disabledRF>>i) & 0x1) //disabled rf
2688 {
2689 if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i])
2690 {
2691 //enable the BB Rx path
2692 //DbgPrint("RF-%d is enabled. \n", 0x1<<i);
2693 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0]
2694 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0]
2695 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2696 disabled_rf_cnt--;
2697 }
2698 }
2699 }
2700 }
2701 }
2702
2703 /*
2704 * Call a workitem to check current RXRF path and Rx Path selection by RSSI.
2705 */
2706 static void dm_check_rx_path_selection(struct net_device *dev)
2707 {
2708 struct r8192_priv *priv = ieee80211_priv(dev);
2709 queue_delayed_work(priv->priv_wq,&priv->rfpath_check_wq,0);
2710 }
2711
2712 static void dm_init_fsync (struct net_device *dev)
2713 {
2714 struct r8192_priv *priv = ieee80211_priv(dev);
2715
2716 priv->ieee80211->fsync_time_interval = 500;
2717 priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
2718 priv->ieee80211->fsync_rssi_threshold = 30;
2719 #ifdef RTL8190P
2720 priv->ieee80211->bfsync_enable = true;
2721 #else
2722 priv->ieee80211->bfsync_enable = false;
2723 #endif
2724 priv->ieee80211->fsync_multiple_timeinterval = 3;
2725 priv->ieee80211->fsync_firstdiff_ratethreshold= 100;
2726 priv->ieee80211->fsync_seconddiff_ratethreshold= 200;
2727 priv->ieee80211->fsync_state = Default_Fsync;
2728 priv->framesyncMonitor = 1; // current default 0xc38 monitor on
2729
2730 init_timer(&priv->fsync_timer);
2731 priv->fsync_timer.data = (unsigned long)dev;
2732 priv->fsync_timer.function = dm_fsync_timer_callback;
2733 }
2734
2735
2736 static void dm_deInit_fsync(struct net_device *dev)
2737 {
2738 struct r8192_priv *priv = ieee80211_priv(dev);
2739 del_timer_sync(&priv->fsync_timer);
2740 }
2741
2742 void dm_fsync_timer_callback(unsigned long data)
2743 {
2744 struct net_device *dev = (struct net_device *)data;
2745 struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);
2746 u32 rate_index, rate_count = 0, rate_count_diff=0;
2747 bool bSwitchFromCountDiff = false;
2748 bool bDoubleTimeInterval = false;
2749
2750 if( priv->ieee80211->state == IEEE80211_LINKED &&
2751 priv->ieee80211->bfsync_enable &&
2752 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
2753 {
2754 // Count rate 54, MCS [7], [12, 13, 14, 15]
2755 u32 rate_bitmap;
2756 for(rate_index = 0; rate_index <= 27; rate_index++)
2757 {
2758 rate_bitmap = 1 << rate_index;
2759 if(priv->ieee80211->fsync_rate_bitmap & rate_bitmap)
2760 rate_count+= priv->stats.received_rate_histogram[1][rate_index];
2761 }
2762
2763 if(rate_count < priv->rate_record)
2764 rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
2765 else
2766 rate_count_diff = rate_count - priv->rate_record;
2767 if(rate_count_diff < priv->rateCountDiffRecord)
2768 {
2769
2770 u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
2771 // Contiune count
2772 if(DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
2773 priv->ContiuneDiffCount++;
2774 else
2775 priv->ContiuneDiffCount = 0;
2776
2777 // Contiune count over
2778 if(priv->ContiuneDiffCount >=2)
2779 {
2780 bSwitchFromCountDiff = true;
2781 priv->ContiuneDiffCount = 0;
2782 }
2783 }
2784 else
2785 {
2786 // Stop contiune count
2787 priv->ContiuneDiffCount = 0;
2788 }
2789
2790 //If Count diff <= FsyncRateCountThreshold
2791 if(rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold)
2792 {
2793 bSwitchFromCountDiff = true;
2794 priv->ContiuneDiffCount = 0;
2795 }
2796 priv->rate_record = rate_count;
2797 priv->rateCountDiffRecord = rate_count_diff;
2798 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
2799 // if we never receive those mcs rate and rssi > 30 % then switch fsyn
2800 if(priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff)
2801 {
2802 bDoubleTimeInterval = true;
2803 priv->bswitch_fsync = !priv->bswitch_fsync;
2804 if(priv->bswitch_fsync)
2805 {
2806 #ifdef RTL8190P
2807 write_nic_byte(dev,0xC36, 0x00);
2808 #else
2809 write_nic_byte(dev,0xC36, 0x1c);
2810 #endif
2811 write_nic_byte(dev, 0xC3e, 0x90);
2812 }
2813 else
2814 {
2815 #ifdef RTL8190P
2816 write_nic_byte(dev, 0xC36, 0x40);
2817 #else
2818 write_nic_byte(dev, 0xC36, 0x5c);
2819 #endif
2820 write_nic_byte(dev, 0xC3e, 0x96);
2821 }
2822 }
2823 else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold)
2824 {
2825 if(priv->bswitch_fsync)
2826 {
2827 priv->bswitch_fsync = false;
2828 #ifdef RTL8190P
2829 write_nic_byte(dev, 0xC36, 0x40);
2830 #else
2831 write_nic_byte(dev, 0xC36, 0x5c);
2832 #endif
2833 write_nic_byte(dev, 0xC3e, 0x96);
2834 }
2835 }
2836 if(bDoubleTimeInterval){
2837 if(timer_pending(&priv->fsync_timer))
2838 del_timer_sync(&priv->fsync_timer);
2839 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval);
2840 add_timer(&priv->fsync_timer);
2841 }
2842 else{
2843 if(timer_pending(&priv->fsync_timer))
2844 del_timer_sync(&priv->fsync_timer);
2845 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
2846 add_timer(&priv->fsync_timer);
2847 }
2848 }
2849 else
2850 {
2851 // Let Register return to default value;
2852 if(priv->bswitch_fsync)
2853 {
2854 priv->bswitch_fsync = false;
2855 #ifdef RTL8190P
2856 write_nic_byte(dev, 0xC36, 0x40);
2857 #else
2858 write_nic_byte(dev, 0xC36, 0x5c);
2859 #endif
2860 write_nic_byte(dev, 0xC3e, 0x96);
2861 }
2862 priv->ContiuneDiffCount = 0;
2863 #ifdef RTL8190P
2864 write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd);
2865 #else
2866 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2867 #endif
2868 }
2869 RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
2870 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
2871 }
2872
2873 static void dm_StartHWFsync(struct net_device *dev)
2874 {
2875 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
2876 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
2877 write_nic_byte(dev, 0xc3b, 0x41);
2878 }
2879
2880 static void dm_EndSWFsync(struct net_device *dev)
2881 {
2882 struct r8192_priv *priv = ieee80211_priv(dev);
2883
2884 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
2885 del_timer_sync(&(priv->fsync_timer));
2886
2887 // Let Register return to default value;
2888 if(priv->bswitch_fsync)
2889 {
2890 priv->bswitch_fsync = false;
2891
2892 #ifdef RTL8190P
2893 write_nic_byte(dev, 0xC36, 0x40);
2894 #else
2895 write_nic_byte(dev, 0xC36, 0x5c);
2896 #endif
2897
2898 write_nic_byte(dev, 0xC3e, 0x96);
2899 }
2900
2901 priv->ContiuneDiffCount = 0;
2902 #ifndef RTL8190P
2903 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2904 #endif
2905
2906 }
2907
2908 static void dm_StartSWFsync(struct net_device *dev)
2909 {
2910 struct r8192_priv *priv = ieee80211_priv(dev);
2911 u32 rateIndex;
2912 u32 rateBitmap;
2913
2914 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
2915 // Initial rate record to zero, start to record.
2916 priv->rate_record = 0;
2917 // Initial contiune diff count to zero, start to record.
2918 priv->ContiuneDiffCount = 0;
2919 priv->rateCountDiffRecord = 0;
2920 priv->bswitch_fsync = false;
2921
2922 if(priv->ieee80211->mode == WIRELESS_MODE_N_24G)
2923 {
2924 priv->ieee80211->fsync_firstdiff_ratethreshold= 600;
2925 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
2926 }
2927 else
2928 {
2929 priv->ieee80211->fsync_firstdiff_ratethreshold= 200;
2930 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
2931 }
2932 for(rateIndex = 0; rateIndex <= 27; rateIndex++)
2933 {
2934 rateBitmap = 1 << rateIndex;
2935 if(priv->ieee80211->fsync_rate_bitmap & rateBitmap)
2936 priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
2937 }
2938 if(timer_pending(&priv->fsync_timer))
2939 del_timer_sync(&priv->fsync_timer);
2940 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
2941 add_timer(&priv->fsync_timer);
2942
2943 #ifndef RTL8190P
2944 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
2945 #endif
2946
2947 }
2948
2949 static void dm_EndHWFsync(struct net_device *dev)
2950 {
2951 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
2952 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2953 write_nic_byte(dev, 0xc3b, 0x49);
2954
2955 }
2956
2957 void dm_check_fsync(struct net_device *dev)
2958 {
2959 #define RegC38_Default 0
2960 #define RegC38_NonFsync_Other_AP 1
2961 #define RegC38_Fsync_AP_BCM 2
2962 struct r8192_priv *priv = ieee80211_priv(dev);
2963 //u32 framesyncC34;
2964 static u8 reg_c38_State=RegC38_Default;
2965 static u32 reset_cnt=0;
2966
2967 RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
2968 RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
2969
2970 if( priv->ieee80211->state == IEEE80211_LINKED &&
2971 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
2972 {
2973 if(priv->ieee80211->bfsync_enable == 0)
2974 {
2975 switch(priv->ieee80211->fsync_state)
2976 {
2977 case Default_Fsync:
2978 dm_StartHWFsync(dev);
2979 priv->ieee80211->fsync_state = HW_Fsync;
2980 break;
2981 case SW_Fsync:
2982 dm_EndSWFsync(dev);
2983 dm_StartHWFsync(dev);
2984 priv->ieee80211->fsync_state = HW_Fsync;
2985 break;
2986 case HW_Fsync:
2987 default:
2988 break;
2989 }
2990 }
2991 else
2992 {
2993 switch(priv->ieee80211->fsync_state)
2994 {
2995 case Default_Fsync:
2996 dm_StartSWFsync(dev);
2997 priv->ieee80211->fsync_state = SW_Fsync;
2998 break;
2999 case HW_Fsync:
3000 dm_EndHWFsync(dev);
3001 dm_StartSWFsync(dev);
3002 priv->ieee80211->fsync_state = SW_Fsync;
3003 break;
3004 case SW_Fsync:
3005 default:
3006 break;
3007
3008 }
3009 }
3010 if(priv->framesyncMonitor)
3011 {
3012 if(reg_c38_State != RegC38_Fsync_AP_BCM)
3013 { //For broadcom AP we write different default value
3014 #ifdef RTL8190P
3015 write_nic_byte(dev, rOFDM0_RxDetector3, 0x15);
3016 #else
3017 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
3018 #endif
3019
3020 reg_c38_State = RegC38_Fsync_AP_BCM;
3021 }
3022 }
3023 }
3024 else
3025 {
3026 switch(priv->ieee80211->fsync_state)
3027 {
3028 case HW_Fsync:
3029 dm_EndHWFsync(dev);
3030 priv->ieee80211->fsync_state = Default_Fsync;
3031 break;
3032 case SW_Fsync:
3033 dm_EndSWFsync(dev);
3034 priv->ieee80211->fsync_state = Default_Fsync;
3035 break;
3036 case Default_Fsync:
3037 default:
3038 break;
3039 }
3040
3041 if(priv->framesyncMonitor)
3042 {
3043 if(priv->ieee80211->state == IEEE80211_LINKED)
3044 {
3045 if(priv->undecorated_smoothed_pwdb <= RegC38_TH)
3046 {
3047 if(reg_c38_State != RegC38_NonFsync_Other_AP)
3048 {
3049 #ifdef RTL8190P
3050 write_nic_byte(dev, rOFDM0_RxDetector3, 0x10);
3051 #else
3052 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
3053 #endif
3054
3055 reg_c38_State = RegC38_NonFsync_Other_AP;
3056 #if 0//cosa
3057 if (Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)
3058 DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x10);
3059 else
3060 DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x90);
3061 #endif
3062 }
3063 }
3064 else if(priv->undecorated_smoothed_pwdb >= (RegC38_TH+5))
3065 {
3066 if(reg_c38_State)
3067 {
3068 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3069 reg_c38_State = RegC38_Default;
3070 //DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x \n", pHalData->framesync);
3071 }
3072 }
3073 }
3074 else
3075 {
3076 if(reg_c38_State)
3077 {
3078 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3079 reg_c38_State = RegC38_Default;
3080 //DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x \n", pHalData->framesync);
3081 }
3082 }
3083 }
3084 }
3085 if(priv->framesyncMonitor)
3086 {
3087 if(priv->reset_count != reset_cnt)
3088 { //After silent reset, the reg_c38_State will be returned to default value
3089 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3090 reg_c38_State = RegC38_Default;
3091 reset_cnt = priv->reset_count;
3092 //DbgPrint("reg_c38_State = 0 for silent reset. \n");
3093 }
3094 }
3095 else
3096 {
3097 if(reg_c38_State)
3098 {
3099 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3100 reg_c38_State = RegC38_Default;
3101 //DbgPrint("framesync no monitor, write 0xc38 = 0x%x \n", pHalData->framesync);
3102 }
3103 }
3104 }
3105
3106 /*
3107 * Detect Signal strength to control TX Registry
3108 * Tx Power Control For Near/Far Range
3109 */
3110 static void dm_init_dynamic_txpower(struct net_device *dev)
3111 {
3112 struct r8192_priv *priv = ieee80211_priv(dev);
3113
3114 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
3115 priv->ieee80211->bdynamic_txpower_enable = true; //Default to enable Tx Power Control
3116 priv->bLastDTPFlag_High = false;
3117 priv->bLastDTPFlag_Low = false;
3118 priv->bDynamicTxHighPower = false;
3119 priv->bDynamicTxLowPower = false;
3120 }
3121
3122 static void dm_dynamic_txpower(struct net_device *dev)
3123 {
3124 struct r8192_priv *priv = ieee80211_priv(dev);
3125 unsigned int txhipower_threshhold=0;
3126 unsigned int txlowpower_threshold=0;
3127 if(priv->ieee80211->bdynamic_txpower_enable != true)
3128 {
3129 priv->bDynamicTxHighPower = false;
3130 priv->bDynamicTxLowPower = false;
3131 return;
3132 }
3133 //printk("priv->ieee80211->current_network.unknown_cap_exist is %d ,priv->ieee80211->current_network.broadcom_cap_exist is %d\n",priv->ieee80211->current_network.unknown_cap_exist,priv->ieee80211->current_network.broadcom_cap_exist);
3134 if((priv->ieee80211->current_network.atheros_cap_exist ) && (priv->ieee80211->mode == IEEE_G)){
3135 txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH;
3136 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
3137 }
3138 else
3139 {
3140 txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
3141 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
3142 }
3143
3144 // printk("=======>%s(): txhipower_threshhold is %d,txlowpower_threshold is %d\n",__FUNCTION__,txhipower_threshhold,txlowpower_threshold);
3145
3146 RT_TRACE(COMP_TXAGC,"priv->undecorated_smoothed_pwdb = %ld \n" , priv->undecorated_smoothed_pwdb);
3147
3148 if(priv->ieee80211->state == IEEE80211_LINKED)
3149 {
3150 if(priv->undecorated_smoothed_pwdb >= txhipower_threshhold)
3151 {
3152 priv->bDynamicTxHighPower = true;
3153 priv->bDynamicTxLowPower = false;
3154 }
3155 else
3156 {
3157 // high power state check
3158 if(priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower == true)
3159 {
3160 priv->bDynamicTxHighPower = false;
3161 }
3162 // low power state check
3163 if(priv->undecorated_smoothed_pwdb < 35)
3164 {
3165 priv->bDynamicTxLowPower = true;
3166 }
3167 else if(priv->undecorated_smoothed_pwdb >= 40)
3168 {
3169 priv->bDynamicTxLowPower = false;
3170 }
3171 }
3172 }
3173 else
3174 {
3175 //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;
3176 priv->bDynamicTxHighPower = false;
3177 priv->bDynamicTxLowPower = false;
3178 }
3179
3180 if( (priv->bDynamicTxHighPower != priv->bLastDTPFlag_High ) ||
3181 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low ) )
3182 {
3183 RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190() channel = %d \n" , priv->ieee80211->current_network.channel);
3184
3185
3186 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
3187
3188 }
3189 priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
3190 priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
3191
3192 }
3193
3194 //added by vivi, for read tx rate and retrycount
3195 static void dm_check_txrateandretrycount(struct net_device * dev)
3196 {
3197 struct r8192_priv *priv = ieee80211_priv(dev);
3198 struct ieee80211_device* ieee = priv->ieee80211;
3199 //for 11n tx rate
3200 // priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
3201 ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
3202 //printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);
3203 //for initial tx rate
3204 // priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);
3205 ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg);
3206 //for tx tx retry count
3207 // priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
3208 ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
3209 }
3210
3211 static void dm_send_rssi_tofw(struct net_device *dev)
3212 {
3213 DCMD_TXCMD_T tx_cmd;
3214 struct r8192_priv *priv = ieee80211_priv(dev);
3215
3216 // If we test chariot, we should stop the TX command ?
3217 // Because 92E will always silent reset when we send tx command. We use register
3218 // 0x1e0(byte) to botify driver.
3219 write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
3220 return;
3221 #if 1
3222 tx_cmd.Op = TXCMD_SET_RX_RSSI;
3223 tx_cmd.Length = 4;
3224 tx_cmd.Value = priv->undecorated_smoothed_pwdb;
3225
3226 cmpk_message_handle_tx(dev, (u8*)&tx_cmd,
3227 DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
3228 #endif
3229 }
3230
(deprecated) Btrfs devel tree