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igb: Cleanups to fix for trailing statement
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
blobbeeebabde38d69762709a5f5fb9d734be59e6c7e
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, see <http://www.gnu.org/licenses/>.
17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25 *******************************************************************************/
26
27 /* e1000_82575
28 * e1000_82576
29 */
30
31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
33 #include <linux/types.h>
34 #include <linux/if_ether.h>
35 #include <linux/i2c.h>
36
37 #include "e1000_mac.h"
38 #include "e1000_82575.h"
39 #include "e1000_i210.h"
40
41 static s32 igb_get_invariants_82575(struct e1000_hw *);
42 static s32 igb_acquire_phy_82575(struct e1000_hw *);
43 static void igb_release_phy_82575(struct e1000_hw *);
44 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
45 static void igb_release_nvm_82575(struct e1000_hw *);
46 static s32 igb_check_for_link_82575(struct e1000_hw *);
47 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
48 static s32 igb_init_hw_82575(struct e1000_hw *);
49 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
50 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
51 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
52 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
53 static s32 igb_reset_hw_82575(struct e1000_hw *);
54 static s32 igb_reset_hw_82580(struct e1000_hw *);
55 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
56 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
57 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
58 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
59 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
60 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
61 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
62 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
63 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
64 u16 *);
65 static s32 igb_get_phy_id_82575(struct e1000_hw *);
66 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
67 static bool igb_sgmii_active_82575(struct e1000_hw *);
68 static s32 igb_reset_init_script_82575(struct e1000_hw *);
69 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
70 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
71 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
72 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
73 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
74 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
75 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
76 static const u16 e1000_82580_rxpbs_table[] = {
77 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
78
79 /**
80 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
81 * @hw: pointer to the HW structure
82 *
83 * Called to determine if the I2C pins are being used for I2C or as an
84 * external MDIO interface since the two options are mutually exclusive.
85 **/
86 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
87 {
88 u32 reg = 0;
89 bool ext_mdio = false;
90
91 switch (hw->mac.type) {
92 case e1000_82575:
93 case e1000_82576:
94 reg = rd32(E1000_MDIC);
95 ext_mdio = !!(reg & E1000_MDIC_DEST);
96 break;
97 case e1000_82580:
98 case e1000_i350:
99 case e1000_i354:
100 case e1000_i210:
101 case e1000_i211:
102 reg = rd32(E1000_MDICNFG);
103 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
104 break;
105 default:
106 break;
107 }
108 return ext_mdio;
109 }
110
111 /**
112 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
113 * @hw: pointer to the HW structure
114 *
115 * Poll the M88E1112 interfaces to see which interface achieved link.
116 */
117 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
118 {
119 struct e1000_phy_info *phy = &hw->phy;
120 s32 ret_val;
121 u16 data;
122 u8 port = 0;
123
124 /* Check the copper medium. */
125 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
126 if (ret_val)
127 return ret_val;
128
129 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
130 if (ret_val)
131 return ret_val;
132
133 if (data & E1000_M88E1112_STATUS_LINK)
134 port = E1000_MEDIA_PORT_COPPER;
135
136 /* Check the other medium. */
137 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
138 if (ret_val)
139 return ret_val;
140
141 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
142 if (ret_val)
143 return ret_val;
144
145 /* reset page to 0 */
146 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
147 if (ret_val)
148 return ret_val;
149
150 if (data & E1000_M88E1112_STATUS_LINK)
151 port = E1000_MEDIA_PORT_OTHER;
152
153 /* Determine if a swap needs to happen. */
154 if (port && (hw->dev_spec._82575.media_port != port)) {
155 hw->dev_spec._82575.media_port = port;
156 hw->dev_spec._82575.media_changed = true;
157 } else {
158 ret_val = igb_check_for_link_82575(hw);
159 }
160
161 return E1000_SUCCESS;
162 }
163
164 /**
165 * igb_init_phy_params_82575 - Init PHY func ptrs.
166 * @hw: pointer to the HW structure
167 **/
168 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
169 {
170 struct e1000_phy_info *phy = &hw->phy;
171 s32 ret_val = 0;
172 u32 ctrl_ext;
173
174 if (hw->phy.media_type != e1000_media_type_copper) {
175 phy->type = e1000_phy_none;
176 goto out;
177 }
178
179 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
180 phy->reset_delay_us = 100;
181
182 ctrl_ext = rd32(E1000_CTRL_EXT);
183
184 if (igb_sgmii_active_82575(hw)) {
185 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
186 ctrl_ext |= E1000_CTRL_I2C_ENA;
187 } else {
188 phy->ops.reset = igb_phy_hw_reset;
189 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
190 }
191
192 wr32(E1000_CTRL_EXT, ctrl_ext);
193 igb_reset_mdicnfg_82580(hw);
194
195 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
196 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
197 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
198 } else {
199 switch (hw->mac.type) {
200 case e1000_82580:
201 case e1000_i350:
202 case e1000_i354:
203 phy->ops.read_reg = igb_read_phy_reg_82580;
204 phy->ops.write_reg = igb_write_phy_reg_82580;
205 break;
206 case e1000_i210:
207 case e1000_i211:
208 phy->ops.read_reg = igb_read_phy_reg_gs40g;
209 phy->ops.write_reg = igb_write_phy_reg_gs40g;
210 break;
211 default:
212 phy->ops.read_reg = igb_read_phy_reg_igp;
213 phy->ops.write_reg = igb_write_phy_reg_igp;
214 }
215 }
216
217 /* set lan id */
218 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
219 E1000_STATUS_FUNC_SHIFT;
220
221 /* Set phy->phy_addr and phy->id. */
222 ret_val = igb_get_phy_id_82575(hw);
223 if (ret_val)
224 return ret_val;
225
226 /* Verify phy id and set remaining function pointers */
227 switch (phy->id) {
228 case M88E1543_E_PHY_ID:
229 case I347AT4_E_PHY_ID:
230 case M88E1112_E_PHY_ID:
231 case M88E1111_I_PHY_ID:
232 phy->type = e1000_phy_m88;
233 phy->ops.check_polarity = igb_check_polarity_m88;
234 phy->ops.get_phy_info = igb_get_phy_info_m88;
235 if (phy->id != M88E1111_I_PHY_ID)
236 phy->ops.get_cable_length =
237 igb_get_cable_length_m88_gen2;
238 else
239 phy->ops.get_cable_length = igb_get_cable_length_m88;
240 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
241 /* Check if this PHY is confgured for media swap. */
242 if (phy->id == M88E1112_E_PHY_ID) {
243 u16 data;
244
245 ret_val = phy->ops.write_reg(hw,
246 E1000_M88E1112_PAGE_ADDR,
247 2);
248 if (ret_val)
249 goto out;
250
251 ret_val = phy->ops.read_reg(hw,
252 E1000_M88E1112_MAC_CTRL_1,
253 &data);
254 if (ret_val)
255 goto out;
256
257 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
258 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
259 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
260 data == E1000_M88E1112_AUTO_COPPER_BASEX)
261 hw->mac.ops.check_for_link =
262 igb_check_for_link_media_swap;
263 }
264 break;
265 case IGP03E1000_E_PHY_ID:
266 phy->type = e1000_phy_igp_3;
267 phy->ops.get_phy_info = igb_get_phy_info_igp;
268 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
269 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
270 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
271 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
272 break;
273 case I82580_I_PHY_ID:
274 case I350_I_PHY_ID:
275 phy->type = e1000_phy_82580;
276 phy->ops.force_speed_duplex =
277 igb_phy_force_speed_duplex_82580;
278 phy->ops.get_cable_length = igb_get_cable_length_82580;
279 phy->ops.get_phy_info = igb_get_phy_info_82580;
280 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
281 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
282 break;
283 case I210_I_PHY_ID:
284 phy->type = e1000_phy_i210;
285 phy->ops.check_polarity = igb_check_polarity_m88;
286 phy->ops.get_phy_info = igb_get_phy_info_m88;
287 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
288 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
289 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
290 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
291 break;
292 default:
293 ret_val = -E1000_ERR_PHY;
294 goto out;
295 }
296
297 out:
298 return ret_val;
299 }
300
301 /**
302 * igb_init_nvm_params_82575 - Init NVM func ptrs.
303 * @hw: pointer to the HW structure
304 **/
305 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
306 {
307 struct e1000_nvm_info *nvm = &hw->nvm;
308 u32 eecd = rd32(E1000_EECD);
309 u16 size;
310
311 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
312 E1000_EECD_SIZE_EX_SHIFT);
313
314 /* Added to a constant, "size" becomes the left-shift value
315 * for setting word_size.
316 */
317 size += NVM_WORD_SIZE_BASE_SHIFT;
318
319 /* Just in case size is out of range, cap it to the largest
320 * EEPROM size supported
321 */
322 if (size > 15)
323 size = 15;
324
325 nvm->word_size = 1 << size;
326 nvm->opcode_bits = 8;
327 nvm->delay_usec = 1;
328
329 switch (nvm->override) {
330 case e1000_nvm_override_spi_large:
331 nvm->page_size = 32;
332 nvm->address_bits = 16;
333 break;
334 case e1000_nvm_override_spi_small:
335 nvm->page_size = 8;
336 nvm->address_bits = 8;
337 break;
338 default:
339 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
340 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
341 16 : 8;
342 break;
343 }
344 if (nvm->word_size == (1 << 15))
345 nvm->page_size = 128;
346
347 nvm->type = e1000_nvm_eeprom_spi;
348
349 /* NVM Function Pointers */
350 nvm->ops.acquire = igb_acquire_nvm_82575;
351 nvm->ops.release = igb_release_nvm_82575;
352 nvm->ops.write = igb_write_nvm_spi;
353 nvm->ops.validate = igb_validate_nvm_checksum;
354 nvm->ops.update = igb_update_nvm_checksum;
355 if (nvm->word_size < (1 << 15))
356 nvm->ops.read = igb_read_nvm_eerd;
357 else
358 nvm->ops.read = igb_read_nvm_spi;
359
360 /* override generic family function pointers for specific descendants */
361 switch (hw->mac.type) {
362 case e1000_82580:
363 nvm->ops.validate = igb_validate_nvm_checksum_82580;
364 nvm->ops.update = igb_update_nvm_checksum_82580;
365 break;
366 case e1000_i354:
367 case e1000_i350:
368 nvm->ops.validate = igb_validate_nvm_checksum_i350;
369 nvm->ops.update = igb_update_nvm_checksum_i350;
370 break;
371 default:
372 break;
373 }
374
375 return 0;
376 }
377
378 /**
379 * igb_init_mac_params_82575 - Init MAC func ptrs.
380 * @hw: pointer to the HW structure
381 **/
382 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
383 {
384 struct e1000_mac_info *mac = &hw->mac;
385 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
386
387 /* Set mta register count */
388 mac->mta_reg_count = 128;
389 /* Set rar entry count */
390 switch (mac->type) {
391 case e1000_82576:
392 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
393 break;
394 case e1000_82580:
395 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
396 break;
397 case e1000_i350:
398 case e1000_i354:
399 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
400 break;
401 default:
402 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
403 break;
404 }
405 /* reset */
406 if (mac->type >= e1000_82580)
407 mac->ops.reset_hw = igb_reset_hw_82580;
408 else
409 mac->ops.reset_hw = igb_reset_hw_82575;
410
411 if (mac->type >= e1000_i210) {
412 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
413 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
414
415 } else {
416 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
417 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
418 }
419
420 /* Set if part includes ASF firmware */
421 mac->asf_firmware_present = true;
422 /* Set if manageability features are enabled. */
423 mac->arc_subsystem_valid =
424 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
425 ? true : false;
426 /* enable EEE on i350 parts and later parts */
427 if (mac->type >= e1000_i350)
428 dev_spec->eee_disable = false;
429 else
430 dev_spec->eee_disable = true;
431 /* Allow a single clear of the SW semaphore on I210 and newer */
432 if (mac->type >= e1000_i210)
433 dev_spec->clear_semaphore_once = true;
434 /* physical interface link setup */
435 mac->ops.setup_physical_interface =
436 (hw->phy.media_type == e1000_media_type_copper)
437 ? igb_setup_copper_link_82575
438 : igb_setup_serdes_link_82575;
439
440 if (mac->type == e1000_82580) {
441 switch (hw->device_id) {
442 /* feature not supported on these id's */
443 case E1000_DEV_ID_DH89XXCC_SGMII:
444 case E1000_DEV_ID_DH89XXCC_SERDES:
445 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
446 case E1000_DEV_ID_DH89XXCC_SFP:
447 break;
448 default:
449 hw->dev_spec._82575.mas_capable = true;
450 break;
451 }
452 }
453 return 0;
454 }
455
456 /**
457 * igb_set_sfp_media_type_82575 - derives SFP module media type.
458 * @hw: pointer to the HW structure
459 *
460 * The media type is chosen based on SFP module.
461 * compatibility flags retrieved from SFP ID EEPROM.
462 **/
463 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
464 {
465 s32 ret_val = E1000_ERR_CONFIG;
466 u32 ctrl_ext = 0;
467 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
468 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
469 u8 tranceiver_type = 0;
470 s32 timeout = 3;
471
472 /* Turn I2C interface ON and power on sfp cage */
473 ctrl_ext = rd32(E1000_CTRL_EXT);
474 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
475 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
476
477 wrfl();
478
479 /* Read SFP module data */
480 while (timeout) {
481 ret_val = igb_read_sfp_data_byte(hw,
482 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
483 &tranceiver_type);
484 if (ret_val == 0)
485 break;
486 msleep(100);
487 timeout--;
488 }
489 if (ret_val != 0)
490 goto out;
491
492 ret_val = igb_read_sfp_data_byte(hw,
493 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
494 (u8 *)eth_flags);
495 if (ret_val != 0)
496 goto out;
497
498 /* Check if there is some SFP module plugged and powered */
499 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
500 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
501 dev_spec->module_plugged = true;
502 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
503 hw->phy.media_type = e1000_media_type_internal_serdes;
504 } else if (eth_flags->e100_base_fx) {
505 dev_spec->sgmii_active = true;
506 hw->phy.media_type = e1000_media_type_internal_serdes;
507 } else if (eth_flags->e1000_base_t) {
508 dev_spec->sgmii_active = true;
509 hw->phy.media_type = e1000_media_type_copper;
510 } else {
511 hw->phy.media_type = e1000_media_type_unknown;
512 hw_dbg("PHY module has not been recognized\n");
513 goto out;
514 }
515 } else {
516 hw->phy.media_type = e1000_media_type_unknown;
517 }
518 ret_val = 0;
519 out:
520 /* Restore I2C interface setting */
521 wr32(E1000_CTRL_EXT, ctrl_ext);
522 return ret_val;
523 }
524
525 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
526 {
527 struct e1000_mac_info *mac = &hw->mac;
528 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
529 s32 ret_val;
530 u32 ctrl_ext = 0;
531 u32 link_mode = 0;
532
533 switch (hw->device_id) {
534 case E1000_DEV_ID_82575EB_COPPER:
535 case E1000_DEV_ID_82575EB_FIBER_SERDES:
536 case E1000_DEV_ID_82575GB_QUAD_COPPER:
537 mac->type = e1000_82575;
538 break;
539 case E1000_DEV_ID_82576:
540 case E1000_DEV_ID_82576_NS:
541 case E1000_DEV_ID_82576_NS_SERDES:
542 case E1000_DEV_ID_82576_FIBER:
543 case E1000_DEV_ID_82576_SERDES:
544 case E1000_DEV_ID_82576_QUAD_COPPER:
545 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
546 case E1000_DEV_ID_82576_SERDES_QUAD:
547 mac->type = e1000_82576;
548 break;
549 case E1000_DEV_ID_82580_COPPER:
550 case E1000_DEV_ID_82580_FIBER:
551 case E1000_DEV_ID_82580_QUAD_FIBER:
552 case E1000_DEV_ID_82580_SERDES:
553 case E1000_DEV_ID_82580_SGMII:
554 case E1000_DEV_ID_82580_COPPER_DUAL:
555 case E1000_DEV_ID_DH89XXCC_SGMII:
556 case E1000_DEV_ID_DH89XXCC_SERDES:
557 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
558 case E1000_DEV_ID_DH89XXCC_SFP:
559 mac->type = e1000_82580;
560 break;
561 case E1000_DEV_ID_I350_COPPER:
562 case E1000_DEV_ID_I350_FIBER:
563 case E1000_DEV_ID_I350_SERDES:
564 case E1000_DEV_ID_I350_SGMII:
565 mac->type = e1000_i350;
566 break;
567 case E1000_DEV_ID_I210_COPPER:
568 case E1000_DEV_ID_I210_FIBER:
569 case E1000_DEV_ID_I210_SERDES:
570 case E1000_DEV_ID_I210_SGMII:
571 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
572 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
573 mac->type = e1000_i210;
574 break;
575 case E1000_DEV_ID_I211_COPPER:
576 mac->type = e1000_i211;
577 break;
578 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
579 case E1000_DEV_ID_I354_SGMII:
580 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
581 mac->type = e1000_i354;
582 break;
583 default:
584 return -E1000_ERR_MAC_INIT;
585 break;
586 }
587
588 /* Set media type */
589 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
590 * based on the EEPROM. We cannot rely upon device ID. There
591 * is no distinguishable difference between fiber and internal
592 * SerDes mode on the 82575. There can be an external PHY attached
593 * on the SGMII interface. For this, we'll set sgmii_active to true.
594 */
595 hw->phy.media_type = e1000_media_type_copper;
596 dev_spec->sgmii_active = false;
597 dev_spec->module_plugged = false;
598
599 ctrl_ext = rd32(E1000_CTRL_EXT);
600
601 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
602 switch (link_mode) {
603 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
604 hw->phy.media_type = e1000_media_type_internal_serdes;
605 break;
606 case E1000_CTRL_EXT_LINK_MODE_SGMII:
607 /* Get phy control interface type set (MDIO vs. I2C)*/
608 if (igb_sgmii_uses_mdio_82575(hw)) {
609 hw->phy.media_type = e1000_media_type_copper;
610 dev_spec->sgmii_active = true;
611 break;
612 }
613 /* fall through for I2C based SGMII */
614 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
615 /* read media type from SFP EEPROM */
616 ret_val = igb_set_sfp_media_type_82575(hw);
617 if ((ret_val != 0) ||
618 (hw->phy.media_type == e1000_media_type_unknown)) {
619 /* If media type was not identified then return media
620 * type defined by the CTRL_EXT settings.
621 */
622 hw->phy.media_type = e1000_media_type_internal_serdes;
623
624 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
625 hw->phy.media_type = e1000_media_type_copper;
626 dev_spec->sgmii_active = true;
627 }
628
629 break;
630 }
631
632 /* do not change link mode for 100BaseFX */
633 if (dev_spec->eth_flags.e100_base_fx)
634 break;
635
636 /* change current link mode setting */
637 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
638
639 if (hw->phy.media_type == e1000_media_type_copper)
640 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
641 else
642 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
643
644 wr32(E1000_CTRL_EXT, ctrl_ext);
645
646 break;
647 default:
648 break;
649 }
650
651 /* mac initialization and operations */
652 ret_val = igb_init_mac_params_82575(hw);
653 if (ret_val)
654 goto out;
655
656 /* NVM initialization */
657 ret_val = igb_init_nvm_params_82575(hw);
658 switch (hw->mac.type) {
659 case e1000_i210:
660 case e1000_i211:
661 ret_val = igb_init_nvm_params_i210(hw);
662 break;
663 default:
664 break;
665 }
666
667 if (ret_val)
668 goto out;
669
670 /* if part supports SR-IOV then initialize mailbox parameters */
671 switch (mac->type) {
672 case e1000_82576:
673 case e1000_i350:
674 igb_init_mbx_params_pf(hw);
675 break;
676 default:
677 break;
678 }
679
680 /* setup PHY parameters */
681 ret_val = igb_init_phy_params_82575(hw);
682
683 out:
684 return ret_val;
685 }
686
687 /**
688 * igb_acquire_phy_82575 - Acquire rights to access PHY
689 * @hw: pointer to the HW structure
690 *
691 * Acquire access rights to the correct PHY. This is a
692 * function pointer entry point called by the api module.
693 **/
694 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
695 {
696 u16 mask = E1000_SWFW_PHY0_SM;
697
698 if (hw->bus.func == E1000_FUNC_1)
699 mask = E1000_SWFW_PHY1_SM;
700 else if (hw->bus.func == E1000_FUNC_2)
701 mask = E1000_SWFW_PHY2_SM;
702 else if (hw->bus.func == E1000_FUNC_3)
703 mask = E1000_SWFW_PHY3_SM;
704
705 return hw->mac.ops.acquire_swfw_sync(hw, mask);
706 }
707
708 /**
709 * igb_release_phy_82575 - Release rights to access PHY
710 * @hw: pointer to the HW structure
711 *
712 * A wrapper to release access rights to the correct PHY. This is a
713 * function pointer entry point called by the api module.
714 **/
715 static void igb_release_phy_82575(struct e1000_hw *hw)
716 {
717 u16 mask = E1000_SWFW_PHY0_SM;
718
719 if (hw->bus.func == E1000_FUNC_1)
720 mask = E1000_SWFW_PHY1_SM;
721 else if (hw->bus.func == E1000_FUNC_2)
722 mask = E1000_SWFW_PHY2_SM;
723 else if (hw->bus.func == E1000_FUNC_3)
724 mask = E1000_SWFW_PHY3_SM;
725
726 hw->mac.ops.release_swfw_sync(hw, mask);
727 }
728
729 /**
730 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
731 * @hw: pointer to the HW structure
732 * @offset: register offset to be read
733 * @data: pointer to the read data
734 *
735 * Reads the PHY register at offset using the serial gigabit media independent
736 * interface and stores the retrieved information in data.
737 **/
738 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
739 u16 *data)
740 {
741 s32 ret_val = -E1000_ERR_PARAM;
742
743 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
744 hw_dbg("PHY Address %u is out of range\n", offset);
745 goto out;
746 }
747
748 ret_val = hw->phy.ops.acquire(hw);
749 if (ret_val)
750 goto out;
751
752 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
753
754 hw->phy.ops.release(hw);
755
756 out:
757 return ret_val;
758 }
759
760 /**
761 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
762 * @hw: pointer to the HW structure
763 * @offset: register offset to write to
764 * @data: data to write at register offset
765 *
766 * Writes the data to PHY register at the offset using the serial gigabit
767 * media independent interface.
768 **/
769 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
770 u16 data)
771 {
772 s32 ret_val = -E1000_ERR_PARAM;
773
774
775 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
776 hw_dbg("PHY Address %d is out of range\n", offset);
777 goto out;
778 }
779
780 ret_val = hw->phy.ops.acquire(hw);
781 if (ret_val)
782 goto out;
783
784 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
785
786 hw->phy.ops.release(hw);
787
788 out:
789 return ret_val;
790 }
791
792 /**
793 * igb_get_phy_id_82575 - Retrieve PHY addr and id
794 * @hw: pointer to the HW structure
795 *
796 * Retrieves the PHY address and ID for both PHY's which do and do not use
797 * sgmi interface.
798 **/
799 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
800 {
801 struct e1000_phy_info *phy = &hw->phy;
802 s32 ret_val = 0;
803 u16 phy_id;
804 u32 ctrl_ext;
805 u32 mdic;
806
807 /* Extra read required for some PHY's on i354 */
808 if (hw->mac.type == e1000_i354)
809 igb_get_phy_id(hw);
810
811 /* For SGMII PHYs, we try the list of possible addresses until
812 * we find one that works. For non-SGMII PHYs
813 * (e.g. integrated copper PHYs), an address of 1 should
814 * work. The result of this function should mean phy->phy_addr
815 * and phy->id are set correctly.
816 */
817 if (!(igb_sgmii_active_82575(hw))) {
818 phy->addr = 1;
819 ret_val = igb_get_phy_id(hw);
820 goto out;
821 }
822
823 if (igb_sgmii_uses_mdio_82575(hw)) {
824 switch (hw->mac.type) {
825 case e1000_82575:
826 case e1000_82576:
827 mdic = rd32(E1000_MDIC);
828 mdic &= E1000_MDIC_PHY_MASK;
829 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
830 break;
831 case e1000_82580:
832 case e1000_i350:
833 case e1000_i354:
834 case e1000_i210:
835 case e1000_i211:
836 mdic = rd32(E1000_MDICNFG);
837 mdic &= E1000_MDICNFG_PHY_MASK;
838 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
839 break;
840 default:
841 ret_val = -E1000_ERR_PHY;
842 goto out;
843 break;
844 }
845 ret_val = igb_get_phy_id(hw);
846 goto out;
847 }
848
849 /* Power on sgmii phy if it is disabled */
850 ctrl_ext = rd32(E1000_CTRL_EXT);
851 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
852 wrfl();
853 msleep(300);
854
855 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
856 * Therefore, we need to test 1-7
857 */
858 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
859 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
860 if (ret_val == 0) {
861 hw_dbg("Vendor ID 0x%08X read at address %u\n",
862 phy_id, phy->addr);
863 /* At the time of this writing, The M88 part is
864 * the only supported SGMII PHY product.
865 */
866 if (phy_id == M88_VENDOR)
867 break;
868 } else {
869 hw_dbg("PHY address %u was unreadable\n", phy->addr);
870 }
871 }
872
873 /* A valid PHY type couldn't be found. */
874 if (phy->addr == 8) {
875 phy->addr = 0;
876 ret_val = -E1000_ERR_PHY;
877 goto out;
878 } else {
879 ret_val = igb_get_phy_id(hw);
880 }
881
882 /* restore previous sfp cage power state */
883 wr32(E1000_CTRL_EXT, ctrl_ext);
884
885 out:
886 return ret_val;
887 }
888
889 /**
890 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
891 * @hw: pointer to the HW structure
892 *
893 * Resets the PHY using the serial gigabit media independent interface.
894 **/
895 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
896 {
897 s32 ret_val;
898
899 /* This isn't a true "hard" reset, but is the only reset
900 * available to us at this time.
901 */
902
903 hw_dbg("Soft resetting SGMII attached PHY...\n");
904
905 /* SFP documentation requires the following to configure the SPF module
906 * to work on SGMII. No further documentation is given.
907 */
908 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
909 if (ret_val)
910 goto out;
911
912 ret_val = igb_phy_sw_reset(hw);
913
914 out:
915 return ret_val;
916 }
917
918 /**
919 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
920 * @hw: pointer to the HW structure
921 * @active: true to enable LPLU, false to disable
922 *
923 * Sets the LPLU D0 state according to the active flag. When
924 * activating LPLU this function also disables smart speed
925 * and vice versa. LPLU will not be activated unless the
926 * device autonegotiation advertisement meets standards of
927 * either 10 or 10/100 or 10/100/1000 at all duplexes.
928 * This is a function pointer entry point only called by
929 * PHY setup routines.
930 **/
931 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
932 {
933 struct e1000_phy_info *phy = &hw->phy;
934 s32 ret_val;
935 u16 data;
936
937 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
938 if (ret_val)
939 goto out;
940
941 if (active) {
942 data |= IGP02E1000_PM_D0_LPLU;
943 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
944 data);
945 if (ret_val)
946 goto out;
947
948 /* When LPLU is enabled, we should disable SmartSpeed */
949 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
950 &data);
951 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
952 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
953 data);
954 if (ret_val)
955 goto out;
956 } else {
957 data &= ~IGP02E1000_PM_D0_LPLU;
958 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
959 data);
960 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
961 * during Dx states where the power conservation is most
962 * important. During driver activity we should enable
963 * SmartSpeed, so performance is maintained.
964 */
965 if (phy->smart_speed == e1000_smart_speed_on) {
966 ret_val = phy->ops.read_reg(hw,
967 IGP01E1000_PHY_PORT_CONFIG, &data);
968 if (ret_val)
969 goto out;
970
971 data |= IGP01E1000_PSCFR_SMART_SPEED;
972 ret_val = phy->ops.write_reg(hw,
973 IGP01E1000_PHY_PORT_CONFIG, data);
974 if (ret_val)
975 goto out;
976 } else if (phy->smart_speed == e1000_smart_speed_off) {
977 ret_val = phy->ops.read_reg(hw,
978 IGP01E1000_PHY_PORT_CONFIG, &data);
979 if (ret_val)
980 goto out;
981
982 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
983 ret_val = phy->ops.write_reg(hw,
984 IGP01E1000_PHY_PORT_CONFIG, data);
985 if (ret_val)
986 goto out;
987 }
988 }
989
990 out:
991 return ret_val;
992 }
993
994 /**
995 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
996 * @hw: pointer to the HW structure
997 * @active: true to enable LPLU, false to disable
998 *
999 * Sets the LPLU D0 state according to the active flag. When
1000 * activating LPLU this function also disables smart speed
1001 * and vice versa. LPLU will not be activated unless the
1002 * device autonegotiation advertisement meets standards of
1003 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1004 * This is a function pointer entry point only called by
1005 * PHY setup routines.
1006 **/
1007 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1008 {
1009 struct e1000_phy_info *phy = &hw->phy;
1010 s32 ret_val = 0;
1011 u16 data;
1012
1013 data = rd32(E1000_82580_PHY_POWER_MGMT);
1014
1015 if (active) {
1016 data |= E1000_82580_PM_D0_LPLU;
1017
1018 /* When LPLU is enabled, we should disable SmartSpeed */
1019 data &= ~E1000_82580_PM_SPD;
1020 } else {
1021 data &= ~E1000_82580_PM_D0_LPLU;
1022
1023 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1024 * during Dx states where the power conservation is most
1025 * important. During driver activity we should enable
1026 * SmartSpeed, so performance is maintained.
1027 */
1028 if (phy->smart_speed == e1000_smart_speed_on)
1029 data |= E1000_82580_PM_SPD;
1030 else if (phy->smart_speed == e1000_smart_speed_off)
1031 data &= ~E1000_82580_PM_SPD; }
1032
1033 wr32(E1000_82580_PHY_POWER_MGMT, data);
1034 return ret_val;
1035 }
1036
1037 /**
1038 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1039 * @hw: pointer to the HW structure
1040 * @active: boolean used to enable/disable lplu
1041 *
1042 * Success returns 0, Failure returns 1
1043 *
1044 * The low power link up (lplu) state is set to the power management level D3
1045 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1046 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1047 * is used during Dx states where the power conservation is most important.
1048 * During driver activity, SmartSpeed should be enabled so performance is
1049 * maintained.
1050 **/
1051 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1052 {
1053 struct e1000_phy_info *phy = &hw->phy;
1054 s32 ret_val = 0;
1055 u16 data;
1056
1057 data = rd32(E1000_82580_PHY_POWER_MGMT);
1058
1059 if (!active) {
1060 data &= ~E1000_82580_PM_D3_LPLU;
1061 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1062 * during Dx states where the power conservation is most
1063 * important. During driver activity we should enable
1064 * SmartSpeed, so performance is maintained.
1065 */
1066 if (phy->smart_speed == e1000_smart_speed_on)
1067 data |= E1000_82580_PM_SPD;
1068 else if (phy->smart_speed == e1000_smart_speed_off)
1069 data &= ~E1000_82580_PM_SPD;
1070 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1071 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1072 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1073 data |= E1000_82580_PM_D3_LPLU;
1074 /* When LPLU is enabled, we should disable SmartSpeed */
1075 data &= ~E1000_82580_PM_SPD;
1076 }
1077
1078 wr32(E1000_82580_PHY_POWER_MGMT, data);
1079 return ret_val;
1080 }
1081
1082 /**
1083 * igb_acquire_nvm_82575 - Request for access to EEPROM
1084 * @hw: pointer to the HW structure
1085 *
1086 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1087 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1088 * Return successful if access grant bit set, else clear the request for
1089 * EEPROM access and return -E1000_ERR_NVM (-1).
1090 **/
1091 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1092 {
1093 s32 ret_val;
1094
1095 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1096 if (ret_val)
1097 goto out;
1098
1099 ret_val = igb_acquire_nvm(hw);
1100
1101 if (ret_val)
1102 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1103
1104 out:
1105 return ret_val;
1106 }
1107
1108 /**
1109 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1110 * @hw: pointer to the HW structure
1111 *
1112 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1113 * then release the semaphores acquired.
1114 **/
1115 static void igb_release_nvm_82575(struct e1000_hw *hw)
1116 {
1117 igb_release_nvm(hw);
1118 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1119 }
1120
1121 /**
1122 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1123 * @hw: pointer to the HW structure
1124 * @mask: specifies which semaphore to acquire
1125 *
1126 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1127 * will also specify which port we're acquiring the lock for.
1128 **/
1129 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1130 {
1131 u32 swfw_sync;
1132 u32 swmask = mask;
1133 u32 fwmask = mask << 16;
1134 s32 ret_val = 0;
1135 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1136
1137 while (i < timeout) {
1138 if (igb_get_hw_semaphore(hw)) {
1139 ret_val = -E1000_ERR_SWFW_SYNC;
1140 goto out;
1141 }
1142
1143 swfw_sync = rd32(E1000_SW_FW_SYNC);
1144 if (!(swfw_sync & (fwmask | swmask)))
1145 break;
1146
1147 /* Firmware currently using resource (fwmask)
1148 * or other software thread using resource (swmask)
1149 */
1150 igb_put_hw_semaphore(hw);
1151 mdelay(5);
1152 i++;
1153 }
1154
1155 if (i == timeout) {
1156 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1157 ret_val = -E1000_ERR_SWFW_SYNC;
1158 goto out;
1159 }
1160
1161 swfw_sync |= swmask;
1162 wr32(E1000_SW_FW_SYNC, swfw_sync);
1163
1164 igb_put_hw_semaphore(hw);
1165
1166 out:
1167 return ret_val;
1168 }
1169
1170 /**
1171 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1172 * @hw: pointer to the HW structure
1173 * @mask: specifies which semaphore to acquire
1174 *
1175 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1176 * will also specify which port we're releasing the lock for.
1177 **/
1178 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1179 {
1180 u32 swfw_sync;
1181
1182 while (igb_get_hw_semaphore(hw) != 0)
1183 ; /* Empty */
1184
1185 swfw_sync = rd32(E1000_SW_FW_SYNC);
1186 swfw_sync &= ~mask;
1187 wr32(E1000_SW_FW_SYNC, swfw_sync);
1188
1189 igb_put_hw_semaphore(hw);
1190 }
1191
1192 /**
1193 * igb_get_cfg_done_82575 - Read config done bit
1194 * @hw: pointer to the HW structure
1195 *
1196 * Read the management control register for the config done bit for
1197 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1198 * to read the config done bit, so an error is *ONLY* logged and returns
1199 * 0. If we were to return with error, EEPROM-less silicon
1200 * would not be able to be reset or change link.
1201 **/
1202 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1203 {
1204 s32 timeout = PHY_CFG_TIMEOUT;
1205 s32 ret_val = 0;
1206 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1207
1208 if (hw->bus.func == 1)
1209 mask = E1000_NVM_CFG_DONE_PORT_1;
1210 else if (hw->bus.func == E1000_FUNC_2)
1211 mask = E1000_NVM_CFG_DONE_PORT_2;
1212 else if (hw->bus.func == E1000_FUNC_3)
1213 mask = E1000_NVM_CFG_DONE_PORT_3;
1214
1215 while (timeout) {
1216 if (rd32(E1000_EEMNGCTL) & mask)
1217 break;
1218 msleep(1);
1219 timeout--;
1220 }
1221 if (!timeout)
1222 hw_dbg("MNG configuration cycle has not completed.\n");
1223
1224 /* If EEPROM is not marked present, init the PHY manually */
1225 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1226 (hw->phy.type == e1000_phy_igp_3))
1227 igb_phy_init_script_igp3(hw);
1228
1229 return ret_val;
1230 }
1231
1232 /**
1233 * igb_get_link_up_info_82575 - Get link speed/duplex info
1234 * @hw: pointer to the HW structure
1235 * @speed: stores the current speed
1236 * @duplex: stores the current duplex
1237 *
1238 * This is a wrapper function, if using the serial gigabit media independent
1239 * interface, use PCS to retrieve the link speed and duplex information.
1240 * Otherwise, use the generic function to get the link speed and duplex info.
1241 **/
1242 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1243 u16 *duplex)
1244 {
1245 s32 ret_val;
1246
1247 if (hw->phy.media_type != e1000_media_type_copper)
1248 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1249 duplex);
1250 else
1251 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1252 duplex);
1253
1254 return ret_val;
1255 }
1256
1257 /**
1258 * igb_check_for_link_82575 - Check for link
1259 * @hw: pointer to the HW structure
1260 *
1261 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1262 * use the generic interface for determining link.
1263 **/
1264 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1265 {
1266 s32 ret_val;
1267 u16 speed, duplex;
1268
1269 if (hw->phy.media_type != e1000_media_type_copper) {
1270 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1271 &duplex);
1272 /* Use this flag to determine if link needs to be checked or
1273 * not. If we have link clear the flag so that we do not
1274 * continue to check for link.
1275 */
1276 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1277
1278 /* Configure Flow Control now that Auto-Neg has completed.
1279 * First, we need to restore the desired flow control
1280 * settings because we may have had to re-autoneg with a
1281 * different link partner.
1282 */
1283 ret_val = igb_config_fc_after_link_up(hw);
1284 if (ret_val)
1285 hw_dbg("Error configuring flow control\n");
1286 } else {
1287 ret_val = igb_check_for_copper_link(hw);
1288 }
1289
1290 return ret_val;
1291 }
1292
1293 /**
1294 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1295 * @hw: pointer to the HW structure
1296 **/
1297 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1298 {
1299 u32 reg;
1300
1301
1302 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1303 !igb_sgmii_active_82575(hw))
1304 return;
1305
1306 /* Enable PCS to turn on link */
1307 reg = rd32(E1000_PCS_CFG0);
1308 reg |= E1000_PCS_CFG_PCS_EN;
1309 wr32(E1000_PCS_CFG0, reg);
1310
1311 /* Power up the laser */
1312 reg = rd32(E1000_CTRL_EXT);
1313 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1314 wr32(E1000_CTRL_EXT, reg);
1315
1316 /* flush the write to verify completion */
1317 wrfl();
1318 msleep(1);
1319 }
1320
1321 /**
1322 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1323 * @hw: pointer to the HW structure
1324 * @speed: stores the current speed
1325 * @duplex: stores the current duplex
1326 *
1327 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1328 * duplex, then store the values in the pointers provided.
1329 **/
1330 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1331 u16 *duplex)
1332 {
1333 struct e1000_mac_info *mac = &hw->mac;
1334 u32 pcs, status;
1335
1336 /* Set up defaults for the return values of this function */
1337 mac->serdes_has_link = false;
1338 *speed = 0;
1339 *duplex = 0;
1340
1341 /* Read the PCS Status register for link state. For non-copper mode,
1342 * the status register is not accurate. The PCS status register is
1343 * used instead.
1344 */
1345 pcs = rd32(E1000_PCS_LSTAT);
1346
1347 /* The link up bit determines when link is up on autoneg. The sync ok
1348 * gets set once both sides sync up and agree upon link. Stable link
1349 * can be determined by checking for both link up and link sync ok
1350 */
1351 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1352 mac->serdes_has_link = true;
1353
1354 /* Detect and store PCS speed */
1355 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1356 *speed = SPEED_1000;
1357 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1358 *speed = SPEED_100;
1359 else
1360 *speed = SPEED_10;
1361
1362 /* Detect and store PCS duplex */
1363 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1364 *duplex = FULL_DUPLEX;
1365 else
1366 *duplex = HALF_DUPLEX;
1367
1368 /* Check if it is an I354 2.5Gb backplane connection. */
1369 if (mac->type == e1000_i354) {
1370 status = rd32(E1000_STATUS);
1371 if ((status & E1000_STATUS_2P5_SKU) &&
1372 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1373 *speed = SPEED_2500;
1374 *duplex = FULL_DUPLEX;
1375 hw_dbg("2500 Mbs, ");
1376 hw_dbg("Full Duplex\n");
1377 }
1378 }
1379
1380 }
1381
1382 return 0;
1383 }
1384
1385 /**
1386 * igb_shutdown_serdes_link_82575 - Remove link during power down
1387 * @hw: pointer to the HW structure
1388 *
1389 * In the case of fiber serdes, shut down optics and PCS on driver unload
1390 * when management pass thru is not enabled.
1391 **/
1392 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1393 {
1394 u32 reg;
1395
1396 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1397 igb_sgmii_active_82575(hw))
1398 return;
1399
1400 if (!igb_enable_mng_pass_thru(hw)) {
1401 /* Disable PCS to turn off link */
1402 reg = rd32(E1000_PCS_CFG0);
1403 reg &= ~E1000_PCS_CFG_PCS_EN;
1404 wr32(E1000_PCS_CFG0, reg);
1405
1406 /* shutdown the laser */
1407 reg = rd32(E1000_CTRL_EXT);
1408 reg |= E1000_CTRL_EXT_SDP3_DATA;
1409 wr32(E1000_CTRL_EXT, reg);
1410
1411 /* flush the write to verify completion */
1412 wrfl();
1413 msleep(1);
1414 }
1415 }
1416
1417 /**
1418 * igb_reset_hw_82575 - Reset hardware
1419 * @hw: pointer to the HW structure
1420 *
1421 * This resets the hardware into a known state. This is a
1422 * function pointer entry point called by the api module.
1423 **/
1424 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1425 {
1426 u32 ctrl;
1427 s32 ret_val;
1428
1429 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1430 * on the last TLP read/write transaction when MAC is reset.
1431 */
1432 ret_val = igb_disable_pcie_master(hw);
1433 if (ret_val)
1434 hw_dbg("PCI-E Master disable polling has failed.\n");
1435
1436 /* set the completion timeout for interface */
1437 ret_val = igb_set_pcie_completion_timeout(hw);
1438 if (ret_val)
1439 hw_dbg("PCI-E Set completion timeout has failed.\n");
1440
1441 hw_dbg("Masking off all interrupts\n");
1442 wr32(E1000_IMC, 0xffffffff);
1443
1444 wr32(E1000_RCTL, 0);
1445 wr32(E1000_TCTL, E1000_TCTL_PSP);
1446 wrfl();
1447
1448 msleep(10);
1449
1450 ctrl = rd32(E1000_CTRL);
1451
1452 hw_dbg("Issuing a global reset to MAC\n");
1453 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1454
1455 ret_val = igb_get_auto_rd_done(hw);
1456 if (ret_val) {
1457 /* When auto config read does not complete, do not
1458 * return with an error. This can happen in situations
1459 * where there is no eeprom and prevents getting link.
1460 */
1461 hw_dbg("Auto Read Done did not complete\n");
1462 }
1463
1464 /* If EEPROM is not present, run manual init scripts */
1465 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1466 igb_reset_init_script_82575(hw);
1467
1468 /* Clear any pending interrupt events. */
1469 wr32(E1000_IMC, 0xffffffff);
1470 rd32(E1000_ICR);
1471
1472 /* Install any alternate MAC address into RAR0 */
1473 ret_val = igb_check_alt_mac_addr(hw);
1474
1475 return ret_val;
1476 }
1477
1478 /**
1479 * igb_init_hw_82575 - Initialize hardware
1480 * @hw: pointer to the HW structure
1481 *
1482 * This inits the hardware readying it for operation.
1483 **/
1484 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1485 {
1486 struct e1000_mac_info *mac = &hw->mac;
1487 s32 ret_val;
1488 u16 i, rar_count = mac->rar_entry_count;
1489
1490 /* Initialize identification LED */
1491 ret_val = igb_id_led_init(hw);
1492 if (ret_val) {
1493 hw_dbg("Error initializing identification LED\n");
1494 /* This is not fatal and we should not stop init due to this */
1495 }
1496
1497 /* Disabling VLAN filtering */
1498 hw_dbg("Initializing the IEEE VLAN\n");
1499 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1500 igb_clear_vfta_i350(hw);
1501 else
1502 igb_clear_vfta(hw);
1503
1504 /* Setup the receive address */
1505 igb_init_rx_addrs(hw, rar_count);
1506
1507 /* Zero out the Multicast HASH table */
1508 hw_dbg("Zeroing the MTA\n");
1509 for (i = 0; i < mac->mta_reg_count; i++)
1510 array_wr32(E1000_MTA, i, 0);
1511
1512 /* Zero out the Unicast HASH table */
1513 hw_dbg("Zeroing the UTA\n");
1514 for (i = 0; i < mac->uta_reg_count; i++)
1515 array_wr32(E1000_UTA, i, 0);
1516
1517 /* Setup link and flow control */
1518 ret_val = igb_setup_link(hw);
1519
1520 /* Clear all of the statistics registers (clear on read). It is
1521 * important that we do this after we have tried to establish link
1522 * because the symbol error count will increment wildly if there
1523 * is no link.
1524 */
1525 igb_clear_hw_cntrs_82575(hw);
1526 return ret_val;
1527 }
1528
1529 /**
1530 * igb_setup_copper_link_82575 - Configure copper link settings
1531 * @hw: pointer to the HW structure
1532 *
1533 * Configures the link for auto-neg or forced speed and duplex. Then we check
1534 * for link, once link is established calls to configure collision distance
1535 * and flow control are called.
1536 **/
1537 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1538 {
1539 u32 ctrl;
1540 s32 ret_val;
1541 u32 phpm_reg;
1542
1543 ctrl = rd32(E1000_CTRL);
1544 ctrl |= E1000_CTRL_SLU;
1545 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1546 wr32(E1000_CTRL, ctrl);
1547
1548 /* Clear Go Link Disconnect bit on supported devices */
1549 switch (hw->mac.type) {
1550 case e1000_82580:
1551 case e1000_i350:
1552 case e1000_i210:
1553 case e1000_i211:
1554 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1555 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1556 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1557 break;
1558 default:
1559 break;
1560 }
1561
1562 ret_val = igb_setup_serdes_link_82575(hw);
1563 if (ret_val)
1564 goto out;
1565
1566 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1567 /* allow time for SFP cage time to power up phy */
1568 msleep(300);
1569
1570 ret_val = hw->phy.ops.reset(hw);
1571 if (ret_val) {
1572 hw_dbg("Error resetting the PHY.\n");
1573 goto out;
1574 }
1575 }
1576 switch (hw->phy.type) {
1577 case e1000_phy_i210:
1578 case e1000_phy_m88:
1579 switch (hw->phy.id) {
1580 case I347AT4_E_PHY_ID:
1581 case M88E1112_E_PHY_ID:
1582 case M88E1543_E_PHY_ID:
1583 case I210_I_PHY_ID:
1584 ret_val = igb_copper_link_setup_m88_gen2(hw);
1585 break;
1586 default:
1587 ret_val = igb_copper_link_setup_m88(hw);
1588 break;
1589 }
1590 break;
1591 case e1000_phy_igp_3:
1592 ret_val = igb_copper_link_setup_igp(hw);
1593 break;
1594 case e1000_phy_82580:
1595 ret_val = igb_copper_link_setup_82580(hw);
1596 break;
1597 default:
1598 ret_val = -E1000_ERR_PHY;
1599 break;
1600 }
1601
1602 if (ret_val)
1603 goto out;
1604
1605 ret_val = igb_setup_copper_link(hw);
1606 out:
1607 return ret_val;
1608 }
1609
1610 /**
1611 * igb_setup_serdes_link_82575 - Setup link for serdes
1612 * @hw: pointer to the HW structure
1613 *
1614 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1615 * used on copper connections where the serialized gigabit media independent
1616 * interface (sgmii), or serdes fiber is being used. Configures the link
1617 * for auto-negotiation or forces speed/duplex.
1618 **/
1619 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1620 {
1621 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1622 bool pcs_autoneg;
1623 s32 ret_val = E1000_SUCCESS;
1624 u16 data;
1625
1626 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1627 !igb_sgmii_active_82575(hw))
1628 return ret_val;
1629
1630
1631 /* On the 82575, SerDes loopback mode persists until it is
1632 * explicitly turned off or a power cycle is performed. A read to
1633 * the register does not indicate its status. Therefore, we ensure
1634 * loopback mode is disabled during initialization.
1635 */
1636 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1637
1638 /* power on the sfp cage if present and turn on I2C */
1639 ctrl_ext = rd32(E1000_CTRL_EXT);
1640 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1641 ctrl_ext |= E1000_CTRL_I2C_ENA;
1642 wr32(E1000_CTRL_EXT, ctrl_ext);
1643
1644 ctrl_reg = rd32(E1000_CTRL);
1645 ctrl_reg |= E1000_CTRL_SLU;
1646
1647 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1648 /* set both sw defined pins */
1649 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1650
1651 /* Set switch control to serdes energy detect */
1652 reg = rd32(E1000_CONNSW);
1653 reg |= E1000_CONNSW_ENRGSRC;
1654 wr32(E1000_CONNSW, reg);
1655 }
1656
1657 reg = rd32(E1000_PCS_LCTL);
1658
1659 /* default pcs_autoneg to the same setting as mac autoneg */
1660 pcs_autoneg = hw->mac.autoneg;
1661
1662 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1663 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1664 /* sgmii mode lets the phy handle forcing speed/duplex */
1665 pcs_autoneg = true;
1666 /* autoneg time out should be disabled for SGMII mode */
1667 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1668 break;
1669 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1670 /* disable PCS autoneg and support parallel detect only */
1671 pcs_autoneg = false;
1672 default:
1673 if (hw->mac.type == e1000_82575 ||
1674 hw->mac.type == e1000_82576) {
1675 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1676 if (ret_val) {
1677 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
1678 return ret_val;
1679 }
1680
1681 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1682 pcs_autoneg = false;
1683 }
1684
1685 /* non-SGMII modes only supports a speed of 1000/Full for the
1686 * link so it is best to just force the MAC and let the pcs
1687 * link either autoneg or be forced to 1000/Full
1688 */
1689 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1690 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1691
1692 /* set speed of 1000/Full if speed/duplex is forced */
1693 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1694 break;
1695 }
1696
1697 wr32(E1000_CTRL, ctrl_reg);
1698
1699 /* New SerDes mode allows for forcing speed or autonegotiating speed
1700 * at 1gb. Autoneg should be default set by most drivers. This is the
1701 * mode that will be compatible with older link partners and switches.
1702 * However, both are supported by the hardware and some drivers/tools.
1703 */
1704 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1705 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1706
1707 if (pcs_autoneg) {
1708 /* Set PCS register for autoneg */
1709 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1710 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1711
1712 /* Disable force flow control for autoneg */
1713 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1714
1715 /* Configure flow control advertisement for autoneg */
1716 anadv_reg = rd32(E1000_PCS_ANADV);
1717 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1718 switch (hw->fc.requested_mode) {
1719 case e1000_fc_full:
1720 case e1000_fc_rx_pause:
1721 anadv_reg |= E1000_TXCW_ASM_DIR;
1722 anadv_reg |= E1000_TXCW_PAUSE;
1723 break;
1724 case e1000_fc_tx_pause:
1725 anadv_reg |= E1000_TXCW_ASM_DIR;
1726 break;
1727 default:
1728 break;
1729 }
1730 wr32(E1000_PCS_ANADV, anadv_reg);
1731
1732 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1733 } else {
1734 /* Set PCS register for forced link */
1735 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1736
1737 /* Force flow control for forced link */
1738 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1739
1740 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1741 }
1742
1743 wr32(E1000_PCS_LCTL, reg);
1744
1745 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1746 igb_force_mac_fc(hw);
1747
1748 return ret_val;
1749 }
1750
1751 /**
1752 * igb_sgmii_active_82575 - Return sgmii state
1753 * @hw: pointer to the HW structure
1754 *
1755 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1756 * which can be enabled for use in the embedded applications. Simply
1757 * return the current state of the sgmii interface.
1758 **/
1759 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1760 {
1761 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1762 return dev_spec->sgmii_active;
1763 }
1764
1765 /**
1766 * igb_reset_init_script_82575 - Inits HW defaults after reset
1767 * @hw: pointer to the HW structure
1768 *
1769 * Inits recommended HW defaults after a reset when there is no EEPROM
1770 * detected. This is only for the 82575.
1771 **/
1772 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1773 {
1774 if (hw->mac.type == e1000_82575) {
1775 hw_dbg("Running reset init script for 82575\n");
1776 /* SerDes configuration via SERDESCTRL */
1777 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1778 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1779 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1780 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1781
1782 /* CCM configuration via CCMCTL register */
1783 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1784 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1785
1786 /* PCIe lanes configuration */
1787 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1788 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1789 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1790 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1791
1792 /* PCIe PLL Configuration */
1793 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1794 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1795 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1796 }
1797
1798 return 0;
1799 }
1800
1801 /**
1802 * igb_read_mac_addr_82575 - Read device MAC address
1803 * @hw: pointer to the HW structure
1804 **/
1805 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1806 {
1807 s32 ret_val = 0;
1808
1809 /* If there's an alternate MAC address place it in RAR0
1810 * so that it will override the Si installed default perm
1811 * address.
1812 */
1813 ret_val = igb_check_alt_mac_addr(hw);
1814 if (ret_val)
1815 goto out;
1816
1817 ret_val = igb_read_mac_addr(hw);
1818
1819 out:
1820 return ret_val;
1821 }
1822
1823 /**
1824 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1825 * @hw: pointer to the HW structure
1826 *
1827 * In the case of a PHY power down to save power, or to turn off link during a
1828 * driver unload, or wake on lan is not enabled, remove the link.
1829 **/
1830 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1831 {
1832 /* If the management interface is not enabled, then power down */
1833 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1834 igb_power_down_phy_copper(hw);
1835 }
1836
1837 /**
1838 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1839 * @hw: pointer to the HW structure
1840 *
1841 * Clears the hardware counters by reading the counter registers.
1842 **/
1843 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1844 {
1845 igb_clear_hw_cntrs_base(hw);
1846
1847 rd32(E1000_PRC64);
1848 rd32(E1000_PRC127);
1849 rd32(E1000_PRC255);
1850 rd32(E1000_PRC511);
1851 rd32(E1000_PRC1023);
1852 rd32(E1000_PRC1522);
1853 rd32(E1000_PTC64);
1854 rd32(E1000_PTC127);
1855 rd32(E1000_PTC255);
1856 rd32(E1000_PTC511);
1857 rd32(E1000_PTC1023);
1858 rd32(E1000_PTC1522);
1859
1860 rd32(E1000_ALGNERRC);
1861 rd32(E1000_RXERRC);
1862 rd32(E1000_TNCRS);
1863 rd32(E1000_CEXTERR);
1864 rd32(E1000_TSCTC);
1865 rd32(E1000_TSCTFC);
1866
1867 rd32(E1000_MGTPRC);
1868 rd32(E1000_MGTPDC);
1869 rd32(E1000_MGTPTC);
1870
1871 rd32(E1000_IAC);
1872 rd32(E1000_ICRXOC);
1873
1874 rd32(E1000_ICRXPTC);
1875 rd32(E1000_ICRXATC);
1876 rd32(E1000_ICTXPTC);
1877 rd32(E1000_ICTXATC);
1878 rd32(E1000_ICTXQEC);
1879 rd32(E1000_ICTXQMTC);
1880 rd32(E1000_ICRXDMTC);
1881
1882 rd32(E1000_CBTMPC);
1883 rd32(E1000_HTDPMC);
1884 rd32(E1000_CBRMPC);
1885 rd32(E1000_RPTHC);
1886 rd32(E1000_HGPTC);
1887 rd32(E1000_HTCBDPC);
1888 rd32(E1000_HGORCL);
1889 rd32(E1000_HGORCH);
1890 rd32(E1000_HGOTCL);
1891 rd32(E1000_HGOTCH);
1892 rd32(E1000_LENERRS);
1893
1894 /* This register should not be read in copper configurations */
1895 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1896 igb_sgmii_active_82575(hw))
1897 rd32(E1000_SCVPC);
1898 }
1899
1900 /**
1901 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1902 * @hw: pointer to the HW structure
1903 *
1904 * After rx enable if managability is enabled then there is likely some
1905 * bad data at the start of the fifo and possibly in the DMA fifo. This
1906 * function clears the fifos and flushes any packets that came in as rx was
1907 * being enabled.
1908 **/
1909 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1910 {
1911 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1912 int i, ms_wait;
1913
1914 if (hw->mac.type != e1000_82575 ||
1915 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1916 return;
1917
1918 /* Disable all RX queues */
1919 for (i = 0; i < 4; i++) {
1920 rxdctl[i] = rd32(E1000_RXDCTL(i));
1921 wr32(E1000_RXDCTL(i),
1922 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1923 }
1924 /* Poll all queues to verify they have shut down */
1925 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1926 msleep(1);
1927 rx_enabled = 0;
1928 for (i = 0; i < 4; i++)
1929 rx_enabled |= rd32(E1000_RXDCTL(i));
1930 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1931 break;
1932 }
1933
1934 if (ms_wait == 10)
1935 hw_dbg("Queue disable timed out after 10ms\n");
1936
1937 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1938 * incoming packets are rejected. Set enable and wait 2ms so that
1939 * any packet that was coming in as RCTL.EN was set is flushed
1940 */
1941 rfctl = rd32(E1000_RFCTL);
1942 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1943
1944 rlpml = rd32(E1000_RLPML);
1945 wr32(E1000_RLPML, 0);
1946
1947 rctl = rd32(E1000_RCTL);
1948 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1949 temp_rctl |= E1000_RCTL_LPE;
1950
1951 wr32(E1000_RCTL, temp_rctl);
1952 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1953 wrfl();
1954 msleep(2);
1955
1956 /* Enable RX queues that were previously enabled and restore our
1957 * previous state
1958 */
1959 for (i = 0; i < 4; i++)
1960 wr32(E1000_RXDCTL(i), rxdctl[i]);
1961 wr32(E1000_RCTL, rctl);
1962 wrfl();
1963
1964 wr32(E1000_RLPML, rlpml);
1965 wr32(E1000_RFCTL, rfctl);
1966
1967 /* Flush receive errors generated by workaround */
1968 rd32(E1000_ROC);
1969 rd32(E1000_RNBC);
1970 rd32(E1000_MPC);
1971 }
1972
1973 /**
1974 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1975 * @hw: pointer to the HW structure
1976 *
1977 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1978 * however the hardware default for these parts is 500us to 1ms which is less
1979 * than the 10ms recommended by the pci-e spec. To address this we need to
1980 * increase the value to either 10ms to 200ms for capability version 1 config,
1981 * or 16ms to 55ms for version 2.
1982 **/
1983 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1984 {
1985 u32 gcr = rd32(E1000_GCR);
1986 s32 ret_val = 0;
1987 u16 pcie_devctl2;
1988
1989 /* only take action if timeout value is defaulted to 0 */
1990 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1991 goto out;
1992
1993 /* if capabilities version is type 1 we can write the
1994 * timeout of 10ms to 200ms through the GCR register
1995 */
1996 if (!(gcr & E1000_GCR_CAP_VER2)) {
1997 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1998 goto out;
1999 }
2000
2001 /* for version 2 capabilities we need to write the config space
2002 * directly in order to set the completion timeout value for
2003 * 16ms to 55ms
2004 */
2005 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2006 &pcie_devctl2);
2007 if (ret_val)
2008 goto out;
2009
2010 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2011
2012 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2013 &pcie_devctl2);
2014 out:
2015 /* disable completion timeout resend */
2016 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2017
2018 wr32(E1000_GCR, gcr);
2019 return ret_val;
2020 }
2021
2022 /**
2023 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2024 * @hw: pointer to the hardware struct
2025 * @enable: state to enter, either enabled or disabled
2026 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2027 *
2028 * enables/disables L2 switch anti-spoofing functionality.
2029 **/
2030 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2031 {
2032 u32 reg_val, reg_offset;
2033
2034 switch (hw->mac.type) {
2035 case e1000_82576:
2036 reg_offset = E1000_DTXSWC;
2037 break;
2038 case e1000_i350:
2039 case e1000_i354:
2040 reg_offset = E1000_TXSWC;
2041 break;
2042 default:
2043 return;
2044 }
2045
2046 reg_val = rd32(reg_offset);
2047 if (enable) {
2048 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2049 E1000_DTXSWC_VLAN_SPOOF_MASK);
2050 /* The PF can spoof - it has to in order to
2051 * support emulation mode NICs
2052 */
2053 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2054 } else {
2055 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2056 E1000_DTXSWC_VLAN_SPOOF_MASK);
2057 }
2058 wr32(reg_offset, reg_val);
2059 }
2060
2061 /**
2062 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2063 * @hw: pointer to the hardware struct
2064 * @enable: state to enter, either enabled or disabled
2065 *
2066 * enables/disables L2 switch loopback functionality.
2067 **/
2068 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2069 {
2070 u32 dtxswc;
2071
2072 switch (hw->mac.type) {
2073 case e1000_82576:
2074 dtxswc = rd32(E1000_DTXSWC);
2075 if (enable)
2076 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2077 else
2078 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2079 wr32(E1000_DTXSWC, dtxswc);
2080 break;
2081 case e1000_i354:
2082 case e1000_i350:
2083 dtxswc = rd32(E1000_TXSWC);
2084 if (enable)
2085 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2086 else
2087 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2088 wr32(E1000_TXSWC, dtxswc);
2089 break;
2090 default:
2091 /* Currently no other hardware supports loopback */
2092 break;
2093 }
2094
2095 }
2096
2097 /**
2098 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2099 * @hw: pointer to the hardware struct
2100 * @enable: state to enter, either enabled or disabled
2101 *
2102 * enables/disables replication of packets across multiple pools.
2103 **/
2104 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2105 {
2106 u32 vt_ctl = rd32(E1000_VT_CTL);
2107
2108 if (enable)
2109 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2110 else
2111 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2112
2113 wr32(E1000_VT_CTL, vt_ctl);
2114 }
2115
2116 /**
2117 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2118 * @hw: pointer to the HW structure
2119 * @offset: register offset to be read
2120 * @data: pointer to the read data
2121 *
2122 * Reads the MDI control register in the PHY at offset and stores the
2123 * information read to data.
2124 **/
2125 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2126 {
2127 s32 ret_val;
2128
2129 ret_val = hw->phy.ops.acquire(hw);
2130 if (ret_val)
2131 goto out;
2132
2133 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2134
2135 hw->phy.ops.release(hw);
2136
2137 out:
2138 return ret_val;
2139 }
2140
2141 /**
2142 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2143 * @hw: pointer to the HW structure
2144 * @offset: register offset to write to
2145 * @data: data to write to register at offset
2146 *
2147 * Writes data to MDI control register in the PHY at offset.
2148 **/
2149 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2150 {
2151 s32 ret_val;
2152
2153
2154 ret_val = hw->phy.ops.acquire(hw);
2155 if (ret_val)
2156 goto out;
2157
2158 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2159
2160 hw->phy.ops.release(hw);
2161
2162 out:
2163 return ret_val;
2164 }
2165
2166 /**
2167 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2168 * @hw: pointer to the HW structure
2169 *
2170 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2171 * the values found in the EEPROM. This addresses an issue in which these
2172 * bits are not restored from EEPROM after reset.
2173 **/
2174 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2175 {
2176 s32 ret_val = 0;
2177 u32 mdicnfg;
2178 u16 nvm_data = 0;
2179
2180 if (hw->mac.type != e1000_82580)
2181 goto out;
2182 if (!igb_sgmii_active_82575(hw))
2183 goto out;
2184
2185 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2186 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2187 &nvm_data);
2188 if (ret_val) {
2189 hw_dbg("NVM Read Error\n");
2190 goto out;
2191 }
2192
2193 mdicnfg = rd32(E1000_MDICNFG);
2194 if (nvm_data & NVM_WORD24_EXT_MDIO)
2195 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2196 if (nvm_data & NVM_WORD24_COM_MDIO)
2197 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2198 wr32(E1000_MDICNFG, mdicnfg);
2199 out:
2200 return ret_val;
2201 }
2202
2203 /**
2204 * igb_reset_hw_82580 - Reset hardware
2205 * @hw: pointer to the HW structure
2206 *
2207 * This resets function or entire device (all ports, etc.)
2208 * to a known state.
2209 **/
2210 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2211 {
2212 s32 ret_val = 0;
2213 /* BH SW mailbox bit in SW_FW_SYNC */
2214 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2215 u32 ctrl;
2216 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2217
2218 hw->dev_spec._82575.global_device_reset = false;
2219
2220 /* due to hw errata, global device reset doesn't always
2221 * work on 82580
2222 */
2223 if (hw->mac.type == e1000_82580)
2224 global_device_reset = false;
2225
2226 /* Get current control state. */
2227 ctrl = rd32(E1000_CTRL);
2228
2229 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2230 * on the last TLP read/write transaction when MAC is reset.
2231 */
2232 ret_val = igb_disable_pcie_master(hw);
2233 if (ret_val)
2234 hw_dbg("PCI-E Master disable polling has failed.\n");
2235
2236 hw_dbg("Masking off all interrupts\n");
2237 wr32(E1000_IMC, 0xffffffff);
2238 wr32(E1000_RCTL, 0);
2239 wr32(E1000_TCTL, E1000_TCTL_PSP);
2240 wrfl();
2241
2242 msleep(10);
2243
2244 /* Determine whether or not a global dev reset is requested */
2245 if (global_device_reset &&
2246 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2247 global_device_reset = false;
2248
2249 if (global_device_reset &&
2250 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2251 ctrl |= E1000_CTRL_DEV_RST;
2252 else
2253 ctrl |= E1000_CTRL_RST;
2254
2255 wr32(E1000_CTRL, ctrl);
2256 wrfl();
2257
2258 /* Add delay to insure DEV_RST has time to complete */
2259 if (global_device_reset)
2260 msleep(5);
2261
2262 ret_val = igb_get_auto_rd_done(hw);
2263 if (ret_val) {
2264 /* When auto config read does not complete, do not
2265 * return with an error. This can happen in situations
2266 * where there is no eeprom and prevents getting link.
2267 */
2268 hw_dbg("Auto Read Done did not complete\n");
2269 }
2270
2271 /* clear global device reset status bit */
2272 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2273
2274 /* Clear any pending interrupt events. */
2275 wr32(E1000_IMC, 0xffffffff);
2276 rd32(E1000_ICR);
2277
2278 ret_val = igb_reset_mdicnfg_82580(hw);
2279 if (ret_val)
2280 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2281
2282 /* Install any alternate MAC address into RAR0 */
2283 ret_val = igb_check_alt_mac_addr(hw);
2284
2285 /* Release semaphore */
2286 if (global_device_reset)
2287 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2288
2289 return ret_val;
2290 }
2291
2292 /**
2293 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2294 * @data: data received by reading RXPBS register
2295 *
2296 * The 82580 uses a table based approach for packet buffer allocation sizes.
2297 * This function converts the retrieved value into the correct table value
2298 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2299 * 0x0 36 72 144 1 2 4 8 16
2300 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2301 */
2302 u16 igb_rxpbs_adjust_82580(u32 data)
2303 {
2304 u16 ret_val = 0;
2305
2306 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2307 ret_val = e1000_82580_rxpbs_table[data];
2308
2309 return ret_val;
2310 }
2311
2312 /**
2313 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2314 * checksum
2315 * @hw: pointer to the HW structure
2316 * @offset: offset in words of the checksum protected region
2317 *
2318 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2319 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2320 **/
2321 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2322 u16 offset)
2323 {
2324 s32 ret_val = 0;
2325 u16 checksum = 0;
2326 u16 i, nvm_data;
2327
2328 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2329 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2330 if (ret_val) {
2331 hw_dbg("NVM Read Error\n");
2332 goto out;
2333 }
2334 checksum += nvm_data;
2335 }
2336
2337 if (checksum != (u16) NVM_SUM) {
2338 hw_dbg("NVM Checksum Invalid\n");
2339 ret_val = -E1000_ERR_NVM;
2340 goto out;
2341 }
2342
2343 out:
2344 return ret_val;
2345 }
2346
2347 /**
2348 * igb_update_nvm_checksum_with_offset - Update EEPROM
2349 * checksum
2350 * @hw: pointer to the HW structure
2351 * @offset: offset in words of the checksum protected region
2352 *
2353 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2354 * up to the checksum. Then calculates the EEPROM checksum and writes the
2355 * value to the EEPROM.
2356 **/
2357 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2358 {
2359 s32 ret_val;
2360 u16 checksum = 0;
2361 u16 i, nvm_data;
2362
2363 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2364 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2365 if (ret_val) {
2366 hw_dbg("NVM Read Error while updating checksum.\n");
2367 goto out;
2368 }
2369 checksum += nvm_data;
2370 }
2371 checksum = (u16) NVM_SUM - checksum;
2372 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2373 &checksum);
2374 if (ret_val)
2375 hw_dbg("NVM Write Error while updating checksum.\n");
2376
2377 out:
2378 return ret_val;
2379 }
2380
2381 /**
2382 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2383 * @hw: pointer to the HW structure
2384 *
2385 * Calculates the EEPROM section checksum by reading/adding each word of
2386 * the EEPROM and then verifies that the sum of the EEPROM is
2387 * equal to 0xBABA.
2388 **/
2389 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2390 {
2391 s32 ret_val = 0;
2392 u16 eeprom_regions_count = 1;
2393 u16 j, nvm_data;
2394 u16 nvm_offset;
2395
2396 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2397 if (ret_val) {
2398 hw_dbg("NVM Read Error\n");
2399 goto out;
2400 }
2401
2402 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2403 /* if checksums compatibility bit is set validate checksums
2404 * for all 4 ports.
2405 */
2406 eeprom_regions_count = 4;
2407 }
2408
2409 for (j = 0; j < eeprom_regions_count; j++) {
2410 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2411 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2412 nvm_offset);
2413 if (ret_val != 0)
2414 goto out;
2415 }
2416
2417 out:
2418 return ret_val;
2419 }
2420
2421 /**
2422 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2423 * @hw: pointer to the HW structure
2424 *
2425 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2426 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2427 * checksum and writes the value to the EEPROM.
2428 **/
2429 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2430 {
2431 s32 ret_val;
2432 u16 j, nvm_data;
2433 u16 nvm_offset;
2434
2435 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2436 if (ret_val) {
2437 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
2438 goto out;
2439 }
2440
2441 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2442 /* set compatibility bit to validate checksums appropriately */
2443 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2444 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2445 &nvm_data);
2446 if (ret_val) {
2447 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
2448 goto out;
2449 }
2450 }
2451
2452 for (j = 0; j < 4; j++) {
2453 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2454 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2455 if (ret_val)
2456 goto out;
2457 }
2458
2459 out:
2460 return ret_val;
2461 }
2462
2463 /**
2464 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2465 * @hw: pointer to the HW structure
2466 *
2467 * Calculates the EEPROM section checksum by reading/adding each word of
2468 * the EEPROM and then verifies that the sum of the EEPROM is
2469 * equal to 0xBABA.
2470 **/
2471 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2472 {
2473 s32 ret_val = 0;
2474 u16 j;
2475 u16 nvm_offset;
2476
2477 for (j = 0; j < 4; j++) {
2478 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2479 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2480 nvm_offset);
2481 if (ret_val != 0)
2482 goto out;
2483 }
2484
2485 out:
2486 return ret_val;
2487 }
2488
2489 /**
2490 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2491 * @hw: pointer to the HW structure
2492 *
2493 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2494 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2495 * checksum and writes the value to the EEPROM.
2496 **/
2497 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2498 {
2499 s32 ret_val = 0;
2500 u16 j;
2501 u16 nvm_offset;
2502
2503 for (j = 0; j < 4; j++) {
2504 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2505 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2506 if (ret_val != 0)
2507 goto out;
2508 }
2509
2510 out:
2511 return ret_val;
2512 }
2513
2514 /**
2515 * __igb_access_emi_reg - Read/write EMI register
2516 * @hw: pointer to the HW structure
2517 * @addr: EMI address to program
2518 * @data: pointer to value to read/write from/to the EMI address
2519 * @read: boolean flag to indicate read or write
2520 **/
2521 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2522 u16 *data, bool read)
2523 {
2524 s32 ret_val = E1000_SUCCESS;
2525
2526 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2527 if (ret_val)
2528 return ret_val;
2529
2530 if (read)
2531 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2532 else
2533 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2534
2535 return ret_val;
2536 }
2537
2538 /**
2539 * igb_read_emi_reg - Read Extended Management Interface register
2540 * @hw: pointer to the HW structure
2541 * @addr: EMI address to program
2542 * @data: value to be read from the EMI address
2543 **/
2544 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2545 {
2546 return __igb_access_emi_reg(hw, addr, data, true);
2547 }
2548
2549 /**
2550 * igb_set_eee_i350 - Enable/disable EEE support
2551 * @hw: pointer to the HW structure
2552 *
2553 * Enable/disable EEE based on setting in dev_spec structure.
2554 *
2555 **/
2556 s32 igb_set_eee_i350(struct e1000_hw *hw)
2557 {
2558 s32 ret_val = 0;
2559 u32 ipcnfg, eeer;
2560
2561 if ((hw->mac.type < e1000_i350) ||
2562 (hw->phy.media_type != e1000_media_type_copper))
2563 goto out;
2564 ipcnfg = rd32(E1000_IPCNFG);
2565 eeer = rd32(E1000_EEER);
2566
2567 /* enable or disable per user setting */
2568 if (!(hw->dev_spec._82575.eee_disable)) {
2569 u32 eee_su = rd32(E1000_EEE_SU);
2570
2571 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2572 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2573 E1000_EEER_LPI_FC);
2574
2575 /* This bit should not be set in normal operation. */
2576 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2577 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2578
2579 } else {
2580 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2581 E1000_IPCNFG_EEE_100M_AN);
2582 eeer &= ~(E1000_EEER_TX_LPI_EN |
2583 E1000_EEER_RX_LPI_EN |
2584 E1000_EEER_LPI_FC);
2585 }
2586 wr32(E1000_IPCNFG, ipcnfg);
2587 wr32(E1000_EEER, eeer);
2588 rd32(E1000_IPCNFG);
2589 rd32(E1000_EEER);
2590 out:
2591
2592 return ret_val;
2593 }
2594
2595 /**
2596 * igb_set_eee_i354 - Enable/disable EEE support
2597 * @hw: pointer to the HW structure
2598 *
2599 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2600 *
2601 **/
2602 s32 igb_set_eee_i354(struct e1000_hw *hw)
2603 {
2604 struct e1000_phy_info *phy = &hw->phy;
2605 s32 ret_val = 0;
2606 u16 phy_data;
2607
2608 if ((hw->phy.media_type != e1000_media_type_copper) ||
2609 (phy->id != M88E1543_E_PHY_ID))
2610 goto out;
2611
2612 if (!hw->dev_spec._82575.eee_disable) {
2613 /* Switch to PHY page 18. */
2614 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2615 if (ret_val)
2616 goto out;
2617
2618 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2619 &phy_data);
2620 if (ret_val)
2621 goto out;
2622
2623 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2624 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2625 phy_data);
2626 if (ret_val)
2627 goto out;
2628
2629 /* Return the PHY to page 0. */
2630 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2631 if (ret_val)
2632 goto out;
2633
2634 /* Turn on EEE advertisement. */
2635 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2636 E1000_EEE_ADV_DEV_I354,
2637 &phy_data);
2638 if (ret_val)
2639 goto out;
2640
2641 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2642 E1000_EEE_ADV_1000_SUPPORTED;
2643 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2644 E1000_EEE_ADV_DEV_I354,
2645 phy_data);
2646 } else {
2647 /* Turn off EEE advertisement. */
2648 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2649 E1000_EEE_ADV_DEV_I354,
2650 &phy_data);
2651 if (ret_val)
2652 goto out;
2653
2654 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2655 E1000_EEE_ADV_1000_SUPPORTED);
2656 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2657 E1000_EEE_ADV_DEV_I354,
2658 phy_data);
2659 }
2660
2661 out:
2662 return ret_val;
2663 }
2664
2665 /**
2666 * igb_get_eee_status_i354 - Get EEE status
2667 * @hw: pointer to the HW structure
2668 * @status: EEE status
2669 *
2670 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2671 * been received.
2672 **/
2673 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2674 {
2675 struct e1000_phy_info *phy = &hw->phy;
2676 s32 ret_val = 0;
2677 u16 phy_data;
2678
2679 /* Check if EEE is supported on this device. */
2680 if ((hw->phy.media_type != e1000_media_type_copper) ||
2681 (phy->id != M88E1543_E_PHY_ID))
2682 goto out;
2683
2684 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2685 E1000_PCS_STATUS_DEV_I354,
2686 &phy_data);
2687 if (ret_val)
2688 goto out;
2689
2690 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2691 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2692
2693 out:
2694 return ret_val;
2695 }
2696
2697 static const u8 e1000_emc_temp_data[4] = {
2698 E1000_EMC_INTERNAL_DATA,
2699 E1000_EMC_DIODE1_DATA,
2700 E1000_EMC_DIODE2_DATA,
2701 E1000_EMC_DIODE3_DATA
2702 };
2703 static const u8 e1000_emc_therm_limit[4] = {
2704 E1000_EMC_INTERNAL_THERM_LIMIT,
2705 E1000_EMC_DIODE1_THERM_LIMIT,
2706 E1000_EMC_DIODE2_THERM_LIMIT,
2707 E1000_EMC_DIODE3_THERM_LIMIT
2708 };
2709
2710 #ifdef CONFIG_IGB_HWMON
2711 /**
2712 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2713 * @hw: pointer to hardware structure
2714 *
2715 * Updates the temperatures in mac.thermal_sensor_data
2716 **/
2717 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2718 {
2719 s32 status = E1000_SUCCESS;
2720 u16 ets_offset;
2721 u16 ets_cfg;
2722 u16 ets_sensor;
2723 u8 num_sensors;
2724 u8 sensor_index;
2725 u8 sensor_location;
2726 u8 i;
2727 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2728
2729 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2730 return E1000_NOT_IMPLEMENTED;
2731
2732 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2733
2734 /* Return the internal sensor only if ETS is unsupported */
2735 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2736 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2737 return status;
2738
2739 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2740 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2741 != NVM_ETS_TYPE_EMC)
2742 return E1000_NOT_IMPLEMENTED;
2743
2744 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2745 if (num_sensors > E1000_MAX_SENSORS)
2746 num_sensors = E1000_MAX_SENSORS;
2747
2748 for (i = 1; i < num_sensors; i++) {
2749 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2750 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2751 NVM_ETS_DATA_INDEX_SHIFT);
2752 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2753 NVM_ETS_DATA_LOC_SHIFT);
2754
2755 if (sensor_location != 0)
2756 hw->phy.ops.read_i2c_byte(hw,
2757 e1000_emc_temp_data[sensor_index],
2758 E1000_I2C_THERMAL_SENSOR_ADDR,
2759 &data->sensor[i].temp);
2760 }
2761 return status;
2762 }
2763
2764 /**
2765 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2766 * @hw: pointer to hardware structure
2767 *
2768 * Sets the thermal sensor thresholds according to the NVM map
2769 * and save off the threshold and location values into mac.thermal_sensor_data
2770 **/
2771 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2772 {
2773 s32 status = E1000_SUCCESS;
2774 u16 ets_offset;
2775 u16 ets_cfg;
2776 u16 ets_sensor;
2777 u8 low_thresh_delta;
2778 u8 num_sensors;
2779 u8 sensor_index;
2780 u8 sensor_location;
2781 u8 therm_limit;
2782 u8 i;
2783 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2784
2785 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2786 return E1000_NOT_IMPLEMENTED;
2787
2788 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2789
2790 data->sensor[0].location = 0x1;
2791 data->sensor[0].caution_thresh =
2792 (rd32(E1000_THHIGHTC) & 0xFF);
2793 data->sensor[0].max_op_thresh =
2794 (rd32(E1000_THLOWTC) & 0xFF);
2795
2796 /* Return the internal sensor only if ETS is unsupported */
2797 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2798 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2799 return status;
2800
2801 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2802 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2803 != NVM_ETS_TYPE_EMC)
2804 return E1000_NOT_IMPLEMENTED;
2805
2806 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2807 NVM_ETS_LTHRES_DELTA_SHIFT);
2808 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2809
2810 for (i = 1; i <= num_sensors; i++) {
2811 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2812 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2813 NVM_ETS_DATA_INDEX_SHIFT);
2814 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2815 NVM_ETS_DATA_LOC_SHIFT);
2816 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2817
2818 hw->phy.ops.write_i2c_byte(hw,
2819 e1000_emc_therm_limit[sensor_index],
2820 E1000_I2C_THERMAL_SENSOR_ADDR,
2821 therm_limit);
2822
2823 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2824 data->sensor[i].location = sensor_location;
2825 data->sensor[i].caution_thresh = therm_limit;
2826 data->sensor[i].max_op_thresh = therm_limit -
2827 low_thresh_delta;
2828 }
2829 }
2830 return status;
2831 }
2832
2833 #endif
2834 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2835 .init_hw = igb_init_hw_82575,
2836 .check_for_link = igb_check_for_link_82575,
2837 .rar_set = igb_rar_set,
2838 .read_mac_addr = igb_read_mac_addr_82575,
2839 .get_speed_and_duplex = igb_get_link_up_info_82575,
2840 #ifdef CONFIG_IGB_HWMON
2841 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2842 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2843 #endif
2844 };
2845
2846 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2847 .acquire = igb_acquire_phy_82575,
2848 .get_cfg_done = igb_get_cfg_done_82575,
2849 .release = igb_release_phy_82575,
2850 .write_i2c_byte = igb_write_i2c_byte,
2851 .read_i2c_byte = igb_read_i2c_byte,
2852 };
2853
2854 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2855 .acquire = igb_acquire_nvm_82575,
2856 .read = igb_read_nvm_eerd,
2857 .release = igb_release_nvm_82575,
2858 .write = igb_write_nvm_spi,
2859 };
2860
2861 const struct e1000_info e1000_82575_info = {
2862 .get_invariants = igb_get_invariants_82575,
2863 .mac_ops = &e1000_mac_ops_82575,
2864 .phy_ops = &e1000_phy_ops_82575,
2865 .nvm_ops = &e1000_nvm_ops_82575,
2866 };
2867
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