2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/debugfs.h>
39 #include <linux/device.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 #define read_ssi(addr) in_be32(addr)
59 #define write_ssi(val, addr) out_be32(addr, val)
60 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
62 #define read_ssi(addr) readl(addr)
63 #define write_ssi(val, addr) writel(val, addr)
65 * FIXME: Proper locking should be added at write_ssi_mask caller level
66 * to ensure this register read/modify/write sequence is race free.
68 static inline void write_ssi_mask(u32 __iomem
*addr
, u32 clear
, u32 set
)
70 u32 val
= readl(addr
);
71 val
= (val
& ~clear
) | set
;
77 * FSLSSI_I2S_RATES: sample rates supported by the I2S
79 * This driver currently only supports the SSI running in I2S slave mode,
80 * which means the codec determines the sample rate. Therefore, we tell
81 * ALSA that we support all rates and let the codec driver decide what rates
82 * are really supported.
84 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
85 SNDRV_PCM_RATE_CONTINUOUS)
88 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
90 * This driver currently only supports the SSI running in I2S slave mode.
92 * The SSI has a limitation in that the samples must be in the same byte
93 * order as the host CPU. This is because when multiple bytes are written
94 * to the STX register, the bytes and bits must be written in the same
95 * order. The STX is a shift register, so all the bits need to be aligned
96 * (bit-endianness must match byte-endianness). Processors typically write
97 * the bits within a byte in the same order that the bytes of a word are
98 * written in. So if the host CPU is big-endian, then only big-endian
99 * samples will be written to STX properly.
102 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
103 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
104 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
106 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
107 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
108 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
111 /* SIER bitflag of interrupts to enable */
112 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
113 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
114 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
115 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
116 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
118 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
119 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
120 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
121 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
122 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
123 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
124 #define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)
135 * fsl_ssi_private: per-SSI private data
137 * @ssi: pointer to the SSI's registers
138 * @ssi_phys: physical address of the SSI registers
139 * @irq: IRQ of this SSI
140 * @playback: the number of playback streams opened
141 * @capture: the number of capture streams opened
142 * @cpu_dai: the CPU DAI for this device
143 * @dev_attr: the sysfs device attribute structure
144 * @stats: SSI statistics
145 * @name: name for this device
147 struct fsl_ssi_private
{
148 struct ccsr_ssi __iomem
*ssi
;
151 unsigned int fifo_depth
;
152 struct snd_soc_dai_driver cpu_dai_drv
;
153 struct platform_device
*pdev
;
155 enum fsl_ssi_type hw_type
;
164 spinlock_t baudclk_lock
;
167 struct snd_dmaengine_dai_dma_data dma_params_tx
;
168 struct snd_dmaengine_dai_dma_data dma_params_rx
;
169 struct imx_dma_data filter_data_tx
;
170 struct imx_dma_data filter_data_rx
;
171 struct imx_pcm_fiq_params fiq_params
;
196 struct dentry
*dbg_dir
;
197 struct dentry
*dbg_stats
;
202 static const struct of_device_id fsl_ssi_ids
[] = {
203 { .compatible
= "fsl,mpc8610-ssi", .data
= (void *) FSL_SSI_MCP8610
},
204 { .compatible
= "fsl,imx51-ssi", .data
= (void *) FSL_SSI_MX51
},
205 { .compatible
= "fsl,imx35-ssi", .data
= (void *) FSL_SSI_MX35
},
206 { .compatible
= "fsl,imx21-ssi", .data
= (void *) FSL_SSI_MX21
},
209 MODULE_DEVICE_TABLE(of
, fsl_ssi_ids
);
212 * fsl_ssi_isr: SSI interrupt handler
214 * Although it's possible to use the interrupt handler to send and receive
215 * data to/from the SSI, we use the DMA instead. Programming is more
216 * complicated, but the performance is much better.
218 * This interrupt handler is used only to gather statistics.
220 * @irq: IRQ of the SSI device
221 * @dev_id: pointer to the ssi_private structure for this SSI device
223 static irqreturn_t
fsl_ssi_isr(int irq
, void *dev_id
)
225 struct fsl_ssi_private
*ssi_private
= dev_id
;
226 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
227 irqreturn_t ret
= IRQ_NONE
;
230 __be32 sisr_write_mask
= 0;
232 switch (ssi_private
->hw_type
) {
237 case FSL_SSI_MCP8610
:
239 sisr_write_mask
= CCSR_SSI_SISR_RFRC
| CCSR_SSI_SISR_TFRC
|
240 CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
241 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
;
245 sisr_write_mask
= CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
246 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
;
250 /* We got an interrupt, so read the status register to see what we
251 were interrupted for. We mask it with the Interrupt Enable register
252 so that we only check for events that we're interested in.
254 sisr
= read_ssi(&ssi
->sisr
) & FSLSSI_SISR_MASK
;
256 if (sisr
& CCSR_SSI_SISR_RFRC
) {
257 ssi_private
->stats
.rfrc
++;
261 if (sisr
& CCSR_SSI_SISR_TFRC
) {
262 ssi_private
->stats
.tfrc
++;
266 if (sisr
& CCSR_SSI_SISR_CMDAU
) {
267 ssi_private
->stats
.cmdau
++;
271 if (sisr
& CCSR_SSI_SISR_CMDDU
) {
272 ssi_private
->stats
.cmddu
++;
276 if (sisr
& CCSR_SSI_SISR_RXT
) {
277 ssi_private
->stats
.rxt
++;
281 if (sisr
& CCSR_SSI_SISR_RDR1
) {
282 ssi_private
->stats
.rdr1
++;
286 if (sisr
& CCSR_SSI_SISR_RDR0
) {
287 ssi_private
->stats
.rdr0
++;
291 if (sisr
& CCSR_SSI_SISR_TDE1
) {
292 ssi_private
->stats
.tde1
++;
296 if (sisr
& CCSR_SSI_SISR_TDE0
) {
297 ssi_private
->stats
.tde0
++;
301 if (sisr
& CCSR_SSI_SISR_ROE1
) {
302 ssi_private
->stats
.roe1
++;
306 if (sisr
& CCSR_SSI_SISR_ROE0
) {
307 ssi_private
->stats
.roe0
++;
311 if (sisr
& CCSR_SSI_SISR_TUE1
) {
312 ssi_private
->stats
.tue1
++;
316 if (sisr
& CCSR_SSI_SISR_TUE0
) {
317 ssi_private
->stats
.tue0
++;
321 if (sisr
& CCSR_SSI_SISR_TFS
) {
322 ssi_private
->stats
.tfs
++;
326 if (sisr
& CCSR_SSI_SISR_RFS
) {
327 ssi_private
->stats
.rfs
++;
331 if (sisr
& CCSR_SSI_SISR_TLS
) {
332 ssi_private
->stats
.tls
++;
336 if (sisr
& CCSR_SSI_SISR_RLS
) {
337 ssi_private
->stats
.rls
++;
341 if (sisr
& CCSR_SSI_SISR_RFF1
) {
342 ssi_private
->stats
.rff1
++;
346 if (sisr
& CCSR_SSI_SISR_RFF0
) {
347 ssi_private
->stats
.rff0
++;
351 if (sisr
& CCSR_SSI_SISR_TFE1
) {
352 ssi_private
->stats
.tfe1
++;
356 if (sisr
& CCSR_SSI_SISR_TFE0
) {
357 ssi_private
->stats
.tfe0
++;
361 sisr2
= sisr
& sisr_write_mask
;
362 /* Clear the bits that we set */
364 write_ssi(sisr2
, &ssi
->sisr
);
369 #if IS_ENABLED(CONFIG_DEBUG_FS)
370 /* Show the statistics of a flag only if its interrupt is enabled. The
371 * compiler will optimze this code to a no-op if the interrupt is not
374 #define SIER_SHOW(flag, name) \
376 if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
377 seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
382 * fsl_sysfs_ssi_show: display SSI statistics
384 * Display the statistics for the current SSI device. To avoid confusion,
385 * we only show those counts that are enabled.
387 static ssize_t
fsl_ssi_stats_show(struct seq_file
*s
, void *unused
)
389 struct fsl_ssi_private
*ssi_private
= s
->private;
391 SIER_SHOW(RFRC_EN
, rfrc
);
392 SIER_SHOW(TFRC_EN
, tfrc
);
393 SIER_SHOW(CMDAU_EN
, cmdau
);
394 SIER_SHOW(CMDDU_EN
, cmddu
);
395 SIER_SHOW(RXT_EN
, rxt
);
396 SIER_SHOW(RDR1_EN
, rdr1
);
397 SIER_SHOW(RDR0_EN
, rdr0
);
398 SIER_SHOW(TDE1_EN
, tde1
);
399 SIER_SHOW(TDE0_EN
, tde0
);
400 SIER_SHOW(ROE1_EN
, roe1
);
401 SIER_SHOW(ROE0_EN
, roe0
);
402 SIER_SHOW(TUE1_EN
, tue1
);
403 SIER_SHOW(TUE0_EN
, tue0
);
404 SIER_SHOW(TFS_EN
, tfs
);
405 SIER_SHOW(RFS_EN
, rfs
);
406 SIER_SHOW(TLS_EN
, tls
);
407 SIER_SHOW(RLS_EN
, rls
);
408 SIER_SHOW(RFF1_EN
, rff1
);
409 SIER_SHOW(RFF0_EN
, rff0
);
410 SIER_SHOW(TFE1_EN
, tfe1
);
411 SIER_SHOW(TFE0_EN
, tfe0
);
416 static int fsl_ssi_stats_open(struct inode
*inode
, struct file
*file
)
418 return single_open(file
, fsl_ssi_stats_show
, inode
->i_private
);
421 static const struct file_operations fsl_ssi_stats_ops
= {
422 .open
= fsl_ssi_stats_open
,
425 .release
= single_release
,
428 static int fsl_ssi_debugfs_create(struct fsl_ssi_private
*ssi_private
,
431 ssi_private
->dbg_dir
= debugfs_create_dir(dev_name(dev
), NULL
);
432 if (!ssi_private
->dbg_dir
)
435 ssi_private
->dbg_stats
= debugfs_create_file("stats", S_IRUGO
,
436 ssi_private
->dbg_dir
, ssi_private
, &fsl_ssi_stats_ops
);
437 if (!ssi_private
->dbg_stats
) {
438 debugfs_remove(ssi_private
->dbg_dir
);
445 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private
*ssi_private
)
447 debugfs_remove(ssi_private
->dbg_stats
);
448 debugfs_remove(ssi_private
->dbg_dir
);
453 static int fsl_ssi_debugfs_create(struct fsl_ssi_private
*ssi_private
,
459 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private
*ssi_private
)
463 #endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
465 static void fsl_ssi_setup_ac97(struct fsl_ssi_private
*ssi_private
)
467 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
470 * Setup the clock control register
472 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
474 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
478 * Enable AC97 mode and startup the SSI
480 write_ssi(CCSR_SSI_SACNT_AC97EN
| CCSR_SSI_SACNT_FV
,
482 write_ssi(0xff, &ssi
->saccdis
);
483 write_ssi(0x300, &ssi
->saccen
);
486 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
487 * codec before a stream is started.
489 write_ssi_mask(&ssi
->scr
, 0, CCSR_SSI_SCR_SSIEN
|
490 CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
);
492 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi
->sor
);
495 static int fsl_ssi_setup(struct fsl_ssi_private
*ssi_private
)
497 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
499 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
;
501 if (ssi_private
->imx_ac97
)
502 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_NORMAL
| CCSR_SSI_SCR_NET
;
504 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
507 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
508 * to be disabled before updating the registers we set here.
510 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, 0);
513 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
514 * enable the transmit and receive FIFO.
516 * FIXME: Little-endian samples require a different shift dir
518 write_ssi_mask(&ssi
->scr
,
519 CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_SYN
,
520 CCSR_SSI_SCR_TFR_CLK_DIS
|
521 ssi_private
->i2s_mode
|
522 (synchronous
? CCSR_SSI_SCR_SYN
: 0));
524 write_ssi(CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFEN0
|
525 CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TEFS
|
526 CCSR_SSI_STCR_TSCKP
, &ssi
->stcr
);
528 write_ssi(CCSR_SSI_SRCR_RXBIT0
| CCSR_SSI_SRCR_RFEN0
|
529 CCSR_SSI_SRCR_RFSI
| CCSR_SSI_SRCR_REFS
|
530 CCSR_SSI_SRCR_RSCKP
, &ssi
->srcr
);
532 * The DC and PM bits are only used if the SSI is the clock master.
536 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
537 * use FIFO 1. We program the transmit water to signal a DMA transfer
538 * if there are only two (or fewer) elements left in the FIFO. Two
539 * elements equals one frame (left channel, right channel). This value,
540 * however, depends on the depth of the transmit buffer.
542 * We set the watermark on the same level as the DMA burstsize. For
543 * fiq it is probably better to use the biggest possible watermark
546 if (ssi_private
->use_dma
)
547 wm
= ssi_private
->fifo_depth
- 2;
549 wm
= ssi_private
->fifo_depth
;
551 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm
) | CCSR_SSI_SFCSR_RFWM0(wm
) |
552 CCSR_SSI_SFCSR_TFWM1(wm
) | CCSR_SSI_SFCSR_RFWM1(wm
),
556 * For ac97 interrupts are enabled with the startup of the substream
557 * because it is also running without an active substream. Normally SSI
558 * is only enabled when there is a substream.
560 if (ssi_private
->imx_ac97
)
561 fsl_ssi_setup_ac97(ssi_private
);
568 * fsl_ssi_startup: create a new substream
570 * This is the first function called when a stream is opened.
572 * If this is the first stream open, then grab the IRQ and program most of
575 static int fsl_ssi_startup(struct snd_pcm_substream
*substream
,
576 struct snd_soc_dai
*dai
)
578 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
579 struct fsl_ssi_private
*ssi_private
=
580 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
583 /* First, we only do fsl_ssi_setup() when SSI is going to be active.
584 * Second, fsl_ssi_setup was already called by ac97_init earlier if
585 * the driver is in ac97 mode.
587 if (!dai
->active
&& !ssi_private
->imx_ac97
) {
588 fsl_ssi_setup(ssi_private
);
589 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
590 ssi_private
->baudclk_locked
= false;
591 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
598 * fsl_ssi_hw_params - program the sample size
600 * Most of the SSI registers have been programmed in the startup function,
601 * but the word length must be programmed here. Unfortunately, programming
602 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
603 * cause a problem with supporting simultaneous playback and capture. If
604 * the SSI is already playing a stream, then that stream may be temporarily
605 * stopped when you start capture.
607 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
610 static int fsl_ssi_hw_params(struct snd_pcm_substream
*substream
,
611 struct snd_pcm_hw_params
*hw_params
, struct snd_soc_dai
*cpu_dai
)
613 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
614 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
615 unsigned int channels
= params_channels(hw_params
);
616 unsigned int sample_size
=
617 snd_pcm_format_width(params_format(hw_params
));
618 u32 wl
= CCSR_SSI_SxCCR_WL(sample_size
);
619 int enabled
= read_ssi(&ssi
->scr
) & CCSR_SSI_SCR_SSIEN
;
622 * If we're in synchronous mode, and the SSI is already enabled,
623 * then STCCR is already set properly.
625 if (enabled
&& ssi_private
->cpu_dai_drv
.symmetric_rates
)
629 * FIXME: The documentation says that SxCCR[WL] should not be
630 * modified while the SSI is enabled. The only time this can
631 * happen is if we're trying to do simultaneous playback and
632 * capture in asynchronous mode. Unfortunately, I have been enable
633 * to get that to work at all on the P1022DS. Therefore, we don't
634 * bother to disable/enable the SSI when setting SxCCR[WL], because
635 * the SSI will stop anyway. Maybe one day, this will get fixed.
638 /* In synchronous mode, the SSI uses STCCR for capture */
639 if ((substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) ||
640 ssi_private
->cpu_dai_drv
.symmetric_rates
)
641 write_ssi_mask(&ssi
->stccr
, CCSR_SSI_SxCCR_WL_MASK
, wl
);
643 write_ssi_mask(&ssi
->srccr
, CCSR_SSI_SxCCR_WL_MASK
, wl
);
645 if (!ssi_private
->imx_ac97
)
646 write_ssi_mask(&ssi
->scr
,
647 CCSR_SSI_SCR_NET
| CCSR_SSI_SCR_I2S_MODE_MASK
,
648 channels
== 1 ? 0 : ssi_private
->i2s_mode
);
654 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
656 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai
*cpu_dai
, unsigned int fmt
)
658 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
659 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
660 u32 strcr
= 0, stcr
, srcr
, scr
, mask
;
662 scr
= read_ssi(&ssi
->scr
) & ~(CCSR_SSI_SCR_SYN
| CCSR_SSI_SCR_I2S_MODE_MASK
);
663 scr
|= CCSR_SSI_SCR_NET
;
665 mask
= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
|
666 CCSR_SSI_STCR_TSCKP
| CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TFSL
|
668 stcr
= read_ssi(&ssi
->stcr
) & ~mask
;
669 srcr
= read_ssi(&ssi
->srcr
) & ~mask
;
671 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
672 case SND_SOC_DAIFMT_I2S
:
673 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
674 case SND_SOC_DAIFMT_CBS_CFS
:
675 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_MASTER
;
677 case SND_SOC_DAIFMT_CBM_CFM
:
678 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
683 scr
|= ssi_private
->i2s_mode
;
685 /* Data on rising edge of bclk, frame low, 1clk before data */
686 strcr
|= CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TSCKP
|
687 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
689 case SND_SOC_DAIFMT_LEFT_J
:
690 /* Data on rising edge of bclk, frame high */
691 strcr
|= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TSCKP
;
693 case SND_SOC_DAIFMT_DSP_A
:
694 /* Data on rising edge of bclk, frame high, 1clk before data */
695 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
696 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
698 case SND_SOC_DAIFMT_DSP_B
:
699 /* Data on rising edge of bclk, frame high */
700 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
701 CCSR_SSI_STCR_TXBIT0
;
707 /* DAI clock inversion */
708 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
709 case SND_SOC_DAIFMT_NB_NF
:
710 /* Nothing to do for both normal cases */
712 case SND_SOC_DAIFMT_IB_NF
:
713 /* Invert bit clock */
714 strcr
^= CCSR_SSI_STCR_TSCKP
;
716 case SND_SOC_DAIFMT_NB_IF
:
717 /* Invert frame clock */
718 strcr
^= CCSR_SSI_STCR_TFSI
;
720 case SND_SOC_DAIFMT_IB_IF
:
721 /* Invert both clocks */
722 strcr
^= CCSR_SSI_STCR_TSCKP
;
723 strcr
^= CCSR_SSI_STCR_TFSI
;
729 /* DAI clock master masks */
730 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
731 case SND_SOC_DAIFMT_CBS_CFS
:
732 strcr
|= CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
;
733 scr
|= CCSR_SSI_SCR_SYS_CLK_EN
;
735 case SND_SOC_DAIFMT_CBM_CFM
:
736 scr
&= ~CCSR_SSI_SCR_SYS_CLK_EN
;
745 if (ssi_private
->cpu_dai_drv
.symmetric_rates
) {
746 /* Need to clear RXDIR when using SYNC mode */
747 srcr
&= ~CCSR_SSI_SRCR_RXDIR
;
748 scr
|= CCSR_SSI_SCR_SYN
;
751 write_ssi(stcr
, &ssi
->stcr
);
752 write_ssi(srcr
, &ssi
->srcr
);
753 write_ssi(scr
, &ssi
->scr
);
759 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
761 * Note: This function can be only called when using SSI as DAI master
763 * Quick instruction for parameters:
764 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
765 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
767 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
768 int clk_id
, unsigned int freq
, int dir
)
770 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
771 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
772 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
, ret
;
773 u32 pm
= 999, div2
, psr
, stccr
, mask
, afreq
, factor
, i
;
774 unsigned long flags
, clkrate
, baudrate
, tmprate
;
775 u64 sub
, savesub
= 100000;
777 /* Don't apply it to any non-baudclk circumstance */
778 if (IS_ERR(ssi_private
->baudclk
))
781 /* It should be already enough to divide clock by setting pm alone */
785 factor
= (div2
+ 1) * (7 * psr
+ 1) * 2;
787 for (i
= 0; i
< 255; i
++) {
788 /* The bclk rate must be smaller than 1/5 sysclk rate */
789 if (factor
* (i
+ 1) < 5)
792 tmprate
= freq
* factor
* (i
+ 2);
793 clkrate
= clk_round_rate(ssi_private
->baudclk
, tmprate
);
795 do_div(clkrate
, factor
);
796 afreq
= (u32
)clkrate
/ (i
+ 1);
800 else if (freq
/ afreq
== 1)
802 else if (afreq
/ freq
== 1)
807 /* Calculate the fraction */
822 /* No proper pm found if it is still remaining the initial value */
824 dev_err(cpu_dai
->dev
, "failed to handle the required sysclk\n");
828 stccr
= CCSR_SSI_SxCCR_PM(pm
+ 1) | (div2
? CCSR_SSI_SxCCR_DIV2
: 0) |
829 (psr
? CCSR_SSI_SxCCR_PSR
: 0);
830 mask
= CCSR_SSI_SxCCR_PM_MASK
| CCSR_SSI_SxCCR_DIV2
| CCSR_SSI_SxCCR_PSR
;
832 if (dir
== SND_SOC_CLOCK_OUT
|| synchronous
)
833 write_ssi_mask(&ssi
->stccr
, mask
, stccr
);
835 write_ssi_mask(&ssi
->srccr
, mask
, stccr
);
837 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
838 if (!ssi_private
->baudclk_locked
) {
839 ret
= clk_set_rate(ssi_private
->baudclk
, baudrate
);
841 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
842 dev_err(cpu_dai
->dev
, "failed to set baudclk rate\n");
845 ssi_private
->baudclk_locked
= true;
847 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
853 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
855 * Note: This function can be only called when using SSI as DAI master
857 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai
*cpu_dai
, u32 tx_mask
,
858 u32 rx_mask
, int slots
, int slot_width
)
860 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
861 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
864 /* The slot number should be >= 2 if using Network mode or I2S mode */
865 val
= read_ssi(&ssi
->scr
) & (CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_NET
);
866 if (val
&& slots
< 2) {
867 dev_err(cpu_dai
->dev
, "slot number should be >= 2 in I2S or NET\n");
871 write_ssi_mask(&ssi
->stccr
, CCSR_SSI_SxCCR_DC_MASK
,
872 CCSR_SSI_SxCCR_DC(slots
));
873 write_ssi_mask(&ssi
->srccr
, CCSR_SSI_SxCCR_DC_MASK
,
874 CCSR_SSI_SxCCR_DC(slots
));
876 /* The register SxMSKs needs SSI to provide essential clock due to
877 * hardware design. So we here temporarily enable SSI to set them.
879 val
= read_ssi(&ssi
->scr
) & CCSR_SSI_SCR_SSIEN
;
880 write_ssi_mask(&ssi
->scr
, 0, CCSR_SSI_SCR_SSIEN
);
882 write_ssi(tx_mask
, &ssi
->stmsk
);
883 write_ssi(rx_mask
, &ssi
->srmsk
);
885 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, val
);
891 * fsl_ssi_trigger: start and stop the DMA transfer.
893 * This function is called by ALSA to start, stop, pause, and resume the DMA
896 * The DMA channel is in external master start and pause mode, which
897 * means the SSI completely controls the flow of data.
899 static int fsl_ssi_trigger(struct snd_pcm_substream
*substream
, int cmd
,
900 struct snd_soc_dai
*dai
)
902 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
903 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
904 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
905 unsigned int sier_bits
;
909 * Enable only the interrupts and DMA requests
910 * that are needed for the channel. As the fiq
911 * is polling for this bits, we have to ensure
912 * that this are aligned with the preallocated
916 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
917 if (ssi_private
->use_dma
)
918 sier_bits
= SIER_FLAGS
;
920 sier_bits
= CCSR_SSI_SIER_TIE
| CCSR_SSI_SIER_TFE0_EN
;
922 if (ssi_private
->use_dma
)
923 sier_bits
= SIER_FLAGS
;
925 sier_bits
= CCSR_SSI_SIER_RIE
| CCSR_SSI_SIER_RFF0_EN
;
929 case SNDRV_PCM_TRIGGER_START
:
930 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
931 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
932 write_ssi_mask(&ssi
->scr
, 0,
933 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
);
935 write_ssi_mask(&ssi
->scr
, 0,
936 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_RE
);
939 case SNDRV_PCM_TRIGGER_STOP
:
940 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
941 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
942 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_TE
, 0);
944 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_RE
, 0);
946 if (!ssi_private
->imx_ac97
&& (read_ssi(&ssi
->scr
) &
947 (CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
)) == 0) {
948 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, 0);
949 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
950 ssi_private
->baudclk_locked
= false;
951 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
959 write_ssi(sier_bits
, &ssi
->sier
);
964 static int fsl_ssi_dai_probe(struct snd_soc_dai
*dai
)
966 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(dai
);
968 if (ssi_private
->ssi_on_imx
&& ssi_private
->use_dma
) {
969 dai
->playback_dma_data
= &ssi_private
->dma_params_tx
;
970 dai
->capture_dma_data
= &ssi_private
->dma_params_rx
;
976 static const struct snd_soc_dai_ops fsl_ssi_dai_ops
= {
977 .startup
= fsl_ssi_startup
,
978 .hw_params
= fsl_ssi_hw_params
,
979 .set_fmt
= fsl_ssi_set_dai_fmt
,
980 .set_sysclk
= fsl_ssi_set_dai_sysclk
,
981 .set_tdm_slot
= fsl_ssi_set_dai_tdm_slot
,
982 .trigger
= fsl_ssi_trigger
,
985 /* Template for the CPU dai driver structure */
986 static struct snd_soc_dai_driver fsl_ssi_dai_template
= {
987 .probe
= fsl_ssi_dai_probe
,
991 .rates
= FSLSSI_I2S_RATES
,
992 .formats
= FSLSSI_I2S_FORMATS
,
997 .rates
= FSLSSI_I2S_RATES
,
998 .formats
= FSLSSI_I2S_FORMATS
,
1000 .ops
= &fsl_ssi_dai_ops
,
1003 static const struct snd_soc_component_driver fsl_ssi_component
= {
1008 * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
1010 * This function is called by ALSA to start, stop, pause, and resume the
1013 static int fsl_ssi_ac97_trigger(struct snd_pcm_substream
*substream
, int cmd
,
1014 struct snd_soc_dai
*dai
)
1016 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1017 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(
1019 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
1022 case SNDRV_PCM_TRIGGER_START
:
1023 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1024 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1025 write_ssi_mask(&ssi
->sier
, 0, CCSR_SSI_SIER_TIE
|
1026 CCSR_SSI_SIER_TFE0_EN
);
1028 write_ssi_mask(&ssi
->sier
, 0, CCSR_SSI_SIER_RIE
|
1029 CCSR_SSI_SIER_RFF0_EN
);
1032 case SNDRV_PCM_TRIGGER_STOP
:
1033 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1034 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1035 write_ssi_mask(&ssi
->sier
, CCSR_SSI_SIER_TIE
|
1036 CCSR_SSI_SIER_TFE0_EN
, 0);
1038 write_ssi_mask(&ssi
->sier
, CCSR_SSI_SIER_RIE
|
1039 CCSR_SSI_SIER_RFF0_EN
, 0);
1046 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1047 write_ssi(CCSR_SSI_SOR_TX_CLR
, &ssi
->sor
);
1049 write_ssi(CCSR_SSI_SOR_RX_CLR
, &ssi
->sor
);
1054 static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops
= {
1055 .startup
= fsl_ssi_startup
,
1056 .trigger
= fsl_ssi_ac97_trigger
,
1059 static struct snd_soc_dai_driver fsl_ssi_ac97_dai
= {
1062 .stream_name
= "AC97 Playback",
1065 .rates
= SNDRV_PCM_RATE_8000_48000
,
1066 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1069 .stream_name
= "AC97 Capture",
1072 .rates
= SNDRV_PCM_RATE_48000
,
1073 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1075 .ops
= &fsl_ssi_ac97_dai_ops
,
1079 static struct fsl_ssi_private
*fsl_ac97_data
;
1081 static void fsl_ssi_ac97_init(void)
1083 fsl_ssi_setup(fsl_ac97_data
);
1086 static void fsl_ssi_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
1089 struct ccsr_ssi
*ssi
= fsl_ac97_data
->ssi
;
1098 write_ssi(lreg
, &ssi
->sacadd
);
1101 write_ssi(lval
, &ssi
->sacdat
);
1103 write_ssi_mask(&ssi
->sacnt
, CCSR_SSI_SACNT_RDWR_MASK
,
1108 static unsigned short fsl_ssi_ac97_read(struct snd_ac97
*ac97
,
1111 struct ccsr_ssi
*ssi
= fsl_ac97_data
->ssi
;
1113 unsigned short val
= -1;
1116 lreg
= (reg
& 0x7f) << 12;
1117 write_ssi(lreg
, &ssi
->sacadd
);
1118 write_ssi_mask(&ssi
->sacnt
, CCSR_SSI_SACNT_RDWR_MASK
,
1123 val
= (read_ssi(&ssi
->sacdat
) >> 4) & 0xffff;
1128 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops
= {
1129 .read
= fsl_ssi_ac97_read
,
1130 .write
= fsl_ssi_ac97_write
,
1134 * Make every character in a string lower-case
1136 static void make_lowercase(char *s
)
1142 if ((c
>= 'A') && (c
<= 'Z'))
1143 *p
= c
+ ('a' - 'A');
1148 static int fsl_ssi_probe(struct platform_device
*pdev
)
1150 struct fsl_ssi_private
*ssi_private
;
1152 struct device_attribute
*dev_attr
= NULL
;
1153 struct device_node
*np
= pdev
->dev
.of_node
;
1154 const struct of_device_id
*of_id
;
1155 enum fsl_ssi_type hw_type
;
1156 const char *p
, *sprop
;
1157 const uint32_t *iprop
;
1158 struct resource res
;
1163 /* SSIs that are not connected on the board should have a
1164 * status = "disabled"
1165 * property in their device tree nodes.
1167 if (!of_device_is_available(np
))
1170 of_id
= of_match_device(fsl_ssi_ids
, &pdev
->dev
);
1173 hw_type
= (enum fsl_ssi_type
) of_id
->data
;
1175 /* We only support the SSI in "I2S Slave" mode */
1176 sprop
= of_get_property(np
, "fsl,mode", NULL
);
1178 dev_err(&pdev
->dev
, "fsl,mode property is necessary\n");
1181 if (!strcmp(sprop
, "ac97-slave")) {
1183 } else if (strcmp(sprop
, "i2s-slave")) {
1184 dev_notice(&pdev
->dev
, "mode %s is unsupported\n", sprop
);
1188 /* The DAI name is the last part of the full name of the node. */
1189 p
= strrchr(np
->full_name
, '/') + 1;
1190 ssi_private
= devm_kzalloc(&pdev
->dev
, sizeof(*ssi_private
) + strlen(p
),
1193 dev_err(&pdev
->dev
, "could not allocate DAI object\n");
1197 strcpy(ssi_private
->name
, p
);
1199 ssi_private
->use_dma
= !of_property_read_bool(np
,
1200 "fsl,fiq-stream-filter");
1201 ssi_private
->hw_type
= hw_type
;
1204 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_ac97_dai
,
1205 sizeof(fsl_ssi_ac97_dai
));
1207 fsl_ac97_data
= ssi_private
;
1208 ssi_private
->imx_ac97
= true;
1210 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops
, pdev
);
1212 /* Initialize this copy of the CPU DAI driver structure */
1213 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_dai_template
,
1214 sizeof(fsl_ssi_dai_template
));
1216 ssi_private
->cpu_dai_drv
.name
= ssi_private
->name
;
1218 /* Get the addresses and IRQ */
1219 ret
= of_address_to_resource(np
, 0, &res
);
1221 dev_err(&pdev
->dev
, "could not determine device resources\n");
1224 ssi_private
->ssi
= of_iomap(np
, 0);
1225 if (!ssi_private
->ssi
) {
1226 dev_err(&pdev
->dev
, "could not map device resources\n");
1229 ssi_private
->ssi_phys
= res
.start
;
1231 ssi_private
->irq
= irq_of_parse_and_map(np
, 0);
1232 if (!ssi_private
->irq
) {
1233 dev_err(&pdev
->dev
, "no irq for node %s\n", np
->full_name
);
1237 /* Are the RX and the TX clocks locked? */
1238 if (!of_find_property(np
, "fsl,ssi-asynchronous", NULL
)) {
1239 ssi_private
->cpu_dai_drv
.symmetric_rates
= 1;
1240 ssi_private
->cpu_dai_drv
.symmetric_channels
= 1;
1241 ssi_private
->cpu_dai_drv
.symmetric_samplebits
= 1;
1244 /* Determine the FIFO depth. */
1245 iprop
= of_get_property(np
, "fsl,fifo-depth", NULL
);
1247 ssi_private
->fifo_depth
= be32_to_cpup(iprop
);
1249 /* Older 8610 DTs didn't have the fifo-depth property */
1250 ssi_private
->fifo_depth
= 8;
1252 ssi_private
->baudclk_locked
= false;
1253 spin_lock_init(&ssi_private
->baudclk_lock
);
1256 * imx51 and later SoCs have a slightly different IP that allows the
1257 * SSI configuration while the SSI unit is running.
1259 * More important, it is necessary on those SoCs to configure the
1260 * sperate TX/RX DMA bits just before starting the stream
1261 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
1262 * sends any DMA requests to the SDMA unit, otherwise it is not defined
1263 * how the SDMA unit handles the DMA request.
1265 * SDMA units are present on devices starting at imx35 but the imx35
1266 * reference manual states that the DMA bits should not be changed
1267 * while the SSI unit is running (SSIEN). So we support the necessary
1268 * online configuration of fsl-ssi starting at imx51.
1271 case FSL_SSI_MCP8610
:
1274 ssi_private
->offline_config
= true;
1277 ssi_private
->offline_config
= false;
1281 if (hw_type
== FSL_SSI_MX21
|| hw_type
== FSL_SSI_MX51
||
1282 hw_type
== FSL_SSI_MX35
) {
1284 ssi_private
->ssi_on_imx
= true;
1286 ssi_private
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1287 if (IS_ERR(ssi_private
->clk
)) {
1288 ret
= PTR_ERR(ssi_private
->clk
);
1289 dev_err(&pdev
->dev
, "could not get clock: %d\n", ret
);
1292 ret
= clk_prepare_enable(ssi_private
->clk
);
1294 dev_err(&pdev
->dev
, "clk_prepare_enable failed: %d\n",
1299 /* For those SLAVE implementations, we ingore non-baudclk cases
1300 * and, instead, abandon MASTER mode that needs baud clock.
1302 ssi_private
->baudclk
= devm_clk_get(&pdev
->dev
, "baud");
1303 if (IS_ERR(ssi_private
->baudclk
))
1304 dev_warn(&pdev
->dev
, "could not get baud clock: %ld\n",
1305 PTR_ERR(ssi_private
->baudclk
));
1307 clk_prepare_enable(ssi_private
->baudclk
);
1310 * We have burstsize be "fifo_depth - 2" to match the SSI
1311 * watermark setting in fsl_ssi_startup().
1313 ssi_private
->dma_params_tx
.maxburst
=
1314 ssi_private
->fifo_depth
- 2;
1315 ssi_private
->dma_params_rx
.maxburst
=
1316 ssi_private
->fifo_depth
- 2;
1317 ssi_private
->dma_params_tx
.addr
=
1318 ssi_private
->ssi_phys
+ offsetof(struct ccsr_ssi
, stx0
);
1319 ssi_private
->dma_params_rx
.addr
=
1320 ssi_private
->ssi_phys
+ offsetof(struct ccsr_ssi
, srx0
);
1321 ssi_private
->dma_params_tx
.filter_data
=
1322 &ssi_private
->filter_data_tx
;
1323 ssi_private
->dma_params_rx
.filter_data
=
1324 &ssi_private
->filter_data_rx
;
1325 if (!of_property_read_bool(pdev
->dev
.of_node
, "dmas") &&
1326 ssi_private
->use_dma
) {
1328 * FIXME: This is a temporary solution until all
1329 * necessary dma drivers support the generic dma
1332 ret
= of_property_read_u32_array(pdev
->dev
.of_node
,
1333 "fsl,ssi-dma-events", dma_events
, 2);
1334 if (ret
&& ssi_private
->use_dma
) {
1335 dev_err(&pdev
->dev
, "could not get dma events but fsl-ssi is configured to use DMA\n");
1340 shared
= of_device_is_compatible(of_get_parent(np
),
1343 imx_pcm_dma_params_init_data(&ssi_private
->filter_data_tx
,
1344 dma_events
[0], shared
? IMX_DMATYPE_SSI_SP
: IMX_DMATYPE_SSI
);
1345 imx_pcm_dma_params_init_data(&ssi_private
->filter_data_rx
,
1346 dma_events
[1], shared
? IMX_DMATYPE_SSI_SP
: IMX_DMATYPE_SSI
);
1350 * Enable interrupts only for MCP8610 and MX51. The other MXs have
1351 * different writeable interrupt status registers.
1353 if (ssi_private
->use_dma
) {
1354 /* The 'name' should not have any slashes in it. */
1355 ret
= devm_request_irq(&pdev
->dev
, ssi_private
->irq
,
1356 fsl_ssi_isr
, 0, ssi_private
->name
,
1358 ssi_private
->irq_stats
= true;
1360 dev_err(&pdev
->dev
, "could not claim irq %u\n",
1366 /* Register with ASoC */
1367 dev_set_drvdata(&pdev
->dev
, ssi_private
);
1369 ret
= snd_soc_register_component(&pdev
->dev
, &fsl_ssi_component
,
1370 &ssi_private
->cpu_dai_drv
, 1);
1372 dev_err(&pdev
->dev
, "failed to register DAI: %d\n", ret
);
1376 ret
= fsl_ssi_debugfs_create(ssi_private
, &pdev
->dev
);
1380 if (ssi_private
->ssi_on_imx
) {
1381 if (!ssi_private
->use_dma
) {
1384 * Some boards use an incompatible codec. To get it
1385 * working, we are using imx-fiq-pcm-audio, that
1386 * can handle those codecs. DMA is not possible in this
1390 ssi_private
->fiq_params
.irq
= ssi_private
->irq
;
1391 ssi_private
->fiq_params
.base
= ssi_private
->ssi
;
1392 ssi_private
->fiq_params
.dma_params_rx
=
1393 &ssi_private
->dma_params_rx
;
1394 ssi_private
->fiq_params
.dma_params_tx
=
1395 &ssi_private
->dma_params_tx
;
1397 ret
= imx_pcm_fiq_init(pdev
, &ssi_private
->fiq_params
);
1401 ret
= imx_pcm_dma_init(pdev
);
1408 * If codec-handle property is missing from SSI node, we assume
1409 * that the machine driver uses new binding which does not require
1410 * SSI driver to trigger machine driver's probe.
1412 if (!of_get_property(np
, "codec-handle", NULL
)) {
1413 ssi_private
->new_binding
= true;
1417 /* Trigger the machine driver's probe function. The platform driver
1418 * name of the machine driver is taken from /compatible property of the
1419 * device tree. We also pass the address of the CPU DAI driver
1422 sprop
= of_get_property(of_find_node_by_path("/"), "compatible", NULL
);
1423 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1424 p
= strrchr(sprop
, ',');
1427 snprintf(name
, sizeof(name
), "snd-soc-%s", sprop
);
1428 make_lowercase(name
);
1431 platform_device_register_data(&pdev
->dev
, name
, 0, NULL
, 0);
1432 if (IS_ERR(ssi_private
->pdev
)) {
1433 ret
= PTR_ERR(ssi_private
->pdev
);
1434 dev_err(&pdev
->dev
, "failed to register platform: %d\n", ret
);
1439 if (ssi_private
->imx_ac97
)
1440 fsl_ssi_ac97_init();
1445 if (ssi_private
->ssi_on_imx
&& !ssi_private
->use_dma
)
1446 imx_pcm_fiq_exit(pdev
);
1449 fsl_ssi_debugfs_remove(ssi_private
);
1452 snd_soc_unregister_component(&pdev
->dev
);
1455 device_remove_file(&pdev
->dev
, dev_attr
);
1458 if (ssi_private
->ssi_on_imx
) {
1459 if (!IS_ERR(ssi_private
->baudclk
))
1460 clk_disable_unprepare(ssi_private
->baudclk
);
1461 clk_disable_unprepare(ssi_private
->clk
);
1465 if (ssi_private
->irq_stats
)
1466 irq_dispose_mapping(ssi_private
->irq
);
1471 static int fsl_ssi_remove(struct platform_device
*pdev
)
1473 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(&pdev
->dev
);
1475 fsl_ssi_debugfs_remove(ssi_private
);
1477 if (!ssi_private
->new_binding
)
1478 platform_device_unregister(ssi_private
->pdev
);
1479 snd_soc_unregister_component(&pdev
->dev
);
1480 if (ssi_private
->ssi_on_imx
) {
1481 if (!IS_ERR(ssi_private
->baudclk
))
1482 clk_disable_unprepare(ssi_private
->baudclk
);
1483 clk_disable_unprepare(ssi_private
->clk
);
1485 if (ssi_private
->irq_stats
)
1486 irq_dispose_mapping(ssi_private
->irq
);
1491 static struct platform_driver fsl_ssi_driver
= {
1493 .name
= "fsl-ssi-dai",
1494 .owner
= THIS_MODULE
,
1495 .of_match_table
= fsl_ssi_ids
,
1497 .probe
= fsl_ssi_probe
,
1498 .remove
= fsl_ssi_remove
,
1501 module_platform_driver(fsl_ssi_driver
);
1503 MODULE_ALIAS("platform:fsl-ssi-dai");
1504 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1505 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1506 MODULE_LICENSE("GPL v2");