2 * drivers/net/ethernet/mellanox/mlxsw/pci.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the names of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
18 * Alternatively, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") version 2 as published by the Free
20 * Software Foundation.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/export.h>
38 #include <linux/err.h>
39 #include <linux/device.h>
40 #include <linux/pci.h>
41 #include <linux/interrupt.h>
42 #include <linux/wait.h>
43 #include <linux/types.h>
44 #include <linux/skbuff.h>
45 #include <linux/if_vlan.h>
46 #include <linux/log2.h>
47 #include <linux/debugfs.h>
48 #include <linux/seq_file.h>
49 #include <linux/string.h>
56 static const char mlxsw_pci_driver_name
[] = "mlxsw_pci";
58 static const struct pci_device_id mlxsw_pci_id_table
[] = {
59 {PCI_VDEVICE(MELLANOX
, PCI_DEVICE_ID_MELLANOX_SWITCHX2
), 0},
63 static struct dentry
*mlxsw_pci_dbg_root
;
65 static const char *mlxsw_pci_device_kind_get(const struct pci_device_id
*id
)
68 case PCI_DEVICE_ID_MELLANOX_SWITCHX2
:
69 return MLXSW_DEVICE_KIND_SWITCHX2
;
75 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
76 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
77 #define mlxsw_pci_read32(mlxsw_pci, reg) \
78 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
80 enum mlxsw_pci_queue_type
{
81 MLXSW_PCI_QUEUE_TYPE_SDQ
,
82 MLXSW_PCI_QUEUE_TYPE_RDQ
,
83 MLXSW_PCI_QUEUE_TYPE_CQ
,
84 MLXSW_PCI_QUEUE_TYPE_EQ
,
87 static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type
)
90 case MLXSW_PCI_QUEUE_TYPE_SDQ
:
92 case MLXSW_PCI_QUEUE_TYPE_RDQ
:
94 case MLXSW_PCI_QUEUE_TYPE_CQ
:
96 case MLXSW_PCI_QUEUE_TYPE_EQ
:
102 #define MLXSW_PCI_QUEUE_TYPE_COUNT 4
104 static const u16 mlxsw_pci_doorbell_type_offset
[] = {
105 MLXSW_PCI_DOORBELL_SDQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
106 MLXSW_PCI_DOORBELL_RDQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
107 MLXSW_PCI_DOORBELL_CQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
108 MLXSW_PCI_DOORBELL_EQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
111 static const u16 mlxsw_pci_doorbell_arm_type_offset
[] = {
114 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
115 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
118 struct mlxsw_pci_mem_item
{
124 struct mlxsw_pci_queue_elem_info
{
125 char *elem
; /* pointer to actual dma mapped element mem chunk */
136 struct mlxsw_pci_queue
{
137 spinlock_t lock
; /* for queue accesses */
138 struct mlxsw_pci_mem_item mem_item
;
139 struct mlxsw_pci_queue_elem_info
*elem_info
;
140 u16 producer_counter
;
141 u16 consumer_counter
;
142 u16 count
; /* number of elements in queue */
143 u8 num
; /* queue number */
144 u8 elem_size
; /* size of one element */
145 enum mlxsw_pci_queue_type type
;
146 struct tasklet_struct tasklet
; /* queue processing tasklet */
147 struct mlxsw_pci
*pci
;
161 struct mlxsw_pci_queue_type_group
{
162 struct mlxsw_pci_queue
*q
;
163 u8 count
; /* number of queues in group */
167 struct pci_dev
*pdev
;
169 struct mlxsw_pci_queue_type_group queues
[MLXSW_PCI_QUEUE_TYPE_COUNT
];
171 struct msix_entry msix_entry
;
172 struct mlxsw_core
*core
;
175 struct mlxsw_pci_mem_item
*items
;
178 struct mlxsw_pci_mem_item out_mbox
;
179 struct mlxsw_pci_mem_item in_mbox
;
180 struct mutex lock
; /* Lock access to command registers */
182 wait_queue_head_t wait
;
189 struct mlxsw_bus_info bus_info
;
190 struct dentry
*dbg_dir
;
193 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue
*q
)
195 tasklet_schedule(&q
->tasklet
);
198 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue
*q
,
199 size_t elem_size
, int elem_index
)
201 return q
->mem_item
.buf
+ (elem_size
* elem_index
);
204 static struct mlxsw_pci_queue_elem_info
*
205 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue
*q
, int elem_index
)
207 return &q
->elem_info
[elem_index
];
210 static struct mlxsw_pci_queue_elem_info
*
211 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue
*q
)
213 int index
= q
->producer_counter
& (q
->count
- 1);
215 if ((q
->producer_counter
- q
->consumer_counter
) == q
->count
)
217 return mlxsw_pci_queue_elem_info_get(q
, index
);
220 static struct mlxsw_pci_queue_elem_info
*
221 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue
*q
)
223 int index
= q
->consumer_counter
& (q
->count
- 1);
225 return mlxsw_pci_queue_elem_info_get(q
, index
);
228 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue
*q
, int elem_index
)
230 return mlxsw_pci_queue_elem_info_get(q
, elem_index
)->elem
;
233 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue
*q
, bool owner_bit
)
235 return owner_bit
!= !!(q
->consumer_counter
& q
->count
);
238 static char *mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue
*q
,
239 u32 (*get_elem_owner_func
)(char *))
241 struct mlxsw_pci_queue_elem_info
*elem_info
;
245 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
246 elem
= elem_info
->elem
;
247 owner_bit
= get_elem_owner_func(elem
);
248 if (mlxsw_pci_elem_hw_owned(q
, owner_bit
))
250 q
->consumer_counter
++;
251 rmb(); /* make sure we read owned bit before the rest of elem */
255 static struct mlxsw_pci_queue_type_group
*
256 mlxsw_pci_queue_type_group_get(struct mlxsw_pci
*mlxsw_pci
,
257 enum mlxsw_pci_queue_type q_type
)
259 return &mlxsw_pci
->queues
[q_type
];
262 static u8
__mlxsw_pci_queue_count(struct mlxsw_pci
*mlxsw_pci
,
263 enum mlxsw_pci_queue_type q_type
)
265 struct mlxsw_pci_queue_type_group
*queue_group
;
267 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_type
);
268 return queue_group
->count
;
271 static u8
mlxsw_pci_sdq_count(struct mlxsw_pci
*mlxsw_pci
)
273 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_SDQ
);
276 static u8
mlxsw_pci_rdq_count(struct mlxsw_pci
*mlxsw_pci
)
278 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_RDQ
);
281 static u8
mlxsw_pci_cq_count(struct mlxsw_pci
*mlxsw_pci
)
283 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_CQ
);
286 static u8
mlxsw_pci_eq_count(struct mlxsw_pci
*mlxsw_pci
)
288 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_EQ
);
291 static struct mlxsw_pci_queue
*
292 __mlxsw_pci_queue_get(struct mlxsw_pci
*mlxsw_pci
,
293 enum mlxsw_pci_queue_type q_type
, u8 q_num
)
295 return &mlxsw_pci
->queues
[q_type
].q
[q_num
];
298 static struct mlxsw_pci_queue
*mlxsw_pci_sdq_get(struct mlxsw_pci
*mlxsw_pci
,
301 return __mlxsw_pci_queue_get(mlxsw_pci
,
302 MLXSW_PCI_QUEUE_TYPE_SDQ
, q_num
);
305 static struct mlxsw_pci_queue
*mlxsw_pci_rdq_get(struct mlxsw_pci
*mlxsw_pci
,
308 return __mlxsw_pci_queue_get(mlxsw_pci
,
309 MLXSW_PCI_QUEUE_TYPE_RDQ
, q_num
);
312 static struct mlxsw_pci_queue
*mlxsw_pci_cq_get(struct mlxsw_pci
*mlxsw_pci
,
315 return __mlxsw_pci_queue_get(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_CQ
, q_num
);
318 static struct mlxsw_pci_queue
*mlxsw_pci_eq_get(struct mlxsw_pci
*mlxsw_pci
,
321 return __mlxsw_pci_queue_get(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_EQ
, q_num
);
324 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci
*mlxsw_pci
,
325 struct mlxsw_pci_queue
*q
,
328 mlxsw_pci_write32(mlxsw_pci
,
329 DOORBELL(mlxsw_pci
->doorbell_offset
,
330 mlxsw_pci_doorbell_type_offset
[q
->type
],
334 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci
*mlxsw_pci
,
335 struct mlxsw_pci_queue
*q
,
338 mlxsw_pci_write32(mlxsw_pci
,
339 DOORBELL(mlxsw_pci
->doorbell_offset
,
340 mlxsw_pci_doorbell_arm_type_offset
[q
->type
],
344 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci
*mlxsw_pci
,
345 struct mlxsw_pci_queue
*q
)
347 wmb(); /* ensure all writes are done before we ring a bell */
348 __mlxsw_pci_queue_doorbell_set(mlxsw_pci
, q
, q
->producer_counter
);
351 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci
*mlxsw_pci
,
352 struct mlxsw_pci_queue
*q
)
354 wmb(); /* ensure all writes are done before we ring a bell */
355 __mlxsw_pci_queue_doorbell_set(mlxsw_pci
, q
,
356 q
->consumer_counter
+ q
->count
);
360 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci
*mlxsw_pci
,
361 struct mlxsw_pci_queue
*q
)
363 wmb(); /* ensure all writes are done before we ring a bell */
364 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci
, q
, q
->consumer_counter
);
367 static dma_addr_t
__mlxsw_pci_queue_page_get(struct mlxsw_pci_queue
*q
,
370 return q
->mem_item
.mapaddr
+ MLXSW_PCI_PAGE_SIZE
* page_index
;
373 static int mlxsw_pci_sdq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
374 struct mlxsw_pci_queue
*q
)
379 q
->producer_counter
= 0;
380 q
->consumer_counter
= 0;
382 /* Set CQ of same number of this SDQ. */
383 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox
, q
->num
);
384 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox
, 7);
385 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox
, 3); /* 8 pages */
386 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
387 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
389 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox
, i
, mapaddr
);
392 err
= mlxsw_cmd_sw2hw_sdq(mlxsw_pci
->core
, mbox
, q
->num
);
395 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
399 static void mlxsw_pci_sdq_fini(struct mlxsw_pci
*mlxsw_pci
,
400 struct mlxsw_pci_queue
*q
)
402 mlxsw_cmd_hw2sw_sdq(mlxsw_pci
->core
, q
->num
);
405 static int mlxsw_pci_sdq_dbg_read(struct seq_file
*file
, void *data
)
407 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
408 struct mlxsw_pci_queue
*q
;
410 static const char hdr
[] =
411 "NUM PROD_COUNT CONS_COUNT COUNT\n";
413 seq_printf(file
, hdr
);
414 for (i
= 0; i
< mlxsw_pci_sdq_count(mlxsw_pci
); i
++) {
415 q
= mlxsw_pci_sdq_get(mlxsw_pci
, i
);
416 spin_lock_bh(&q
->lock
);
417 seq_printf(file
, "%3d %10d %10d %5d\n",
418 i
, q
->producer_counter
, q
->consumer_counter
,
420 spin_unlock_bh(&q
->lock
);
425 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci
*mlxsw_pci
, char *wqe
,
426 int index
, char *frag_data
, size_t frag_len
,
429 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
432 mapaddr
= pci_map_single(pdev
, frag_data
, frag_len
, direction
);
433 if (unlikely(pci_dma_mapping_error(pdev
, mapaddr
))) {
435 dev_err(&pdev
->dev
, "failed to dma map tx frag\n");
438 mlxsw_pci_wqe_address_set(wqe
, index
, mapaddr
);
439 mlxsw_pci_wqe_byte_count_set(wqe
, index
, frag_len
);
443 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci
*mlxsw_pci
, char *wqe
,
444 int index
, int direction
)
446 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
447 size_t frag_len
= mlxsw_pci_wqe_byte_count_get(wqe
, index
);
448 dma_addr_t mapaddr
= mlxsw_pci_wqe_address_get(wqe
, index
);
452 pci_unmap_single(pdev
, mapaddr
, frag_len
, direction
);
455 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci
*mlxsw_pci
,
456 struct mlxsw_pci_queue_elem_info
*elem_info
)
458 size_t buf_len
= MLXSW_PORT_MAX_MTU
;
459 char *wqe
= elem_info
->elem
;
463 elem_info
->u
.rdq
.skb
= NULL
;
464 skb
= netdev_alloc_skb_ip_align(NULL
, buf_len
);
468 /* Assume that wqe was previously zeroed. */
470 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, 0, skb
->data
,
471 buf_len
, DMA_FROM_DEVICE
);
475 elem_info
->u
.rdq
.skb
= skb
;
479 dev_kfree_skb_any(skb
);
483 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci
*mlxsw_pci
,
484 struct mlxsw_pci_queue_elem_info
*elem_info
)
489 skb
= elem_info
->u
.rdq
.skb
;
490 wqe
= elem_info
->elem
;
492 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, 0, DMA_FROM_DEVICE
);
493 dev_kfree_skb_any(skb
);
496 static int mlxsw_pci_rdq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
497 struct mlxsw_pci_queue
*q
)
499 struct mlxsw_pci_queue_elem_info
*elem_info
;
503 q
->producer_counter
= 0;
504 q
->consumer_counter
= 0;
506 /* Set CQ of same number of this RDQ with base
507 * above MLXSW_PCI_SDQS_MAX as the lower ones are assigned to SDQs.
509 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox
, q
->num
+ MLXSW_PCI_SDQS_COUNT
);
510 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox
, 3); /* 8 pages */
511 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
512 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
514 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox
, i
, mapaddr
);
517 err
= mlxsw_cmd_sw2hw_rdq(mlxsw_pci
->core
, mbox
, q
->num
);
521 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
523 for (i
= 0; i
< q
->count
; i
++) {
524 elem_info
= mlxsw_pci_queue_elem_info_producer_get(q
);
526 err
= mlxsw_pci_rdq_skb_alloc(mlxsw_pci
, elem_info
);
529 /* Everything is set up, ring doorbell to pass elem to HW */
530 q
->producer_counter
++;
531 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
537 for (i
--; i
>= 0; i
--) {
538 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
539 mlxsw_pci_rdq_skb_free(mlxsw_pci
, elem_info
);
541 mlxsw_cmd_hw2sw_rdq(mlxsw_pci
->core
, q
->num
);
546 static void mlxsw_pci_rdq_fini(struct mlxsw_pci
*mlxsw_pci
,
547 struct mlxsw_pci_queue
*q
)
549 struct mlxsw_pci_queue_elem_info
*elem_info
;
552 mlxsw_cmd_hw2sw_rdq(mlxsw_pci
->core
, q
->num
);
553 for (i
= 0; i
< q
->count
; i
++) {
554 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
555 mlxsw_pci_rdq_skb_free(mlxsw_pci
, elem_info
);
559 static int mlxsw_pci_rdq_dbg_read(struct seq_file
*file
, void *data
)
561 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
562 struct mlxsw_pci_queue
*q
;
564 static const char hdr
[] =
565 "NUM PROD_COUNT CONS_COUNT COUNT\n";
567 seq_printf(file
, hdr
);
568 for (i
= 0; i
< mlxsw_pci_rdq_count(mlxsw_pci
); i
++) {
569 q
= mlxsw_pci_rdq_get(mlxsw_pci
, i
);
570 spin_lock_bh(&q
->lock
);
571 seq_printf(file
, "%3d %10d %10d %5d\n",
572 i
, q
->producer_counter
, q
->consumer_counter
,
574 spin_unlock_bh(&q
->lock
);
579 static int mlxsw_pci_cq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
580 struct mlxsw_pci_queue
*q
)
585 q
->consumer_counter
= 0;
587 for (i
= 0; i
< q
->count
; i
++) {
588 char *elem
= mlxsw_pci_queue_elem_get(q
, i
);
590 mlxsw_pci_cqe_owner_set(elem
, 1);
593 mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox
, 0); /* CQE ver 0 */
594 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox
, MLXSW_PCI_EQ_COMP_NUM
);
595 mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox
, 0);
596 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox
, 0);
597 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox
, ilog2(q
->count
));
598 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
599 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
601 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox
, i
, mapaddr
);
603 err
= mlxsw_cmd_sw2hw_cq(mlxsw_pci
->core
, mbox
, q
->num
);
606 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
607 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
611 static void mlxsw_pci_cq_fini(struct mlxsw_pci
*mlxsw_pci
,
612 struct mlxsw_pci_queue
*q
)
614 mlxsw_cmd_hw2sw_cq(mlxsw_pci
->core
, q
->num
);
617 static int mlxsw_pci_cq_dbg_read(struct seq_file
*file
, void *data
)
619 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
621 struct mlxsw_pci_queue
*q
;
623 static const char hdr
[] =
624 "NUM CONS_INDEX SDQ_COUNT RDQ_COUNT COUNT\n";
626 seq_printf(file
, hdr
);
627 for (i
= 0; i
< mlxsw_pci_cq_count(mlxsw_pci
); i
++) {
628 q
= mlxsw_pci_cq_get(mlxsw_pci
, i
);
629 spin_lock_bh(&q
->lock
);
630 seq_printf(file
, "%3d %10d %10d %10d %5d\n",
631 i
, q
->consumer_counter
, q
->u
.cq
.comp_sdq_count
,
632 q
->u
.cq
.comp_rdq_count
, q
->count
);
633 spin_unlock_bh(&q
->lock
);
638 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci
*mlxsw_pci
,
639 struct mlxsw_pci_queue
*q
,
640 u16 consumer_counter_limit
,
643 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
644 struct mlxsw_pci_queue_elem_info
*elem_info
;
650 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
651 skb
= elem_info
->u
.sdq
.skb
;
652 wqe
= elem_info
->elem
;
653 for (i
= 0; i
< MLXSW_PCI_WQE_SG_ENTRIES
; i
++)
654 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, i
, DMA_TO_DEVICE
);
655 dev_kfree_skb_any(skb
);
656 elem_info
->u
.sdq
.skb
= NULL
;
658 if (q
->consumer_counter
++ != consumer_counter_limit
)
659 dev_dbg_ratelimited(&pdev
->dev
, "Consumer counter does not match limit in SDQ\n");
660 spin_unlock(&q
->lock
);
663 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci
*mlxsw_pci
,
664 struct mlxsw_pci_queue
*q
,
665 u16 consumer_counter_limit
,
668 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
669 struct mlxsw_pci_queue_elem_info
*elem_info
;
672 struct mlxsw_rx_info rx_info
;
676 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
677 skb
= elem_info
->u
.sdq
.skb
;
680 wqe
= elem_info
->elem
;
681 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, 0, DMA_FROM_DEVICE
);
683 if (q
->consumer_counter
++ != consumer_counter_limit
)
684 dev_dbg_ratelimited(&pdev
->dev
, "Consumer counter does not match limit in RDQ\n");
686 /* We do not support lag now */
687 if (mlxsw_pci_cqe_lag_get(cqe
))
690 rx_info
.sys_port
= mlxsw_pci_cqe_system_port_get(cqe
);
691 rx_info
.trap_id
= mlxsw_pci_cqe_trap_id_get(cqe
);
693 byte_count
= mlxsw_pci_cqe_byte_count_get(cqe
);
694 if (mlxsw_pci_cqe_crc_get(cqe
))
695 byte_count
-= ETH_FCS_LEN
;
696 skb_put(skb
, byte_count
);
697 mlxsw_core_skb_receive(mlxsw_pci
->core
, skb
, &rx_info
);
700 memset(wqe
, 0, q
->elem_size
);
701 err
= mlxsw_pci_rdq_skb_alloc(mlxsw_pci
, elem_info
);
702 if (err
&& net_ratelimit())
703 dev_dbg(&pdev
->dev
, "Failed to alloc skb for RDQ\n");
704 /* Everything is set up, ring doorbell to pass elem to HW */
705 q
->producer_counter
++;
706 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
710 dev_kfree_skb_any(skb
);
714 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue
*q
)
716 return mlxsw_pci_queue_sw_elem_get(q
, mlxsw_pci_cqe_owner_get
);
719 static void mlxsw_pci_cq_tasklet(unsigned long data
)
721 struct mlxsw_pci_queue
*q
= (struct mlxsw_pci_queue
*) data
;
722 struct mlxsw_pci
*mlxsw_pci
= q
->pci
;
725 int credits
= q
->count
>> 1;
727 while ((cqe
= mlxsw_pci_cq_sw_cqe_get(q
))) {
728 u16 wqe_counter
= mlxsw_pci_cqe_wqe_counter_get(cqe
);
729 u8 sendq
= mlxsw_pci_cqe_sr_get(cqe
);
730 u8 dqn
= mlxsw_pci_cqe_dqn_get(cqe
);
733 struct mlxsw_pci_queue
*sdq
;
735 sdq
= mlxsw_pci_sdq_get(mlxsw_pci
, dqn
);
736 mlxsw_pci_cqe_sdq_handle(mlxsw_pci
, sdq
,
738 q
->u
.cq
.comp_sdq_count
++;
740 struct mlxsw_pci_queue
*rdq
;
742 rdq
= mlxsw_pci_rdq_get(mlxsw_pci
, dqn
);
743 mlxsw_pci_cqe_rdq_handle(mlxsw_pci
, rdq
,
745 q
->u
.cq
.comp_rdq_count
++;
747 if (++items
== credits
)
751 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
752 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
756 static int mlxsw_pci_eq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
757 struct mlxsw_pci_queue
*q
)
762 q
->consumer_counter
= 0;
764 for (i
= 0; i
< q
->count
; i
++) {
765 char *elem
= mlxsw_pci_queue_elem_get(q
, i
);
767 mlxsw_pci_eqe_owner_set(elem
, 1);
770 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox
, 1); /* MSI-X used */
771 mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox
, 0);
772 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox
, 1); /* armed */
773 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox
, ilog2(q
->count
));
774 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
775 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
777 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox
, i
, mapaddr
);
779 err
= mlxsw_cmd_sw2hw_eq(mlxsw_pci
->core
, mbox
, q
->num
);
782 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
783 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
787 static void mlxsw_pci_eq_fini(struct mlxsw_pci
*mlxsw_pci
,
788 struct mlxsw_pci_queue
*q
)
790 mlxsw_cmd_hw2sw_eq(mlxsw_pci
->core
, q
->num
);
793 static int mlxsw_pci_eq_dbg_read(struct seq_file
*file
, void *data
)
795 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
796 struct mlxsw_pci_queue
*q
;
798 static const char hdr
[] =
799 "NUM CONS_COUNT EV_CMD EV_COMP EV_OTHER COUNT\n";
801 seq_printf(file
, hdr
);
802 for (i
= 0; i
< mlxsw_pci_eq_count(mlxsw_pci
); i
++) {
803 q
= mlxsw_pci_eq_get(mlxsw_pci
, i
);
804 spin_lock_bh(&q
->lock
);
805 seq_printf(file
, "%3d %10d %10d %10d %10d %5d\n",
806 i
, q
->consumer_counter
, q
->u
.eq
.ev_cmd_count
,
807 q
->u
.eq
.ev_comp_count
, q
->u
.eq
.ev_other_count
,
809 spin_unlock_bh(&q
->lock
);
814 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci
*mlxsw_pci
, char *eqe
)
816 mlxsw_pci
->cmd
.comp
.status
= mlxsw_pci_eqe_cmd_status_get(eqe
);
817 mlxsw_pci
->cmd
.comp
.out_param
=
818 ((u64
) mlxsw_pci_eqe_cmd_out_param_h_get(eqe
)) << 32 |
819 mlxsw_pci_eqe_cmd_out_param_l_get(eqe
);
820 mlxsw_pci
->cmd
.wait_done
= true;
821 wake_up(&mlxsw_pci
->cmd
.wait
);
824 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue
*q
)
826 return mlxsw_pci_queue_sw_elem_get(q
, mlxsw_pci_eqe_owner_get
);
829 static void mlxsw_pci_eq_tasklet(unsigned long data
)
831 struct mlxsw_pci_queue
*q
= (struct mlxsw_pci_queue
*) data
;
832 struct mlxsw_pci
*mlxsw_pci
= q
->pci
;
833 unsigned long active_cqns
[BITS_TO_LONGS(MLXSW_PCI_CQS_COUNT
)];
836 bool cq_handle
= false;
838 int credits
= q
->count
>> 1;
840 memset(&active_cqns
, 0, sizeof(active_cqns
));
842 while ((eqe
= mlxsw_pci_eq_sw_eqe_get(q
))) {
843 u8 event_type
= mlxsw_pci_eqe_event_type_get(eqe
);
845 switch (event_type
) {
846 case MLXSW_PCI_EQE_EVENT_TYPE_CMD
:
847 mlxsw_pci_eq_cmd_event(mlxsw_pci
, eqe
);
848 q
->u
.eq
.ev_cmd_count
++;
850 case MLXSW_PCI_EQE_EVENT_TYPE_COMP
:
851 cqn
= mlxsw_pci_eqe_cqn_get(eqe
);
852 set_bit(cqn
, active_cqns
);
854 q
->u
.eq
.ev_comp_count
++;
857 q
->u
.eq
.ev_other_count
++;
859 if (++items
== credits
)
863 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
864 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
869 for_each_set_bit(cqn
, active_cqns
, MLXSW_PCI_CQS_COUNT
) {
870 q
= mlxsw_pci_cq_get(mlxsw_pci
, cqn
);
871 mlxsw_pci_queue_tasklet_schedule(q
);
875 struct mlxsw_pci_queue_ops
{
877 enum mlxsw_pci_queue_type type
;
878 int (*init
)(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
879 struct mlxsw_pci_queue
*q
);
880 void (*fini
)(struct mlxsw_pci
*mlxsw_pci
,
881 struct mlxsw_pci_queue
*q
);
882 void (*tasklet
)(unsigned long data
);
883 int (*dbg_read
)(struct seq_file
*s
, void *data
);
888 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops
= {
889 .type
= MLXSW_PCI_QUEUE_TYPE_SDQ
,
890 .init
= mlxsw_pci_sdq_init
,
891 .fini
= mlxsw_pci_sdq_fini
,
892 .dbg_read
= mlxsw_pci_sdq_dbg_read
,
893 .elem_count
= MLXSW_PCI_WQE_COUNT
,
894 .elem_size
= MLXSW_PCI_WQE_SIZE
,
897 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops
= {
898 .type
= MLXSW_PCI_QUEUE_TYPE_RDQ
,
899 .init
= mlxsw_pci_rdq_init
,
900 .fini
= mlxsw_pci_rdq_fini
,
901 .dbg_read
= mlxsw_pci_rdq_dbg_read
,
902 .elem_count
= MLXSW_PCI_WQE_COUNT
,
903 .elem_size
= MLXSW_PCI_WQE_SIZE
906 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops
= {
907 .type
= MLXSW_PCI_QUEUE_TYPE_CQ
,
908 .init
= mlxsw_pci_cq_init
,
909 .fini
= mlxsw_pci_cq_fini
,
910 .tasklet
= mlxsw_pci_cq_tasklet
,
911 .dbg_read
= mlxsw_pci_cq_dbg_read
,
912 .elem_count
= MLXSW_PCI_CQE_COUNT
,
913 .elem_size
= MLXSW_PCI_CQE_SIZE
916 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops
= {
917 .type
= MLXSW_PCI_QUEUE_TYPE_EQ
,
918 .init
= mlxsw_pci_eq_init
,
919 .fini
= mlxsw_pci_eq_fini
,
920 .tasklet
= mlxsw_pci_eq_tasklet
,
921 .dbg_read
= mlxsw_pci_eq_dbg_read
,
922 .elem_count
= MLXSW_PCI_EQE_COUNT
,
923 .elem_size
= MLXSW_PCI_EQE_SIZE
926 static int mlxsw_pci_queue_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
927 const struct mlxsw_pci_queue_ops
*q_ops
,
928 struct mlxsw_pci_queue
*q
, u8 q_num
)
930 struct mlxsw_pci_mem_item
*mem_item
= &q
->mem_item
;
934 spin_lock_init(&q
->lock
);
936 q
->count
= q_ops
->elem_count
;
937 q
->elem_size
= q_ops
->elem_size
;
938 q
->type
= q_ops
->type
;
942 tasklet_init(&q
->tasklet
, q_ops
->tasklet
, (unsigned long) q
);
944 mem_item
->size
= MLXSW_PCI_AQ_SIZE
;
945 mem_item
->buf
= pci_alloc_consistent(mlxsw_pci
->pdev
,
950 memset(mem_item
->buf
, 0, mem_item
->size
);
952 q
->elem_info
= kcalloc(q
->count
, sizeof(*q
->elem_info
), GFP_KERNEL
);
955 goto err_elem_info_alloc
;
958 /* Initialize dma mapped elements info elem_info for
959 * future easy access.
961 for (i
= 0; i
< q
->count
; i
++) {
962 struct mlxsw_pci_queue_elem_info
*elem_info
;
964 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
966 __mlxsw_pci_queue_elem_get(q
, q_ops
->elem_size
, i
);
969 mlxsw_cmd_mbox_zero(mbox
);
970 err
= q_ops
->init(mlxsw_pci
, mbox
, q
);
978 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
979 mem_item
->buf
, mem_item
->mapaddr
);
983 static void mlxsw_pci_queue_fini(struct mlxsw_pci
*mlxsw_pci
,
984 const struct mlxsw_pci_queue_ops
*q_ops
,
985 struct mlxsw_pci_queue
*q
)
987 struct mlxsw_pci_mem_item
*mem_item
= &q
->mem_item
;
989 q_ops
->fini(mlxsw_pci
, q
);
991 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
992 mem_item
->buf
, mem_item
->mapaddr
);
995 static int mlxsw_pci_queue_group_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
996 const struct mlxsw_pci_queue_ops
*q_ops
,
999 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1000 struct mlxsw_pci_queue_type_group
*queue_group
;
1005 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_ops
->type
);
1006 queue_group
->q
= kcalloc(num_qs
, sizeof(*queue_group
->q
), GFP_KERNEL
);
1007 if (!queue_group
->q
)
1010 for (i
= 0; i
< num_qs
; i
++) {
1011 err
= mlxsw_pci_queue_init(mlxsw_pci
, mbox
, q_ops
,
1012 &queue_group
->q
[i
], i
);
1014 goto err_queue_init
;
1016 queue_group
->count
= num_qs
;
1018 sprintf(tmp
, "%s_stats", mlxsw_pci_queue_type_str(q_ops
->type
));
1019 debugfs_create_devm_seqfile(&pdev
->dev
, tmp
, mlxsw_pci
->dbg_dir
,
1025 for (i
--; i
>= 0; i
--)
1026 mlxsw_pci_queue_fini(mlxsw_pci
, q_ops
, &queue_group
->q
[i
]);
1027 kfree(queue_group
->q
);
1031 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci
*mlxsw_pci
,
1032 const struct mlxsw_pci_queue_ops
*q_ops
)
1034 struct mlxsw_pci_queue_type_group
*queue_group
;
1037 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_ops
->type
);
1038 for (i
= 0; i
< queue_group
->count
; i
++)
1039 mlxsw_pci_queue_fini(mlxsw_pci
, q_ops
, &queue_group
->q
[i
]);
1040 kfree(queue_group
->q
);
1043 static int mlxsw_pci_aqs_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
)
1045 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1056 mlxsw_cmd_mbox_zero(mbox
);
1057 err
= mlxsw_cmd_query_aq_cap(mlxsw_pci
->core
, mbox
);
1061 num_sdqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox
);
1062 sdq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox
);
1063 num_rdqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox
);
1064 rdq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox
);
1065 num_cqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox
);
1066 cq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox
);
1067 num_eqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox
);
1068 eq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox
);
1070 if ((num_sdqs
!= MLXSW_PCI_SDQS_COUNT
) ||
1071 (num_rdqs
!= MLXSW_PCI_RDQS_COUNT
) ||
1072 (num_cqs
!= MLXSW_PCI_CQS_COUNT
) ||
1073 (num_eqs
!= MLXSW_PCI_EQS_COUNT
)) {
1074 dev_err(&pdev
->dev
, "Unsupported number of queues\n");
1078 if ((1 << sdq_log2sz
!= MLXSW_PCI_WQE_COUNT
) ||
1079 (1 << rdq_log2sz
!= MLXSW_PCI_WQE_COUNT
) ||
1080 (1 << cq_log2sz
!= MLXSW_PCI_CQE_COUNT
) ||
1081 (1 << eq_log2sz
!= MLXSW_PCI_EQE_COUNT
)) {
1082 dev_err(&pdev
->dev
, "Unsupported number of async queue descriptors\n");
1086 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_eq_ops
,
1089 dev_err(&pdev
->dev
, "Failed to initialize event queues\n");
1093 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_cq_ops
,
1096 dev_err(&pdev
->dev
, "Failed to initialize completion queues\n");
1100 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_sdq_ops
,
1103 dev_err(&pdev
->dev
, "Failed to initialize send descriptor queues\n");
1107 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_rdq_ops
,
1110 dev_err(&pdev
->dev
, "Failed to initialize receive descriptor queues\n");
1114 /* We have to poll in command interface until queues are initialized */
1115 mlxsw_pci
->cmd
.nopoll
= true;
1119 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_sdq_ops
);
1121 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_cq_ops
);
1123 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_eq_ops
);
1127 static void mlxsw_pci_aqs_fini(struct mlxsw_pci
*mlxsw_pci
)
1129 mlxsw_pci
->cmd
.nopoll
= false;
1130 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_rdq_ops
);
1131 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_sdq_ops
);
1132 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_cq_ops
);
1133 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_eq_ops
);
1137 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci
*mlxsw_pci
,
1138 char *mbox
, int index
,
1139 const struct mlxsw_swid_config
*swid
)
1143 if (swid
->used_type
) {
1144 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1145 mbox
, index
, swid
->type
);
1148 if (swid
->used_properties
) {
1149 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1150 mbox
, index
, swid
->properties
);
1153 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox
, index
, mask
);
1156 static int mlxsw_pci_config_profile(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
1157 const struct mlxsw_config_profile
*profile
)
1161 mlxsw_cmd_mbox_zero(mbox
);
1163 if (profile
->used_max_vepa_channels
) {
1164 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1166 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1167 mbox
, profile
->max_vepa_channels
);
1169 if (profile
->used_max_lag
) {
1170 mlxsw_cmd_mbox_config_profile_set_max_lag_set(
1172 mlxsw_cmd_mbox_config_profile_max_lag_set(
1173 mbox
, profile
->max_lag
);
1175 if (profile
->used_max_port_per_lag
) {
1176 mlxsw_cmd_mbox_config_profile_set_max_port_per_lag_set(
1178 mlxsw_cmd_mbox_config_profile_max_port_per_lag_set(
1179 mbox
, profile
->max_port_per_lag
);
1181 if (profile
->used_max_mid
) {
1182 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1184 mlxsw_cmd_mbox_config_profile_max_mid_set(
1185 mbox
, profile
->max_mid
);
1187 if (profile
->used_max_pgt
) {
1188 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1190 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1191 mbox
, profile
->max_pgt
);
1193 if (profile
->used_max_system_port
) {
1194 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1196 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1197 mbox
, profile
->max_system_port
);
1199 if (profile
->used_max_vlan_groups
) {
1200 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1202 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1203 mbox
, profile
->max_vlan_groups
);
1205 if (profile
->used_max_regions
) {
1206 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1208 mlxsw_cmd_mbox_config_profile_max_regions_set(
1209 mbox
, profile
->max_regions
);
1211 if (profile
->used_flood_tables
) {
1212 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1214 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1215 mbox
, profile
->max_flood_tables
);
1216 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1217 mbox
, profile
->max_vid_flood_tables
);
1219 if (profile
->used_flood_mode
) {
1220 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1222 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1223 mbox
, profile
->flood_mode
);
1225 if (profile
->used_max_ib_mc
) {
1226 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1228 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1229 mbox
, profile
->max_ib_mc
);
1231 if (profile
->used_max_pkey
) {
1232 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1234 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1235 mbox
, profile
->max_pkey
);
1237 if (profile
->used_ar_sec
) {
1238 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1240 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1241 mbox
, profile
->ar_sec
);
1243 if (profile
->used_adaptive_routing_group_cap
) {
1244 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1246 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1247 mbox
, profile
->adaptive_routing_group_cap
);
1250 for (i
= 0; i
< MLXSW_CONFIG_PROFILE_SWID_COUNT
; i
++)
1251 mlxsw_pci_config_profile_swid_config(mlxsw_pci
, mbox
, i
,
1252 &profile
->swid_config
[i
]);
1254 return mlxsw_cmd_config_profile_set(mlxsw_pci
->core
, mbox
);
1257 static int mlxsw_pci_boardinfo(struct mlxsw_pci
*mlxsw_pci
, char *mbox
)
1259 struct mlxsw_bus_info
*bus_info
= &mlxsw_pci
->bus_info
;
1262 mlxsw_cmd_mbox_zero(mbox
);
1263 err
= mlxsw_cmd_boardinfo(mlxsw_pci
->core
, mbox
);
1266 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox
, bus_info
->vsd
);
1267 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox
, bus_info
->psid
);
1271 static int mlxsw_pci_fw_area_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
1274 struct mlxsw_pci_mem_item
*mem_item
;
1278 mlxsw_pci
->fw_area
.items
= kcalloc(num_pages
, sizeof(*mem_item
),
1280 if (!mlxsw_pci
->fw_area
.items
)
1282 mlxsw_pci
->fw_area
.num_pages
= num_pages
;
1284 mlxsw_cmd_mbox_zero(mbox
);
1285 for (i
= 0; i
< num_pages
; i
++) {
1286 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1288 mem_item
->size
= MLXSW_PCI_PAGE_SIZE
;
1289 mem_item
->buf
= pci_alloc_consistent(mlxsw_pci
->pdev
,
1291 &mem_item
->mapaddr
);
1292 if (!mem_item
->buf
) {
1296 mlxsw_cmd_mbox_map_fa_pa_set(mbox
, i
, mem_item
->mapaddr
);
1297 mlxsw_cmd_mbox_map_fa_log2size_set(mbox
, i
, 0); /* 1 page */
1300 err
= mlxsw_cmd_map_fa(mlxsw_pci
->core
, mbox
, num_pages
);
1302 goto err_cmd_map_fa
;
1308 for (i
--; i
>= 0; i
--) {
1309 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1311 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
1312 mem_item
->buf
, mem_item
->mapaddr
);
1314 kfree(mlxsw_pci
->fw_area
.items
);
1318 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci
*mlxsw_pci
)
1320 struct mlxsw_pci_mem_item
*mem_item
;
1323 mlxsw_cmd_unmap_fa(mlxsw_pci
->core
);
1325 for (i
= 0; i
< mlxsw_pci
->fw_area
.num_pages
; i
++) {
1326 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1328 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
1329 mem_item
->buf
, mem_item
->mapaddr
);
1331 kfree(mlxsw_pci
->fw_area
.items
);
1334 static irqreturn_t
mlxsw_pci_eq_irq_handler(int irq
, void *dev_id
)
1336 struct mlxsw_pci
*mlxsw_pci
= dev_id
;
1337 struct mlxsw_pci_queue
*q
;
1340 for (i
= 0; i
< MLXSW_PCI_EQS_COUNT
; i
++) {
1341 q
= mlxsw_pci_eq_get(mlxsw_pci
, i
);
1342 mlxsw_pci_queue_tasklet_schedule(q
);
1347 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci
*mlxsw_pci
,
1348 struct mlxsw_pci_mem_item
*mbox
)
1350 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1353 mbox
->size
= MLXSW_CMD_MBOX_SIZE
;
1354 mbox
->buf
= pci_alloc_consistent(pdev
, MLXSW_CMD_MBOX_SIZE
,
1357 dev_err(&pdev
->dev
, "Failed allocating memory for mailbox\n");
1364 static void mlxsw_pci_mbox_free(struct mlxsw_pci
*mlxsw_pci
,
1365 struct mlxsw_pci_mem_item
*mbox
)
1367 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1369 pci_free_consistent(pdev
, MLXSW_CMD_MBOX_SIZE
, mbox
->buf
,
1373 static int mlxsw_pci_init(void *bus_priv
, struct mlxsw_core
*mlxsw_core
,
1374 const struct mlxsw_config_profile
*profile
)
1376 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1377 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1382 mutex_init(&mlxsw_pci
->cmd
.lock
);
1383 init_waitqueue_head(&mlxsw_pci
->cmd
.wait
);
1385 mlxsw_pci
->core
= mlxsw_core
;
1387 mbox
= mlxsw_cmd_mbox_alloc();
1391 err
= mlxsw_pci_mbox_alloc(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1395 err
= mlxsw_pci_mbox_alloc(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1397 goto err_out_mbox_alloc
;
1399 err
= mlxsw_cmd_query_fw(mlxsw_core
, mbox
);
1403 mlxsw_pci
->bus_info
.fw_rev
.major
=
1404 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox
);
1405 mlxsw_pci
->bus_info
.fw_rev
.minor
=
1406 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox
);
1407 mlxsw_pci
->bus_info
.fw_rev
.subminor
=
1408 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox
);
1410 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox
) != 1) {
1411 dev_err(&pdev
->dev
, "Unsupported cmd interface revision ID queried from hw\n");
1415 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox
) != 0) {
1416 dev_err(&pdev
->dev
, "Unsupported doorbell page bar queried from hw\n");
1418 goto err_doorbell_page_bar
;
1421 mlxsw_pci
->doorbell_offset
=
1422 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox
);
1424 num_pages
= mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox
);
1425 err
= mlxsw_pci_fw_area_init(mlxsw_pci
, mbox
, num_pages
);
1427 goto err_fw_area_init
;
1429 err
= mlxsw_pci_boardinfo(mlxsw_pci
, mbox
);
1433 err
= mlxsw_pci_config_profile(mlxsw_pci
, mbox
, profile
);
1435 goto err_config_profile
;
1437 err
= mlxsw_pci_aqs_init(mlxsw_pci
, mbox
);
1441 err
= request_irq(mlxsw_pci
->msix_entry
.vector
,
1442 mlxsw_pci_eq_irq_handler
, 0,
1443 mlxsw_pci_driver_name
, mlxsw_pci
);
1445 dev_err(&pdev
->dev
, "IRQ request failed\n");
1446 goto err_request_eq_irq
;
1452 mlxsw_pci_aqs_fini(mlxsw_pci
);
1456 mlxsw_pci_fw_area_fini(mlxsw_pci
);
1458 err_doorbell_page_bar
:
1461 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1463 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1465 mlxsw_cmd_mbox_free(mbox
);
1469 static void mlxsw_pci_fini(void *bus_priv
)
1471 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1473 free_irq(mlxsw_pci
->msix_entry
.vector
, mlxsw_pci
);
1474 mlxsw_pci_aqs_fini(mlxsw_pci
);
1475 mlxsw_pci_fw_area_fini(mlxsw_pci
);
1476 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1477 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1480 static struct mlxsw_pci_queue
*
1481 mlxsw_pci_sdq_pick(struct mlxsw_pci
*mlxsw_pci
,
1482 const struct mlxsw_tx_info
*tx_info
)
1484 u8 sdqn
= tx_info
->local_port
% mlxsw_pci_sdq_count(mlxsw_pci
);
1486 return mlxsw_pci_sdq_get(mlxsw_pci
, sdqn
);
1489 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv
,
1490 const struct mlxsw_tx_info
*tx_info
)
1492 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1493 struct mlxsw_pci_queue
*q
= mlxsw_pci_sdq_pick(mlxsw_pci
, tx_info
);
1495 return !mlxsw_pci_queue_elem_info_producer_get(q
);
1498 static int mlxsw_pci_skb_transmit(void *bus_priv
, struct sk_buff
*skb
,
1499 const struct mlxsw_tx_info
*tx_info
)
1501 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1502 struct mlxsw_pci_queue
*q
;
1503 struct mlxsw_pci_queue_elem_info
*elem_info
;
1508 if (skb_shinfo(skb
)->nr_frags
> MLXSW_PCI_WQE_SG_ENTRIES
- 1) {
1509 err
= skb_linearize(skb
);
1514 q
= mlxsw_pci_sdq_pick(mlxsw_pci
, tx_info
);
1515 spin_lock_bh(&q
->lock
);
1516 elem_info
= mlxsw_pci_queue_elem_info_producer_get(q
);
1522 elem_info
->u
.sdq
.skb
= skb
;
1524 wqe
= elem_info
->elem
;
1525 mlxsw_pci_wqe_c_set(wqe
, 1); /* always report completion */
1526 mlxsw_pci_wqe_lp_set(wqe
, !!tx_info
->is_emad
);
1527 mlxsw_pci_wqe_type_set(wqe
, MLXSW_PCI_WQE_TYPE_ETHERNET
);
1529 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, 0, skb
->data
,
1530 skb_headlen(skb
), DMA_TO_DEVICE
);
1534 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1535 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1537 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, i
+ 1,
1538 skb_frag_address(frag
),
1539 skb_frag_size(frag
),
1545 /* Set unused sq entries byte count to zero. */
1546 for (i
++; i
< MLXSW_PCI_WQE_SG_ENTRIES
; i
++)
1547 mlxsw_pci_wqe_byte_count_set(wqe
, i
, 0);
1549 /* Everything is set up, ring producer doorbell to get HW going */
1550 q
->producer_counter
++;
1551 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
1557 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, i
, DMA_TO_DEVICE
);
1559 spin_unlock_bh(&q
->lock
);
1563 static int mlxsw_pci_cmd_exec(void *bus_priv
, u16 opcode
, u8 opcode_mod
,
1564 u32 in_mod
, bool out_mbox_direct
,
1565 char *in_mbox
, size_t in_mbox_size
,
1566 char *out_mbox
, size_t out_mbox_size
,
1569 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1570 dma_addr_t in_mapaddr
= mlxsw_pci
->cmd
.in_mbox
.mapaddr
;
1571 dma_addr_t out_mapaddr
= mlxsw_pci
->cmd
.out_mbox
.mapaddr
;
1572 bool evreq
= mlxsw_pci
->cmd
.nopoll
;
1573 unsigned long timeout
= msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS
);
1574 bool *p_wait_done
= &mlxsw_pci
->cmd
.wait_done
;
1577 *p_status
= MLXSW_CMD_STATUS_OK
;
1579 err
= mutex_lock_interruptible(&mlxsw_pci
->cmd
.lock
);
1584 memcpy(mlxsw_pci
->cmd
.in_mbox
.buf
, in_mbox
, in_mbox_size
);
1585 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_PARAM_HI
, upper_32_bits(in_mapaddr
));
1586 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_PARAM_LO
, lower_32_bits(in_mapaddr
));
1588 mlxsw_pci_write32(mlxsw_pci
, CIR_OUT_PARAM_HI
, upper_32_bits(out_mapaddr
));
1589 mlxsw_pci_write32(mlxsw_pci
, CIR_OUT_PARAM_LO
, lower_32_bits(out_mapaddr
));
1591 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_MODIFIER
, in_mod
);
1592 mlxsw_pci_write32(mlxsw_pci
, CIR_TOKEN
, 0);
1594 *p_wait_done
= false;
1596 wmb(); /* all needs to be written before we write control register */
1597 mlxsw_pci_write32(mlxsw_pci
, CIR_CTRL
,
1598 MLXSW_PCI_CIR_CTRL_GO_BIT
|
1599 (evreq
? MLXSW_PCI_CIR_CTRL_EVREQ_BIT
: 0) |
1600 (opcode_mod
<< MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT
) |
1606 end
= jiffies
+ timeout
;
1608 u32 ctrl
= mlxsw_pci_read32(mlxsw_pci
, CIR_CTRL
);
1610 if (!(ctrl
& MLXSW_PCI_CIR_CTRL_GO_BIT
)) {
1611 *p_wait_done
= true;
1612 *p_status
= ctrl
>> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT
;
1616 } while (time_before(jiffies
, end
));
1618 wait_event_timeout(mlxsw_pci
->cmd
.wait
, *p_wait_done
, timeout
);
1619 *p_status
= mlxsw_pci
->cmd
.comp
.status
;
1630 if (!err
&& out_mbox
&& out_mbox_direct
) {
1631 /* Some commands don't use output param as address to mailbox
1632 * but they store output directly into registers. In that case,
1633 * copy registers into mbox buffer.
1638 tmp
= cpu_to_be32(mlxsw_pci_read32(mlxsw_pci
,
1640 memcpy(out_mbox
, &tmp
, sizeof(tmp
));
1641 tmp
= cpu_to_be32(mlxsw_pci_read32(mlxsw_pci
,
1643 memcpy(out_mbox
+ sizeof(tmp
), &tmp
, sizeof(tmp
));
1645 } else if (!err
&& out_mbox
)
1646 memcpy(out_mbox
, mlxsw_pci
->cmd
.out_mbox
.buf
, out_mbox_size
);
1648 mutex_unlock(&mlxsw_pci
->cmd
.lock
);
1653 static const struct mlxsw_bus mlxsw_pci_bus
= {
1655 .init
= mlxsw_pci_init
,
1656 .fini
= mlxsw_pci_fini
,
1657 .skb_transmit_busy
= mlxsw_pci_skb_transmit_busy
,
1658 .skb_transmit
= mlxsw_pci_skb_transmit
,
1659 .cmd_exec
= mlxsw_pci_cmd_exec
,
1662 static int mlxsw_pci_sw_reset(struct mlxsw_pci
*mlxsw_pci
)
1664 mlxsw_pci_write32(mlxsw_pci
, SW_RESET
, MLXSW_PCI_SW_RESET_RST_BIT
);
1665 /* Current firware does not let us know when the reset is done.
1666 * So we just wait here for constant time and hope for the best.
1668 msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS
);
1672 static int mlxsw_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1674 struct mlxsw_pci
*mlxsw_pci
;
1677 mlxsw_pci
= kzalloc(sizeof(*mlxsw_pci
), GFP_KERNEL
);
1681 err
= pci_enable_device(pdev
);
1683 dev_err(&pdev
->dev
, "pci_enable_device failed\n");
1684 goto err_pci_enable_device
;
1687 err
= pci_request_regions(pdev
, mlxsw_pci_driver_name
);
1689 dev_err(&pdev
->dev
, "pci_request_regions failed\n");
1690 goto err_pci_request_regions
;
1693 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
1695 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
1697 dev_err(&pdev
->dev
, "pci_set_consistent_dma_mask failed\n");
1698 goto err_pci_set_dma_mask
;
1701 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
1703 dev_err(&pdev
->dev
, "pci_set_dma_mask failed\n");
1704 goto err_pci_set_dma_mask
;
1708 if (pci_resource_len(pdev
, 0) < MLXSW_PCI_BAR0_SIZE
) {
1709 dev_err(&pdev
->dev
, "invalid PCI region size\n");
1711 goto err_pci_resource_len_check
;
1714 mlxsw_pci
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
1715 pci_resource_len(pdev
, 0));
1716 if (!mlxsw_pci
->hw_addr
) {
1717 dev_err(&pdev
->dev
, "ioremap failed\n");
1721 pci_set_master(pdev
);
1723 mlxsw_pci
->pdev
= pdev
;
1724 pci_set_drvdata(pdev
, mlxsw_pci
);
1726 err
= mlxsw_pci_sw_reset(mlxsw_pci
);
1728 dev_err(&pdev
->dev
, "Software reset failed\n");
1732 err
= pci_enable_msix_exact(pdev
, &mlxsw_pci
->msix_entry
, 1);
1734 dev_err(&pdev
->dev
, "MSI-X init failed\n");
1738 mlxsw_pci
->bus_info
.device_kind
= mlxsw_pci_device_kind_get(id
);
1739 mlxsw_pci
->bus_info
.device_name
= pci_name(mlxsw_pci
->pdev
);
1740 mlxsw_pci
->bus_info
.dev
= &pdev
->dev
;
1742 mlxsw_pci
->dbg_dir
= debugfs_create_dir(mlxsw_pci
->bus_info
.device_name
,
1743 mlxsw_pci_dbg_root
);
1744 if (!mlxsw_pci
->dbg_dir
) {
1745 dev_err(&pdev
->dev
, "Failed to create debugfs dir\n");
1747 goto err_dbg_create_dir
;
1750 err
= mlxsw_core_bus_device_register(&mlxsw_pci
->bus_info
,
1751 &mlxsw_pci_bus
, mlxsw_pci
);
1753 dev_err(&pdev
->dev
, "cannot register bus device\n");
1754 goto err_bus_device_register
;
1759 err_bus_device_register
:
1760 debugfs_remove_recursive(mlxsw_pci
->dbg_dir
);
1762 pci_disable_msix(mlxsw_pci
->pdev
);
1765 iounmap(mlxsw_pci
->hw_addr
);
1767 err_pci_resource_len_check
:
1768 err_pci_set_dma_mask
:
1769 pci_release_regions(pdev
);
1770 err_pci_request_regions
:
1771 pci_disable_device(pdev
);
1772 err_pci_enable_device
:
1777 static void mlxsw_pci_remove(struct pci_dev
*pdev
)
1779 struct mlxsw_pci
*mlxsw_pci
= pci_get_drvdata(pdev
);
1781 mlxsw_core_bus_device_unregister(mlxsw_pci
->core
);
1782 debugfs_remove_recursive(mlxsw_pci
->dbg_dir
);
1783 pci_disable_msix(mlxsw_pci
->pdev
);
1784 iounmap(mlxsw_pci
->hw_addr
);
1785 pci_release_regions(mlxsw_pci
->pdev
);
1786 pci_disable_device(mlxsw_pci
->pdev
);
1790 static struct pci_driver mlxsw_pci_driver
= {
1791 .name
= mlxsw_pci_driver_name
,
1792 .id_table
= mlxsw_pci_id_table
,
1793 .probe
= mlxsw_pci_probe
,
1794 .remove
= mlxsw_pci_remove
,
1797 static int __init
mlxsw_pci_module_init(void)
1801 mlxsw_pci_dbg_root
= debugfs_create_dir(mlxsw_pci_driver_name
, NULL
);
1802 if (!mlxsw_pci_dbg_root
)
1804 err
= pci_register_driver(&mlxsw_pci_driver
);
1806 goto err_register_driver
;
1809 err_register_driver
:
1810 debugfs_remove_recursive(mlxsw_pci_dbg_root
);
1814 static void __exit
mlxsw_pci_module_exit(void)
1816 pci_unregister_driver(&mlxsw_pci_driver
);
1817 debugfs_remove_recursive(mlxsw_pci_dbg_root
);
1820 module_init(mlxsw_pci_module_init
);
1821 module_exit(mlxsw_pci_module_exit
);
1823 MODULE_LICENSE("Dual BSD/GPL");
1824 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1825 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");
1826 MODULE_DEVICE_TABLE(pci
, mlxsw_pci_id_table
);