include/linux/mfd/abx500/ab8500.h

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License Terms: GNU General Public License v2
   5  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
   6  */
   7 #ifndef MFD_AB8500_H
   8 #define MFD_AB8500_H
   9
  10 #include <linux/device.h>
  11 /*
  12  * AB IC versions
  13  *
  14  * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
  15  * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
  16  * print of version string.
  17  */
  18 enum ab8500_version {
  19         AB8500_VERSION_AB8500 = 0x0,
  20         AB8500_VERSION_AB8505 = 0x1,
  21         AB8500_VERSION_AB9540 = 0x2,
  22         AB8500_VERSION_AB8540 = 0x3,
  23         AB8500_VERSION_UNDEFINED,
  24 };
  25
  26 /* AB8500 CIDs*/
  27 #define AB8500_CUTEARLY 0x00
  28 #define AB8500_CUT1P0   0x10
  29 #define AB8500_CUT1P1   0x11
  30 #define AB8500_CUT2P0   0x20
  31 #define AB8500_CUT3P0   0x30
  32 #define AB8500_CUT3P3   0x33
  33
  34 /*
  35  * AB8500 bank addresses
  36  */
  37 #define AB8500_SYS_CTRL1_BLOCK  0x1
  38 #define AB8500_SYS_CTRL2_BLOCK  0x2
  39 #define AB8500_REGU_CTRL1       0x3
  40 #define AB8500_REGU_CTRL2       0x4
  41 #define AB8500_USB              0x5
  42 #define AB8500_TVOUT            0x6
  43 #define AB8500_DBI              0x7
  44 #define AB8500_ECI_AV_ACC       0x8
  45 #define AB8500_RESERVED         0x9
  46 #define AB8500_GPADC            0xA
  47 #define AB8500_CHARGER          0xB
  48 #define AB8500_GAS_GAUGE        0xC
  49 #define AB8500_AUDIO            0xD
  50 #define AB8500_INTERRUPT        0xE
  51 #define AB8500_RTC              0xF
  52 #define AB8500_MISC             0x10
  53 #define AB8500_DEVELOPMENT      0x11
  54 #define AB8500_DEBUG            0x12
  55 #define AB8500_PROD_TEST        0x13
  56 #define AB8500_OTP_EMUL         0x15
  57
  58 /*
  59  * Interrupts
  60  * Values used to index into array ab8500_irq_regoffset[] defined in
  61  * drivers/mdf/ab8500-core.c
  62  */
  63 /* Definitions for AB8500 and AB9540 */
  64 /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
  65 #define AB8500_INT_MAIN_EXT_CH_NOT_OK   0 /* not 8505/9540 */
  66 #define AB8500_INT_UN_PLUG_TV_DET       1 /* not 8505/9540 */
  67 #define AB8500_INT_PLUG_TV_DET          2 /* not 8505/9540 */
  68 #define AB8500_INT_TEMP_WARM            3
  69 #define AB8500_INT_PON_KEY2DB_F         4
  70 #define AB8500_INT_PON_KEY2DB_R         5
  71 #define AB8500_INT_PON_KEY1DB_F         6
  72 #define AB8500_INT_PON_KEY1DB_R         7
  73 /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
  74 #define AB8500_INT_BATT_OVV             8
  75 #define AB8500_INT_MAIN_CH_UNPLUG_DET   10 /* not 8505 */
  76 #define AB8500_INT_MAIN_CH_PLUG_DET     11 /* not 8505 */
  77 #define AB8500_INT_VBUS_DET_F           14
  78 #define AB8500_INT_VBUS_DET_R           15
  79 /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
  80 #define AB8500_INT_VBUS_CH_DROP_END     16
  81 #define AB8500_INT_RTC_60S              17
  82 #define AB8500_INT_RTC_ALARM            18
  83 #define AB8500_INT_BAT_CTRL_INDB        20
  84 #define AB8500_INT_CH_WD_EXP            21
  85 #define AB8500_INT_VBUS_OVV             22
  86 #define AB8500_INT_MAIN_CH_DROP_END     23 /* not 8505/9540 */
  87 /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
  88 #define AB8500_INT_CCN_CONV_ACC         24
  89 #define AB8500_INT_INT_AUD              25
  90 #define AB8500_INT_CCEOC                26
  91 #define AB8500_INT_CC_INT_CALIB         27
  92 #define AB8500_INT_LOW_BAT_F            28
  93 #define AB8500_INT_LOW_BAT_R            29
  94 #define AB8500_INT_BUP_CHG_NOT_OK       30
  95 #define AB8500_INT_BUP_CHG_OK           31
  96 /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
  97 #define AB8500_INT_GP_HW_ADC_CONV_END   32 /* not 8505 */
  98 #define AB8500_INT_ACC_DETECT_1DB_F     33
  99 #define AB8500_INT_ACC_DETECT_1DB_R     34
 100 #define AB8500_INT_ACC_DETECT_22DB_F    35
 101 #define AB8500_INT_ACC_DETECT_22DB_R    36
 102 #define AB8500_INT_ACC_DETECT_21DB_F    37
 103 #define AB8500_INT_ACC_DETECT_21DB_R    38
 104 #define AB8500_INT_GP_SW_ADC_CONV_END   39
 105 /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
 106 #define AB8500_INT_GPIO6R               40 /* not 8505/9540 */
 107 #define AB8500_INT_GPIO7R               41 /* not 8505/9540 */
 108 #define AB8500_INT_GPIO8R               42 /* not 8505/9540 */
 109 #define AB8500_INT_GPIO9R               43 /* not 8505/9540 */
 110 #define AB8500_INT_GPIO10R              44
 111 #define AB8500_INT_GPIO11R              45
 112 #define AB8500_INT_GPIO12R              46 /* not 8505 */
 113 #define AB8500_INT_GPIO13R              47
 114 /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
 115 #define AB8500_INT_GPIO24R              48 /* not 8505 */
 116 #define AB8500_INT_GPIO25R              49 /* not 8505 */
 117 #define AB8500_INT_GPIO36R              50 /* not 8505/9540 */
 118 #define AB8500_INT_GPIO37R              51 /* not 8505/9540 */
 119 #define AB8500_INT_GPIO38R              52 /* not 8505/9540 */
 120 #define AB8500_INT_GPIO39R              53 /* not 8505/9540 */
 121 #define AB8500_INT_GPIO40R              54
 122 #define AB8500_INT_GPIO41R              55
 123 /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
 124 #define AB8500_INT_GPIO6F               56 /* not 8505/9540 */
 125 #define AB8500_INT_GPIO7F               57 /* not 8505/9540 */
 126 #define AB8500_INT_GPIO8F               58 /* not 8505/9540 */
 127 #define AB8500_INT_GPIO9F               59 /* not 8505/9540 */
 128 #define AB8500_INT_GPIO10F              60
 129 #define AB8500_INT_GPIO11F              61
 130 #define AB8500_INT_GPIO12F              62 /* not 8505 */
 131 #define AB8500_INT_GPIO13F              63
 132 /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
 133 #define AB8500_INT_GPIO24F              64 /* not 8505 */
 134 #define AB8500_INT_GPIO25F              65 /* not 8505 */
 135 #define AB8500_INT_GPIO36F              66 /* not 8505/9540 */
 136 #define AB8500_INT_GPIO37F              67 /* not 8505/9540 */
 137 #define AB8500_INT_GPIO38F              68 /* not 8505/9540 */
 138 #define AB8500_INT_GPIO39F              69 /* not 8505/9540 */
 139 #define AB8500_INT_GPIO40F              70
 140 #define AB8500_INT_GPIO41F              71
 141 /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
 142 #define AB8500_INT_ADP_SOURCE_ERROR     72
 143 #define AB8500_INT_ADP_SINK_ERROR       73
 144 #define AB8500_INT_ADP_PROBE_PLUG       74
 145 #define AB8500_INT_ADP_PROBE_UNPLUG     75
 146 #define AB8500_INT_ADP_SENSE_OFF        76
 147 #define AB8500_INT_USB_PHY_POWER_ERR    78
 148 #define AB8500_INT_USB_LINK_STATUS      79
 149 /* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
 150 #define AB8500_INT_BTEMP_LOW            80
 151 #define AB8500_INT_BTEMP_LOW_MEDIUM     81
 152 #define AB8500_INT_BTEMP_MEDIUM_HIGH    82
 153 #define AB8500_INT_BTEMP_HIGH           83
 154 /* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
 155 #define AB8500_INT_SRP_DETECT           88
 156 #define AB8500_INT_USB_CHARGER_NOT_OKR  89
 157 #define AB8500_INT_ID_WAKEUP_R          90
 158 #define AB8500_INT_ID_DET_R1R           92
 159 #define AB8500_INT_ID_DET_R2R           93
 160 #define AB8500_INT_ID_DET_R3R           94
 161 #define AB8500_INT_ID_DET_R4R           95
 162 /* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
 163 #define AB8500_INT_ID_WAKEUP_F          96
 164 #define AB8500_INT_ID_DET_R1F           98
 165 #define AB8500_INT_ID_DET_R2F           99
 166 #define AB8500_INT_ID_DET_R3F           100
 167 #define AB8500_INT_ID_DET_R4F           101
 168 #define AB8500_INT_CHAUTORESTARTAFTSEC  102
 169 #define AB8500_INT_CHSTOPBYSEC          103
 170 /* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
 171 #define AB8500_INT_USB_CH_TH_PROT_F     104
 172 #define AB8500_INT_USB_CH_TH_PROT_R    105
 173 #define AB8500_INT_MAIN_CH_TH_PROT_F    106 /* not 8505/9540 */
 174 #define AB8500_INT_MAIN_CH_TH_PROT_R    107 /* not 8505/9540 */
 175 #define AB8500_INT_CHCURLIMNOHSCHIRP    109
 176 #define AB8500_INT_CHCURLIMHSCHIRP      110
 177 #define AB8500_INT_XTAL32K_KO           111
 178
 179 /* Definitions for AB9540 */
 180 /* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
 181 #define AB9540_INT_GPIO50R              113
 182 #define AB9540_INT_GPIO51R              114 /* not 8505 */
 183 #define AB9540_INT_GPIO52R              115
 184 #define AB9540_INT_GPIO53R              116
 185 #define AB9540_INT_GPIO54R              117 /* not 8505 */
 186 #define AB9540_INT_IEXT_CH_RF_BFN_R     118
 187 #define AB9540_INT_IEXT_CH_RF_BFN_F     119
 188 /* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
 189 #define AB9540_INT_GPIO50F              121
 190 #define AB9540_INT_GPIO51F              122 /* not 8505 */
 191 #define AB9540_INT_GPIO52F              123
 192 #define AB9540_INT_GPIO53F              124
 193 #define AB9540_INT_GPIO54F              125 /* not 8505 */
 194
 195 /*
 196  * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
 197  * entire platform. This is a "compile time" constant so this must be set to
 198  * the largest possible value that may be encountered with different AB SOCs.
 199  * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
 200  * which is larger.
 201  */
 202 #define AB8500_NR_IRQS                  112
 203 #define AB8505_NR_IRQS                  128
 204 #define AB9540_NR_IRQS                  128
 205 /* This is set to the roof of any AB8500 chip variant IRQ counts */
 206 #define AB8500_MAX_NR_IRQS              AB9540_NR_IRQS
 207
 208 #define AB8500_NUM_IRQ_REGS             14
 209 #define AB9540_NUM_IRQ_REGS             17
 210
 211 /**
 212  * struct ab8500 - ab8500 internal structure
 213  * @dev: parent device
 214  * @lock: read/write operations lock
 215  * @irq_lock: genirq bus lock
 216  * @irq: irq line
 217  * @version: chip version id (e.g. ab8500 or ab9540)
 218  * @chip_id: chip revision id
 219  * @write: register write
 220  * @write_masked: masked register write
 221  * @read: register read
 222  * @rx_buf: rx buf for SPI
 223  * @tx_buf: tx buf for SPI
 224  * @mask: cache of IRQ regs for bus lock
 225  * @oldmask: cache of previous IRQ regs for bus lock
 226  * @mask_size: Actual number of valid entries in mask[], oldmask[] and
 227  * irq_reg_offset
 228  * @irq_reg_offset: Array of offsets into IRQ registers
 229  */
 230 struct ab8500 {
 231         struct device   *dev;
 232         struct mutex    lock;
 233         struct mutex    irq_lock;
 234
 235         int             irq_base;
 236         int             irq;
 237         enum ab8500_version version;
 238         u8              chip_id;
 239
 240         int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
 241         int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
 242         int (*read)(struct ab8500 *ab8500, u16 addr);
 243
 244         unsigned long   tx_buf[4];
 245         unsigned long   rx_buf[4];
 246
 247         u8 *mask;
 248         u8 *oldmask;
 249         int mask_size;
 250         const int *irq_reg_offset;
 251 };
 252
 253 struct regulator_reg_init;
 254 struct regulator_init_data;
 255 struct ab8500_gpio_platform_data;
 256
 257 /**
 258  * struct ab8500_platform_data - AB8500 platform data
 259  * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
 260  * @init: board-specific initialization after detection of ab8500
 261  * @num_regulator_reg_init: number of regulator init registers
 262  * @regulator_reg_init: regulator init registers
 263  * @num_regulator: number of regulators
 264  * @regulator: machine-specific constraints for regulators
 265  */
 266 struct ab8500_platform_data {
 267         int irq_base;
 268         void (*init) (struct ab8500 *);
 269         int num_regulator_reg_init;
 270         struct ab8500_regulator_reg_init *regulator_reg_init;
 271         int num_regulator;
 272         struct regulator_init_data *regulator;
 273         struct ab8500_gpio_platform_data *gpio;
 274 };
 275
 276 extern int __devinit ab8500_init(struct ab8500 *ab8500,
 277                                  enum ab8500_version version);
 278 extern int __devexit ab8500_exit(struct ab8500 *ab8500);
 279
 280 static inline int is_ab8500(struct ab8500 *ab)
 281 {
 282         return ab->version == AB8500_VERSION_AB8500;
 283 }
 284
 285 static inline int is_ab8505(struct ab8500 *ab)
 286 {
 287         return ab->version == AB8500_VERSION_AB8505;
 288 }
 289
 290 static inline int is_ab9540(struct ab8500 *ab)
 291 {
 292         return ab->version == AB8500_VERSION_AB9540;
 293 }
 294
 295 static inline int is_ab8540(struct ab8500 *ab)
 296 {
 297         return ab->version == AB8500_VERSION_AB8540;
 298 }
 299
 300 /* exclude also ab8505, ab9540... */
 301 static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
 302 {
 303         return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
 304 }
 305
 306 /* exclude also ab8505, ab9540... */
 307 static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
 308 {
 309         return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
 310 }
 311
 312 /* exclude also ab8505, ab9540... */
 313 static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
 314 {
 315         return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
 316 }
 317
 318 /* exclude also ab8505, ab9540... */
 319 static inline int is_ab8500_2p0(struct ab8500 *ab)
 320 {
 321         return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
 322 }
 323
 324 #endif /* MFD_AB8500_H */